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stm32f30x_misc.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_misc.c 00004 * @author MCD Application Team 00005 * @version V1.2.3 00006 * @date 10-July-2015 00007 * @brief This file provides all the miscellaneous firmware functions (add-on 00008 * to CMSIS functions). 00009 * 00010 @verbatim 00011 00012 =============================================================================== 00013 ##### How to configure Interrupts using driver ##### 00014 =============================================================================== 00015 [..] This section provide functions allowing to configure the NVIC interrupts 00016 (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions. 00017 (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() 00018 function according to the following table. 00019 The table below gives the allowed values of the pre-emption priority 00020 and subpriority according to the Priority Grouping configuration 00021 performed by NVIC_PriorityGroupConfig function. 00022 00023 (#) Enable and Configure the priority of the selected IRQ Channels. 00024 [..] 00025 (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt, 00026 the IRQ priority will be managed only by subpriority. 00027 The sub-priority is only used to sort pending exception priorities, 00028 and does not affect active exceptions. 00029 (@) Lower priority values gives higher priority. 00030 (@) Priority Order: 00031 (#@) Lowest Preemption priority. 00032 (#@) Lowest Subpriority. 00033 (#@) Lowest hardware priority (IRQn position). 00034 00035 @endverbatim 00036 00037 ****************************************************************************** 00038 * @attention 00039 * 00040 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00041 * 00042 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00043 * You may not use this file except in compliance with the License. 00044 * You may obtain a copy of the License at: 00045 * 00046 * http://www.st.com/software_license_agreement_liberty_v2 00047 * 00048 * Unless required by applicable law or agreed to in writing, software 00049 * distributed under the License is distributed on an "AS IS" BASIS, 00050 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00051 * See the License for the specific language governing permissions and 00052 * limitations under the License. 00053 * 00054 ****************************************************************************** 00055 */ 00056 00057 /* Includes ------------------------------------------------------------------*/ 00058 #include "stm32f30x_misc.h" 00059 00060 /** @addtogroup STM32F30x_StdPeriph_Driver 00061 * @{ 00062 */ 00063 00064 /** @defgroup MISC 00065 * @brief MISC driver modules 00066 * @{ 00067 */ 00068 00069 /* Private typedef -----------------------------------------------------------*/ 00070 /* Private define ------------------------------------------------------------*/ 00071 #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 00072 00073 /* Private macro -------------------------------------------------------------*/ 00074 /* Private variables ---------------------------------------------------------*/ 00075 /* Private function prototypes -----------------------------------------------*/ 00076 /* Private functions ---------------------------------------------------------*/ 00077 00078 /** @defgroup MISC_Private_Functions 00079 * @{ 00080 */ 00081 00082 /** 00083 * @brief Configures the priority grouping: pre-emption priority and subpriority. 00084 * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 00085 * This parameter can be one of the following values: 00086 * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority. 00087 * 4 bits for subpriority. 00088 * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority. 00089 * 3 bits for subpriority. 00090 * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority. 00091 * 2 bits for subpriority. 00092 * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority. 00093 * 1 bits for subpriority. 00094 * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority. 00095 * 0 bits for subpriority. 00096 * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested 00097 * interrupt. This interrupts priority is managed only with subpriority. 00098 * @retval None 00099 */ 00100 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 00101 { 00102 /* Check the parameters */ 00103 assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 00104 00105 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 00106 SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 00107 } 00108 00109 /** 00110 * @brief Initializes the NVIC peripheral according to the specified 00111 * parameters in the NVIC_InitStruct. 00112 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 00113 * function should be called before. 00114 * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 00115 * the configuration information for the specified NVIC peripheral. 00116 * @retval None 00117 */ 00118 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 00119 { 00120 uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 00121 00122 /* Check the parameters */ 00123 assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 00124 assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 00125 assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 00126 00127 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 00128 { 00129 /* Compute the Corresponding IRQ Priority --------------------------------*/ 00130 tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 00131 tmppre = (0x4 - tmppriority); 00132 tmpsub = tmpsub >> tmppriority; 00133 00134 tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 00135 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 00136 tmppriority = tmppriority << 0x04; 00137 00138 NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 00139 00140 /* Enable the Selected IRQ Channels --------------------------------------*/ 00141 NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 00142 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 00143 } 00144 else 00145 { 00146 /* Disable the Selected IRQ Channels -------------------------------------*/ 00147 NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 00148 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 00149 } 00150 } 00151 00152 /** 00153 * @brief Sets the vector table location and Offset. 00154 * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 00155 * This parameter can be one of the following values: 00156 * @arg NVIC_VectTab_RAM 00157 * @arg NVIC_VectTab_FLASH 00158 * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. 00159 * @retval None 00160 */ 00161 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 00162 { 00163 /* Check the parameters */ 00164 assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 00165 assert_param(IS_NVIC_OFFSET(Offset)); 00166 00167 SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 00168 } 00169 00170 /** 00171 * @brief Selects the condition for the system to enter low power mode. 00172 * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 00173 * This parameter can be one of the following values: 00174 * @arg NVIC_LP_SEVONPEND 00175 * @arg NVIC_LP_SLEEPDEEP 00176 * @arg NVIC_LP_SLEEPONEXIT 00177 * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 00178 * @retval None 00179 */ 00180 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 00181 { 00182 /* Check the parameters */ 00183 assert_param(IS_NVIC_LP(LowPowerMode)); 00184 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00185 00186 if (NewState != DISABLE) 00187 { 00188 SCB->SCR |= LowPowerMode; 00189 } 00190 else 00191 { 00192 SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 00193 } 00194 } 00195 00196 /** 00197 * @brief Configures the SysTick clock source. 00198 * @param SysTick_CLKSource: specifies the SysTick clock source. 00199 * This parameter can be one of the following values: 00200 * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 00201 * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 00202 * @retval None 00203 */ 00204 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 00205 { 00206 /* Check the parameters */ 00207 assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 00208 if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 00209 { 00210 SysTick->CTRL |= SysTick_CLKSource_HCLK; 00211 } 00212 else 00213 { 00214 SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 00215 } 00216 } 00217 00218 /** 00219 * @} 00220 */ 00221 00222 /** 00223 * @} 00224 */ 00225 00226 /** 00227 * @} 00228 */ 00229 00230 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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