stm32f30x_fmc.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32f30x_fmc.h
00004   * @author  MCD Application Team
00005   * @version V1.2.3
00006   * @date    10-July-2015
00007   * @brief   This file contains all the functions prototypes for the FMC firmware 
00008   *          library.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00013   *
00014   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00015   * You may not use this file except in compliance with the License.
00016   * You may obtain a copy of the License at:
00017   *
00018   *        http://www.st.com/software_license_agreement_liberty_v2
00019   *
00020   * Unless required by applicable law or agreed to in writing, software 
00021   * distributed under the License is distributed on an "AS IS" BASIS, 
00022   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00023   * See the License for the specific language governing permissions and
00024   * limitations under the License.
00025   *
00026   ******************************************************************************
00027   */ 
00028 
00029 /* Define to prevent recursive inclusion -------------------------------------*/
00030 #ifndef __STM32F30x_FMC_H
00031 #define __STM32F30x_FMC_H
00032 
00033 #ifdef __cplusplus
00034  extern "C" {
00035 #endif
00036 
00037 /* Includes ------------------------------------------------------------------*/
00038 #include "stm32f30x.h"
00039 
00040 /** @addtogroup STM32F30x_StdPeriph_Driver
00041   * @{
00042   */
00043 
00044 /** @addtogroup FMC
00045   * @{
00046   */
00047 
00048 /* Exported types ------------------------------------------------------------*/  
00049    
00050 /** 
00051   * @brief  Timing parameters For NOR/SRAM Banks  
00052   */
00053 typedef struct
00054 {
00055   uint32_t FMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
00056                                              the duration of the address setup time. 
00057                                              This parameter can be a value between 0 and 15.
00058                                              @note This parameter is not used with synchronous NOR Flash memories. */
00059 
00060   uint32_t FMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
00061                                              the duration of the address hold time.
00062                                              This parameter can be a value between 1 and 15. 
00063                                              @note This parameter is not used with synchronous NOR Flash memories.*/
00064 
00065   uint32_t FMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
00066                                              the duration of the data setup time.
00067                                              This parameter can be a value between 1 and 255.
00068                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
00069 
00070   uint32_t FMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
00071                                              the duration of the bus turnaround.
00072                                              This parameter can be a value between 0 and 15.
00073                                              @note This parameter is only used for multiplexed NOR Flash memories. */
00074 
00075   uint32_t FMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
00076                                              This parameter can be a value between 2 and 16.
00077                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
00078 
00079   uint32_t FMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
00080                                              to the memory before getting the first data.
00081                                              The parameter value depends on the memory type as shown below:
00082                                               - It must be set to 0 in case of a CRAM
00083                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
00084                                               - It may assume a value between 2 and 17 in NOR Flash memories
00085                                                 with synchronous burst mode enable */
00086 
00087   uint32_t FMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
00088                                              This parameter can be a value of @ref FMC_Access_Mode */
00089 }FMC_NORSRAMTimingInitTypeDef;
00090 
00091 /** 
00092   * @brief  FMC NOR/SRAM Init structure definition
00093   */
00094 typedef struct
00095 {
00096   uint32_t FMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
00097                                           This parameter can be a value of @ref FMC_NORSRAM_Bank */
00098 
00099   uint32_t FMC_DataAddressMux;      /*!< Specifies whether the address and data values are
00100                                           multiplexed on the databus or not. 
00101                                           This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
00102 
00103   uint32_t FMC_MemoryType;          /*!< Specifies the type of external memory attached to
00104                                           the corresponding memory bank.
00105                                           This parameter can be a value of @ref FMC_Memory_Type */
00106 
00107   uint32_t FMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
00108                                           This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
00109 
00110   uint32_t FMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
00111                                           valid only with synchronous burst Flash memories.
00112                                           This parameter can be a value of @ref FMC_Burst_Access_Mode */                                        
00113 
00114   uint32_t FMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
00115                                           the Flash memory in burst mode.
00116                                           This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
00117 
00118   uint32_t FMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
00119                                           memory, valid only when accessing Flash memories in burst mode.
00120                                           This parameter can be a value of @ref FMC_Wrap_Mode */
00121 
00122   uint32_t FMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
00123                                           clock cycle before the wait state or during the wait state,
00124                                           valid only when accessing memories in burst mode. 
00125                                           This parameter can be a value of @ref FMC_Wait_Timing */
00126 
00127   uint32_t FMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FMC. 
00128                                           This parameter can be a value of @ref FMC_Write_Operation */
00129 
00130   uint32_t FMC_WaitSignal;          /*!< Enables or disables the wait state insertion via wait
00131                                           signal, valid for Flash memory access in burst mode. 
00132                                           This parameter can be a value of @ref FMC_Wait_Signal */
00133 
00134   uint32_t FMC_ExtendedMode;        /*!< Enables or disables the extended mode.
00135                                           This parameter can be a value of @ref FMC_Extended_Mode */
00136   
00137   uint32_t FMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
00138                                           valid only with asynchronous Flash memories.
00139                                           This parameter can be a value of @ref FMC_AsynchronousWait */  
00140 
00141   uint32_t FMC_WriteBurst;          /*!< Enables or disables the write burst operation.
00142                                           This parameter can be a value of @ref FMC_Write_Burst */
00143 
00144   
00145   FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  Extended Mode is not used*/  
00146 
00147   FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  Extended Mode is used*/      
00148 }FMC_NORSRAMInitTypeDef;
00149 
00150 /** 
00151   * @brief  Timing parameters For FMC NAND and PCCARD Banks
00152   */
00153 typedef struct
00154 {
00155   uint32_t FMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
00156                                      the command assertion for NAND-Flash read or write access
00157                                      to common/Attribute or I/O memory space (depending on
00158                                      the memory space timing to be configured).
00159                                      This parameter can be a value between 0 and 255.*/
00160 
00161   uint32_t FMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
00162                                      command for NAND-Flash read or write access to
00163                                      common/Attribute or I/O memory space (depending on the
00164                                      memory space timing to be configured). 
00165                                      This parameter can be a number between 0 and 255 */
00166 
00167   uint32_t FMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
00168                                      (and data for write access) after the command de-assertion
00169                                      for NAND-Flash read or write access to common/Attribute
00170                                      or I/O memory space (depending on the memory space timing
00171                                      to be configured).
00172                                      This parameter can be a number between 0 and 255 */
00173 
00174   uint32_t FMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
00175                                      databus is kept in HiZ after the start of a NAND-Flash
00176                                      write access to common/Attribute or I/O memory space (depending
00177                                      on the memory space timing to be configured).
00178                                      This parameter can be a number between 0 and 255 */
00179 }FMC_NAND_PCCARDTimingInitTypeDef;
00180 
00181 /** 
00182   * @brief  FMC NAND Init structure definition
00183   */
00184 typedef struct
00185 {
00186   uint32_t FMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
00187                                       This parameter can be a value of @ref FMC_NAND_Bank */
00188 
00189   uint32_t FMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
00190                                        This parameter can be any value of @ref FMC_Wait_feature */
00191 
00192   uint32_t FMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
00193                                        This parameter can be any value of @ref FMC_NAND_Data_Width */
00194 
00195   uint32_t FMC_ECC;              /*!< Enables or disables the ECC computation.
00196                                        This parameter can be any value of @ref FMC_ECC */
00197 
00198   uint32_t FMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
00199                                        This parameter can be any value of @ref FMC_ECC_Page_Size */
00200 
00201   uint32_t FMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
00202                                        delay between CLE low and RE low.
00203                                        This parameter can be a value between 0 and 255. */
00204 
00205   uint32_t FMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
00206                                        delay between ALE low and RE low.
00207                                        This parameter can be a number between 0 and 255 */ 
00208 
00209   FMC_NAND_PCCARDTimingInitTypeDef*  FMC_CommonSpaceTimingStruct;   /*!< FMC Common Space Timing */ 
00210 
00211   FMC_NAND_PCCARDTimingInitTypeDef*  FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
00212 }FMC_NANDInitTypeDef;
00213 
00214 /** 
00215   * @brief  FMC PCCARD Init structure definition
00216   */
00217 
00218 typedef struct
00219 {
00220   uint32_t FMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
00221                                     This parameter can be any value of @ref FMC_Wait_feature */
00222 
00223   uint32_t FMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
00224                                      delay between CLE low and RE low.
00225                                      This parameter can be a value between 0 and 255. */
00226 
00227   uint32_t FMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
00228                                      delay between ALE low and RE low.
00229                                      This parameter can be a number between 0 and 255 */ 
00230 
00231   
00232   FMC_NAND_PCCARDTimingInitTypeDef*  FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
00233 
00234   FMC_NAND_PCCARDTimingInitTypeDef*  FMC_AttributeSpaceTimingStruct;  /*!< FMC Attribute Space Timing */ 
00235   
00236   FMC_NAND_PCCARDTimingInitTypeDef*  FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */  
00237 }FMC_PCCARDInitTypeDef;
00238 
00239 
00240 /* Exported constants --------------------------------------------------------*/
00241 
00242 /** @defgroup FMC_Exported_Constants
00243   * @{
00244   */ 
00245 
00246 /** @defgroup FMC_NORSRAM_Bank 
00247   * @{
00248   */
00249 #define FMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
00250 #define FMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
00251 #define FMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
00252 #define FMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
00253 
00254 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
00255                                    ((BANK) == FMC_Bank1_NORSRAM2) || \
00256                                    ((BANK) == FMC_Bank1_NORSRAM3) || \
00257                                    ((BANK) == FMC_Bank1_NORSRAM4))
00258 /**
00259   * @}
00260   */
00261 
00262 /** @defgroup FMC_NAND_Bank 
00263   * @{
00264   */  
00265 #define FMC_Bank2_NAND                          ((uint32_t)0x00000010)
00266 #define FMC_Bank3_NAND                          ((uint32_t)0x00000100)
00267 
00268 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
00269                                 ((BANK) == FMC_Bank3_NAND))
00270 /**
00271   * @}
00272   */
00273 
00274 /** @defgroup FMC_PCCARD_Bank 
00275   * @{
00276   */    
00277 #define FMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
00278 /**
00279   * @}                                                         
00280   */                              
00281 
00282                               
00283 /** @defgroup FMC_NOR_SRAM_Controller 
00284   * @{
00285   */
00286 
00287 /** @defgroup FMC_Data_Address_Bus_Multiplexing 
00288   * @{
00289   */
00290 
00291 #define FMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
00292 #define FMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
00293 
00294 #define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
00295                          ((MUX) == FMC_DataAddressMux_Enable))
00296 /**
00297   * @}
00298   */
00299 
00300 /** @defgroup FMC_Memory_Type 
00301   * @{
00302   */
00303 
00304 #define FMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
00305 #define FMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
00306 #define FMC_MemoryType_NOR                      ((uint32_t)0x00000008)
00307 
00308 #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
00309                                ((MEMORY) == FMC_MemoryType_PSRAM)|| \
00310                                ((MEMORY) == FMC_MemoryType_NOR))
00311 /**
00312   * @}
00313   */
00314 
00315 /** @defgroup FMC_NORSRAM_Data_Width 
00316   * @{
00317   */
00318 
00319 #define FMC_NORSRAM_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
00320 #define FMC_NORSRAM_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
00321 
00322 #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b)  || \
00323                                             ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b))
00324 /**
00325   * @}
00326   */
00327 
00328 /** @defgroup FMC_Burst_Access_Mode 
00329   * @{
00330   */
00331 
00332 #define FMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
00333 #define FMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
00334 
00335 #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
00336                                   ((STATE) == FMC_BurstAccessMode_Enable))
00337 /**
00338   * @}
00339   */
00340     
00341 /** @defgroup FMC_AsynchronousWait 
00342   * @{
00343   */
00344 #define FMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
00345 #define FMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
00346 
00347 #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
00348                                  ((STATE) == FMC_AsynchronousWait_Enable))
00349 /**
00350   * @}
00351   */
00352 
00353 /** @defgroup FMC_Wait_Signal_Polarity 
00354   * @{
00355   */
00356 #define FMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
00357 #define FMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
00358 
00359 #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
00360                                          ((POLARITY) == FMC_WaitSignalPolarity_High))
00361 /**
00362   * @}
00363   */
00364 
00365 /** @defgroup FMC_Wrap_Mode 
00366   * @{
00367   */
00368 #define FMC_WrapMode_Disable                    ((uint32_t)0x00000000)
00369 #define FMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
00370 
00371 #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
00372                                  ((MODE) == FMC_WrapMode_Enable))
00373 /**
00374   * @}
00375   */
00376 
00377 /** @defgroup FMC_Wait_Timing 
00378   * @{
00379   */
00380 #define FMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
00381 #define FMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
00382 
00383 #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
00384                                             ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
00385 /**
00386   * @}
00387   */
00388 
00389 /** @defgroup FMC_Write_Operation 
00390   * @{
00391   */
00392 #define FMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
00393 #define FMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
00394 
00395 #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
00396                                             ((OPERATION) == FMC_WriteOperation_Enable))                         
00397 /**
00398   * @}
00399   */
00400 
00401 /** @defgroup FMC_Wait_Signal 
00402   * @{
00403   */
00404 #define FMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
00405 #define FMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
00406 
00407 #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
00408                                       ((SIGNAL) == FMC_WaitSignal_Enable))
00409 /**
00410   * @}
00411   */
00412 
00413 /** @defgroup FMC_Extended_Mode 
00414   * @{
00415   */
00416 #define FMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
00417 #define FMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
00418 
00419 #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
00420                                      ((MODE) == FMC_ExtendedMode_Enable)) 
00421 /**
00422   * @}
00423   */
00424 
00425 /** @defgroup FMC_Write_Burst 
00426   * @{
00427   */
00428 
00429 #define FMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
00430 #define FMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
00431 
00432 #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
00433                                     ((BURST) == FMC_WriteBurst_Enable))
00434 /**
00435   * @}
00436   */
00437   
00438 /** @defgroup FMC_Continous_Clock 
00439   * @{
00440   */
00441 
00442 #define FMC_CClock_SyncOnly                     ((uint32_t)0x00000000)
00443 #define FMC_CClock_SyncAsync                    ((uint32_t)0x00100000) 
00444 
00445 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
00446                                         ((CCLOCK) == FMC_CClock_SyncAsync))
00447 /**
00448   * @}
00449   */  
00450 
00451 /** @defgroup FMC_Address_Setup_Time 
00452   * @{
00453   */
00454 #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
00455 /**
00456   * @}
00457   */
00458 
00459 /** @defgroup FMC_Address_Hold_Time 
00460   * @{
00461   */
00462 #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
00463 /**
00464   * @}
00465   */
00466 
00467 /** @defgroup FMC_Data_Setup_Time 
00468   * @{
00469   */
00470 #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
00471 /**
00472   * @}
00473   */
00474 
00475 /** @defgroup FMC_Bus_Turn_around_Duration 
00476   * @{
00477   */
00478 #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
00479 /**
00480   * @}
00481   */
00482 
00483 /** @defgroup FMC_CLK_Division 
00484   * @{
00485   */
00486 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
00487 /**
00488   * @}
00489   */
00490 
00491 /** @defgroup FMC_Data_Latency 
00492   * @{
00493   */
00494 #define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
00495 /**
00496   * @}
00497   */
00498 
00499 /** @defgroup FMC_Access_Mode 
00500   * @{
00501   */
00502 #define FMC_AccessMode_A                        ((uint32_t)0x00000000)
00503 #define FMC_AccessMode_B                        ((uint32_t)0x10000000) 
00504 #define FMC_AccessMode_C                        ((uint32_t)0x20000000)
00505 #define FMC_AccessMode_D                        ((uint32_t)0x30000000)
00506 
00507 #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A)  || \
00508                                    ((MODE) == FMC_AccessMode_B) || \
00509                                    ((MODE) == FMC_AccessMode_C) || \
00510                                    ((MODE) == FMC_AccessMode_D))
00511 /**
00512   * @}
00513   */
00514 
00515 /**
00516   * @}
00517   */
00518   
00519 /** @defgroup FMC_NAND_PCCARD_Controller 
00520   * @{
00521   */
00522 
00523 /** @defgroup FMC_Wait_feature 
00524   * @{
00525   */
00526 #define FMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
00527 #define FMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
00528 
00529 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
00530                                        ((FEATURE) == FMC_Waitfeature_Enable))
00531 /**
00532   * @}
00533   */
00534 
00535 /** @defgroup FMC_NAND_Data_Width 
00536   * @{
00537   */
00538 #define FMC_NAND_MemoryDataWidth_8b             ((uint32_t)0x00000000)
00539 #define FMC_NAND_MemoryDataWidth_16b            ((uint32_t)0x00000010)
00540 
00541 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
00542                                          ((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
00543 /**
00544   * @}
00545   */
00546 
00547 /** @defgroup FMC_ECC 
00548   * @{
00549   */
00550 #define FMC_ECC_Disable                         ((uint32_t)0x00000000)
00551 #define FMC_ECC_Enable                          ((uint32_t)0x00000040)
00552 
00553 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
00554                                   ((STATE) == FMC_ECC_Enable))
00555 /**
00556   * @}
00557   */
00558 
00559 /** @defgroup FMC_ECC_Page_Size 
00560   * @{
00561   */
00562 #define FMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
00563 #define FMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
00564 #define FMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
00565 #define FMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
00566 #define FMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
00567 #define FMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
00568 
00569 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes)   || \
00570                                     ((SIZE) == FMC_ECCPageSize_512Bytes)  || \
00571                                     ((SIZE) == FMC_ECCPageSize_1024Bytes) || \
00572                                     ((SIZE) == FMC_ECCPageSize_2048Bytes) || \
00573                                     ((SIZE) == FMC_ECCPageSize_4096Bytes) || \
00574                                     ((SIZE) == FMC_ECCPageSize_8192Bytes))
00575 /**
00576   * @}
00577   */
00578 
00579 /** @defgroup FMC_TCLR_Setup_Time 
00580   * @{
00581   */
00582 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
00583 /**
00584   * @}
00585   */
00586 
00587 /** @defgroup FMC_TAR_Setup_Time 
00588   * @{
00589   */
00590 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
00591 /**
00592   * @}
00593   */
00594 
00595 /** @defgroup FMC_Setup_Time 
00596   * @{
00597   */
00598 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
00599 /**
00600   * @}
00601   */
00602 
00603 /** @defgroup FMC_Wait_Setup_Time 
00604   * @{
00605   */
00606 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
00607 /**
00608   * @}
00609   */
00610 
00611 /** @defgroup FMC_Hold_Setup_Time 
00612   * @{
00613   */
00614 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
00615 /**
00616   * @}
00617   */
00618 
00619 /** @defgroup FMC_HiZ_Setup_Time 
00620   * @{
00621   */
00622 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
00623 /**
00624   * @}
00625   */ 
00626 
00627 /**
00628   * @}
00629   */  
00630 
00631 /** @defgroup FMC_Interrupt_sources 
00632   * @{
00633   */
00634 #define FMC_IT_RisingEdge                       ((uint32_t)0x00000008)
00635 #define FMC_IT_Level                            ((uint32_t)0x00000010)
00636 #define FMC_IT_FallingEdge                      ((uint32_t)0x00000020)
00637 
00638 #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
00639 #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge)  || \
00640                            ((IT) == FMC_IT_Level)       || \
00641                            ((IT) == FMC_IT_FallingEdge)) 
00642                            
00643 #define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND)   || \
00644                               ((BANK) == FMC_Bank3_NAND)   || \
00645                               ((BANK) == FMC_Bank4_PCCARD))                           
00646 /**
00647   * @}
00648   */
00649 
00650 /** @defgroup FMC_Flags 
00651   * @{
00652   */
00653 #define FMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
00654 #define FMC_FLAG_Level                          ((uint32_t)0x00000002)
00655 #define FMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
00656 #define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
00657 
00658 #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge)       || \
00659                                ((FLAG) == FMC_FLAG_Level)            || \
00660                                ((FLAG) == FMC_FLAG_FallingEdge)      || \
00661                                ((FLAG) == FMC_FLAG_FEMPT))
00662 
00663 #define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND)    || \
00664                                    ((BANK) == FMC_Bank3_NAND)    || \
00665                                    ((BANK) == FMC_Bank4_PCCARD))
00666                                    
00667 #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
00668 
00669 
00670 /**
00671   * @}
00672   */
00673 
00674 /**
00675   * @}
00676   */
00677 
00678 
00679 /* Exported macro ------------------------------------------------------------*/
00680 /* Exported functions --------------------------------------------------------*/ 
00681 
00682 /* NOR/SRAM Controller functions **********************************************/
00683 void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
00684 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
00685 void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
00686 void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
00687 
00688 /* NAND Controller functions **************************************************/
00689 void     FMC_NANDDeInit(uint32_t FMC_Bank);
00690 void     FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
00691 void     FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
00692 void     FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
00693 void     FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
00694 uint32_t FMC_GetECC(uint32_t FMC_Bank);
00695 
00696 /* PCCARD Controller functions ************************************************/
00697 void FMC_PCCARDDeInit(void);
00698 void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
00699 void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
00700 void FMC_PCCARDCmd(FunctionalState NewState);
00701 
00702 /* Interrupts and flags management functions **********************************/
00703 void       FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
00704 FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
00705 void       FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
00706 ITStatus   FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
00707 void       FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
00708 
00709 #ifdef __cplusplus
00710 }
00711 #endif
00712 
00713 #endif /*__STM32F30x_FMC_H */
00714 /**
00715   * @}
00716   */
00717 
00718 /**
00719   * @}
00720   */ 
00721 
00722 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/