Martin Johnson
/
STM32F3-Discovery
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Dependents: Space_Invaders_Demo neopixels gpio_test_stm32f3_discovery gpio_test_systimer ... more
Embed:
(wiki syntax)
Show/hide line numbers
stm32f30x_fmc.c
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x_fmc.c 00004 * @author MCD Application Team 00005 * @version V1.2.3 00006 * @date 10-July-2015 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the FMC peripheral: 00009 * + Interface with SRAM, PSRAM, NOR and OneNAND memories 00010 * + Interface with NAND memories 00011 * + Interface with 16-bit PC Card compatible memories 00012 * + Interrupts and flags management 00013 * 00014 ****************************************************************************** 00015 * @attention 00016 * 00017 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00018 * 00019 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00020 * You may not use this file except in compliance with the License. 00021 * You may obtain a copy of the License at: 00022 * 00023 * http://www.st.com/software_license_agreement_liberty_v2 00024 * 00025 * Unless required by applicable law or agreed to in writing, software 00026 * distributed under the License is distributed on an "AS IS" BASIS, 00027 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00028 * See the License for the specific language governing permissions and 00029 * limitations under the License. 00030 * 00031 ****************************************************************************** 00032 */ 00033 00034 /* Includes ------------------------------------------------------------------*/ 00035 #include "stm32f30x_fmc.h" 00036 #include "stm32f30x_rcc.h" 00037 00038 /** @addtogroup STM32F30x_StdPeriph_Driver 00039 * @{ 00040 */ 00041 00042 /** @defgroup FMC 00043 * @brief FMC driver modules 00044 * @{ 00045 */ 00046 00047 /* Private typedef -----------------------------------------------------------*/ 00048 /* Private define ------------------------------------------------------------*/ 00049 00050 /* --------------------- FMC registers bit mask ---------------------------- */ 00051 /* FMC BCRx Mask */ 00052 #define BCR_MBKEN_SET ((uint32_t)0x00000001) 00053 #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) 00054 #define BCR_FACCEN_SET ((uint32_t)0x00000040) 00055 00056 /* FMC PCRx Mask */ 00057 #define PCR_PBKEN_SET ((uint32_t)0x00000004) 00058 #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) 00059 #define PCR_ECCEN_SET ((uint32_t)0x00000040) 00060 #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) 00061 #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) 00062 00063 /* Private macro -------------------------------------------------------------*/ 00064 /* Private variables ---------------------------------------------------------*/ 00065 /* Private function prototypes -----------------------------------------------*/ 00066 /* Private functions ---------------------------------------------------------*/ 00067 00068 /** @defgroup FMC_Private_Functions 00069 * @{ 00070 */ 00071 00072 /** @defgroup FMC_Group1 NOR/SRAM Controller functions 00073 * @brief NOR/SRAM Controller functions 00074 * 00075 @verbatim 00076 =============================================================================== 00077 ##### NOR and SRAM Controller functions ##### 00078 =============================================================================== 00079 00080 [..] The following sequence should be followed to configure the FMC to interface 00081 with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: 00082 00083 (#) Enable the clock for the FMC and associated GPIOs using the following functions: 00084 RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); 00085 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 00086 00087 (#) FMC pins configuration 00088 (++) Connect the involved FMC pins to AF12 using the following function 00089 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); 00090 (++) Configure these FMC pins in alternate function mode by calling the function 00091 GPIO_Init(); 00092 00093 (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: 00094 FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; 00095 and fill the FMC_NORSRAMInitStructure variable with the allowed values of 00096 the structure member. 00097 00098 (#) Initialize the NOR/SRAM Controller by calling the function 00099 FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); 00100 00101 (#) Then enable the NOR/SRAM Bank, for example: 00102 FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); 00103 00104 (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. 00105 00106 @endverbatim 00107 * @{ 00108 */ 00109 00110 /** 00111 * @brief De-initializes the FMC NOR/SRAM Banks registers to their default 00112 * reset values. 00113 * @param FMC_Bank: specifies the FMC Bank to be used 00114 * This parameter can be one of the following values: 00115 * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 00116 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 00117 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 00118 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 00119 * @retval None 00120 */ 00121 void FMC_NORSRAMDeInit(uint32_t FMC_Bank) 00122 { 00123 /* Check the parameter */ 00124 assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); 00125 00126 /* FMC_Bank1_NORSRAM1 */ 00127 if(FMC_Bank == FMC_Bank1_NORSRAM1) 00128 { 00129 FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; 00130 } 00131 /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ 00132 else 00133 { 00134 FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; 00135 } 00136 FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; 00137 FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; 00138 } 00139 00140 /** 00141 * @brief Initializes the FMC NOR/SRAM Banks according to the specified 00142 * parameters in the FMC_NORSRAMInitStruct. 00143 * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure 00144 * that contains the configuration information for the FMC NOR/SRAM 00145 * specified Banks. 00146 * @retval None 00147 */ 00148 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) 00149 { 00150 /* Check the parameters */ 00151 assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); 00152 assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); 00153 assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); 00154 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); 00155 assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); 00156 assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); 00157 assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); 00158 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); 00159 assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); 00160 assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); 00161 assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); 00162 assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); 00163 assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); 00164 assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); 00165 assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); 00166 assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); 00167 assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); 00168 assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); 00169 assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); 00170 assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); 00171 00172 /* NOR/SRAM Bank control register configuration */ 00173 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = 00174 (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | 00175 FMC_NORSRAMInitStruct->FMC_MemoryType | 00176 FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | 00177 FMC_NORSRAMInitStruct->FMC_BurstAccessMode | 00178 FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | 00179 FMC_NORSRAMInitStruct->FMC_WrapMode | 00180 FMC_NORSRAMInitStruct->FMC_WaitSignalActive | 00181 FMC_NORSRAMInitStruct->FMC_WriteOperation | 00182 FMC_NORSRAMInitStruct->FMC_WaitSignal | 00183 FMC_NORSRAMInitStruct->FMC_ExtendedMode | 00184 FMC_NORSRAMInitStruct->FMC_AsynchronousWait | 00185 FMC_NORSRAMInitStruct->FMC_WriteBurst; 00186 00187 00188 if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) 00189 { 00190 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; 00191 } 00192 00193 /* NOR/SRAM Bank timing register configuration */ 00194 FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = 00195 (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | 00196 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | 00197 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | 00198 (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | 00199 (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20) | 00200 (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)-2) << 24) | 00201 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; 00202 00203 /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ 00204 if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) 00205 { 00206 assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); 00207 assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); 00208 assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); 00209 assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)); 00210 assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)); 00211 assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); 00212 00213 FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 00214 (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | 00215 (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )| 00216 (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | 00217 (((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)-1) << 20) | 00218 (((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)-2) << 24) | 00219 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode; 00220 } 00221 else 00222 { 00223 FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; 00224 } 00225 00226 } 00227 00228 /** 00229 * @brief Fills each FMC_NORSRAMInitStruct member with its default value. 00230 * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure 00231 * which will be initialized. 00232 * @retval None 00233 */ 00234 void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) 00235 { 00236 /* Reset NOR/SRAM Init structure parameters values */ 00237 FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; 00238 FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; 00239 FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; 00240 FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; 00241 FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; 00242 FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; 00243 FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; 00244 FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; 00245 FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; 00246 FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; 00247 FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; 00248 FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; 00249 FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; 00250 00251 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15; 00252 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15; 00253 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255; 00254 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15; 00255 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15; 00256 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15; 00257 FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; 00258 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15; 00259 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15; 00260 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255; 00261 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15; 00262 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 16; 00263 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 17; 00264 FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; 00265 } 00266 00267 /** 00268 * @brief Enables or disables the specified NOR/SRAM Memory Bank. 00269 * @param FMC_Bank: specifies the FMC Bank to be used 00270 * This parameter can be one of the following values: 00271 * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 00272 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 00273 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 00274 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 00275 * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. 00276 * @retval None 00277 */ 00278 void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) 00279 { 00280 assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); 00281 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00282 00283 if (NewState != DISABLE) 00284 { 00285 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ 00286 FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; 00287 } 00288 else 00289 { 00290 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ 00291 FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; 00292 } 00293 } 00294 /** 00295 * @} 00296 */ 00297 00298 /** @defgroup FMC_Group2 NAND Controller functions 00299 * @brief NAND Controller functions 00300 * 00301 @verbatim 00302 =============================================================================== 00303 ##### NAND Controller functions ##### 00304 =============================================================================== 00305 00306 [..] The following sequence should be followed to configure the FMC to interface 00307 with 8-bit or 16-bit NAND memory connected to the NAND Bank: 00308 00309 (#) Enable the clock for the FMC and associated GPIOs using the following functions: 00310 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); 00311 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 00312 00313 (#) FMC pins configuration 00314 (++) Connect the involved FMC pins to AF12 using the following function 00315 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); 00316 (++) Configure these FMC pins in alternate function mode by calling the function 00317 GPIO_Init(); 00318 00319 (#) Declare a FMC_NANDInitTypeDef structure, for example: 00320 FMC_NANDInitTypeDef FMC_NANDInitStructure; 00321 and fill the FMC_NANDInitStructure variable with the allowed values of 00322 the structure member. 00323 00324 (#) Initialize the NAND Controller by calling the function 00325 FMC_NANDInit(&FMC_NANDInitStructure); 00326 00327 (#) Then enable the NAND Bank, for example: 00328 FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); 00329 00330 (#) At this stage you can read/write from/to the memory connected to the NAND Bank. 00331 00332 [..] 00333 (@) To enable the Error Correction Code (ECC), you have to use the function 00334 FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); 00335 [..] 00336 (@) and to get the current ECC value you have to use the function 00337 ECCval = FMC_GetECC(FMC_Bank3_NAND); 00338 00339 @endverbatim 00340 * @{ 00341 */ 00342 00343 /** 00344 * @brief De-initializes the FMC NAND Banks registers to their default reset values. 00345 * @param FMC_Bank: specifies the FMC Bank to be used 00346 * This parameter can be one of the following values: 00347 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00348 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00349 * @retval None 00350 */ 00351 void FMC_NANDDeInit(uint32_t FMC_Bank) 00352 { 00353 /* Check the parameter */ 00354 assert_param(IS_FMC_NAND_BANK(FMC_Bank)); 00355 00356 if(FMC_Bank == FMC_Bank2_NAND) 00357 { 00358 /* Set the FMC_Bank2 registers to their reset values */ 00359 FMC_Bank2->PCR2 = 0x00000018; 00360 FMC_Bank2->SR2 = 0x00000040; 00361 FMC_Bank2->PMEM2 = 0xFCFCFCFC; 00362 FMC_Bank2->PATT2 = 0xFCFCFCFC; 00363 } 00364 /* FMC_Bank3_NAND */ 00365 else 00366 { 00367 /* Set the FMC_Bank3 registers to their reset values */ 00368 FMC_Bank3->PCR3 = 0x00000018; 00369 FMC_Bank3->SR3 = 0x00000040; 00370 FMC_Bank3->PMEM3 = 0xFCFCFCFC; 00371 FMC_Bank3->PATT3 = 0xFCFCFCFC; 00372 } 00373 } 00374 00375 /** 00376 * @brief Initializes the FMC NAND Banks according to the specified parameters 00377 * in the FMC_NANDInitStruct. 00378 * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that 00379 * contains the configuration information for the FMC NAND specified Banks. 00380 * @retval None 00381 */ 00382 void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) 00383 { 00384 uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 00385 00386 /* Check the parameters */ 00387 assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); 00388 assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); 00389 assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); 00390 assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); 00391 assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); 00392 assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); 00393 assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); 00394 assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); 00395 assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); 00396 assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); 00397 assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); 00398 assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); 00399 assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); 00400 assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); 00401 assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); 00402 00403 /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ 00404 tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | 00405 PCR_MEMORYTYPE_NAND | 00406 FMC_NANDInitStruct->FMC_MemoryDataWidth | 00407 FMC_NANDInitStruct->FMC_ECC | 00408 FMC_NANDInitStruct->FMC_ECCPageSize | 00409 (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| 00410 (FMC_NANDInitStruct->FMC_TARSetupTime << 13); 00411 00412 /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ 00413 tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | 00414 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | 00415 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| 00416 (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); 00417 00418 /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ 00419 tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | 00420 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | 00421 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| 00422 (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); 00423 00424 if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) 00425 { 00426 /* FMC_Bank2_NAND registers configuration */ 00427 FMC_Bank2->PCR2 = tmppcr; 00428 FMC_Bank2->PMEM2 = tmppmem; 00429 FMC_Bank2->PATT2 = tmppatt; 00430 } 00431 else 00432 { 00433 /* FMC_Bank3_NAND registers configuration */ 00434 FMC_Bank3->PCR3 = tmppcr; 00435 FMC_Bank3->PMEM3 = tmppmem; 00436 FMC_Bank3->PATT3 = tmppatt; 00437 } 00438 } 00439 00440 00441 /** 00442 * @brief Fills each FMC_NANDInitStruct member with its default value. 00443 * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which 00444 * will be initialized. 00445 * @retval None 00446 */ 00447 void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) 00448 { 00449 /* Reset NAND Init structure parameters values */ 00450 FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; 00451 FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; 00452 FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; 00453 FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; 00454 FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; 00455 FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; 00456 FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; 00457 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; 00458 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; 00459 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; 00460 FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; 00461 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; 00462 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; 00463 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; 00464 FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; 00465 } 00466 00467 /** 00468 * @brief Enables or disables the specified NAND Memory Bank. 00469 * @param FMC_Bank: specifies the FMC Bank to be used 00470 * This parameter can be one of the following values: 00471 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00472 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00473 * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. 00474 * @retval None 00475 */ 00476 void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) 00477 { 00478 assert_param(IS_FMC_NAND_BANK(FMC_Bank)); 00479 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00480 00481 if (NewState != DISABLE) 00482 { 00483 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ 00484 if(FMC_Bank == FMC_Bank2_NAND) 00485 { 00486 FMC_Bank2->PCR2 |= PCR_PBKEN_SET; 00487 } 00488 else 00489 { 00490 FMC_Bank3->PCR3 |= PCR_PBKEN_SET; 00491 } 00492 } 00493 else 00494 { 00495 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ 00496 if(FMC_Bank == FMC_Bank2_NAND) 00497 { 00498 FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; 00499 } 00500 else 00501 { 00502 FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; 00503 } 00504 } 00505 } 00506 /** 00507 * @brief Enables or disables the FMC NAND ECC feature. 00508 * @param FMC_Bank: specifies the FMC Bank to be used 00509 * This parameter can be one of the following values: 00510 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00511 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00512 * @param NewState: new state of the FMC NAND ECC feature. 00513 * This parameter can be: ENABLE or DISABLE. 00514 * @retval None 00515 */ 00516 void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) 00517 { 00518 assert_param(IS_FMC_NAND_BANK(FMC_Bank)); 00519 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00520 00521 if (NewState != DISABLE) 00522 { 00523 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ 00524 if(FMC_Bank == FMC_Bank2_NAND) 00525 { 00526 FMC_Bank2->PCR2 |= PCR_ECCEN_SET; 00527 } 00528 else 00529 { 00530 FMC_Bank3->PCR3 |= PCR_ECCEN_SET; 00531 } 00532 } 00533 else 00534 { 00535 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ 00536 if(FMC_Bank == FMC_Bank2_NAND) 00537 { 00538 FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; 00539 } 00540 else 00541 { 00542 FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; 00543 } 00544 } 00545 } 00546 00547 /** 00548 * @brief Returns the error correction code register value. 00549 * @param FMC_Bank: specifies the FMC Bank to be used 00550 * This parameter can be one of the following values: 00551 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00552 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00553 * @retval The Error Correction Code (ECC) value. 00554 */ 00555 uint32_t FMC_GetECC(uint32_t FMC_Bank) 00556 { 00557 uint32_t eccval = 0x00000000; 00558 00559 if(FMC_Bank == FMC_Bank2_NAND) 00560 { 00561 /* Get the ECCR2 register value */ 00562 eccval = FMC_Bank2->ECCR2; 00563 } 00564 else 00565 { 00566 /* Get the ECCR3 register value */ 00567 eccval = FMC_Bank3->ECCR3; 00568 } 00569 /* Return the error correction code value */ 00570 return(eccval); 00571 } 00572 /** 00573 * @} 00574 */ 00575 00576 /** @defgroup FMC_Group3 PCCARD Controller functions 00577 * @brief PCCARD Controller functions 00578 * 00579 @verbatim 00580 =============================================================================== 00581 ##### PCCARD Controller functions ##### 00582 =============================================================================== 00583 00584 [..] he following sequence should be followed to configure the FMC to interface 00585 with 16-bit PC Card compatible memory connected to the PCCARD Bank: 00586 00587 (#) Enable the clock for the FMC and associated GPIOs using the following functions: 00588 (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); 00589 (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); 00590 00591 (#) FMC pins configuration 00592 (++) Connect the involved FMC pins to AF12 using the following function 00593 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); 00594 (++) Configure these FMC pins in alternate function mode by calling the function 00595 GPIO_Init(); 00596 00597 (#) Declare a FMC_PCCARDInitTypeDef structure, for example: 00598 FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; 00599 and fill the FMC_PCCARDInitStructure variable with the allowed values of 00600 the structure member. 00601 00602 (#) Initialize the PCCARD Controller by calling the function 00603 FMC_PCCARDInit(&FMC_PCCARDInitStructure); 00604 00605 (#) Then enable the PCCARD Bank: 00606 FMC_PCCARDCmd(ENABLE); 00607 00608 (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. 00609 00610 @endverbatim 00611 * @{ 00612 */ 00613 00614 /** 00615 * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. 00616 * @param None 00617 * @retval None 00618 */ 00619 void FMC_PCCARDDeInit(void) 00620 { 00621 /* Set the FMC_Bank4 registers to their reset values */ 00622 FMC_Bank4->PCR4 = 0x00000018; 00623 FMC_Bank4->SR4 = 0x00000000; 00624 FMC_Bank4->PMEM4 = 0xFCFCFCFC; 00625 FMC_Bank4->PATT4 = 0xFCFCFCFC; 00626 FMC_Bank4->PIO4 = 0xFCFCFCFC; 00627 } 00628 00629 /** 00630 * @brief Initializes the FMC PCCARD Bank according to the specified parameters 00631 * in the FMC_PCCARDInitStruct. 00632 * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure 00633 * that contains the configuration information for the FMC PCCARD Bank. 00634 * @retval None 00635 */ 00636 void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) 00637 { 00638 /* Check the parameters */ 00639 assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); 00640 assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); 00641 assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); 00642 00643 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); 00644 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); 00645 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); 00646 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); 00647 00648 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); 00649 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); 00650 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); 00651 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); 00652 assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); 00653 assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); 00654 assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); 00655 assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); 00656 00657 /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ 00658 FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | 00659 FMC_NAND_MemoryDataWidth_16b | 00660 (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | 00661 (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); 00662 00663 /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ 00664 FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | 00665 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | 00666 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| 00667 (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); 00668 00669 /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ 00670 FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | 00671 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | 00672 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| 00673 (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); 00674 00675 /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ 00676 FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | 00677 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | 00678 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| 00679 (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); 00680 } 00681 00682 /** 00683 * @brief Fills each FMC_PCCARDInitStruct member with its default value. 00684 * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure 00685 * which will be initialized. 00686 * @retval None 00687 */ 00688 void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) 00689 { 00690 /* Reset PCCARD Init structure parameters values */ 00691 FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; 00692 FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; 00693 FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; 00694 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; 00695 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; 00696 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; 00697 FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; 00698 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; 00699 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; 00700 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; 00701 FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; 00702 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; 00703 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; 00704 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; 00705 FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; 00706 } 00707 00708 /** 00709 * @brief Enables or disables the PCCARD Memory Bank. 00710 * @param NewState: new state of the PCCARD Memory Bank. 00711 * This parameter can be: ENABLE or DISABLE. 00712 * @retval None 00713 */ 00714 void FMC_PCCARDCmd(FunctionalState NewState) 00715 { 00716 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00717 00718 if (NewState != DISABLE) 00719 { 00720 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ 00721 FMC_Bank4->PCR4 |= PCR_PBKEN_SET; 00722 } 00723 else 00724 { 00725 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ 00726 FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; 00727 } 00728 } 00729 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup FMC_Group4 Interrupts and flags management functions 00735 * @brief Interrupts and flags management functions 00736 * 00737 @verbatim 00738 =============================================================================== 00739 ##### Interrupts and flags management functions ##### 00740 =============================================================================== 00741 00742 @endverbatim 00743 * @{ 00744 */ 00745 00746 /** 00747 * @brief Enables or disables the specified FMC interrupts. 00748 * @param FMC_Bank: specifies the FMC Bank to be used 00749 * This parameter can be one of the following values: 00750 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00751 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00752 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD 00753 * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM 00754 * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM 00755 * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. 00756 * This parameter can be any combination of the following values: 00757 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. 00758 * @arg FMC_IT_Level: Level edge detection interrupt. 00759 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. 00760 * @param NewState: new state of the specified FMC interrupts. 00761 * This parameter can be: ENABLE or DISABLE. 00762 * @retval None 00763 */ 00764 void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) 00765 { 00766 assert_param(IS_FMC_IT_BANK(FMC_Bank)); 00767 assert_param(IS_FMC_IT(FMC_IT)); 00768 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00769 00770 if (NewState != DISABLE) 00771 { 00772 /* Enable the selected FMC_Bank2 interrupts */ 00773 if(FMC_Bank == FMC_Bank2_NAND) 00774 { 00775 FMC_Bank2->SR2 |= FMC_IT; 00776 } 00777 /* Enable the selected FMC_Bank3 interrupts */ 00778 else if (FMC_Bank == FMC_Bank3_NAND) 00779 { 00780 FMC_Bank3->SR3 |= FMC_IT; 00781 } 00782 /* Enable the selected FMC_Bank4 interrupts */ 00783 else 00784 { 00785 FMC_Bank4->SR4 |= FMC_IT; 00786 } 00787 } 00788 else 00789 { 00790 /* Disable the selected FMC_Bank2 interrupts */ 00791 if(FMC_Bank == FMC_Bank2_NAND) 00792 { 00793 FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; 00794 } 00795 /* Disable the selected FMC_Bank3 interrupts */ 00796 else if (FMC_Bank == FMC_Bank3_NAND) 00797 { 00798 FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; 00799 } 00800 /* Disable the selected FMC_Bank4 interrupts */ 00801 else 00802 { 00803 FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; 00804 } 00805 } 00806 } 00807 00808 /** 00809 * @brief Checks whether the specified FMC flag is set or not. 00810 * @param FMC_Bank: specifies the FMC Bank to be used 00811 * This parameter can be one of the following values: 00812 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00813 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00814 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD 00815 * @param FMC_FLAG: specifies the flag to check. 00816 * This parameter can be one of the following values: 00817 * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. 00818 * @arg FMC_FLAG_Level: Level detection Flag. 00819 * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. 00820 * @arg FMC_FLAG_FEMPT: Fifo empty Flag. 00821 * @retval The new state of FMC_FLAG (SET or RESET). 00822 */ 00823 FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) 00824 { 00825 FlagStatus bitstatus = RESET; 00826 uint32_t tmpsr = 0x00000000; 00827 00828 /* Check the parameters */ 00829 assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); 00830 assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); 00831 00832 if(FMC_Bank == FMC_Bank2_NAND) 00833 { 00834 tmpsr = FMC_Bank2->SR2; 00835 } 00836 else if(FMC_Bank == FMC_Bank3_NAND) 00837 { 00838 tmpsr = FMC_Bank3->SR3; 00839 } 00840 else 00841 { 00842 tmpsr = FMC_Bank4->SR4; 00843 } 00844 00845 /* Get the flag status */ 00846 if ((tmpsr & FMC_FLAG) != FMC_FLAG ) 00847 { 00848 bitstatus = RESET; 00849 } 00850 else 00851 { 00852 bitstatus = SET; 00853 } 00854 /* Return the flag status */ 00855 return bitstatus; 00856 } 00857 00858 /** 00859 * @brief Clears the FMC's pending flags. 00860 * @param FMC_Bank: specifies the FMC Bank to be used 00861 * This parameter can be one of the following values: 00862 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00863 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00864 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD 00865 * @param FMC_FLAG: specifies the flag to clear. 00866 * This parameter can be any combination of the following values: 00867 * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. 00868 * @arg FMC_FLAG_Level: Level detection Flag. 00869 * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. 00870 * @retval None 00871 */ 00872 void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) 00873 { 00874 /* Check the parameters */ 00875 assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); 00876 assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; 00877 00878 if(FMC_Bank == FMC_Bank2_NAND) 00879 { 00880 FMC_Bank2->SR2 &= (~FMC_FLAG); 00881 } 00882 else if(FMC_Bank == FMC_Bank3_NAND) 00883 { 00884 FMC_Bank3->SR3 &= (~FMC_FLAG); 00885 } 00886 /* FMC_Bank4 PCCARD */ 00887 else 00888 { 00889 FMC_Bank4->SR4 &= (~FMC_FLAG); 00890 } 00891 00892 } 00893 00894 /** 00895 * @brief Checks whether the specified FMC interrupt has occurred or not. 00896 * @param FMC_Bank: specifies the FMC Bank to be used 00897 * This parameter can be one of the following values: 00898 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00899 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00900 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD 00901 * @param FMC_IT: specifies the FMC interrupt source to check. 00902 * This parameter can be one of the following values: 00903 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. 00904 * @arg FMC_IT_Level: Level edge detection interrupt. 00905 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. 00906 * @retval The new state of FMC_IT (SET or RESET). 00907 */ 00908 ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) 00909 { 00910 ITStatus bitstatus = RESET; 00911 uint32_t tmpsr = 0; 00912 uint32_t itstatus = 0; 00913 uint32_t itenable = 0; 00914 00915 /* Check the parameters */ 00916 assert_param(IS_FMC_IT_BANK(FMC_Bank)); 00917 assert_param(IS_FMC_GET_IT(FMC_IT)); 00918 00919 if(FMC_Bank == FMC_Bank2_NAND) 00920 { 00921 tmpsr = FMC_Bank2->SR2; 00922 } 00923 else if(FMC_Bank == FMC_Bank3_NAND) 00924 { 00925 tmpsr = FMC_Bank3->SR3; 00926 } 00927 /* FMC_Bank4 PCCARD */ 00928 else 00929 { 00930 tmpsr = FMC_Bank4->SR4; 00931 } 00932 00933 /* get the IT enable bit status*/ 00934 itenable = tmpsr & FMC_IT; 00935 00936 /* get the corresponding IT Flag status*/ 00937 itstatus = tmpsr & (FMC_IT >> 3); 00938 00939 if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) 00940 { 00941 bitstatus = SET; 00942 } 00943 else 00944 { 00945 bitstatus = RESET; 00946 } 00947 return bitstatus; 00948 } 00949 00950 /** 00951 * @brief Clears the FMC's interrupt pending bits. 00952 * @param FMC_Bank: specifies the FMC Bank to be used 00953 * This parameter can be one of the following values: 00954 * @arg FMC_Bank2_NAND: FMC Bank2 NAND 00955 * @arg FMC_Bank3_NAND: FMC Bank3 NAND 00956 * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD 00957 * @param FMC_IT: specifies the interrupt pending bit to clear. 00958 * This parameter can be any combination of the following values: 00959 * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. 00960 * @arg FMC_IT_Level: Level edge detection interrupt. 00961 * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. 00962 * @retval None 00963 */ 00964 void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) 00965 { 00966 /* Check the parameters */ 00967 assert_param(IS_FMC_IT_BANK(FMC_Bank)); 00968 assert_param(IS_FMC_IT(FMC_IT)); 00969 00970 if(FMC_Bank == FMC_Bank2_NAND) 00971 { 00972 FMC_Bank2->SR2 &= ~(FMC_IT >> 3); 00973 } 00974 else if(FMC_Bank == FMC_Bank3_NAND) 00975 { 00976 FMC_Bank3->SR3 &= ~(FMC_IT >> 3); 00977 } 00978 /* FMC_Bank4 PCCARD */ 00979 else 00980 { 00981 FMC_Bank4->SR4 &= ~(FMC_IT >> 3); 00982 } 00983 } 00984 00985 /** 00986 * @} 00987 */ 00988 00989 /** 00990 * @} 00991 */ 00992 00993 /** 00994 * @} 00995 */ 00996 00997 /** 00998 * @} 00999 */ 01000 01001 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Generated on Tue Jul 12 2022 17:34:44 by
1.7.2