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STM32F3-Discovery
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stm32f30x.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f30x.h 00004 * @author MCD Application Team 00005 * @version V1.2.2 00006 * @date 27-February-2015 00007 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 00008 * This file contains all the peripheral registers definitions, bits 00009 * definitions and memory mapping for STM32F30x devices. 00010 * 00011 * The file is the unique include file that the application programmer 00012 * is using in the C source code, usually in main.c. This file contains: 00013 * - Configuration section that allows to select: 00014 * - The device used in the target application 00015 * - To use or not the peripheral�s drivers in application code(i.e. 00016 * code will be based on direct access to peripheral�s registers 00017 * rather than drivers API), this option is controlled by 00018 * "#define USE_STDPERIPH_DRIVER" 00019 * - To change few application-specific parameters such as the HSE 00020 * crystal frequency 00021 * - Data structures and the address mapping for all peripherals 00022 * - Peripheral registers declarations and bits definition 00023 * - Macros to access peripheral registers hardware 00024 * 00025 ****************************************************************************** 00026 * @attention 00027 * 00028 * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> 00029 * 00030 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00031 * You may not use this file except in compliance with the License. 00032 * You may obtain a copy of the License at: 00033 * 00034 * http://www.st.com/software_license_agreement_liberty_v2 00035 * 00036 * Unless required by applicable law or agreed to in writing, software 00037 * distributed under the License is distributed on an "AS IS" BASIS, 00038 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00039 * See the License for the specific language governing permissions and 00040 * limitations under the License. 00041 * 00042 ****************************************************************************** 00043 */ 00044 00045 /** @addtogroup CMSIS 00046 * @{ 00047 */ 00048 00049 /** @addtogroup stm32f30x 00050 * @{ 00051 */ 00052 00053 #ifndef __STM32F30x_H 00054 #define __STM32F30x_H 00055 00056 #ifdef __cplusplus 00057 extern "C" { 00058 #endif /* __cplusplus */ 00059 00060 /** @addtogroup Library_configuration_section 00061 * @{ 00062 */ 00063 00064 /* Uncomment the line below according to the target STM32 device used in your 00065 application 00066 */ 00067 00068 /* Old STM32F30X definition, maintained for legacy purpose */ 00069 #if defined(STM32F30X) 00070 #define STM32F303xC 00071 #endif /* STM32F30X */ 00072 00073 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8) && !defined (STM32F303xE) 00074 #define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB, STM32F303VC 00075 STM32F302CB, STM32F302CC, STM32F302RC, STM32F302RB, STM32F302VC, STM32F302VB, 00076 STM32F358CC, STM32F358RC and STM32F358VC Devices */ 00077 /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334K4, STM32F334C6, STM32F334R6, STM32F334K6, STM32F334C8, STM32F334R8, STM32F334K8, 00078 STM32F303K8, STM32F303K6, STM32F303C8, STM32F303C6, STM32F303R8, STM32F303R6 and STM32F328C8 Devices */ 00079 /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8, STM32F302R6, STM32F302R8, 00080 STM32F301K8, STM32F301C8, STM32F301R8, STM32F301K6, STM32F301C6, STM32F301R6, STM32F313K8 and STM32F318C8 Devices */ 00081 /* #define STM32F303xE */ /*!< STM32F303CE, STM32F303CD, STM32F303RE, STM32F303RD, STM32F303VE, STM32F303VD, STM32F303ZE, 00082 STM32F303ZD, STM32F302CE, STM32F302CD, STM32F302RE, STM32F302RD, STM32F302VE, STM32F302ZE, 00083 STM32F302ZD and STM32F398VE Devices */ 00084 #endif /* STM32F303xC || STM32F334x8 || STM32F302x8 || STM32F303xE */ 00085 00086 00087 /* Tip: To avoid modifying this file each time you need to switch between these 00088 devices, you can define the device in your toolchain compiler preprocessor. 00089 */ 00090 00091 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8) && !defined (STM32F303xE) 00092 #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)" 00093 #endif 00094 00095 #if !defined (USE_STDPERIPH_DRIVER) 00096 /** 00097 * @brief Comment the line below if you will not use the peripherals drivers. 00098 In this case, these drivers will not be included and the application code will 00099 be based on direct access to peripherals registers 00100 */ 00101 #define USE_STDPERIPH_DRIVER 00102 #endif /* USE_STDPERIPH_DRIVER */ 00103 00104 /** 00105 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 00106 used in your application 00107 00108 Tip: To avoid modifying this file each time you need to use different HSE, you 00109 can define the HSE value in your toolchain compiler preprocessor. 00110 */ 00111 #if !defined (HSE_VALUE) 00112 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ 00113 #endif /* HSE_VALUE */ 00114 00115 /** 00116 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 00117 Timeout value 00118 */ 00119 #if !defined (HSE_STARTUP_TIMEOUT) 00120 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ 00121 #endif /* HSE_STARTUP_TIMEOUT */ 00122 00123 /** 00124 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 00125 Timeout value 00126 */ 00127 #if !defined (HSI_STARTUP_TIMEOUT) 00128 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ 00129 #endif /* HSI_STARTUP_TIMEOUT */ 00130 00131 #if !defined (HSI_VALUE) 00132 #define HSI_VALUE ((uint32_t)8000000) 00133 #endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz. 00134 The real value may vary depending on the variations 00135 in voltage and temperature. */ 00136 #if !defined (LSI_VALUE) 00137 #define LSI_VALUE ((uint32_t)40000) 00138 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 00139 The real value may vary depending on the variations 00140 in voltage and temperature. */ 00141 #if !defined (LSE_VALUE) 00142 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ 00143 #endif /* LSE_VALUE */ 00144 00145 00146 /** 00147 * @brief STM32F30x Standard Peripherals Library version number V1.2.2 00148 */ 00149 #define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 00150 #define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ 00151 #define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ 00152 #define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 00153 #define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\ 00154 |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\ 00155 |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\ 00156 |(__STM32F30X_STDPERIPH_VERSION_RC)) 00157 00158 /** 00159 * @} 00160 */ 00161 00162 /** @addtogroup Configuration_section_for_CMSIS 00163 * @{ 00164 */ 00165 00166 /** 00167 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 00168 */ 00169 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ 00170 #define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */ 00171 #define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */ 00172 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00173 #define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */ 00174 00175 00176 /** 00177 * @brief STM32F30X Interrupt Number Definition, according to the selected device 00178 * in @ref Library_configuration_section 00179 */ 00180 typedef enum IRQn 00181 { 00182 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 00183 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00184 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 00185 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 00186 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 00187 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 00188 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 00189 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 00190 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 00191 /****** STM32 specific Interrupt Numbers **********************************************************************/ 00192 #ifdef STM32F303xC 00193 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 00194 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 00195 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ 00196 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ 00197 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 00198 RCC_IRQn = 5, /*!< RCC global Interrupt */ 00199 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 00200 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 00201 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ 00202 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 00203 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 00204 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 00205 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 00206 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 00207 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 00208 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 00209 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 00210 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 00211 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ 00212 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ 00213 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ 00214 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 00215 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 00216 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 00217 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 00218 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 00219 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 00220 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 00221 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 00222 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 00223 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 00224 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 00225 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 00226 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 00227 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 00228 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 00229 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 00230 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 00231 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 00232 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 00233 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 00234 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 00235 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ 00236 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ 00237 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ 00238 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ 00239 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ 00240 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ 00241 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 00242 UART4_IRQn = 52, /*!< UART4 global Interrupt */ 00243 UART5_IRQn = 53, /*!< UART5 global Interrupt */ 00244 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ 00245 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ 00246 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ 00247 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ 00248 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ 00249 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ 00250 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ 00251 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ 00252 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ 00253 COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ 00254 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ 00255 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ 00256 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ 00257 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ 00258 FPU_IRQn = 81 /*!< Floating point Interrupt */ 00259 #endif /* STM32F303xC */ 00260 #ifdef STM32F334x8 00261 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 00262 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 00263 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ 00264 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ 00265 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 00266 RCC_IRQn = 5, /*!< RCC global Interrupt */ 00267 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 00268 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 00269 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ 00270 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 00271 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 00272 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 00273 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 00274 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 00275 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 00276 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 00277 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 00278 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 00279 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ 00280 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ 00281 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ 00282 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 00283 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 00284 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 00285 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 00286 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 00287 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 00288 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 00289 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 00290 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 00291 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 00292 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 00293 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 00294 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 00295 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 00296 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 00297 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 00298 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 00299 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error interrupts */ 00300 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 underrun error Interrupt */ 00301 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */ 00302 COMP4_6_IRQn = 65, /*!< COMP6 and COMP4 global Interrupt */ 00303 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ 00304 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ 00305 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ 00306 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ 00307 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ 00308 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ 00309 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ 00310 FPU_IRQn = 81 /*!< Floating point Interrupt */ 00311 #endif /* STM32F334x8 */ 00312 #ifdef STM32F302x8 00313 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 00314 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 00315 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ 00316 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 20 */ 00317 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 00318 RCC_IRQn = 5, /*!< RCC global Interrupt */ 00319 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 00320 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 00321 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ 00322 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 00323 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 00324 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 00325 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 00326 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 00327 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 00328 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 00329 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 00330 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 00331 ADC1_IRQn = 18, /*!< ADC1 Interrupts */ 00332 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ 00333 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ 00334 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 00335 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 00336 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 00337 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 00338 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 00339 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 00340 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 00341 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 00342 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 00343 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 00344 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 00345 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 00346 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 00347 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 00348 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 00349 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 00350 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 00351 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 00352 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ 00353 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 00354 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ 00355 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */ 00356 COMP4_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ 00357 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ 00358 I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt */ 00359 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */ 00360 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ 00361 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ 00362 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ 00363 FPU_IRQn = 81 /*!< Floating point Interrupt */ 00364 #endif /* STM32F302x8 */ 00365 #ifdef STM32F303xE 00366 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 00367 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 00368 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */ 00369 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */ 00370 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 00371 RCC_IRQn = 5, /*!< RCC global Interrupt */ 00372 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 00373 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 00374 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */ 00375 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 00376 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 00377 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ 00378 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ 00379 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ 00380 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ 00381 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ 00382 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ 00383 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ 00384 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ 00385 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ 00386 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ 00387 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 00388 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 00389 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 00390 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 00391 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 00392 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 00393 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 00394 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 00395 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 00396 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 00397 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 00398 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 00399 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 00400 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 00401 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 00402 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 00403 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 00404 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 00405 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 00406 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 00407 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ 00408 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */ 00409 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ 00410 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ 00411 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ 00412 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ 00413 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ 00414 FMC_IRQn = 48, /*!< FMC global Interrupt */ 00415 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ 00416 UART4_IRQn = 52, /*!< UART4 global Interrupt */ 00417 UART5_IRQn = 53, /*!< UART5 global Interrupt */ 00418 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ 00419 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ 00420 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ 00421 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ 00422 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ 00423 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ 00424 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ 00425 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */ 00426 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */ 00427 COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */ 00428 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */ 00429 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ 00430 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ 00431 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */ 00432 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */ 00433 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */ 00434 TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */ 00435 TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */ 00436 TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */ 00437 TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */ 00438 FPU_IRQn = 81, /*!< Floating point Interrupt */ 00439 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ 00440 #endif /* STM32F303xE */ 00441 } IRQn_Type; 00442 00443 /** 00444 * @} 00445 */ 00446 00447 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 00448 #include "system_stm32f30x.h" /* STM32F30x System Header */ 00449 #include <stdint.h> 00450 00451 /** @addtogroup Exported_types 00452 * @{ 00453 */ 00454 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ 00455 typedef int32_t s32; 00456 typedef int16_t s16; 00457 typedef int8_t s8; 00458 00459 typedef const int32_t sc32; /*!< Read Only */ 00460 typedef const int16_t sc16; /*!< Read Only */ 00461 typedef const int8_t sc8; /*!< Read Only */ 00462 00463 typedef __IO int32_t vs32; 00464 typedef __IO int16_t vs16; 00465 typedef __IO int8_t vs8; 00466 00467 typedef __I int32_t vsc32; /*!< Read Only */ 00468 typedef __I int16_t vsc16; /*!< Read Only */ 00469 typedef __I int8_t vsc8; /*!< Read Only */ 00470 00471 //typedef uint32_t u32; 00472 typedef uint16_t u16; 00473 typedef uint8_t u8; 00474 00475 typedef const uint32_t uc32; /*!< Read Only */ 00476 typedef const uint16_t uc16; /*!< Read Only */ 00477 typedef const uint8_t uc8; /*!< Read Only */ 00478 00479 typedef __IO uint32_t vu32; 00480 typedef __IO uint16_t vu16; 00481 typedef __IO uint8_t vu8; 00482 00483 typedef __I uint32_t vuc32; /*!< Read Only */ 00484 typedef __I uint16_t vuc16; /*!< Read Only */ 00485 typedef __I uint8_t vuc8; /*!< Read Only */ 00486 00487 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 00488 00489 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00490 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00491 00492 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00493 00494 /** 00495 * @} 00496 */ 00497 00498 /** @addtogroup Peripheral_registers_structures 00499 * @{ 00500 */ 00501 00502 /** 00503 * @brief Analog to Digital Converter 00504 */ 00505 00506 typedef struct 00507 { 00508 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ 00509 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ 00510 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ 00511 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ 00512 uint32_t RESERVED0; /*!< Reserved, 0x010 */ 00513 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ 00514 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ 00515 uint32_t RESERVED1; /*!< Reserved, 0x01C */ 00516 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ 00517 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ 00518 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ 00519 uint32_t RESERVED2; /*!< Reserved, 0x02C */ 00520 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ 00521 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ 00522 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ 00523 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ 00524 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ 00525 uint32_t RESERVED3; /*!< Reserved, 0x044 */ 00526 uint32_t RESERVED4; /*!< Reserved, 0x048 */ 00527 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ 00528 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ 00529 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ 00530 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ 00531 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ 00532 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ 00533 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ 00534 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ 00535 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ 00536 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ 00537 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ 00538 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ 00539 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ 00540 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ 00541 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ 00542 uint32_t RESERVED9; /*!< Reserved, 0x0AC */ 00543 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ 00544 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ 00545 00546 } ADC_TypeDef; 00547 00548 typedef struct 00549 { 00550 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ 00551 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ 00552 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ 00553 __IO uint32_t CDR; /*!< ADC common regular data register for dual 00554 modes, Address offset: ADC1/3 base address + 0x30A */ 00555 } ADC_Common_TypeDef; 00556 00557 00558 /** 00559 * @brief Controller Area Network TxMailBox 00560 */ 00561 typedef struct 00562 { 00563 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 00564 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 00565 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 00566 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 00567 } CAN_TxMailBox_TypeDef; 00568 00569 /** 00570 * @brief Controller Area Network FIFOMailBox 00571 */ 00572 typedef struct 00573 { 00574 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 00575 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 00576 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 00577 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 00578 } CAN_FIFOMailBox_TypeDef; 00579 00580 /** 00581 * @brief Controller Area Network FilterRegister 00582 */ 00583 typedef struct 00584 { 00585 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 00586 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 00587 } CAN_FilterRegister_TypeDef; 00588 00589 /** 00590 * @brief Controller Area Network 00591 */ 00592 typedef struct 00593 { 00594 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 00595 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 00596 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 00597 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 00598 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 00599 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 00600 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 00601 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 00602 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 00603 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 00604 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 00605 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 00606 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 00607 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 00608 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 00609 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 00610 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 00611 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 00612 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 00613 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 00614 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 00615 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 00616 } CAN_TypeDef; 00617 00618 00619 /** 00620 * @brief Analog Comparators 00621 */ 00622 00623 typedef struct 00624 { 00625 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ 00626 } COMP_TypeDef; 00627 00628 /** 00629 * @brief CRC calculation unit 00630 */ 00631 00632 typedef struct 00633 { 00634 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 00635 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 00636 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 00637 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 00638 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 00639 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 00640 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 00641 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 00642 } CRC_TypeDef; 00643 00644 /** 00645 * @brief Digital to Analog Converter 00646 */ 00647 00648 typedef struct 00649 { 00650 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 00651 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 00652 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 00653 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 00654 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 00655 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 00656 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 00657 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 00658 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 00659 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 00660 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 00661 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 00662 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 00663 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 00664 } DAC_TypeDef; 00665 00666 /** 00667 * @brief Debug MCU 00668 */ 00669 00670 typedef struct 00671 { 00672 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 00673 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 00674 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 00675 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 00676 }DBGMCU_TypeDef; 00677 00678 /** 00679 * @brief DMA Controller 00680 */ 00681 00682 typedef struct 00683 { 00684 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 00685 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 00686 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 00687 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 00688 } DMA_Channel_TypeDef; 00689 00690 typedef struct 00691 { 00692 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 00693 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ 00694 } DMA_TypeDef; 00695 00696 /** 00697 * @brief External Interrupt/Event Controller 00698 */ 00699 00700 typedef struct 00701 { 00702 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ 00703 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ 00704 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ 00705 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ 00706 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ 00707 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ 00708 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 00709 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 00710 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ 00711 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ 00712 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ 00713 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ 00714 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ 00715 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ 00716 }EXTI_TypeDef; 00717 00718 /** 00719 * @brief FLASH Registers 00720 */ 00721 00722 typedef struct 00723 { 00724 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ 00725 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ 00726 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ 00727 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ 00728 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ 00729 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ 00730 uint32_t RESERVED; /*!< Reserved, 0x18 */ 00731 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ 00732 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ 00733 00734 } FLASH_TypeDef; 00735 00736 /** 00737 * @brief Flexible Memory Controller 00738 */ 00739 00740 typedef struct 00741 { 00742 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ 00743 } FMC_Bank1_TypeDef; 00744 00745 /** 00746 * @brief Flexible Memory Controller Bank1E 00747 */ 00748 00749 typedef struct 00750 { 00751 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ 00752 } FMC_Bank1E_TypeDef; 00753 00754 /** 00755 * @brief Flexible Memory Controller Bank2 00756 */ 00757 00758 typedef struct 00759 { 00760 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ 00761 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ 00762 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ 00763 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ 00764 uint32_t RESERVED0; /*!< Reserved, 0x70 */ 00765 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ 00766 } FMC_Bank2_TypeDef; 00767 00768 /** 00769 * @brief Flexible Memory Controller Bank3 00770 */ 00771 00772 typedef struct 00773 { 00774 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ 00775 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ 00776 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ 00777 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ 00778 uint32_t RESERVED0; /*!< Reserved, 0x90 */ 00779 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ 00780 } FMC_Bank3_TypeDef; 00781 00782 /** 00783 * @brief Flexible Memory Controller Bank4 00784 */ 00785 00786 typedef struct 00787 { 00788 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ 00789 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ 00790 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ 00791 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ 00792 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ 00793 } FMC_Bank4_TypeDef; 00794 00795 /** 00796 * @brief Option Bytes Registers 00797 */ 00798 typedef struct 00799 { 00800 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ 00801 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ 00802 uint16_t RESERVED0; /*!< Reserved, 0x04 */ 00803 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 00804 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ 00805 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ 00806 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */ 00807 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */ 00808 } OB_TypeDef; 00809 00810 /** 00811 * @brief General Purpose I/O 00812 */ 00813 00814 typedef struct 00815 { 00816 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 00817 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 00818 uint16_t RESERVED0; /*!< Reserved, 0x06 */ 00819 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 00820 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 00821 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 00822 uint16_t RESERVED1; /*!< Reserved, 0x12 */ 00823 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 00824 uint16_t RESERVED2; /*!< Reserved, 0x16 */ 00825 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 00826 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 00827 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 00828 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 00829 uint16_t RESERVED3; /*!< Reserved, 0x2A */ 00830 }GPIO_TypeDef; 00831 00832 /** 00833 * @brief High resolution Timer (HRTIM) 00834 */ 00835 /* HRTIM master definition */ 00836 typedef struct 00837 { 00838 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ 00839 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ 00840 __IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */ 00841 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ 00842 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ 00843 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ 00844 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ 00845 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ 00846 uint32_t RESERVED0; /*!< Reserved, 0x20 */ 00847 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ 00848 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ 00849 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ 00850 }HRTIM_Master_TypeDef; 00851 00852 /* HRTIM slave definition */ 00853 typedef struct 00854 { 00855 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ 00856 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ 00857 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ 00858 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ 00859 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ 00860 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ 00861 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ 00862 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ 00863 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ 00864 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ 00865 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ 00866 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ 00867 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ 00868 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ 00869 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ 00870 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ 00871 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ 00872 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ 00873 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ 00874 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ 00875 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ 00876 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ 00877 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ 00878 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ 00879 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ 00880 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ 00881 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ 00882 uint32_t RESERVED0[5];/*!< Reserved, */ 00883 }HRTIM_Timerx_TypeDef; 00884 00885 /* HRTIM common register definition */ 00886 typedef struct 00887 { 00888 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ 00889 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ 00890 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ 00891 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ 00892 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ 00893 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ 00894 __IO uint32_t DISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ 00895 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ 00896 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ 00897 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ 00898 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ 00899 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ 00900 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ 00901 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ 00902 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ 00903 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ 00904 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ 00905 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ 00906 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ 00907 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ 00908 __IO uint32_t FLTINxR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ 00909 __IO uint32_t FLTINxR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ 00910 __IO uint32_t BDMUPDR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ 00911 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ 00912 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ 00913 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ 00914 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ 00915 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ 00916 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ 00917 }HRTIM_Common_TypeDef; 00918 00919 /* HRTIM register definition */ 00920 typedef struct { 00921 HRTIM_Master_TypeDef HRTIM_MASTER; 00922 uint32_t RESERVED0[20]; 00923 HRTIM_Timerx_TypeDef HRTIM_TIMERx[5]; 00924 uint32_t RESERVED1[32]; 00925 HRTIM_Common_TypeDef HRTIM_COMMON; 00926 }HRTIM_TypeDef; 00927 00928 /** 00929 * @brief Operational Amplifier (OPAMP) 00930 */ 00931 00932 typedef struct 00933 { 00934 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ 00935 } OPAMP_TypeDef; 00936 00937 00938 /** 00939 * @brief System configuration controller 00940 */ 00941 00942 typedef struct 00943 { 00944 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 00945 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ 00946 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ 00947 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 00948 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */ 00949 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */ 00950 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */ 00951 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */ 00952 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */ 00953 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */ 00954 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */ 00955 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */ 00956 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */ 00957 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */ 00958 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */ 00959 __IO uint32_t CFGR4; /*!< SYSCFG configuration register 4, Address offset: 0x48 */ 00960 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */ 00961 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */ 00962 } SYSCFG_TypeDef; 00963 00964 /** 00965 * @brief Inter-integrated Circuit Interface 00966 */ 00967 00968 typedef struct 00969 { 00970 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 00971 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 00972 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 00973 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 00974 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 00975 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 00976 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 00977 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 00978 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 00979 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 00980 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 00981 }I2C_TypeDef; 00982 00983 /** 00984 * @brief Independent WATCHDOG 00985 */ 00986 00987 typedef struct 00988 { 00989 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 00990 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 00991 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 00992 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 00993 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 00994 } IWDG_TypeDef; 00995 00996 /** 00997 * @brief Power Control 00998 */ 00999 01000 typedef struct 01001 { 01002 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 01003 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 01004 } PWR_TypeDef; 01005 01006 /** 01007 * @brief Reset and Clock Control 01008 */ 01009 typedef struct 01010 { 01011 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 01012 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 01013 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 01014 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 01015 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 01016 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 01017 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 01018 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 01019 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 01020 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 01021 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 01022 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 01023 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 01024 } RCC_TypeDef; 01025 01026 /** 01027 * @brief Real-Time Clock 01028 */ 01029 01030 typedef struct 01031 { 01032 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 01033 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 01034 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 01035 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 01036 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 01037 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 01038 uint32_t RESERVED0; /*!< Reserved, 0x18 */ 01039 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 01040 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 01041 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 01042 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 01043 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 01044 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 01045 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 01046 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 01047 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 01048 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 01049 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 01050 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 01051 uint32_t RESERVED7; /*!< Reserved, 0x4C */ 01052 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 01053 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 01054 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 01055 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 01056 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 01057 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ 01058 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ 01059 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ 01060 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ 01061 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ 01062 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ 01063 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ 01064 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ 01065 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ 01066 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ 01067 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ 01068 } RTC_TypeDef; 01069 01070 01071 /** 01072 * @brief Serial Peripheral Interface 01073 */ 01074 01075 typedef struct 01076 { 01077 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 01078 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01079 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 01080 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 01081 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ 01082 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 01083 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ 01084 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 01085 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 01086 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 01087 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 01088 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 01089 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 01090 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 01091 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 01092 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 01093 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 01094 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 01095 } SPI_TypeDef; 01096 01097 /** 01098 * @brief TIM 01099 */ 01100 typedef struct 01101 { 01102 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 01103 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 01104 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 01105 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ 01106 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 01107 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 01108 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 01109 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 01110 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 01111 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 01112 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 01113 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ 01114 uint16_t RESERVED9; /*!< Reserved, 0x2A */ 01115 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 01116 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 01117 uint16_t RESERVED10; /*!< Reserved, 0x32 */ 01118 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 01119 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 01120 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 01121 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 01122 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 01123 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 01124 uint16_t RESERVED12; /*!< Reserved, 0x4A */ 01125 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ 01126 uint16_t RESERVED13; /*!< Reserved, 0x4E */ 01127 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ 01128 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ 01129 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ 01130 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ 01131 } TIM_TypeDef; 01132 01133 01134 /** 01135 * @brief Touch Sensing Controller (TSC) 01136 */ 01137 typedef struct 01138 { 01139 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 01140 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 01141 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 01142 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 01143 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 01144 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 01145 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 01146 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 01147 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 01148 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 01149 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 01150 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 01151 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 01152 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 01153 } TSC_TypeDef; 01154 01155 /** 01156 * @brief Universal Synchronous Asynchronous Receiver Transmitter 01157 */ 01158 01159 typedef struct 01160 { 01161 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 01162 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 01163 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 01164 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 01165 uint16_t RESERVED1; /*!< Reserved, 0x0E */ 01166 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 01167 uint16_t RESERVED2; /*!< Reserved, 0x12 */ 01168 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 01169 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ 01170 uint16_t RESERVED3; /*!< Reserved, 0x1A */ 01171 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 01172 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 01173 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 01174 uint16_t RESERVED4; /*!< Reserved, 0x26 */ 01175 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 01176 uint16_t RESERVED5; /*!< Reserved, 0x2A */ 01177 } USART_TypeDef; 01178 01179 /** 01180 * @brief Window WATCHDOG 01181 */ 01182 typedef struct 01183 { 01184 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 01185 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 01186 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 01187 } WWDG_TypeDef; 01188 01189 01190 /** @addtogroup Peripheral_memory_map 01191 * @{ 01192 */ 01193 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ 01194 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(16 KB) base address in the alias region */ 01195 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ 01196 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ 01197 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ 01198 01199 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM base address in the bit-band region */ 01200 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ 01201 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ 01202 01203 /*!< Peripheral memory map */ 01204 #define APB1PERIPH_BASE PERIPH_BASE 01205 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) 01206 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) 01207 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) 01208 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000) 01209 01210 /*!< APB1 peripherals */ 01211 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) 01212 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) 01213 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800) 01214 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) 01215 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) 01216 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800) 01217 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) 01218 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) 01219 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400) 01220 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800) 01221 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00) 01222 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000) 01223 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400) 01224 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800) 01225 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00) 01226 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000) 01227 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) 01228 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800) 01229 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400) 01230 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000) 01231 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400) 01232 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800) 01233 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) 01234 #define DAC_BASE DAC1_BASE 01235 01236 /*!< APB2 peripherals */ 01237 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) 01238 #define COMP_BASE (APB2PERIPH_BASE + 0x0000001C) 01239 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C) 01240 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020) 01241 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024) 01242 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028) 01243 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C) 01244 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030) 01245 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034) 01246 #define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038) 01247 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038) 01248 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C) 01249 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040) 01250 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044) 01251 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) 01252 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00) 01253 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) 01254 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400) 01255 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800) 01256 #define SPI4_BASE (APB2PERIPH_BASE + 0x00003C00) 01257 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000) 01258 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400) 01259 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800) 01260 #define TIM20_BASE (APB2PERIPH_BASE + 0x00005000) 01261 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400) 01262 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080) 01263 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100) 01264 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180) 01265 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200) 01266 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280) 01267 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380) 01268 01269 /*!< AHB1 peripherals */ 01270 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000) 01271 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008) 01272 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C) 01273 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030) 01274 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044) 01275 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058) 01276 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C) 01277 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080) 01278 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400) 01279 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408) 01280 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C) 01281 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430) 01282 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444) 01283 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458) 01284 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000) 01285 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */ 01286 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ 01287 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000) 01288 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000) 01289 01290 /*!< AHB2 peripherals */ 01291 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) 01292 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) 01293 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) 01294 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) 01295 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) 01296 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) 01297 #define GPIOG_BASE (AHB2PERIPH_BASE + 0x00001800) 01298 #define GPIOH_BASE (AHB2PERIPH_BASE + 0x00001C00) 01299 01300 /*!< AHB3 peripherals */ 01301 #define ADC1_BASE (AHB3PERIPH_BASE + 0x0000) 01302 #define ADC2_BASE (AHB3PERIPH_BASE + 0x0100) 01303 #define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300) 01304 #define ADC3_BASE (AHB3PERIPH_BASE + 0x0400) 01305 #define ADC4_BASE (AHB3PERIPH_BASE + 0x0500) 01306 #define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700) 01307 01308 /*!< FMC Banks registers base address */ 01309 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) 01310 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) 01311 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) 01312 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) 01313 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) 01314 01315 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ 01316 /** 01317 * @} 01318 */ 01319 01320 /** @addtogroup Peripheral_declaration 01321 * @{ 01322 */ 01323 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 01324 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 01325 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 01326 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 01327 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 01328 #define RTC ((RTC_TypeDef *) RTC_BASE) 01329 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 01330 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 01331 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) 01332 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 01333 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 01334 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) 01335 #define USART2 ((USART_TypeDef *) USART2_BASE) 01336 #define USART3 ((USART_TypeDef *) USART3_BASE) 01337 #define UART4 ((USART_TypeDef *) UART4_BASE) 01338 #define UART5 ((USART_TypeDef *) UART5_BASE) 01339 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 01340 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 01341 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 01342 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 01343 #define PWR ((PWR_TypeDef *) PWR_BASE) 01344 #define DAC1 ((DAC_TypeDef *) DAC1_BASE) 01345 #define DAC2 ((DAC_TypeDef *) DAC2_BASE) 01346 #define DAC DAC1 01347 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 01348 #define COMP ((COMP_TypeDef *) COMP_BASE) 01349 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 01350 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 01351 #define COMP3 ((COMP_TypeDef *) COMP3_BASE) 01352 #define COMP4 ((COMP_TypeDef *) COMP4_BASE) 01353 #define COMP5 ((COMP_TypeDef *) COMP5_BASE) 01354 #define COMP6 ((COMP_TypeDef *) COMP6_BASE) 01355 #define COMP7 ((COMP_TypeDef *) COMP7_BASE) 01356 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 01357 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) 01358 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) 01359 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE) 01360 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE) 01361 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 01362 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 01363 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01364 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 01365 #define USART1 ((USART_TypeDef *) USART1_BASE) 01366 #define SPI4 ((SPI_TypeDef *) SPI4_BASE) 01367 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 01368 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 01369 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 01370 #define TIM20 ((TIM_TypeDef *) TIM20_BASE) 01371 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) 01372 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) 01373 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) 01374 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) 01375 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) 01376 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) 01377 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) 01378 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01379 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01380 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 01381 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 01382 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 01383 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 01384 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 01385 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 01386 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 01387 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01388 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 01389 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 01390 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 01391 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 01392 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 01393 #define RCC ((RCC_TypeDef *) RCC_BASE) 01394 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01395 #define OB ((OB_TypeDef *) OB_BASE) 01396 #define CRC ((CRC_TypeDef *) CRC_BASE) 01397 #define TSC ((TSC_TypeDef *) TSC_BASE) 01398 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01399 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01400 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01401 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01402 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01403 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01404 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01405 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 01406 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 01407 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 01408 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 01409 #define ADC4 ((ADC_TypeDef *) ADC4_BASE) 01410 #define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE) 01411 #define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE) 01412 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) 01413 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) 01414 #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) 01415 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) 01416 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) 01417 /** 01418 * @} 01419 */ 01420 01421 /** @addtogroup Exported_constants 01422 * @{ 01423 */ 01424 01425 /** @addtogroup Peripheral_Registers_Bits_Definition 01426 * @{ 01427 */ 01428 01429 /******************************************************************************/ 01430 /* Peripheral Registers_Bits_Definition */ 01431 /******************************************************************************/ 01432 /******************************************************************************/ 01433 /* */ 01434 /* High Resolution Timer (HRTIM) */ 01435 /* */ 01436 /******************************************************************************/ 01437 /******************** Master Timer control register ***************************/ 01438 #define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */ 01439 #define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */ 01440 #define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */ 01441 #define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */ 01442 01443 #define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */ 01444 #define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */ 01445 #define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */ 01446 01447 #define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */ 01448 #define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */ 01449 #define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */ 01450 #define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */ 01451 #define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */ 01452 #define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */ 01453 #define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */ 01454 #define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */ 01455 #define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */ 01456 #define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */ 01457 #define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */ 01458 01459 #define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */ 01460 #define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */ 01461 #define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */ 01462 #define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */ 01463 #define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */ 01464 #define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */ 01465 01466 #define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */ 01467 #define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */ 01468 #define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */ 01469 01470 #define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */ 01471 #define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */ 01472 01473 #define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */ 01474 #define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/ 01475 #define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */ 01476 01477 /******************** Master Timer Interrupt status register ******************/ 01478 #define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */ 01479 #define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */ 01480 #define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */ 01481 #define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */ 01482 #define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */ 01483 #define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */ 01484 #define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */ 01485 01486 /******************** Master Timer Interrupt clear register *******************/ 01487 #define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */ 01488 #define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */ 01489 #define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */ 01490 #define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */ 01491 #define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */ 01492 #define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */ 01493 #define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */ 01494 01495 /******************** Master Timer DMA/Interrupt enable register **************/ 01496 #define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */ 01497 #define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */ 01498 #define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */ 01499 #define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */ 01500 #define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */ 01501 #define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */ 01502 #define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */ 01503 01504 #define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */ 01505 #define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */ 01506 #define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */ 01507 #define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */ 01508 #define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */ 01509 #define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */ 01510 #define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */ 01511 01512 /******************* Bit definition for HRTIM_MCNTR register ****************/ 01513 #define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ 01514 01515 /******************* Bit definition for HRTIM_MPER register *****************/ 01516 #define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ 01517 01518 /******************* Bit definition for HRTIM_MREP register *****************/ 01519 #define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */ 01520 01521 /******************* Bit definition for HRTIM_MCMP1R register *****************/ 01522 #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ 01523 01524 /******************* Bit definition for HRTIM_MCMP2R register *****************/ 01525 #define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ 01526 01527 /******************* Bit definition for HRTIM_MCMP3R register *****************/ 01528 #define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ 01529 01530 /******************* Bit definition for HRTIM_MCMP4R register *****************/ 01531 #define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ 01532 01533 /******************** Slave control register **********************************/ 01534 #define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/ 01535 #define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */ 01536 #define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */ 01537 #define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */ 01538 01539 #define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */ 01540 #define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */ 01541 #define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */ 01542 #define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */ 01543 01544 #define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */ 01545 #define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */ 01546 01547 #define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed comparator 2 mode mask */ 01548 #define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed comparator 2 bit 0 */ 01549 #define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed comparator 2 bit 1 */ 01550 #define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed comparator 4 mode mask */ 01551 #define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed comparator 4 bit 0 */ 01552 #define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed comparator 4 bit 1 */ 01553 01554 #define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */ 01555 #define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */ 01556 #define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */ 01557 #define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */ 01558 #define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */ 01559 #define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */ 01560 #define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */ 01561 #define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */ 01562 01563 #define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */ 01564 #define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */ 01565 #define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */ 01566 #define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */ 01567 01568 #define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */ 01569 #define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */ 01570 #define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */ 01571 #define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */ 01572 #define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */ 01573 01574 /******************** Slave Interrupt status register **************************/ 01575 #define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */ 01576 #define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */ 01577 #define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */ 01578 #define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */ 01579 #define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */ 01580 #define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */ 01581 #define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */ 01582 #define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */ 01583 #define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */ 01584 #define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */ 01585 #define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */ 01586 #define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */ 01587 #define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */ 01588 #define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */ 01589 #define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */ 01590 #define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */ 01591 #define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */ 01592 #define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */ 01593 #define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */ 01594 #define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */ 01595 01596 /******************** Slave Interrupt clear register **************************/ 01597 #define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */ 01598 #define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */ 01599 #define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */ 01600 #define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */ 01601 #define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */ 01602 #define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */ 01603 #define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */ 01604 #define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */ 01605 #define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */ 01606 #define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */ 01607 #define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */ 01608 #define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */ 01609 #define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */ 01610 #define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */ 01611 #define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */ 01612 01613 /******************** Slave DMA/Interrupt enable register *********************/ 01614 #define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */ 01615 #define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */ 01616 #define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */ 01617 #define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */ 01618 #define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */ 01619 #define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */ 01620 #define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */ 01621 #define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */ 01622 #define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */ 01623 #define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */ 01624 #define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */ 01625 #define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */ 01626 #define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */ 01627 #define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */ 01628 01629 #define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */ 01630 #define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */ 01631 #define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */ 01632 #define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */ 01633 #define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */ 01634 #define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */ 01635 #define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */ 01636 #define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */ 01637 #define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */ 01638 #define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */ 01639 #define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */ 01640 #define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */ 01641 #define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */ 01642 #define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slave delay protection request enable */ 01643 01644 /****************** Bit definition for HRTIM_CNTR register ****************/ 01645 #define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */ 01646 01647 /******************* Bit definition for HRTIM_PER register *****************/ 01648 #define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ 01649 01650 /******************* Bit definition for HRTIM_REP register *****************/ 01651 #define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */ 01652 01653 /******************* Bit definition for HRTIM_CMP1R register *****************/ 01654 #define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ 01655 01656 /******************* Bit definition for HRTIM_CMP1CR register *****************/ 01657 #define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ 01658 01659 /******************* Bit definition for HRTIM_CMP2R register *****************/ 01660 #define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ 01661 01662 /******************* Bit definition for HRTIM_CMP3R register *****************/ 01663 #define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ 01664 01665 /******************* Bit definition for HRTIM_CMP4R register *****************/ 01666 #define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ 01667 01668 /******************* Bit definition for HRTIM_CPT1R register ****************/ 01669 #define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ 01670 01671 /******************* Bit definition for HRTIM_CPT2R register ****************/ 01672 #define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ 01673 01674 /******************** Bit definition for Slave Deadtime register **************/ 01675 #define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */ 01676 #define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */ 01677 #define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */ 01678 #define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */ 01679 #define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */ 01680 #define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */ 01681 #define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */ 01682 #define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */ 01683 #define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */ 01684 #define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */ 01685 #define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */ 01686 #define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */ 01687 #define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */ 01688 #define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */ 01689 #define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */ 01690 #define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */ 01691 #define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */ 01692 #define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */ 01693 #define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */ 01694 #define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */ 01695 #define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */ 01696 #define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */ 01697 #define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */ 01698 #define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */ 01699 #define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */ 01700 #define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */ 01701 #define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */ 01702 #define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */ 01703 #define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */ 01704 #define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */ 01705 01706 /**** Bit definition for Slave Output 1 set register **************************/ 01707 #define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */ 01708 #define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ 01709 #define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ 01710 #define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ 01711 #define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ 01712 #define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ 01713 #define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ 01714 01715 #define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ 01716 #define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ 01717 #define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ 01718 #define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ 01719 #define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ 01720 01721 #define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ 01722 #define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ 01723 #define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ 01724 #define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ 01725 #define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ 01726 #define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ 01727 #define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ 01728 #define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ 01729 #define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ 01730 01731 #define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ 01732 #define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ 01733 #define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ 01734 #define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ 01735 #define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ 01736 #define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ 01737 #define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ 01738 #define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ 01739 #define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ 01740 #define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ 01741 01742 #define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ 01743 01744 /**** Bit definition for Slave Output 1 reset register ************************/ 01745 #define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ 01746 #define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ 01747 #define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ 01748 #define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ 01749 #define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ 01750 #define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ 01751 #define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ 01752 01753 #define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ 01754 #define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ 01755 #define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ 01756 #define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ 01757 #define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ 01758 01759 #define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ 01760 #define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ 01761 #define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ 01762 #define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ 01763 #define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ 01764 #define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ 01765 #define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ 01766 #define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ 01767 #define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ 01768 01769 #define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ 01770 #define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ 01771 #define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ 01772 #define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ 01773 #define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ 01774 #define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ 01775 #define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ 01776 #define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ 01777 #define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ 01778 #define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ 01779 01780 #define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ 01781 01782 01783 /**** Bit definition for Slave Output 2 set register **************************/ 01784 #define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */ 01785 #define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ 01786 #define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ 01787 #define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ 01788 #define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ 01789 #define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ 01790 #define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ 01791 01792 #define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ 01793 #define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ 01794 #define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ 01795 #define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ 01796 #define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ 01797 01798 #define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ 01799 #define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ 01800 #define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ 01801 #define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ 01802 #define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ 01803 #define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ 01804 #define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ 01805 #define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ 01806 #define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ 01807 01808 #define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ 01809 #define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ 01810 #define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ 01811 #define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ 01812 #define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ 01813 #define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ 01814 #define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ 01815 #define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ 01816 #define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ 01817 #define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ 01818 01819 #define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ 01820 01821 /**** Bit definition for Slave Output 2 reset register ************************/ 01822 #define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ 01823 #define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ 01824 #define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ 01825 #define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ 01826 #define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ 01827 #define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ 01828 #define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ 01829 01830 #define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ 01831 #define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ 01832 #define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ 01833 #define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ 01834 #define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ 01835 01836 #define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ 01837 #define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ 01838 #define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ 01839 #define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ 01840 #define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ 01841 #define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ 01842 #define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ 01843 #define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ 01844 #define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ 01845 01846 #define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ 01847 #define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ 01848 #define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ 01849 #define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ 01850 #define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ 01851 #define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ 01852 #define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ 01853 #define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ 01854 #define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ 01855 #define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ 01856 01857 #define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ 01858 01859 /**** Bit definition for Slave external event filtering register 1 ***********/ 01860 #define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */ 01861 #define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */ 01862 #define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */ 01863 #define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/ 01864 #define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */ 01865 #define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */ 01866 01867 #define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */ 01868 #define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */ 01869 #define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */ 01870 #define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/ 01871 #define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */ 01872 #define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */ 01873 01874 #define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */ 01875 #define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */ 01876 #define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */ 01877 #define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/ 01878 #define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */ 01879 #define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */ 01880 01881 #define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */ 01882 #define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */ 01883 #define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */ 01884 #define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/ 01885 #define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */ 01886 #define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */ 01887 01888 #define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */ 01889 #define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */ 01890 #define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */ 01891 #define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/ 01892 #define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */ 01893 #define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */ 01894 01895 /**** Bit definition for Slave external event filtering register 2 ***********/ 01896 #define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */ 01897 #define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */ 01898 #define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */ 01899 #define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/ 01900 #define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */ 01901 #define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */ 01902 01903 #define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */ 01904 #define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */ 01905 #define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */ 01906 #define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/ 01907 #define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */ 01908 #define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */ 01909 01910 #define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */ 01911 #define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */ 01912 #define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */ 01913 #define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/ 01914 #define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */ 01915 #define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */ 01916 01917 #define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */ 01918 #define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */ 01919 #define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */ 01920 #define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/ 01921 #define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */ 01922 #define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */ 01923 01924 #define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */ 01925 #define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */ 01926 #define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */ 01927 #define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/ 01928 #define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */ 01929 #define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */ 01930 01931 /**** Bit definition for Slave Timer reset register ***************************/ 01932 #define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */ 01933 #define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */ 01934 #define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */ 01935 01936 #define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */ 01937 #define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */ 01938 #define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */ 01939 #define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */ 01940 #define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */ 01941 01942 #define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */ 01943 #define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */ 01944 #define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */ 01945 #define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */ 01946 #define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */ 01947 #define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */ 01948 #define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */ 01949 #define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */ 01950 #define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */ 01951 #define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */ 01952 01953 #define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */ 01954 #define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */ 01955 #define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */ 01956 01957 #define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ 01958 #define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ 01959 #define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */ 01960 01961 #define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */ 01962 #define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */ 01963 #define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */ 01964 01965 #define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */ 01966 #define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */ 01967 #define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */ 01968 01969 /**** Bit definition for Slave Timer Chopper register *************************/ 01970 #define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */ 01971 #define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */ 01972 #define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */ 01973 #define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */ 01974 #define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */ 01975 01976 #define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */ 01977 #define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */ 01978 #define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */ 01979 #define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */ 01980 01981 #define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */ 01982 #define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */ 01983 #define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */ 01984 #define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */ 01985 #define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */ 01986 01987 /**** Bit definition for Slave Timer Capture 1 control register ***************/ 01988 #define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ 01989 #define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ 01990 #define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ 01991 #define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ 01992 #define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ 01993 #define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ 01994 #define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ 01995 #define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ 01996 #define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ 01997 #define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ 01998 #define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ 01999 #define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ 02000 02001 #define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ 02002 #define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ 02003 #define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ 02004 #define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ 02005 02006 #define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ 02007 #define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ 02008 #define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ 02009 #define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ 02010 02011 #define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ 02012 #define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ 02013 #define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ 02014 #define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ 02015 02016 #define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ 02017 #define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ 02018 #define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ 02019 #define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ 02020 02021 #define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ 02022 #define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ 02023 #define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ 02024 #define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ 02025 02026 /**** Bit definition for Slave Timer Capture 2 control register ***************/ 02027 #define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ 02028 #define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ 02029 #define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ 02030 #define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ 02031 #define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ 02032 #define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ 02033 #define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ 02034 #define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ 02035 #define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ 02036 #define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ 02037 #define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ 02038 #define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ 02039 02040 #define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ 02041 #define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ 02042 #define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ 02043 #define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ 02044 02045 #define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ 02046 #define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ 02047 #define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ 02048 #define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ 02049 02050 #define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ 02051 #define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ 02052 #define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ 02053 #define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ 02054 02055 #define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ 02056 #define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ 02057 #define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ 02058 #define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ 02059 02060 #define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ 02061 #define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ 02062 #define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ 02063 #define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ 02064 02065 /**** Bit definition for Slave Timer Output register **************************/ 02066 #define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */ 02067 #define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */ 02068 #define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */ 02069 #define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */ 02070 #define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */ 02071 #define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */ 02072 #define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */ 02073 #define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */ 02074 02075 #define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */ 02076 #define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */ 02077 #define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */ 02078 #define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */ 02079 #define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */ 02080 #define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */ 02081 02082 #define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */ 02083 #define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */ 02084 #define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */ 02085 #define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */ 02086 #define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */ 02087 #define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */ 02088 #define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */ 02089 #define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */ 02090 02091 /**** Bit definition for Slave Timer Fault register ***************************/ 02092 #define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */ 02093 #define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */ 02094 #define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */ 02095 #define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */ 02096 #define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */ 02097 #define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /*!< Fault sources lock */ 02098 02099 /**** Bit definition for Common HRTIM Timer control register 1 ****************/ 02100 #define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/ 02101 #define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/ 02102 #define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/ 02103 #define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/ 02104 #define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/ 02105 #define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/ 02106 #define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */ 02107 #define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */ 02108 #define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */ 02109 #define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */ 02110 #define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */ 02111 #define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */ 02112 #define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */ 02113 #define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */ 02114 #define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */ 02115 #define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */ 02116 #define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */ 02117 #define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */ 02118 #define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */ 02119 #define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */ 02120 #define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */ 02121 #define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */ 02122 02123 /**** Bit definition for Common HRTIM Timer control register 2 ****************/ 02124 #define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */ 02125 #define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */ 02126 #define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */ 02127 #define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */ 02128 #define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */ 02129 #define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */ 02130 #define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */ 02131 #define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */ 02132 #define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */ 02133 #define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */ 02134 #define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */ 02135 #define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */ 02136 02137 /**** Bit definition for Common HRTIM Timer interrupt status register *********/ 02138 #define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */ 02139 #define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */ 02140 #define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */ 02141 #define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */ 02142 #define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */ 02143 #define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */ 02144 #define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */ 02145 #define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */ 02146 02147 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/ 02148 #define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */ 02149 #define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */ 02150 #define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */ 02151 #define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */ 02152 #define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */ 02153 #define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */ 02154 #define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */ 02155 #define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */ 02156 02157 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/ 02158 #define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */ 02159 #define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */ 02160 #define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */ 02161 #define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */ 02162 #define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */ 02163 #define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */ 02164 #define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */ 02165 #define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */ 02166 02167 /**** Bit definition for Common HRTIM Timer output enable register ************/ 02168 #define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */ 02169 #define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */ 02170 #define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */ 02171 #define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */ 02172 #define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */ 02173 #define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */ 02174 #define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */ 02175 #define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */ 02176 #define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */ 02177 #define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */ 02178 02179 /**** Bit definition for Common HRTIM Timer output disable register ***********/ 02180 #define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */ 02181 #define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */ 02182 #define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */ 02183 #define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */ 02184 #define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */ 02185 #define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */ 02186 #define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */ 02187 #define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */ 02188 #define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */ 02189 #define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */ 02190 02191 /**** Bit definition for Common HRTIM Timer output disable status register *****/ 02192 #define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */ 02193 #define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */ 02194 #define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */ 02195 #define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */ 02196 #define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */ 02197 #define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */ 02198 #define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */ 02199 #define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */ 02200 #define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */ 02201 #define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */ 02202 02203 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/ 02204 #define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enable */ 02205 #define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */ 02206 #define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */ 02207 #define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */ 02208 #define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */ 02209 #define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */ 02210 #define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */ 02211 #define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */ 02212 #define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */ 02213 #define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */ 02214 #define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */ 02215 #define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */ 02216 #define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */ 02217 #define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */ 02218 #define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */ 02219 #define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */ 02220 #define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */ 02221 #define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */ 02222 #define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */ 02223 #define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */ 02224 02225 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/ 02226 #define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */ 02227 #define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */ 02228 #define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */ 02229 #define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */ 02230 #define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */ 02231 #define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */ 02232 #define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */ 02233 #define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */ 02234 #define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */ 02235 #define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */ 02236 #define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */ 02237 #define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */ 02238 #define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */ 02239 #define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */ 02240 #define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */ 02241 #define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */ 02242 #define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */ 02243 #define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */ 02244 #define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */ 02245 #define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */ 02246 #define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */ 02247 #define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */ 02248 #define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */ 02249 #define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */ 02250 #define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */ 02251 #define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */ 02252 #define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */ 02253 #define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */ 02254 #define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */ 02255 #define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */ 02256 #define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */ 02257 #define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */ 02258 02259 /******************* Bit definition for HRTIM_BMCMPR register ***************/ 02260 #define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */ 02261 02262 /******************* Bit definition for HRTIM_BMPER register ****************/ 02263 #define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */ 02264 02265 /******************* Bit definition for HRTIM_EECR1 register ****************/ 02266 #define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */ 02267 #define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */ 02268 #define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */ 02269 #define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */ 02270 #define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */ 02271 #define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */ 02272 #define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */ 02273 #define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */ 02274 02275 #define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */ 02276 #define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */ 02277 #define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */ 02278 #define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */ 02279 #define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */ 02280 #define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */ 02281 #define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */ 02282 #define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */ 02283 02284 #define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */ 02285 #define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */ 02286 #define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */ 02287 #define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */ 02288 #define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */ 02289 #define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */ 02290 #define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */ 02291 #define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */ 02292 02293 #define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */ 02294 #define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */ 02295 #define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */ 02296 #define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */ 02297 #define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */ 02298 #define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */ 02299 #define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */ 02300 #define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */ 02301 02302 #define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */ 02303 #define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */ 02304 #define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */ 02305 #define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */ 02306 #define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */ 02307 #define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */ 02308 #define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */ 02309 #define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */ 02310 02311 /******************* Bit definition for HRTIM_EECR2 register ****************/ 02312 #define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */ 02313 #define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */ 02314 #define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */ 02315 #define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */ 02316 #define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */ 02317 #define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */ 02318 #define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */ 02319 02320 #define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */ 02321 #define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */ 02322 #define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */ 02323 #define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */ 02324 #define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */ 02325 #define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */ 02326 #define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */ 02327 02328 #define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */ 02329 #define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */ 02330 #define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */ 02331 #define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */ 02332 #define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */ 02333 #define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */ 02334 #define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */ 02335 02336 #define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */ 02337 #define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */ 02338 #define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */ 02339 #define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */ 02340 #define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */ 02341 #define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */ 02342 #define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */ 02343 02344 #define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */ 02345 #define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */ 02346 #define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */ 02347 #define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */ 02348 #define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */ 02349 #define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */ 02350 #define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */ 02351 02352 /******************* Bit definition for HRTIM_EECR3 register ****************/ 02353 #define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */ 02354 #define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */ 02355 #define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */ 02356 #define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */ 02357 #define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */ 02358 #define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */ 02359 #define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */ 02360 #define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */ 02361 #define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */ 02362 #define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */ 02363 #define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */ 02364 #define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */ 02365 #define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */ 02366 #define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */ 02367 #define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */ 02368 #define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */ 02369 #define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */ 02370 #define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */ 02371 #define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */ 02372 #define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */ 02373 #define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */ 02374 #define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */ 02375 #define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */ 02376 #define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */ 02377 #define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */ 02378 #define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */ 02379 #define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */ 02380 #define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */ 02381 02382 /******************* Bit definition for HRTIM_ADC1R register ****************/ 02383 #define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */ 02384 #define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */ 02385 #define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */ 02386 #define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */ 02387 #define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */ 02388 #define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */ 02389 #define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */ 02390 #define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */ 02391 #define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */ 02392 #define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */ 02393 #define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */ 02394 #define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */ 02395 #define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */ 02396 #define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */ 02397 #define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */ 02398 #define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */ 02399 #define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */ 02400 #define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */ 02401 #define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */ 02402 #define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */ 02403 #define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */ 02404 #define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */ 02405 #define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */ 02406 #define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */ 02407 #define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */ 02408 #define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */ 02409 #define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */ 02410 #define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */ 02411 #define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */ 02412 #define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */ 02413 #define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */ 02414 #define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */ 02415 02416 /******************* Bit definition for HRTIM_ADC2R register ****************/ 02417 #define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */ 02418 #define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */ 02419 #define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */ 02420 #define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */ 02421 #define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */ 02422 #define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */ 02423 #define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */ 02424 #define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */ 02425 #define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */ 02426 #define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */ 02427 #define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */ 02428 #define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */ 02429 #define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/ 02430 #define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */ 02431 #define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */ 02432 #define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */ 02433 #define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */ 02434 #define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */ 02435 #define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */ 02436 #define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */ 02437 #define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */ 02438 #define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */ 02439 #define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */ 02440 #define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */ 02441 #define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */ 02442 #define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/ 02443 #define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */ 02444 #define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */ 02445 #define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */ 02446 #define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */ 02447 #define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */ 02448 #define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */ 02449 02450 /******************* Bit definition for HRTIM_ADC3R register ****************/ 02451 #define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */ 02452 #define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */ 02453 #define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */ 02454 #define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */ 02455 #define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */ 02456 #define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */ 02457 #define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */ 02458 #define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */ 02459 #define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */ 02460 #define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */ 02461 #define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */ 02462 #define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */ 02463 #define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */ 02464 #define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */ 02465 #define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */ 02466 #define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */ 02467 #define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */ 02468 #define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */ 02469 #define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */ 02470 #define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */ 02471 #define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */ 02472 #define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */ 02473 #define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */ 02474 #define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */ 02475 #define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */ 02476 #define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */ 02477 #define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */ 02478 #define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */ 02479 #define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */ 02480 #define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */ 02481 #define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */ 02482 #define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */ 02483 02484 /******************* Bit definition for HRTIM_ADC4R register ****************/ 02485 #define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */ 02486 #define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */ 02487 #define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */ 02488 #define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */ 02489 #define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */ 02490 #define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */ 02491 #define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */ 02492 #define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */ 02493 #define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */ 02494 #define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */ 02495 #define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */ 02496 #define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */ 02497 #define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/ 02498 #define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */ 02499 #define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */ 02500 #define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */ 02501 #define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */ 02502 #define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */ 02503 #define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */ 02504 #define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */ 02505 #define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */ 02506 #define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */ 02507 #define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */ 02508 #define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */ 02509 #define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */ 02510 #define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/ 02511 #define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */ 02512 #define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */ 02513 #define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */ 02514 #define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */ 02515 #define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */ 02516 #define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */ 02517 02518 /******************* Bit definition for HRTIM_DLLCR register ****************/ 02519 #define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */ 02520 #define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */ 02521 #define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */ 02522 #define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */ 02523 #define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */ 02524 02525 /******************* Bit definition for HRTIM_FLTINR1 register ***************/ 02526 #define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */ 02527 #define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */ 02528 #define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */ 02529 #define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */ 02530 #define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */ 02531 #define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */ 02532 #define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */ 02533 #define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */ 02534 #define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */ 02535 02536 #define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */ 02537 #define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */ 02538 #define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */ 02539 #define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */ 02540 #define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */ 02541 #define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */ 02542 #define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */ 02543 #define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */ 02544 #define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */ 02545 02546 #define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */ 02547 #define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */ 02548 #define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */ 02549 #define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */ 02550 #define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */ 02551 #define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */ 02552 #define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */ 02553 #define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */ 02554 #define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */ 02555 02556 #define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */ 02557 #define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */ 02558 #define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */ 02559 #define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */ 02560 #define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */ 02561 #define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */ 02562 #define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */ 02563 #define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */ 02564 #define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */ 02565 02566 /******************* Bit definition for HRTIM_FLTINR2 register ***************/ 02567 #define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */ 02568 #define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */ 02569 #define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */ 02570 #define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */ 02571 #define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */ 02572 #define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */ 02573 #define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */ 02574 #define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */ 02575 #define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */ 02576 #define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */ 02577 #define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */ 02578 #define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */ 02579 02580 /******************* Bit definition for HRTIM_BDMUPR register ***************/ 02581 #define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */ 02582 #define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */ 02583 #define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */ 02584 #define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */ 02585 #define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */ 02586 #define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */ 02587 #define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */ 02588 #define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */ 02589 #define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */ 02590 #define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */ 02591 02592 /******************* Bit definition for HRTIM_BDTUPR register ***************/ 02593 #define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */ 02594 #define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */ 02595 #define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */ 02596 #define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */ 02597 #define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */ 02598 #define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */ 02599 #define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */ 02600 #define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */ 02601 #define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */ 02602 #define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */ 02603 #define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */ 02604 #define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */ 02605 #define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */ 02606 #define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */ 02607 #define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */ 02608 #define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */ 02609 #define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */ 02610 #define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */ 02611 #define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */ 02612 #define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */ 02613 #define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */ 02614 02615 /******************* Bit definition for HRTIM_BDMADR register ***************/ 02616 #define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */ 02617 02618 /******************************************************************************/ 02619 /* */ 02620 /* Analog to Digital Converter SAR (ADC) */ 02621 /* */ 02622 /******************************************************************************/ 02623 /******************** Bit definition for ADC_ISR register ********************/ 02624 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ 02625 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ 02626 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ 02627 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ 02628 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ 02629 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ 02630 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ 02631 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ 02632 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ 02633 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ 02634 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ 02635 02636 /******************** Bit definition for ADC_IER register ********************/ 02637 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ 02638 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ 02639 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ 02640 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ 02641 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ 02642 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ 02643 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ 02644 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ 02645 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ 02646 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ 02647 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ 02648 02649 /******************** Bit definition for ADC_CR register ********************/ 02650 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ 02651 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ 02652 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ 02653 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ 02654 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ 02655 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ 02656 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */ 02657 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */ 02658 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */ 02659 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ 02660 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ 02661 02662 /******************** Bit definition for ADC_CFGR register ********************/ 02663 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ 02664 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ 02665 02666 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ 02667 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ 02668 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ 02669 02670 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignment */ 02671 02672 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ 02673 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ 02674 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ 02675 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ 02676 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ 02677 02678 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ 02679 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ 02680 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ 02681 02682 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ 02683 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ 02684 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ 02685 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ 02686 02687 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ 02688 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ 02689 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ 02690 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ 02691 02692 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */ 02693 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ 02694 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */ 02695 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ 02696 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ 02697 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ 02698 02699 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ 02700 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ 02701 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ 02702 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ 02703 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ 02704 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ 02705 02706 /******************** Bit definition for ADC_SMPR1 register ********************/ 02707 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ 02708 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ 02709 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ 02710 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ 02711 02712 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ 02713 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ 02714 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ 02715 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ 02716 02717 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ 02718 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ 02719 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ 02720 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ 02721 02722 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ 02723 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ 02724 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ 02725 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ 02726 02727 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ 02728 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ 02729 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ 02730 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ 02731 02732 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ 02733 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ 02734 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ 02735 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ 02736 02737 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ 02738 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ 02739 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ 02740 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ 02741 02742 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ 02743 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ 02744 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ 02745 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ 02746 02747 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ 02748 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ 02749 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ 02750 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ 02751 02752 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ 02753 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ 02754 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ 02755 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ 02756 02757 /******************** Bit definition for ADC_SMPR2 register ********************/ 02758 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ 02759 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ 02760 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ 02761 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ 02762 02763 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ 02764 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ 02765 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ 02766 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ 02767 02768 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ 02769 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ 02770 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ 02771 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ 02772 02773 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ 02774 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ 02775 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ 02776 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ 02777 02778 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ 02779 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ 02780 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ 02781 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ 02782 02783 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ 02784 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ 02785 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ 02786 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ 02787 02788 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ 02789 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ 02790 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ 02791 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ 02792 02793 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ 02794 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ 02795 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ 02796 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ 02797 02798 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ 02799 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ 02800 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ 02801 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ 02802 02803 /******************** Bit definition for ADC_TR1 register ********************/ 02804 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ 02805 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ 02806 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ 02807 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ 02808 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ 02809 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ 02810 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ 02811 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ 02812 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ 02813 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ 02814 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ 02815 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ 02816 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ 02817 02818 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ 02819 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ 02820 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ 02821 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ 02822 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ 02823 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ 02824 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ 02825 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ 02826 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ 02827 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ 02828 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ 02829 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ 02830 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ 02831 02832 /******************** Bit definition for ADC_TR2 register ********************/ 02833 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ 02834 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ 02835 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ 02836 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ 02837 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ 02838 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ 02839 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ 02840 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ 02841 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ 02842 02843 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ 02844 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ 02845 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ 02846 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ 02847 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ 02848 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ 02849 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ 02850 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ 02851 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ 02852 02853 /******************** Bit definition for ADC_TR3 register ********************/ 02854 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ 02855 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ 02856 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ 02857 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ 02858 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ 02859 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ 02860 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ 02861 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ 02862 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ 02863 02864 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ 02865 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ 02866 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ 02867 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ 02868 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ 02869 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ 02870 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ 02871 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ 02872 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ 02873 02874 /******************** Bit definition for ADC_SQR1 register ********************/ 02875 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence length */ 02876 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ 02877 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ 02878 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ 02879 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ 02880 02881 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ 02882 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ 02883 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ 02884 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ 02885 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ 02886 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ 02887 02888 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ 02889 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ 02890 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ 02891 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ 02892 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ 02893 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ 02894 02895 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ 02896 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ 02897 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ 02898 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ 02899 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ 02900 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ 02901 02902 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ 02903 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ 02904 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ 02905 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ 02906 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ 02907 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ 02908 02909 /******************** Bit definition for ADC_SQR2 register ********************/ 02910 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ 02911 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ 02912 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ 02913 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ 02914 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ 02915 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ 02916 02917 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ 02918 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ 02919 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ 02920 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ 02921 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ 02922 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ 02923 02924 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ 02925 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ 02926 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ 02927 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ 02928 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ 02929 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ 02930 02931 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ 02932 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ 02933 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ 02934 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ 02935 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ 02936 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ 02937 02938 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ 02939 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ 02940 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ 02941 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ 02942 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ 02943 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ 02944 02945 /******************** Bit definition for ADC_SQR3 register ********************/ 02946 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ 02947 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ 02948 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ 02949 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ 02950 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ 02951 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ 02952 02953 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ 02954 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ 02955 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ 02956 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ 02957 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ 02958 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ 02959 02960 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ 02961 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ 02962 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ 02963 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ 02964 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ 02965 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ 02966 02967 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ 02968 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ 02969 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ 02970 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ 02971 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ 02972 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ 02973 02974 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ 02975 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ 02976 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ 02977 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ 02978 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ 02979 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ 02980 02981 /******************** Bit definition for ADC_SQR4 register ********************/ 02982 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ 02983 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ 02984 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ 02985 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ 02986 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ 02987 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ 02988 02989 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ 02990 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ 02991 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ 02992 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ 02993 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ 02994 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ 02995 02996 /* these defines are maintained for legacy purpose */ 02997 #define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /*!< ADC 15th conversion in regular sequence */ 02998 #define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /*!< ADC SQ15 bit 0 */ 02999 #define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /*!< ADC SQ15 bit 1 */ 03000 #define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /*!< ADC SQ15 bit 2 */ 03001 #define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /*!< ADC SQ15 bit 3 */ 03002 #define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /*!< ADC SQ105 bit 4 */ 03003 03004 #define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /*!< ADC 16th conversion in regular sequence */ 03005 #define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /*!< ADC SQ16 bit 0 */ 03006 #define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /*!< ADC SQ16 bit 1 */ 03007 #define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /*!< ADC SQ16 bit 2 */ 03008 #define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /*!< ADC SQ16 bit 3 */ 03009 #define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /*!< ADC SQ16 bit 4 */ 03010 /******************** Bit definition for ADC_DR register ********************/ 03011 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ 03012 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ 03013 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ 03014 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ 03015 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ 03016 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ 03017 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ 03018 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ 03019 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ 03020 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ 03021 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ 03022 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ 03023 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ 03024 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ 03025 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ 03026 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ 03027 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ 03028 03029 /******************** Bit definition for ADC_JSQR register ********************/ 03030 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ 03031 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ 03032 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ 03033 03034 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ 03035 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ 03036 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ 03037 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ 03038 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ 03039 03040 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ 03041 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ 03042 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ 03043 03044 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ 03045 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ 03046 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ 03047 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ 03048 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ 03049 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ 03050 03051 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ 03052 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ 03053 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ 03054 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ 03055 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ 03056 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ 03057 03058 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ 03059 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ 03060 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ 03061 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ 03062 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ 03063 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ 03064 03065 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ 03066 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ 03067 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ 03068 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ 03069 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ 03070 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ 03071 03072 /******************** Bit definition for ADC_OFR1 register ********************/ 03073 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ 03074 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ 03075 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ 03076 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ 03077 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ 03078 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ 03079 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ 03080 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ 03081 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ 03082 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ 03083 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ 03084 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ 03085 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ 03086 03087 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ 03088 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ 03089 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ 03090 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ 03091 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ 03092 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ 03093 03094 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ 03095 03096 /******************** Bit definition for ADC_OFR2 register ********************/ 03097 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ 03098 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ 03099 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ 03100 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ 03101 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ 03102 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ 03103 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ 03104 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ 03105 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ 03106 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ 03107 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ 03108 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ 03109 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ 03110 03111 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ 03112 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ 03113 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ 03114 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ 03115 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ 03116 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ 03117 03118 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ 03119 03120 /******************** Bit definition for ADC_OFR3 register ********************/ 03121 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ 03122 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ 03123 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ 03124 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ 03125 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ 03126 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ 03127 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ 03128 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ 03129 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ 03130 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ 03131 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ 03132 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ 03133 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ 03134 03135 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ 03136 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ 03137 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ 03138 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ 03139 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ 03140 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ 03141 03142 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ 03143 03144 /******************** Bit definition for ADC_OFR4 register ********************/ 03145 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ 03146 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ 03147 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ 03148 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ 03149 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ 03150 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ 03151 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ 03152 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ 03153 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ 03154 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ 03155 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ 03156 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ 03157 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ 03158 03159 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ 03160 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ 03161 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ 03162 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ 03163 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ 03164 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ 03165 03166 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ 03167 03168 /******************** Bit definition for ADC_JDR1 register ********************/ 03169 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ 03170 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ 03171 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ 03172 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ 03173 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ 03174 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ 03175 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ 03176 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ 03177 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ 03178 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ 03179 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ 03180 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ 03181 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ 03182 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ 03183 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ 03184 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ 03185 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ 03186 03187 /******************** Bit definition for ADC_JDR2 register ********************/ 03188 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ 03189 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ 03190 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ 03191 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ 03192 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ 03193 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ 03194 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ 03195 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ 03196 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ 03197 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ 03198 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ 03199 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ 03200 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ 03201 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ 03202 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ 03203 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ 03204 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ 03205 03206 /******************** Bit definition for ADC_JDR3 register ********************/ 03207 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ 03208 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ 03209 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ 03210 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ 03211 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ 03212 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ 03213 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ 03214 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ 03215 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ 03216 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ 03217 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ 03218 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ 03219 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ 03220 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ 03221 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ 03222 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ 03223 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ 03224 03225 /******************** Bit definition for ADC_JDR4 register ********************/ 03226 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ 03227 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ 03228 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ 03229 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ 03230 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ 03231 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ 03232 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ 03233 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ 03234 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ 03235 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ 03236 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ 03237 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ 03238 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ 03239 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ 03240 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ 03241 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ 03242 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ 03243 03244 /******************** Bit definition for ADC_AWD2CR register ********************/ 03245 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ 03246 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */ 03247 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */ 03248 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */ 03249 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */ 03250 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */ 03251 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */ 03252 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */ 03253 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */ 03254 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */ 03255 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */ 03256 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */ 03257 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */ 03258 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */ 03259 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */ 03260 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */ 03261 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */ 03262 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */ 03263 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */ 03264 03265 /******************** Bit definition for ADC_AWD3CR register ********************/ 03266 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ 03267 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */ 03268 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */ 03269 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */ 03270 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */ 03271 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */ 03272 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */ 03273 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */ 03274 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */ 03275 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */ 03276 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */ 03277 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */ 03278 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */ 03279 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */ 03280 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */ 03281 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */ 03282 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */ 03283 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */ 03284 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */ 03285 03286 /******************** Bit definition for ADC_DIFSEL register ********************/ 03287 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */ 03288 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */ 03289 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */ 03290 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */ 03291 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */ 03292 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */ 03293 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */ 03294 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */ 03295 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */ 03296 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */ 03297 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */ 03298 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */ 03299 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */ 03300 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */ 03301 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */ 03302 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */ 03303 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */ 03304 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */ 03305 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */ 03306 03307 /******************** Bit definition for ADC_CALFACT register ********************/ 03308 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ 03309 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ 03310 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ 03311 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ 03312 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ 03313 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ 03314 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ 03315 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ 03316 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ 03317 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ 03318 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ 03319 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ 03320 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ 03321 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ 03322 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ 03323 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ 03324 03325 /************************* ADC Common registers *****************************/ 03326 /******************** Bit definition for ADC12_CSR register ********************/ 03327 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ 03328 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ 03329 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ 03330 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ 03331 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ 03332 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ 03333 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ 03334 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ 03335 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ 03336 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ 03337 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ 03338 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ 03339 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ 03340 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ 03341 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ 03342 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ 03343 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ 03344 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ 03345 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ 03346 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ 03347 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ 03348 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ 03349 03350 /******************** Bit definition for ADC34_CSR register ********************/ 03351 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ 03352 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ 03353 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ 03354 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ 03355 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ 03356 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ 03357 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ 03358 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ 03359 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ 03360 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ 03361 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ 03362 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ 03363 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ 03364 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ 03365 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ 03366 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ 03367 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ 03368 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ 03369 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ 03370 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ 03371 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ 03372 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ 03373 03374 /******************** Bit definition for ADC_CCR register ********************/ 03375 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ 03376 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ 03377 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ 03378 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ 03379 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ 03380 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ 03381 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ 03382 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ 03383 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ 03384 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ 03385 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ 03386 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ 03387 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ 03388 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ 03389 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ 03390 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ 03391 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ 03392 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ 03393 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ 03394 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ 03395 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ 03396 03397 /******************** Bit definition for ADC_CCR register ********************/ 03398 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ 03399 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ 03400 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ 03401 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ 03402 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ 03403 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ 03404 03405 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ 03406 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ 03407 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ 03408 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ 03409 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ 03410 03411 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ 03412 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ 03413 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ 03414 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ 03415 03416 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ 03417 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ 03418 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ 03419 03420 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ 03421 03422 /******************** Bit definition for ADC_CDR register ********************/ 03423 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ 03424 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ 03425 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ 03426 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ 03427 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ 03428 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ 03429 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ 03430 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ 03431 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ 03432 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ 03433 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ 03434 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ 03435 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ 03436 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ 03437 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ 03438 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ 03439 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ 03440 03441 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ 03442 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ 03443 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ 03444 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ 03445 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ 03446 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ 03447 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ 03448 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ 03449 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ 03450 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ 03451 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ 03452 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ 03453 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ 03454 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ 03455 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ 03456 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ 03457 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ 03458 03459 /******************** Bit definition for ADC_CDR register ********************/ 03460 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ 03461 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ 03462 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ 03463 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ 03464 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ 03465 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ 03466 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ 03467 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ 03468 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ 03469 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ 03470 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ 03471 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ 03472 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ 03473 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ 03474 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ 03475 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ 03476 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ 03477 03478 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ 03479 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ 03480 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ 03481 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ 03482 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ 03483 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ 03484 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ 03485 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ 03486 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ 03487 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ 03488 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ 03489 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ 03490 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ 03491 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ 03492 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ 03493 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ 03494 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ 03495 03496 /******************************************************************************/ 03497 /* */ 03498 /* Analog Comparators (COMP) */ 03499 /* */ 03500 /******************************************************************************/ 03501 /********************** Bit definition for COMP1_CSR register ***************/ 03502 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */ 03503 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ 03504 #define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */ 03505 #define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */ 03506 #define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */ 03507 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */ 03508 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */ 03509 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */ 03510 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */ 03511 #define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */ 03512 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */ 03513 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */ 03514 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */ 03515 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */ 03516 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */ 03517 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */ 03518 #define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */ 03519 #define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */ 03520 #define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */ 03521 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */ 03522 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */ 03523 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */ 03524 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */ 03525 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */ 03526 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */ 03527 03528 /********************** Bit definition for COMP2_CSR register ***************/ 03529 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */ 03530 #define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */ 03531 #define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */ 03532 #define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */ 03533 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */ 03534 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */ 03535 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */ 03536 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */ 03537 #define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */ 03538 #define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */ 03539 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */ 03540 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */ 03541 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */ 03542 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */ 03543 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */ 03544 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */ 03545 #define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */ 03546 #define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */ 03547 #define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */ 03548 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */ 03549 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */ 03550 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */ 03551 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */ 03552 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ 03553 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ 03554 03555 /********************** Bit definition for COMP3_CSR register ***************/ 03556 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */ 03557 #define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */ 03558 #define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */ 03559 #define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */ 03560 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */ 03561 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */ 03562 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */ 03563 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */ 03564 #define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */ 03565 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */ 03566 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */ 03567 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */ 03568 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */ 03569 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */ 03570 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */ 03571 #define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */ 03572 #define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */ 03573 #define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */ 03574 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */ 03575 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */ 03576 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */ 03577 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */ 03578 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */ 03579 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */ 03580 03581 /********************** Bit definition for COMP4_CSR register ***************/ 03582 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */ 03583 #define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */ 03584 #define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */ 03585 #define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */ 03586 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */ 03587 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */ 03588 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */ 03589 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */ 03590 #define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */ 03591 #define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */ 03592 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */ 03593 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */ 03594 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */ 03595 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */ 03596 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */ 03597 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */ 03598 #define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */ 03599 #define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */ 03600 #define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */ 03601 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */ 03602 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */ 03603 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */ 03604 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */ 03605 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */ 03606 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */ 03607 03608 /********************** Bit definition for COMP5_CSR register ***************/ 03609 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */ 03610 #define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */ 03611 #define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */ 03612 #define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */ 03613 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */ 03614 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */ 03615 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */ 03616 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */ 03617 #define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */ 03618 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */ 03619 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */ 03620 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */ 03621 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */ 03622 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */ 03623 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */ 03624 #define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */ 03625 #define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */ 03626 #define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */ 03627 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */ 03628 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */ 03629 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */ 03630 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */ 03631 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */ 03632 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */ 03633 03634 /********************** Bit definition for COMP6_CSR register ***************/ 03635 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */ 03636 #define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */ 03637 #define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */ 03638 #define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */ 03639 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */ 03640 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */ 03641 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */ 03642 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */ 03643 #define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */ 03644 #define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */ 03645 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */ 03646 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */ 03647 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */ 03648 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */ 03649 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */ 03650 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */ 03651 #define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */ 03652 #define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */ 03653 #define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */ 03654 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */ 03655 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */ 03656 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */ 03657 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */ 03658 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */ 03659 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */ 03660 03661 /********************** Bit definition for COMP7_CSR register ***************/ 03662 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */ 03663 #define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */ 03664 #define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */ 03665 #define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */ 03666 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */ 03667 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */ 03668 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */ 03669 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */ 03670 #define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */ 03671 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */ 03672 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */ 03673 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */ 03674 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */ 03675 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */ 03676 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */ 03677 #define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */ 03678 #define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */ 03679 #define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */ 03680 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */ 03681 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */ 03682 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */ 03683 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */ 03684 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */ 03685 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */ 03686 03687 /********************** Bit definition for COMP_CSR register ****************/ 03688 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ 03689 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */ 03690 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ 03691 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ 03692 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ 03693 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */ 03694 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ 03695 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ 03696 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ 03697 #define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */ 03698 #define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */ 03699 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */ 03700 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */ 03701 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */ 03702 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */ 03703 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */ 03704 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */ 03705 #define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */ 03706 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */ 03707 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */ 03708 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */ 03709 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */ 03710 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */ 03711 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */ 03712 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */ 03713 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */ 03714 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */ 03715 03716 /******************************************************************************/ 03717 /* */ 03718 /* Operational Amplifier (OPAMP) */ 03719 /* */ 03720 /******************************************************************************/ 03721 /********************* Bit definition for OPAMP1_CSR register ***************/ 03722 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */ 03723 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ 03724 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ 03725 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 03726 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 03727 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ 03728 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 03729 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 03730 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ 03731 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ 03732 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ 03733 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 03734 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 03735 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ 03736 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ 03737 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 03738 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 03739 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ 03740 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ 03741 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ 03742 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ 03743 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ 03744 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ 03745 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ 03746 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ 03747 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ 03748 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ 03749 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ 03750 03751 /********************* Bit definition for OPAMP2_CSR register ***************/ 03752 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */ 03753 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ 03754 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ 03755 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 03756 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 03757 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ 03758 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 03759 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 03760 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ 03761 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ 03762 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ 03763 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 03764 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 03765 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ 03766 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ 03767 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 03768 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 03769 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ 03770 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ 03771 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ 03772 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ 03773 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ 03774 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ 03775 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ 03776 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ 03777 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ 03778 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ 03779 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ 03780 03781 /********************* Bit definition for OPAMP3_CSR register ***************/ 03782 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */ 03783 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ 03784 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ 03785 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 03786 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 03787 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ 03788 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 03789 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 03790 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ 03791 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ 03792 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ 03793 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 03794 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 03795 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ 03796 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ 03797 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 03798 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 03799 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ 03800 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ 03801 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ 03802 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ 03803 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ 03804 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ 03805 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ 03806 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ 03807 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ 03808 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ 03809 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ 03810 03811 /********************* Bit definition for OPAMP4_CSR register ***************/ 03812 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */ 03813 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ 03814 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ 03815 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 03816 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 03817 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ 03818 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 03819 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 03820 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ 03821 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ 03822 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ 03823 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 03824 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 03825 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ 03826 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ 03827 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 03828 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 03829 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ 03830 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ 03831 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ 03832 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ 03833 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ 03834 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ 03835 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ 03836 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ 03837 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ 03838 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ 03839 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ 03840 03841 /********************* Bit definition for OPAMPx_CSR register ***************/ 03842 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */ 03843 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ 03844 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ 03845 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 03846 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 03847 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ 03848 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 03849 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 03850 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ 03851 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ 03852 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ 03853 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 03854 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 03855 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ 03856 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ 03857 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 03858 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 03859 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ 03860 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ 03861 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ 03862 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ 03863 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ 03864 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ 03865 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ 03866 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ 03867 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ 03868 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */ 03869 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ 03870 03871 03872 /******************************************************************************/ 03873 /* */ 03874 /* Controller Area Network (CAN ) */ 03875 /* */ 03876 /******************************************************************************/ 03877 /*!<CAN control and status registers */ 03878 /******************* Bit definition for CAN_MCR register ********************/ 03879 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ 03880 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ 03881 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ 03882 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ 03883 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ 03884 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ 03885 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ 03886 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ 03887 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ 03888 03889 /******************* Bit definition for CAN_MSR register ********************/ 03890 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ 03891 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ 03892 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ 03893 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ 03894 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ 03895 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ 03896 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ 03897 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ 03898 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ 03899 03900 /******************* Bit definition for CAN_TSR register ********************/ 03901 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ 03902 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ 03903 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ 03904 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ 03905 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ 03906 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ 03907 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ 03908 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ 03909 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ 03910 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ 03911 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ 03912 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ 03913 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ 03914 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ 03915 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ 03916 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ 03917 03918 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ 03919 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ 03920 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ 03921 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ 03922 03923 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ 03924 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ 03925 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ 03926 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ 03927 03928 /******************* Bit definition for CAN_RF0R register *******************/ 03929 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ 03930 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ 03931 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ 03932 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ 03933 03934 /******************* Bit definition for CAN_RF1R register *******************/ 03935 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ 03936 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ 03937 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ 03938 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ 03939 03940 /******************** Bit definition for CAN_IER register *******************/ 03941 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ 03942 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ 03943 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ 03944 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ 03945 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ 03946 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ 03947 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ 03948 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ 03949 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ 03950 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ 03951 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ 03952 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ 03953 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ 03954 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ 03955 03956 /******************** Bit definition for CAN_ESR register *******************/ 03957 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ 03958 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ 03959 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ 03960 03961 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ 03962 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 03963 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 03964 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 03965 03966 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ 03967 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ 03968 03969 /******************* Bit definition for CAN_BTR register ********************/ 03970 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ 03971 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ 03972 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ 03973 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ 03974 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ 03975 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ 03976 03977 /*!<Mailbox registers */ 03978 /****************** Bit definition for CAN_TI0R register ********************/ 03979 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 03980 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 03981 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 03982 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 03983 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 03984 03985 /****************** Bit definition for CAN_TDT0R register *******************/ 03986 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 03987 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 03988 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 03989 03990 /****************** Bit definition for CAN_TDL0R register *******************/ 03991 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 03992 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 03993 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 03994 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 03995 03996 /****************** Bit definition for CAN_TDH0R register *******************/ 03997 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 03998 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 03999 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 04000 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 04001 04002 /******************* Bit definition for CAN_TI1R register *******************/ 04003 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 04004 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 04005 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 04006 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 04007 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 04008 04009 /******************* Bit definition for CAN_TDT1R register ******************/ 04010 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 04011 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 04012 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 04013 04014 /******************* Bit definition for CAN_TDL1R register ******************/ 04015 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 04016 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 04017 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 04018 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 04019 04020 /******************* Bit definition for CAN_TDH1R register ******************/ 04021 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 04022 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 04023 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 04024 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 04025 04026 /******************* Bit definition for CAN_TI2R register *******************/ 04027 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 04028 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 04029 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 04030 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ 04031 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 04032 04033 /******************* Bit definition for CAN_TDT2R register ******************/ 04034 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 04035 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 04036 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 04037 04038 /******************* Bit definition for CAN_TDL2R register ******************/ 04039 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 04040 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 04041 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 04042 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 04043 04044 /******************* Bit definition for CAN_TDH2R register ******************/ 04045 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 04046 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 04047 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 04048 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 04049 04050 /******************* Bit definition for CAN_RI0R register *******************/ 04051 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 04052 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 04053 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 04054 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 04055 04056 /******************* Bit definition for CAN_RDT0R register ******************/ 04057 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 04058 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ 04059 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 04060 04061 /******************* Bit definition for CAN_RDL0R register ******************/ 04062 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 04063 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 04064 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 04065 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 04066 04067 /******************* Bit definition for CAN_RDH0R register ******************/ 04068 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 04069 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 04070 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 04071 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 04072 04073 /******************* Bit definition for CAN_RI1R register *******************/ 04074 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 04075 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 04076 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ 04077 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 04078 04079 /******************* Bit definition for CAN_RDT1R register ******************/ 04080 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 04081 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ 04082 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 04083 04084 /******************* Bit definition for CAN_RDL1R register ******************/ 04085 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 04086 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 04087 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 04088 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 04089 04090 /******************* Bit definition for CAN_RDH1R register ******************/ 04091 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 04092 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 04093 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 04094 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 04095 04096 /*!<CAN filter registers */ 04097 /******************* Bit definition for CAN_FMR register ********************/ 04098 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ 04099 04100 /******************* Bit definition for CAN_FM1R register *******************/ 04101 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ 04102 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ 04103 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ 04104 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ 04105 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ 04106 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ 04107 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ 04108 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ 04109 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ 04110 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ 04111 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ 04112 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ 04113 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ 04114 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ 04115 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ 04116 04117 /******************* Bit definition for CAN_FS1R register *******************/ 04118 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ 04119 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ 04120 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ 04121 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ 04122 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ 04123 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ 04124 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ 04125 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ 04126 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ 04127 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ 04128 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ 04129 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ 04130 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ 04131 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ 04132 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ 04133 04134 /****************** Bit definition for CAN_FFA1R register *******************/ 04135 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ 04136 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ 04137 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ 04138 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ 04139 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ 04140 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ 04141 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ 04142 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ 04143 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ 04144 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ 04145 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ 04146 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ 04147 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ 04148 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ 04149 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ 04150 04151 /******************* Bit definition for CAN_FA1R register *******************/ 04152 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ 04153 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ 04154 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ 04155 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ 04156 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ 04157 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ 04158 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ 04159 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ 04160 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ 04161 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ 04162 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ 04163 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ 04164 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ 04165 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ 04166 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ 04167 04168 /******************* Bit definition for CAN_F0R1 register *******************/ 04169 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04170 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04171 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04172 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04173 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04174 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04175 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04176 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04177 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04178 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04179 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04180 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04181 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04182 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04183 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04184 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04185 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04186 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04187 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04188 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04189 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04190 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04191 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04192 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04193 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04194 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04195 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04196 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04197 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04198 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04199 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04200 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04201 04202 /******************* Bit definition for CAN_F1R1 register *******************/ 04203 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04204 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04205 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04206 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04207 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04208 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04209 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04210 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04211 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04212 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04213 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04214 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04215 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04216 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04217 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04218 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04219 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04220 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04221 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04222 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04223 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04224 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04225 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04226 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04227 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04228 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04229 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04230 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04231 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04232 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04233 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04234 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04235 04236 /******************* Bit definition for CAN_F2R1 register *******************/ 04237 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04238 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04239 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04240 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04241 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04242 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04243 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04244 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04245 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04246 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04247 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04248 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04249 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04250 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04251 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04252 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04253 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04254 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04255 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04256 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04257 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04258 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04259 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04260 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04261 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04262 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04263 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04264 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04265 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04266 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04267 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04268 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04269 04270 /******************* Bit definition for CAN_F3R1 register *******************/ 04271 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04272 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04273 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04274 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04275 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04276 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04277 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04278 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04279 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04280 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04281 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04282 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04283 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04284 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04285 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04286 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04287 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04288 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04289 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04290 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04291 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04292 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04293 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04294 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04295 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04296 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04297 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04298 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04299 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04300 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04301 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04302 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04303 04304 /******************* Bit definition for CAN_F4R1 register *******************/ 04305 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04306 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04307 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04308 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04309 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04310 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04311 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04312 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04313 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04314 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04315 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04316 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04317 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04318 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04319 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04320 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04321 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04322 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04323 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04324 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04325 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04326 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04327 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04328 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04329 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04330 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04331 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04332 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04333 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04334 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04335 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04336 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04337 04338 /******************* Bit definition for CAN_F5R1 register *******************/ 04339 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04340 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04341 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04342 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04343 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04344 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04345 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04346 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04347 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04348 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04349 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04350 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04351 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04352 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04353 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04354 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04355 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04356 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04357 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04358 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04359 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04360 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04361 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04362 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04363 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04364 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04365 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04366 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04367 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04368 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04369 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04370 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04371 04372 /******************* Bit definition for CAN_F6R1 register *******************/ 04373 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04374 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04375 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04376 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04377 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04378 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04379 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04380 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04381 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04382 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04383 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04384 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04385 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04386 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04387 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04388 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04389 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04390 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04391 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04392 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04393 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04394 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04395 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04396 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04397 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04398 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04399 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04400 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04401 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04402 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04403 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04404 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04405 04406 /******************* Bit definition for CAN_F7R1 register *******************/ 04407 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04408 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04409 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04410 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04411 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04412 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04413 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04414 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04415 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04416 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04417 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04418 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04419 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04420 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04421 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04422 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04423 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04424 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04425 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04426 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04427 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04428 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04429 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04430 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04431 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04432 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04433 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04434 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04435 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04436 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04437 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04438 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04439 04440 /******************* Bit definition for CAN_F8R1 register *******************/ 04441 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04442 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04443 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04444 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04445 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04446 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04447 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04448 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04449 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04450 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04451 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04452 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04453 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04454 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04455 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04456 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04457 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04458 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04459 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04460 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04461 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04462 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04463 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04464 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04465 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04466 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04467 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04468 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04469 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04470 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04471 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04472 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04473 04474 /******************* Bit definition for CAN_F9R1 register *******************/ 04475 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04476 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04477 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04478 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04479 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04480 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04481 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04482 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04483 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04484 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04485 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04486 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04487 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04488 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04489 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04490 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04491 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04492 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04493 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04494 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04495 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04496 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04497 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04498 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04499 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04500 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04501 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04502 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04503 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04504 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04505 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04506 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04507 04508 /******************* Bit definition for CAN_F10R1 register ******************/ 04509 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04510 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04511 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04512 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04513 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04514 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04515 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04516 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04517 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04518 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04519 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04520 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04521 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04522 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04523 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04524 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04525 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04526 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04527 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04528 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04529 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04530 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04531 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04532 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04533 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04534 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04535 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04536 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04537 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04538 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04539 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04540 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04541 04542 /******************* Bit definition for CAN_F11R1 register ******************/ 04543 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04544 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04545 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04546 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04547 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04548 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04549 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04550 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04551 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04552 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04553 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04554 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04555 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04556 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04557 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04558 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04559 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04560 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04561 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04562 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04563 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04564 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04565 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04566 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04567 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04568 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04569 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04570 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04571 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04572 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04573 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04574 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04575 04576 /******************* Bit definition for CAN_F12R1 register ******************/ 04577 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04578 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04579 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04580 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04581 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04582 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04583 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04584 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04585 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04586 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04587 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04588 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04589 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04590 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04591 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04592 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04593 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04594 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04595 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04596 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04597 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04598 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04599 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04600 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04601 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04602 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04603 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04604 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04605 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04606 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04607 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04608 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04609 04610 /******************* Bit definition for CAN_F13R1 register ******************/ 04611 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04612 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04613 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04614 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04615 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04616 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04617 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04618 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04619 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04620 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04621 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04622 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04623 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04624 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04625 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04626 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04627 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04628 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04629 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04630 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04631 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04632 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04633 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04634 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04635 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04636 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04637 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04638 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04639 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04640 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04641 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04642 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04643 04644 /******************* Bit definition for CAN_F0R2 register *******************/ 04645 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04646 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04647 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04648 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04649 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04650 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04651 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04652 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04653 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04654 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04655 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04656 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04657 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04658 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04659 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04660 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04661 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04662 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04663 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04664 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04665 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04666 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04667 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04668 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04669 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04670 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04671 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04672 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04673 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04674 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04675 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04676 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04677 04678 /******************* Bit definition for CAN_F1R2 register *******************/ 04679 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04680 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04681 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04682 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04683 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04684 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04685 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04686 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04687 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04688 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04689 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04690 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04691 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04692 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04693 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04694 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04695 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04696 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04697 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04698 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04699 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04700 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04701 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04702 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04703 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04704 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04705 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04706 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04707 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04708 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04709 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04710 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04711 04712 /******************* Bit definition for CAN_F2R2 register *******************/ 04713 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04714 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04715 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04716 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04717 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04718 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04719 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04720 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04721 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04722 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04723 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04724 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04725 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04726 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04727 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04728 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04729 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04730 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04731 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04732 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04733 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04734 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04735 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04736 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04737 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04738 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04739 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04740 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04741 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04742 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04743 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04744 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04745 04746 /******************* Bit definition for CAN_F3R2 register *******************/ 04747 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04748 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04749 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04750 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04751 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04752 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04753 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04754 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04755 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04756 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04757 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04758 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04759 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04760 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04761 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04762 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04763 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04764 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04765 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04766 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04767 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04768 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04769 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04770 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04771 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04772 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04773 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04774 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04775 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04776 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04777 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04778 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04779 04780 /******************* Bit definition for CAN_F4R2 register *******************/ 04781 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04782 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04783 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04784 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04785 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04786 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04787 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04788 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04789 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04790 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04791 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04792 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04793 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04794 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04795 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04796 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04797 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04798 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04799 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04800 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04801 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04802 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04803 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04804 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04805 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04806 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04807 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04808 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04809 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04810 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04811 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04812 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04813 04814 /******************* Bit definition for CAN_F5R2 register *******************/ 04815 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04816 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04817 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04818 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04819 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04820 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04821 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04822 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04823 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04824 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04825 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04826 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04827 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04828 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04829 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04830 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04831 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04832 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04833 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04834 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04835 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04836 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04837 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04838 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04839 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04840 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04841 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04842 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04843 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04844 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04845 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04846 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04847 04848 /******************* Bit definition for CAN_F6R2 register *******************/ 04849 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04850 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04851 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04852 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04853 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04854 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04855 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04856 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04857 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04858 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04859 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04860 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04861 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04862 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04863 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04864 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04865 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04866 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04867 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04868 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04869 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04870 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04871 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04872 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04873 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04874 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04875 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04876 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04877 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04878 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04879 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04880 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04881 04882 /******************* Bit definition for CAN_F7R2 register *******************/ 04883 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04884 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04885 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04886 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04887 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04888 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04889 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04890 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04891 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04892 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04893 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04894 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04895 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04896 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04897 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04898 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04899 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04900 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04901 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04902 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04903 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04904 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04905 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04906 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04907 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04908 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04909 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04910 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04911 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04912 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04913 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04914 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04915 04916 /******************* Bit definition for CAN_F8R2 register *******************/ 04917 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04918 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04919 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04920 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04921 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04922 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04923 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04924 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04925 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04926 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04927 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04928 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04929 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04930 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04931 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04932 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04933 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04934 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04935 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04936 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04937 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04938 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04939 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04940 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04941 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04942 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04943 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04944 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04945 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04946 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04947 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04948 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04949 04950 /******************* Bit definition for CAN_F9R2 register *******************/ 04951 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04952 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04953 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04954 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04955 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04956 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04957 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04958 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04959 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04960 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04961 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04962 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04963 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04964 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04965 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 04966 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 04967 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 04968 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 04969 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 04970 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 04971 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 04972 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 04973 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 04974 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 04975 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 04976 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 04977 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 04978 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 04979 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 04980 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 04981 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 04982 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 04983 04984 /******************* Bit definition for CAN_F10R2 register ******************/ 04985 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 04986 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 04987 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 04988 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 04989 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 04990 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 04991 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 04992 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 04993 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 04994 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 04995 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 04996 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 04997 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 04998 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 04999 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 05000 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 05001 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 05002 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 05003 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 05004 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 05005 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 05006 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 05007 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 05008 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 05009 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 05010 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 05011 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 05012 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 05013 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 05014 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 05015 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 05016 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 05017 05018 /******************* Bit definition for CAN_F11R2 register ******************/ 05019 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 05020 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 05021 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 05022 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 05023 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 05024 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 05025 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 05026 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 05027 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 05028 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 05029 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 05030 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 05031 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 05032 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 05033 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 05034 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 05035 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 05036 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 05037 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 05038 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 05039 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 05040 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 05041 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 05042 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 05043 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 05044 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 05045 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 05046 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 05047 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 05048 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 05049 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 05050 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 05051 05052 /******************* Bit definition for CAN_F12R2 register ******************/ 05053 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 05054 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 05055 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 05056 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 05057 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 05058 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 05059 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 05060 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 05061 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 05062 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 05063 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 05064 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 05065 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 05066 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 05067 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 05068 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 05069 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 05070 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 05071 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 05072 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 05073 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 05074 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 05075 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 05076 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 05077 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 05078 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 05079 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 05080 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 05081 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 05082 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 05083 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 05084 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 05085 05086 /******************* Bit definition for CAN_F13R2 register ******************/ 05087 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 05088 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 05089 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 05090 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 05091 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 05092 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 05093 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 05094 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 05095 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 05096 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 05097 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 05098 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 05099 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 05100 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 05101 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 05102 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 05103 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 05104 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 05105 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 05106 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 05107 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 05108 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 05109 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 05110 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 05111 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 05112 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 05113 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 05114 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 05115 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 05116 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 05117 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 05118 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 05119 05120 /******************************************************************************/ 05121 /* */ 05122 /* CRC calculation unit (CRC) */ 05123 /* */ 05124 /******************************************************************************/ 05125 /******************* Bit definition for CRC_DR register *********************/ 05126 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ 05127 05128 /******************* Bit definition for CRC_IDR register ********************/ 05129 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ 05130 05131 /******************** Bit definition for CRC_CR register ********************/ 05132 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ 05133 #define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ 05134 #define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ 05135 #define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ 05136 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ 05137 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */ 05138 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */ 05139 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ 05140 05141 /******************* Bit definition for CRC_INIT register *******************/ 05142 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ 05143 05144 /******************* Bit definition for CRC_POL register ********************/ 05145 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ 05146 /******************************************************************************/ 05147 /* */ 05148 /* Digital to Analog Converter (DAC) */ 05149 /* */ 05150 /******************************************************************************/ 05151 /******************** Bit definition for DAC_CR register ********************/ 05152 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ 05153 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ 05154 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ 05155 05156 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 05157 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ 05158 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ 05159 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ 05160 05161 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 05162 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ 05163 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ 05164 05165 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 05166 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 05167 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 05168 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ 05169 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ 05170 05171 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ 05172 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */ 05173 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ 05174 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ 05175 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ 05176 05177 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ 05178 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ 05179 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ 05180 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ 05181 05182 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 05183 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ 05184 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ 05185 05186 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 05187 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ 05188 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ 05189 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ 05190 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ 05191 05192 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ 05193 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */ 05194 05195 /***************** Bit definition for DAC_SWTRIGR register ******************/ 05196 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */ 05197 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */ 05198 05199 /***************** Bit definition for DAC_DHR12R1 register ******************/ 05200 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */ 05201 05202 /***************** Bit definition for DAC_DHR12L1 register ******************/ 05203 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */ 05204 05205 /****************** Bit definition for DAC_DHR8R1 register ******************/ 05206 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */ 05207 05208 /***************** Bit definition for DAC_DHR12R2 register ******************/ 05209 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */ 05210 05211 /***************** Bit definition for DAC_DHR12L2 register ******************/ 05212 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */ 05213 05214 /****************** Bit definition for DAC_DHR8R2 register ******************/ 05215 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */ 05216 05217 /***************** Bit definition for DAC_DHR12RD register ******************/ 05218 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ 05219 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ 05220 05221 /***************** Bit definition for DAC_DHR12LD register ******************/ 05222 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ 05223 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ 05224 05225 /****************** Bit definition for DAC_DHR8RD register ******************/ 05226 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */ 05227 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */ 05228 05229 /******************* Bit definition for DAC_DOR1 register *******************/ 05230 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */ 05231 05232 /******************* Bit definition for DAC_DOR2 register *******************/ 05233 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */ 05234 05235 /******************** Bit definition for DAC_SR register ********************/ 05236 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ 05237 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ 05238 05239 /******************************************************************************/ 05240 /* */ 05241 /* Debug MCU (DBGMCU) */ 05242 /* */ 05243 /******************************************************************************/ 05244 /******************** Bit definition for DBGMCU_IDCODE register *************/ 05245 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 05246 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 05247 05248 /******************** Bit definition for DBGMCU_CR register *****************/ 05249 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 05250 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 05251 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 05252 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 05253 05254 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 05255 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ 05256 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ 05257 05258 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 05259 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) 05260 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) 05261 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) 05262 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) 05263 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) 05264 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) 05265 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) 05266 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) 05267 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) 05268 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) 05269 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) 05270 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x04000000) 05271 05272 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 05273 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) 05274 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) 05275 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) 05276 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) 05277 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) 05278 #define DBGMCU_APB2_FZ_DBG_TIM20_STOP ((uint32_t)0x00000020) 05279 05280 /******************************************************************************/ 05281 /* */ 05282 /* DMA Controller (DMA) */ 05283 /* */ 05284 /******************************************************************************/ 05285 /******************* Bit definition for DMA_ISR register ********************/ 05286 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ 05287 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ 05288 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ 05289 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ 05290 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ 05291 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ 05292 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ 05293 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ 05294 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ 05295 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ 05296 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ 05297 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ 05298 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ 05299 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ 05300 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ 05301 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ 05302 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ 05303 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ 05304 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ 05305 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ 05306 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ 05307 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ 05308 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ 05309 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ 05310 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ 05311 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ 05312 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ 05313 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ 05314 05315 /******************* Bit definition for DMA_IFCR register *******************/ 05316 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ 05317 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ 05318 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ 05319 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ 05320 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ 05321 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ 05322 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ 05323 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ 05324 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ 05325 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ 05326 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ 05327 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ 05328 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ 05329 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ 05330 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ 05331 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ 05332 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ 05333 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ 05334 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ 05335 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ 05336 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ 05337 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ 05338 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ 05339 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ 05340 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ 05341 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ 05342 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ 05343 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ 05344 05345 /******************* Bit definition for DMA_CCR register ********************/ 05346 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ 05347 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ 05348 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ 05349 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ 05350 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ 05351 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ 05352 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ 05353 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ 05354 05355 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ 05356 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 05357 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 05358 05359 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ 05360 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05361 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05362 05363 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ 05364 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 05365 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 05366 05367 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ 05368 05369 /****************** Bit definition for DMA_CNDTR register *******************/ 05370 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ 05371 05372 /****************** Bit definition for DMA_CPAR register ********************/ 05373 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ 05374 05375 /****************** Bit definition for DMA_CMAR register ********************/ 05376 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 05377 05378 /******************************************************************************/ 05379 /* */ 05380 /* External Interrupt/Event Controller (EXTI) */ 05381 /* */ 05382 /******************************************************************************/ 05383 /******************* Bit definition for EXTI_IMR register *******************/ 05384 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ 05385 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ 05386 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ 05387 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ 05388 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ 05389 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ 05390 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ 05391 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ 05392 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ 05393 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ 05394 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ 05395 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ 05396 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ 05397 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ 05398 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ 05399 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ 05400 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ 05401 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ 05402 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ 05403 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ 05404 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ 05405 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ 05406 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ 05407 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ 05408 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ 05409 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ 05410 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ 05411 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ 05412 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ 05413 #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */ 05414 #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */ 05415 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */ 05416 /******************* Bit definition for EXTI_EMR register *******************/ 05417 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ 05418 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ 05419 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ 05420 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ 05421 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ 05422 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ 05423 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ 05424 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ 05425 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ 05426 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ 05427 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ 05428 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ 05429 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ 05430 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ 05431 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ 05432 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ 05433 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ 05434 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ 05435 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ 05436 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ 05437 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ 05438 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ 05439 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ 05440 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ 05441 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ 05442 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ 05443 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ 05444 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ 05445 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ 05446 #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */ 05447 #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */ 05448 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */ 05449 /****************** Bit definition for EXTI_RTSR register *******************/ 05450 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ 05451 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ 05452 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ 05453 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ 05454 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ 05455 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ 05456 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ 05457 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ 05458 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ 05459 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ 05460 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ 05461 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ 05462 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ 05463 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ 05464 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ 05465 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ 05466 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ 05467 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ 05468 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ 05469 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ 05470 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ 05471 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ 05472 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ 05473 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ 05474 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ 05475 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ 05476 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ 05477 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ 05478 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ 05479 #define EXTI_RTSR_TR29 ((uint32_t)0x20000000) /*!< Rising trigger event configuration bit of line 29 */ 05480 #define EXTI_RTSR_TR30 ((uint32_t)0x40000000) /*!< Rising trigger event configuration bit of line 30 */ 05481 #define EXTI_RTSR_TR31 ((uint32_t)0x80000000) /*!< Rising trigger event configuration bit of line 31 */ 05482 /****************** Bit definition for EXTI_FTSR register *******************/ 05483 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ 05484 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ 05485 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ 05486 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ 05487 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ 05488 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ 05489 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ 05490 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ 05491 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ 05492 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ 05493 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ 05494 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ 05495 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ 05496 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ 05497 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ 05498 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ 05499 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ 05500 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ 05501 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ 05502 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ 05503 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ 05504 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ 05505 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ 05506 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ 05507 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ 05508 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ 05509 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ 05510 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ 05511 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ 05512 #define EXTI_FTSR_TR29 ((uint32_t)0x20000000) /*!< Falling trigger event configuration bit of line 29 */ 05513 #define EXTI_FTSR_TR30 ((uint32_t)0x40000000) /*!< Falling trigger event configuration bit of line 30 */ 05514 #define EXTI_FTSR_TR31 ((uint32_t)0x80000000) /*!< Falling trigger event configuration bit of line 31 */ 05515 /****************** Bit definition for EXTI_SWIER register ******************/ 05516 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ 05517 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ 05518 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ 05519 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ 05520 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ 05521 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ 05522 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ 05523 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ 05524 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ 05525 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ 05526 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ 05527 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ 05528 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ 05529 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ 05530 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ 05531 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ 05532 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ 05533 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ 05534 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ 05535 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ 05536 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ 05537 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ 05538 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ 05539 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ 05540 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ 05541 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ 05542 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ 05543 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ 05544 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ 05545 #define EXTI_SWIER_SWIER29 ((uint32_t)0x20000000) /*!< Software Interrupt on line 29 */ 05546 #define EXTI_SWIER_SWIER30 ((uint32_t)0x40000000) /*!< Software Interrupt on line 30 */ 05547 #define EXTI_SWIER_SWIER31 ((uint32_t)0x80000000) /*!< Software Interrupt on line 31 */ 05548 /******************* Bit definition for EXTI_PR register ********************/ 05549 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ 05550 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ 05551 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ 05552 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ 05553 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ 05554 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ 05555 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ 05556 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ 05557 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ 05558 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ 05559 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ 05560 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ 05561 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ 05562 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ 05563 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ 05564 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ 05565 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ 05566 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ 05567 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ 05568 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ 05569 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ 05570 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ 05571 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ 05572 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ 05573 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ 05574 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ 05575 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ 05576 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ 05577 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ 05578 #define EXTI_PR_PR29 ((uint32_t)0x20000000) /*!< Pending bit for line 29 */ 05579 #define EXTI_PR_PR30 ((uint32_t)0x40000000) /*!< Pending bit for line 30 */ 05580 #define EXTI_PR_PR31 ((uint32_t)0x80000000) /*!< Pending bit for line 31 */ 05581 /******************* Bit definition for EXTI_IMR2 register ******************/ 05582 #define EXTI_IMR2_MR32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */ 05583 #define EXTI_IMR2_MR33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */ 05584 #define EXTI_IMR2_MR34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */ 05585 #define EXTI_IMR2_MR35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */ 05586 /******************* Bit definition for EXTI_EMR2 register ******************/ 05587 #define EXTI_EMR2_MR32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */ 05588 #define EXTI_EMR2_MR33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */ 05589 #define EXTI_EMR2_MR34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */ 05590 #define EXTI_EMR2_MR35 ((uint32_t)0x00000008) /*!< Event Mask on line 35 */ 05591 /****************** Bit definition for EXTI_RTSR2 register ******************/ 05592 #define EXTI_RTSR2_TR32 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 32 */ 05593 #define EXTI_RTSR2_TR33 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 33 */ 05594 /****************** Bit definition for EXTI_FTSR2 register ******************/ 05595 #define EXTI_FTSR2_TR32 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 32 */ 05596 #define EXTI_FTSR2_TR33 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 32 */ 05597 /****************** Bit definition for EXTI_SWIER2 register *****************/ 05598 #define EXTI_SWIER2_SWIER32 ((uint32_t)0x00000001) /*!< Software Interrupt on line 32 */ 05599 #define EXTI_SWIER2_SWIER33 ((uint32_t)0x00000002) /*!< Software Interrupt on line 32 */ 05600 /******************* Bit definition for EXTI_PR2 register *******************/ 05601 #define EXTI_PR2_PR32 ((uint32_t)0x00000001) /*!< Pending bit for line 32 */ 05602 #define EXTI_PR2_PR33 ((uint32_t)0x00000002) /*!< Pending bit for line 32 */ 05603 05604 /******************************************************************************/ 05605 /* */ 05606 /* FLASH */ 05607 /* */ 05608 /******************************************************************************/ 05609 /******************* Bit definition for FLASH_ACR register ******************/ 05610 #define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */ 05611 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */ 05612 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */ 05613 05614 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */ 05615 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */ 05616 #define FLASH_ACR_PRFTBS ((uint8_t)0x20) 05617 05618 /****************** Bit definition for FLASH_KEYR register ******************/ 05619 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ 05620 05621 #define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */ 05622 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ 05623 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ 05624 05625 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 05626 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ 05627 05628 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 05629 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 05630 05631 /****************** Bit definition for FLASH_SR register *******************/ 05632 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ 05633 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ 05634 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */ 05635 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ 05636 05637 /******************* Bit definition for FLASH_CR register *******************/ 05638 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ 05639 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ 05640 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ 05641 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ 05642 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ 05643 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ 05644 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ 05645 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ 05646 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ 05647 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ 05648 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */ 05649 05650 /******************* Bit definition for FLASH_AR register *******************/ 05651 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ 05652 05653 /****************** Bit definition for FLASH_OBR register *******************/ 05654 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ 05655 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ 05656 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */ 05657 05658 #ifdef STM32F303xE 05659 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ 05660 #else 05661 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ 05662 #endif /* STM32F303xE */ 05663 05664 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ 05665 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ 05666 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ 05667 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ 05668 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */ 05669 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */ 05670 05671 05672 /****************** Bit definition for FLASH_WRPR register ******************/ 05673 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ 05674 05675 /*----------------------------------------------------------------------------*/ 05676 05677 /****************** Bit definition for OB_RDP register **********************/ 05678 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ 05679 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ 05680 05681 /****************** Bit definition for OB_USER register *********************/ 05682 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ 05683 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ 05684 05685 /****************** Bit definition for FLASH_WRP0 register ******************/ 05686 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ 05687 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ 05688 05689 /****************** Bit definition for FLASH_WRP1 register ******************/ 05690 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ 05691 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ 05692 05693 /****************** Bit definition for FLASH_WRP2 register ******************/ 05694 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ 05695 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ 05696 05697 /****************** Bit definition for FLASH_WRP3 register ******************/ 05698 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ 05699 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ 05700 05701 /******************************************************************************/ 05702 /* */ 05703 /* Flexible Memory Controller */ 05704 /* */ 05705 /******************************************************************************/ 05706 /****************** Bit definition for FMC_BCR1 register *******************/ 05707 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ 05708 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ 05709 05710 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ 05711 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 05712 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 05713 05714 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ 05715 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05716 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05717 05718 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ 05719 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ 05720 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ 05721 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ 05722 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ 05723 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ 05724 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ 05725 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ 05726 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ 05727 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ 05728 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Conitnuous clock enable */ 05729 05730 /****************** Bit definition for FMC_BCR2 register *******************/ 05731 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ 05732 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ 05733 05734 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ 05735 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 05736 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 05737 05738 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ 05739 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05740 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05741 05742 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ 05743 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ 05744 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ 05745 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ 05746 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ 05747 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ 05748 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ 05749 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ 05750 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ 05751 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ 05752 05753 /****************** Bit definition for FMC_BCR3 register *******************/ 05754 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ 05755 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ 05756 05757 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ 05758 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 05759 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 05760 05761 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ 05762 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05763 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05764 05765 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ 05766 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ 05767 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ 05768 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ 05769 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ 05770 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ 05771 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ 05772 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ 05773 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ 05774 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ 05775 05776 /****************** Bit definition for FMC_BCR4 register *******************/ 05777 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ 05778 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ 05779 05780 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ 05781 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 05782 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 05783 05784 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ 05785 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05786 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05787 05788 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ 05789 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ 05790 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ 05791 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */ 05792 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ 05793 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ 05794 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ 05795 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ 05796 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ 05797 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ 05798 05799 /****************** Bit definition for FMC_BTR1 register ******************/ 05800 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 05801 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 05802 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 05803 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 05804 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 05805 05806 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 05807 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05808 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05809 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 05810 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 05811 05812 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 05813 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 05814 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 05815 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 05816 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 05817 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 05818 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 05819 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 05820 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 05821 05822 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 05823 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 05824 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 05825 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 05826 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 05827 05828 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 05829 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 05830 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 05831 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 05832 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 05833 05834 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 05835 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 05836 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 05837 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 05838 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 05839 05840 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 05841 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 05842 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 05843 05844 /****************** Bit definition for FMC_BTR2 register *******************/ 05845 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 05846 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 05847 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 05848 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 05849 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 05850 05851 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 05852 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05853 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05854 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 05855 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 05856 05857 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 05858 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 05859 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 05860 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 05861 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 05862 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 05863 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 05864 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 05865 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 05866 05867 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 05868 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 05869 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 05870 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 05871 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 05872 05873 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 05874 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 05875 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 05876 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 05877 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 05878 05879 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 05880 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 05881 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 05882 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 05883 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 05884 05885 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 05886 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 05887 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 05888 05889 /******************* Bit definition for FMC_BTR3 register *******************/ 05890 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 05891 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 05892 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 05893 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 05894 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 05895 05896 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 05897 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05898 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05899 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 05900 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 05901 05902 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 05903 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 05904 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 05905 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 05906 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 05907 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 05908 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 05909 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 05910 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 05911 05912 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 05913 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 05914 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 05915 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 05916 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 05917 05918 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 05919 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 05920 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 05921 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 05922 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 05923 05924 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 05925 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 05926 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 05927 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 05928 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 05929 05930 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 05931 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 05932 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 05933 05934 /****************** Bit definition for FMC_BTR4 register *******************/ 05935 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 05936 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 05937 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 05938 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 05939 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 05940 05941 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 05942 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05943 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05944 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 05945 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 05946 05947 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 05948 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 05949 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 05950 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 05951 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 05952 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 05953 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 05954 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 05955 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 05956 05957 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ 05958 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 05959 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 05960 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 05961 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 05962 05963 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 05964 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 05965 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 05966 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 05967 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 05968 05969 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 05970 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 05971 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 05972 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 05973 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 05974 05975 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 05976 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 05977 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 05978 05979 /****************** Bit definition for FMC_BWTR1 register ******************/ 05980 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 05981 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 05982 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 05983 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 05984 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 05985 05986 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 05987 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 05988 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 05989 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 05990 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 05991 05992 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 05993 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 05994 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 05995 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 05996 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 05997 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 05998 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 05999 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06000 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06001 06002 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 06003 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06004 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 06005 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06006 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 06007 06008 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 06009 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06010 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06011 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06012 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06013 06014 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 06015 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 06016 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 06017 06018 /****************** Bit definition for FMC_BWTR2 register ******************/ 06019 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 06020 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06021 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06022 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06023 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06024 06025 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 06026 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06027 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06028 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 06029 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 06030 06031 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 06032 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06033 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06034 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06035 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06036 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06037 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06038 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06039 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06040 06041 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 06042 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06043 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/ 06044 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06045 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 06046 06047 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 06048 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06049 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06050 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06051 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06052 06053 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 06054 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 06055 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 06056 06057 /****************** Bit definition for FMC_BWTR3 register ******************/ 06058 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 06059 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06060 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06061 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06062 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06063 06064 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 06065 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06066 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06067 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 06068 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 06069 06070 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 06071 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06072 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06073 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06074 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06075 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06076 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06077 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06078 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06079 06080 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 06081 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06082 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 06083 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06084 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 06085 06086 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 06087 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06088 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06089 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06090 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06091 06092 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 06093 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 06094 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 06095 06096 /****************** Bit definition for FMC_BWTR4 register ******************/ 06097 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ 06098 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06099 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06100 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06101 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06102 06103 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ 06104 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06105 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06106 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 06107 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 06108 06109 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ 06110 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06111 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06112 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06113 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06114 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06115 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06116 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06117 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06118 06119 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ 06120 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06121 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 06122 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06123 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ 06124 06125 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ 06126 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06127 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06128 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06129 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06130 06131 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ 06132 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ 06133 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ 06134 06135 /****************** Bit definition for FMC_PCR2 register *******************/ 06136 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ 06137 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ 06138 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */ 06139 06140 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ 06141 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06142 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06143 06144 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ 06145 06146 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ 06147 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ 06148 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ 06149 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ 06150 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ 06151 06152 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ 06153 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ 06154 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ 06155 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ 06156 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 06157 06158 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ 06159 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ 06160 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ 06161 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ 06162 06163 /****************** Bit definition for FMC_PCR3 register *******************/ 06164 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ 06165 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ 06166 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */ 06167 06168 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ 06169 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06170 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06171 06172 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ 06173 06174 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ 06175 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ 06176 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ 06177 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ 06178 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ 06179 06180 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ 06181 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ 06182 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ 06183 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ 06184 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 06185 06186 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ 06187 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ 06188 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ 06189 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ 06190 06191 /****************** Bit definition for FMC_PCR4 register *******************/ 06192 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ 06193 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */ 06194 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */ 06195 06196 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ 06197 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06198 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06199 06200 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ 06201 06202 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ 06203 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ 06204 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ 06205 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ 06206 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ 06207 06208 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ 06209 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ 06210 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ 06211 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ 06212 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 06213 06214 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */ 06215 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ 06216 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ 06217 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ 06218 06219 /******************* Bit definition for FMC_SR2 register *******************/ 06220 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ 06221 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ 06222 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ 06223 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ 06224 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ 06225 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ 06226 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ 06227 06228 /******************* Bit definition for FMC_SR3 register *******************/ 06229 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ 06230 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ 06231 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ 06232 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ 06233 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ 06234 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ 06235 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ 06236 06237 /******************* Bit definition for FMC_SR4 register *******************/ 06238 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */ 06239 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */ 06240 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */ 06241 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */ 06242 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */ 06243 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */ 06244 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */ 06245 06246 /****************** Bit definition for FMC_PMEM2 register ******************/ 06247 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ 06248 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06249 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06250 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06251 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06252 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06253 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06254 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06255 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06256 06257 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ 06258 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06259 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06260 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06261 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06262 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06263 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06264 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06265 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06266 06267 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ 06268 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06269 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06270 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06271 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06272 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06273 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06274 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06275 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06276 06277 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ 06278 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06279 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06280 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06281 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06282 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06283 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06284 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06285 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06286 06287 /****************** Bit definition for FMC_PMEM3 register ******************/ 06288 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */ 06289 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06290 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06291 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06292 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06293 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06294 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06295 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06296 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06297 06298 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */ 06299 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06300 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06301 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06302 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06303 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06304 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06305 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06306 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06307 06308 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */ 06309 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06310 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06311 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06312 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06313 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06314 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06315 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06316 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06317 06318 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */ 06319 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06320 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06321 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06322 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06323 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06324 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06325 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06326 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06327 06328 /****************** Bit definition for FMC_PMEM4 register ******************/ 06329 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */ 06330 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06331 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06332 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06333 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06334 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06335 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06336 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06337 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06338 06339 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */ 06340 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06341 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06342 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06343 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06344 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06345 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06346 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06347 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06348 06349 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */ 06350 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06351 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06352 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06353 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06354 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06355 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06356 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06357 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06358 06359 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */ 06360 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06361 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06362 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06363 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06364 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06365 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06366 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06367 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06368 06369 /****************** Bit definition for FMC_PATT2 register ******************/ 06370 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ 06371 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06372 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06373 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06374 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06375 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06376 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06377 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06378 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06379 06380 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ 06381 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06382 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06383 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06384 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06385 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06386 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06387 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06388 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06389 06390 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ 06391 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06392 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06393 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06394 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06395 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06396 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06397 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06398 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06399 06400 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ 06401 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06402 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06403 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06404 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06405 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06406 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06407 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06408 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06409 06410 /****************** Bit definition for FMC_PATT3 register ******************/ 06411 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */ 06412 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06413 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06414 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06415 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06416 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06417 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06418 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06419 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06420 06421 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */ 06422 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06423 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06424 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06425 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06426 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06427 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06428 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06429 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06430 06431 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */ 06432 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06433 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06434 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06435 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06436 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06437 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06438 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06439 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06440 06441 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */ 06442 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06443 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06444 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06445 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06446 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06447 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06448 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06449 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06450 06451 /****************** Bit definition for FMC_PATT4 register ******************/ 06452 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */ 06453 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06454 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06455 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06456 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06457 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06458 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06459 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06460 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06461 06462 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */ 06463 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06464 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06465 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06466 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06467 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06468 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06469 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06470 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06471 06472 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */ 06473 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06474 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06475 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06476 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06477 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06478 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06479 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06480 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06481 06482 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */ 06483 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06484 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06485 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06486 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06487 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06488 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06489 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06490 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06491 06492 /****************** Bit definition for FMC_PIO4 register *******************/ 06493 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */ 06494 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06495 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06496 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06497 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06498 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 06499 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 06500 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 06501 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 06502 06503 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */ 06504 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06505 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06506 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06507 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06508 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */ 06509 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */ 06510 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */ 06511 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */ 06512 06513 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */ 06514 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06515 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06516 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06517 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */ 06518 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */ 06519 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */ 06520 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */ 06521 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */ 06522 06523 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */ 06524 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06525 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06526 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06527 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */ 06528 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */ 06529 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */ 06530 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */ 06531 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */ 06532 06533 /****************** Bit definition for FMC_ECCR2 register ******************/ 06534 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ 06535 06536 /****************** Bit definition for FMC_ECCR3 register ******************/ 06537 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */ 06538 06539 /****************** Bit definition for FMC_SDCR1 register ******************/ 06540 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */ 06541 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06542 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06543 06544 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */ 06545 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 06546 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 06547 06548 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */ 06549 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06550 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06551 06552 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */ 06553 06554 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */ 06555 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */ 06556 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */ 06557 06558 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */ 06559 06560 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */ 06561 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */ 06562 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */ 06563 06564 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */ 06565 06566 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */ 06567 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */ 06568 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */ 06569 06570 /****************** Bit definition for FMC_SDCR2 register ******************/ 06571 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */ 06572 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06573 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06574 06575 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */ 06576 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 06577 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 06578 06579 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */ 06580 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06581 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06582 06583 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */ 06584 06585 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */ 06586 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */ 06587 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */ 06588 06589 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */ 06590 06591 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */ 06592 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */ 06593 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */ 06594 06595 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */ 06596 06597 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */ 06598 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */ 06599 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */ 06600 06601 /****************** Bit definition for FMC_SDTR1 register ******************/ 06602 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */ 06603 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06604 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06605 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06606 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06607 06608 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */ 06609 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06610 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06611 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 06612 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 06613 06614 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */ 06615 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06616 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06617 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06618 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06619 06620 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */ 06621 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 06622 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 06623 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 06624 06625 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */ 06626 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06627 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06628 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06629 06630 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */ 06631 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06632 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 06633 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06634 06635 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */ 06636 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06637 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06638 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06639 06640 /****************** Bit definition for FMC_SDTR2 register ******************/ 06641 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */ 06642 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06643 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06644 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 06645 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 06646 06647 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */ 06648 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 06649 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 06650 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 06651 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 06652 06653 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */ 06654 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 06655 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 06656 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 06657 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 06658 06659 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */ 06660 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 06661 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 06662 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 06663 06664 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */ 06665 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */ 06666 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */ 06667 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */ 06668 06669 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */ 06670 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 06671 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 06672 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 06673 06674 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */ 06675 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */ 06676 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */ 06677 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */ 06678 06679 /****************** Bit definition for FMC_SDCMR register ******************/ 06680 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */ 06681 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 06682 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 06683 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */ 06684 06685 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */ 06686 06687 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */ 06688 06689 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */ 06690 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ 06691 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ 06692 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */ 06693 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */ 06694 06695 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */ 06696 06697 /****************** Bit definition for FMC_SDRTR register ******************/ 06698 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */ 06699 06700 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */ 06701 06702 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interrupt enable */ 06703 06704 /****************** Bit definition for FMC_SDSR register ******************/ 06705 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */ 06706 06707 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */ 06708 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */ 06709 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */ 06710 06711 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */ 06712 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */ 06713 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */ 06714 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */ 06715 06716 /******************************************************************************/ 06717 /* */ 06718 /* General Purpose I/O (GPIO) */ 06719 /* */ 06720 /******************************************************************************/ 06721 /******************* Bit definition for GPIO_MODER register *****************/ 06722 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) 06723 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) 06724 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) 06725 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) 06726 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) 06727 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) 06728 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) 06729 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) 06730 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) 06731 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) 06732 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) 06733 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) 06734 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) 06735 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) 06736 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) 06737 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) 06738 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) 06739 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) 06740 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) 06741 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) 06742 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) 06743 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) 06744 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) 06745 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) 06746 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) 06747 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) 06748 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) 06749 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) 06750 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) 06751 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) 06752 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) 06753 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) 06754 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) 06755 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) 06756 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) 06757 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) 06758 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) 06759 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) 06760 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) 06761 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) 06762 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) 06763 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) 06764 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) 06765 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) 06766 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) 06767 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) 06768 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) 06769 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) 06770 06771 06772 /****************** Bit definition for GPIO_OTYPER register *****************/ 06773 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) 06774 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) 06775 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) 06776 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) 06777 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) 06778 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) 06779 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) 06780 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) 06781 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) 06782 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) 06783 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) 06784 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) 06785 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) 06786 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) 06787 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) 06788 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) 06789 06790 06791 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 06792 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) 06793 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) 06794 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) 06795 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) 06796 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) 06797 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) 06798 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) 06799 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) 06800 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) 06801 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) 06802 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) 06803 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) 06804 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) 06805 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) 06806 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) 06807 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) 06808 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) 06809 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) 06810 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) 06811 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) 06812 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) 06813 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) 06814 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) 06815 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) 06816 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) 06817 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) 06818 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) 06819 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) 06820 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) 06821 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) 06822 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) 06823 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) 06824 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) 06825 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) 06826 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) 06827 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) 06828 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) 06829 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) 06830 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) 06831 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) 06832 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) 06833 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) 06834 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) 06835 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) 06836 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) 06837 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) 06838 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) 06839 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) 06840 06841 /******************* Bit definition for GPIO_PUPDR register ******************/ 06842 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) 06843 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) 06844 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) 06845 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) 06846 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) 06847 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) 06848 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) 06849 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) 06850 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) 06851 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) 06852 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) 06853 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) 06854 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) 06855 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) 06856 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) 06857 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) 06858 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) 06859 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) 06860 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) 06861 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) 06862 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) 06863 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) 06864 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) 06865 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) 06866 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) 06867 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) 06868 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) 06869 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) 06870 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) 06871 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) 06872 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) 06873 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) 06874 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) 06875 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) 06876 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) 06877 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) 06878 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) 06879 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) 06880 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) 06881 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) 06882 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) 06883 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) 06884 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) 06885 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) 06886 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) 06887 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) 06888 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) 06889 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) 06890 06891 /******************* Bit definition for GPIO_IDR register *******************/ 06892 #define GPIO_IDR_0 ((uint32_t)0x00000001) 06893 #define GPIO_IDR_1 ((uint32_t)0x00000002) 06894 #define GPIO_IDR_2 ((uint32_t)0x00000004) 06895 #define GPIO_IDR_3 ((uint32_t)0x00000008) 06896 #define GPIO_IDR_4 ((uint32_t)0x00000010) 06897 #define GPIO_IDR_5 ((uint32_t)0x00000020) 06898 #define GPIO_IDR_6 ((uint32_t)0x00000040) 06899 #define GPIO_IDR_7 ((uint32_t)0x00000080) 06900 #define GPIO_IDR_8 ((uint32_t)0x00000100) 06901 #define GPIO_IDR_9 ((uint32_t)0x00000200) 06902 #define GPIO_IDR_10 ((uint32_t)0x00000400) 06903 #define GPIO_IDR_11 ((uint32_t)0x00000800) 06904 #define GPIO_IDR_12 ((uint32_t)0x00001000) 06905 #define GPIO_IDR_13 ((uint32_t)0x00002000) 06906 #define GPIO_IDR_14 ((uint32_t)0x00004000) 06907 #define GPIO_IDR_15 ((uint32_t)0x00008000) 06908 06909 /****************** Bit definition for GPIO_ODR register ********************/ 06910 #define GPIO_ODR_0 ((uint32_t)0x00000001) 06911 #define GPIO_ODR_1 ((uint32_t)0x00000002) 06912 #define GPIO_ODR_2 ((uint32_t)0x00000004) 06913 #define GPIO_ODR_3 ((uint32_t)0x00000008) 06914 #define GPIO_ODR_4 ((uint32_t)0x00000010) 06915 #define GPIO_ODR_5 ((uint32_t)0x00000020) 06916 #define GPIO_ODR_6 ((uint32_t)0x00000040) 06917 #define GPIO_ODR_7 ((uint32_t)0x00000080) 06918 #define GPIO_ODR_8 ((uint32_t)0x00000100) 06919 #define GPIO_ODR_9 ((uint32_t)0x00000200) 06920 #define GPIO_ODR_10 ((uint32_t)0x00000400) 06921 #define GPIO_ODR_11 ((uint32_t)0x00000800) 06922 #define GPIO_ODR_12 ((uint32_t)0x00001000) 06923 #define GPIO_ODR_13 ((uint32_t)0x00002000) 06924 #define GPIO_ODR_14 ((uint32_t)0x00004000) 06925 #define GPIO_ODR_15 ((uint32_t)0x00008000) 06926 06927 /****************** Bit definition for GPIO_BSRR register ********************/ 06928 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) 06929 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) 06930 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) 06931 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) 06932 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) 06933 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) 06934 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) 06935 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) 06936 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) 06937 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) 06938 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) 06939 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) 06940 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) 06941 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) 06942 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) 06943 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) 06944 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) 06945 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) 06946 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) 06947 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) 06948 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) 06949 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) 06950 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) 06951 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) 06952 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) 06953 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) 06954 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) 06955 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) 06956 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) 06957 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) 06958 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) 06959 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) 06960 06961 /****************** Bit definition for GPIO_LCKR register ********************/ 06962 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) 06963 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) 06964 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) 06965 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) 06966 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) 06967 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) 06968 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) 06969 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) 06970 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) 06971 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) 06972 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) 06973 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) 06974 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) 06975 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) 06976 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) 06977 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) 06978 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) 06979 06980 /****************** Bit definition for GPIO_AFRL register ********************/ 06981 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) 06982 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) 06983 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) 06984 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) 06985 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) 06986 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) 06987 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) 06988 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) 06989 06990 /****************** Bit definition for GPIO_AFRH register ********************/ 06991 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) 06992 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) 06993 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) 06994 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) 06995 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) 06996 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) 06997 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) 06998 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) 06999 07000 /****************** Bit definition for GPIO_BRR register *********************/ 07001 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001) 07002 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002) 07003 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004) 07004 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008) 07005 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010) 07006 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020) 07007 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040) 07008 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080) 07009 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100) 07010 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200) 07011 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400) 07012 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800) 07013 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000) 07014 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000) 07015 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000) 07016 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000) 07017 07018 /******************************************************************************/ 07019 /* */ 07020 /* Inter-integrated Circuit Interface (I2C) */ 07021 /* */ 07022 /******************************************************************************/ 07023 /******************* Bit definition for I2C_CR1 register *******************/ 07024 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ 07025 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ 07026 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ 07027 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ 07028 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ 07029 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ 07030 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ 07031 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ 07032 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ 07033 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ 07034 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ 07035 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ 07036 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ 07037 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ 07038 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ 07039 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ 07040 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ 07041 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ 07042 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ 07043 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ 07044 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ 07045 07046 /****************** Bit definition for I2C_CR2 register ********************/ 07047 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ 07048 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ 07049 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ 07050 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ 07051 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ 07052 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ 07053 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ 07054 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ 07055 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ 07056 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ 07057 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ 07058 07059 /******************* Bit definition for I2C_OAR1 register ******************/ 07060 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ 07061 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ 07062 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ 07063 07064 /******************* Bit definition for I2C_OAR2 register *******************/ 07065 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ 07066 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ 07067 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ 07068 07069 /******************* Bit definition for I2C_TIMINGR register *****************/ 07070 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ 07071 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ 07072 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ 07073 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ 07074 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ 07075 07076 /******************* Bit definition for I2C_TIMEOUTR register *****************/ 07077 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ 07078 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ 07079 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ 07080 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ 07081 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ 07082 07083 /****************** Bit definition for I2C_ISR register *********************/ 07084 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ 07085 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ 07086 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ 07087 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ 07088 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ 07089 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ 07090 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ 07091 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ 07092 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ 07093 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ 07094 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ 07095 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ 07096 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ 07097 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ 07098 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ 07099 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ 07100 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ 07101 07102 /****************** Bit definition for I2C_ICR register *********************/ 07103 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ 07104 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ 07105 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ 07106 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ 07107 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ 07108 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ 07109 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ 07110 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ 07111 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ 07112 07113 /****************** Bit definition for I2C_PECR register ********************/ 07114 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ 07115 07116 /****************** Bit definition for I2C_RXDR register *********************/ 07117 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ 07118 07119 /****************** Bit definition for I2C_TXDR register *********************/ 07120 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ 07121 07122 07123 /******************************************************************************/ 07124 /* */ 07125 /* Independent WATCHDOG (IWDG) */ 07126 /* */ 07127 /******************************************************************************/ 07128 /******************* Bit definition for IWDG_KR register ********************/ 07129 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ 07130 07131 /******************* Bit definition for IWDG_PR register ********************/ 07132 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ 07133 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ 07134 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ 07135 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ 07136 07137 /******************* Bit definition for IWDG_RLR register *******************/ 07138 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ 07139 07140 /******************* Bit definition for IWDG_SR register ********************/ 07141 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ 07142 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ 07143 #define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */ 07144 07145 /******************* Bit definition for IWDG_KR register ********************/ 07146 #define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */ 07147 07148 /******************************************************************************/ 07149 /* */ 07150 /* Power Control */ 07151 /* */ 07152 /******************************************************************************/ 07153 /******************** Bit definition for PWR_CR register ********************/ 07154 #define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */ 07155 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ 07156 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ 07157 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ 07158 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ 07159 07160 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ 07161 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ 07162 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ 07163 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ 07164 07165 /*!< PVD level configuration */ 07166 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */ 07167 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */ 07168 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */ 07169 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */ 07170 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */ 07171 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */ 07172 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */ 07173 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */ 07174 07175 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ 07176 07177 /******************* Bit definition for PWR_CSR register ********************/ 07178 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ 07179 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ 07180 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ 07181 #define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */ 07182 07183 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */ 07184 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */ 07185 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */ 07186 07187 /******************************************************************************/ 07188 /* */ 07189 /* Reset and Clock Control */ 07190 /* */ 07191 /******************************************************************************/ 07192 /******************** Bit definition for RCC_CR register ********************/ 07193 #define RCC_CR_HSION ((uint32_t)0x00000001) 07194 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 07195 07196 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 07197 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ 07198 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ 07199 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ 07200 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ 07201 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ 07202 07203 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) 07204 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ 07205 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ 07206 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ 07207 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ 07208 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ 07209 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ 07210 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ 07211 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ 07212 07213 #define RCC_CR_HSEON ((uint32_t)0x00010000) 07214 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 07215 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 07216 #define RCC_CR_CSSON ((uint32_t)0x00080000) 07217 07218 #define RCC_CR_PLLON ((uint32_t)0x01000000) 07219 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 07220 07221 /******************** Bit definition for RCC_CFGR register ******************/ 07222 /*!< SW configuration */ 07223 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ 07224 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 07225 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 07226 07227 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ 07228 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ 07229 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ 07230 07231 /*!< SWS configuration */ 07232 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ 07233 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 07234 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 07235 07236 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ 07237 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ 07238 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ 07239 07240 /*!< HPRE configuration */ 07241 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ 07242 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ 07243 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ 07244 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ 07245 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ 07246 07247 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ 07248 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ 07249 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ 07250 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ 07251 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ 07252 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ 07253 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ 07254 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ 07255 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ 07256 07257 /*!< PPRE1 configuration */ 07258 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ 07259 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 07260 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 07261 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ 07262 07263 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 07264 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ 07265 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ 07266 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ 07267 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ 07268 07269 /*!< PPRE2 configuration */ 07270 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ 07271 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ 07272 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ 07273 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ 07274 07275 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 07276 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ 07277 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ 07278 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ 07279 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ 07280 07281 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ 07282 07283 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ 07284 07285 /*!< PLLMUL configuration */ 07286 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 07287 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ 07288 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ 07289 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ 07290 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ 07291 07292 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 07293 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source 07294 (This bit and configuration is only available for STM32F303xE devices)*/ 07295 07296 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ 07297 07298 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ 07299 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ 07300 07301 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ 07302 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ 07303 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ 07304 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ 07305 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ 07306 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ 07307 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ 07308 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ 07309 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ 07310 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ 07311 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ 07312 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ 07313 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ 07314 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ 07315 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ 07316 07317 /*!< USB configuration */ 07318 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */ 07319 07320 /*!< I2S configuration */ 07321 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */ 07322 07323 /*!< MCO configuration */ 07324 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 07325 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ 07326 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ 07327 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ 07328 07329 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 07330 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */ 07331 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */ 07332 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ 07333 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ 07334 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ 07335 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ 07336 07337 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */ 07338 07339 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */ 07340 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */ 07341 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */ 07342 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */ 07343 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */ 07344 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */ 07345 #define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */ 07346 #define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */ 07347 #define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */ 07348 07349 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */ 07350 07351 /********************* Bit definition for RCC_CIR register ********************/ 07352 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ 07353 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ 07354 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ 07355 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ 07356 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ 07357 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ 07358 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ 07359 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ 07360 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ 07361 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ 07362 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ 07363 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ 07364 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ 07365 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ 07366 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ 07367 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ 07368 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ 07369 07370 /****************** Bit definition for RCC_APB2RSTR register *****************/ 07371 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */ 07372 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */ 07373 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */ 07374 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */ 07375 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ 07376 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00008000) /*!< SPI4 reset */ 07377 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */ 07378 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */ 07379 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */ 07380 #define RCC_APB2RSTR_TIM20RST ((uint32_t)0x00100000) /*!< TIM20 reset */ 07381 #define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */ 07382 07383 /****************** Bit definition for RCC_APB1RSTR register ******************/ 07384 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ 07385 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ 07386 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ 07387 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ 07388 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ 07389 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ 07390 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */ 07391 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */ 07392 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ 07393 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ 07394 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ 07395 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ 07396 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ 07397 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ 07398 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */ 07399 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */ 07400 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */ 07401 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */ 07402 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */ 07403 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */ 07404 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /*!< DAC reset */ 07405 07406 /****************** Bit definition for RCC_AHBENR register ******************/ 07407 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ 07408 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ 07409 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ 07410 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ 07411 #define RCC_AHBENR_FMCEN ((uint32_t)0x00000020) /*!< FMC clock enable */ 07412 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ 07413 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00010000) /*!< GPIOH clock enable */ 07414 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */ 07415 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */ 07416 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */ 07417 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */ 07418 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */ 07419 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */ 07420 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00800000) /*!< GPIOG clock enable */ 07421 #define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */ 07422 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */ 07423 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */ 07424 07425 /***************** Bit definition for RCC_APB2ENR register ******************/ 07426 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */ 07427 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */ 07428 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ 07429 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */ 07430 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ 07431 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00008000) /*!< SPI4 clock enable */ 07432 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */ 07433 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */ 07434 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */ 07435 #define RCC_APB2ENR_TIM20EN ((uint32_t)0x00100000) /*!< TIM20 clock enable */ 07436 #define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /*!< HRTIM1 clock enable */ 07437 07438 /****************** Bit definition for RCC_APB1ENR register ******************/ 07439 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */ 07440 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ 07441 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ 07442 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ 07443 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ 07444 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ 07445 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */ 07446 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */ 07447 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ 07448 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ 07449 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ 07450 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ 07451 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ 07452 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ 07453 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ 07454 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */ 07455 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */ 07456 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ 07457 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC clock enable */ 07458 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */ 07459 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN 07460 07461 /******************** Bit definition for RCC_BDCR register ******************/ 07462 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ 07463 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ 07464 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ 07465 07466 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 07467 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */ 07468 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */ 07469 07470 07471 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 07472 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 07473 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 07474 07475 /*!< RTC configuration */ 07476 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 07477 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ 07478 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ 07479 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 07480 07481 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ 07482 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ 07483 07484 /******************** Bit definition for RCC_CSR register *******************/ 07485 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ 07486 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ 07487 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ 07488 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ 07489 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ 07490 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ 07491 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ 07492 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ 07493 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ 07494 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ 07495 07496 /******************* Bit definition for RCC_AHBRSTR register ****************/ 07497 #define RCC_AHBRSTR_FMCRST ((uint32_t)0x00000020) /*!< FMC reset */ 07498 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00010000) /*!< GPIOH reset */ 07499 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */ 07500 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */ 07501 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */ 07502 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */ 07503 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */ 07504 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */ 07505 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00800000) /*!< GPIOG reset */ 07506 #define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */ 07507 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */ 07508 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */ 07509 07510 /******************* Bit definition for RCC_CFGR2 register ******************/ 07511 /*!< PREDIV1 configuration */ 07512 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ 07513 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 07514 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 07515 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ 07516 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ 07517 07518 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ 07519 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ 07520 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ 07521 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ 07522 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ 07523 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ 07524 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ 07525 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ 07526 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ 07527 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ 07528 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ 07529 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ 07530 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ 07531 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ 07532 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ 07533 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ 07534 07535 /*!< ADCPRE12 configuration */ 07536 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */ 07537 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */ 07538 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */ 07539 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */ 07540 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */ 07541 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */ 07542 07543 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ 07544 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */ 07545 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */ 07546 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */ 07547 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */ 07548 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */ 07549 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */ 07550 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */ 07551 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */ 07552 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */ 07553 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */ 07554 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */ 07555 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */ 07556 07557 /*!< ADCPRE34 configuration */ 07558 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */ 07559 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */ 07560 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */ 07561 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */ 07562 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */ 07563 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */ 07564 07565 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */ 07566 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */ 07567 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */ 07568 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */ 07569 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */ 07570 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */ 07571 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */ 07572 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */ 07573 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */ 07574 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */ 07575 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */ 07576 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */ 07577 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */ 07578 07579 /******************* Bit definition for RCC_CFGR3 register ******************/ 07580 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */ 07581 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 07582 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 07583 07584 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */ 07585 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ 07586 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */ 07587 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */ 07588 07589 #define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /*!< TIMSW bits */ 07590 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */ 07591 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */ 07592 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */ 07593 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */ 07594 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */ 07595 #define RCC_CFGR3_TIM20SW ((uint32_t)0x00008000) /*!< TIM20SW bits */ 07596 #define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM3SW bits */ 07597 #define RCC_CFGR3_TIM3SW ((uint32_t)0x02000000) /*!< TIM2SW bits */ 07598 07599 07600 #define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */ 07601 07602 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ 07603 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ 07604 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ 07605 07606 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */ 07607 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ 07608 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ 07609 07610 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */ 07611 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */ 07612 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */ 07613 07614 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */ 07615 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */ 07616 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */ 07617 07618 #define RCC_CFGR3_TIM2SW ((uint32_t)0x01000000) /*!< TIM3SW bits */ 07619 #define RCC_CFGR3_TIM3SW ((uint32_t)0x02000000) /*!< TIM2SW bits */ 07620 07621 /******************************************************************************/ 07622 /* */ 07623 /* Real-Time Clock (RTC) */ 07624 /* */ 07625 /******************************************************************************/ 07626 /******************** Bits definition for RTC_TR register *******************/ 07627 #define RTC_TR_PM ((uint32_t)0x00400000) 07628 #define RTC_TR_HT ((uint32_t)0x00300000) 07629 #define RTC_TR_HT_0 ((uint32_t)0x00100000) 07630 #define RTC_TR_HT_1 ((uint32_t)0x00200000) 07631 #define RTC_TR_HU ((uint32_t)0x000F0000) 07632 #define RTC_TR_HU_0 ((uint32_t)0x00010000) 07633 #define RTC_TR_HU_1 ((uint32_t)0x00020000) 07634 #define RTC_TR_HU_2 ((uint32_t)0x00040000) 07635 #define RTC_TR_HU_3 ((uint32_t)0x00080000) 07636 #define RTC_TR_MNT ((uint32_t)0x00007000) 07637 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) 07638 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) 07639 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) 07640 #define RTC_TR_MNU ((uint32_t)0x00000F00) 07641 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) 07642 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) 07643 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) 07644 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) 07645 #define RTC_TR_ST ((uint32_t)0x00000070) 07646 #define RTC_TR_ST_0 ((uint32_t)0x00000010) 07647 #define RTC_TR_ST_1 ((uint32_t)0x00000020) 07648 #define RTC_TR_ST_2 ((uint32_t)0x00000040) 07649 #define RTC_TR_SU ((uint32_t)0x0000000F) 07650 #define RTC_TR_SU_0 ((uint32_t)0x00000001) 07651 #define RTC_TR_SU_1 ((uint32_t)0x00000002) 07652 #define RTC_TR_SU_2 ((uint32_t)0x00000004) 07653 #define RTC_TR_SU_3 ((uint32_t)0x00000008) 07654 07655 /******************** Bits definition for RTC_DR register *******************/ 07656 #define RTC_DR_YT ((uint32_t)0x00F00000) 07657 #define RTC_DR_YT_0 ((uint32_t)0x00100000) 07658 #define RTC_DR_YT_1 ((uint32_t)0x00200000) 07659 #define RTC_DR_YT_2 ((uint32_t)0x00400000) 07660 #define RTC_DR_YT_3 ((uint32_t)0x00800000) 07661 #define RTC_DR_YU ((uint32_t)0x000F0000) 07662 #define RTC_DR_YU_0 ((uint32_t)0x00010000) 07663 #define RTC_DR_YU_1 ((uint32_t)0x00020000) 07664 #define RTC_DR_YU_2 ((uint32_t)0x00040000) 07665 #define RTC_DR_YU_3 ((uint32_t)0x00080000) 07666 #define RTC_DR_WDU ((uint32_t)0x0000E000) 07667 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) 07668 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) 07669 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) 07670 #define RTC_DR_MT ((uint32_t)0x00001000) 07671 #define RTC_DR_MU ((uint32_t)0x00000F00) 07672 #define RTC_DR_MU_0 ((uint32_t)0x00000100) 07673 #define RTC_DR_MU_1 ((uint32_t)0x00000200) 07674 #define RTC_DR_MU_2 ((uint32_t)0x00000400) 07675 #define RTC_DR_MU_3 ((uint32_t)0x00000800) 07676 #define RTC_DR_DT ((uint32_t)0x00000030) 07677 #define RTC_DR_DT_0 ((uint32_t)0x00000010) 07678 #define RTC_DR_DT_1 ((uint32_t)0x00000020) 07679 #define RTC_DR_DU ((uint32_t)0x0000000F) 07680 #define RTC_DR_DU_0 ((uint32_t)0x00000001) 07681 #define RTC_DR_DU_1 ((uint32_t)0x00000002) 07682 #define RTC_DR_DU_2 ((uint32_t)0x00000004) 07683 #define RTC_DR_DU_3 ((uint32_t)0x00000008) 07684 07685 /******************** Bits definition for RTC_CR register *******************/ 07686 #define RTC_CR_COE ((uint32_t)0x00800000) 07687 #define RTC_CR_OSEL ((uint32_t)0x00600000) 07688 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) 07689 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) 07690 #define RTC_CR_POL ((uint32_t)0x00100000) 07691 #define RTC_CR_COSEL ((uint32_t)0x00080000) 07692 #define RTC_CR_BCK ((uint32_t)0x00040000) 07693 #define RTC_CR_SUB1H ((uint32_t)0x00020000) 07694 #define RTC_CR_ADD1H ((uint32_t)0x00010000) 07695 #define RTC_CR_TSIE ((uint32_t)0x00008000) 07696 #define RTC_CR_WUTIE ((uint32_t)0x00004000) 07697 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) 07698 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) 07699 #define RTC_CR_TSE ((uint32_t)0x00000800) 07700 #define RTC_CR_WUTE ((uint32_t)0x00000400) 07701 #define RTC_CR_ALRBE ((uint32_t)0x00000200) 07702 #define RTC_CR_ALRAE ((uint32_t)0x00000100) 07703 #define RTC_CR_FMT ((uint32_t)0x00000040) 07704 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) 07705 #define RTC_CR_REFCKON ((uint32_t)0x00000010) 07706 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) 07707 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) 07708 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) 07709 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) 07710 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) 07711 07712 /******************** Bits definition for RTC_ISR register ******************/ 07713 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) 07714 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) 07715 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) 07716 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) 07717 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) 07718 #define RTC_ISR_TSF ((uint32_t)0x00000800) 07719 #define RTC_ISR_WUTF ((uint32_t)0x00000400) 07720 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) 07721 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) 07722 #define RTC_ISR_INIT ((uint32_t)0x00000080) 07723 #define RTC_ISR_INITF ((uint32_t)0x00000040) 07724 #define RTC_ISR_RSF ((uint32_t)0x00000020) 07725 #define RTC_ISR_INITS ((uint32_t)0x00000010) 07726 #define RTC_ISR_SHPF ((uint32_t)0x00000008) 07727 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) 07728 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) 07729 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) 07730 07731 /******************** Bits definition for RTC_PRER register *****************/ 07732 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) 07733 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) 07734 07735 /******************** Bits definition for RTC_WUTR register *****************/ 07736 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) 07737 07738 /******************** Bits definition for RTC_ALRMAR register ***************/ 07739 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) 07740 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) 07741 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) 07742 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) 07743 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) 07744 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) 07745 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) 07746 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) 07747 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) 07748 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) 07749 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) 07750 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) 07751 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) 07752 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) 07753 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) 07754 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) 07755 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) 07756 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) 07757 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) 07758 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) 07759 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) 07760 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) 07761 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) 07762 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) 07763 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) 07764 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) 07765 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) 07766 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) 07767 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) 07768 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) 07769 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) 07770 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) 07771 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) 07772 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) 07773 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) 07774 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) 07775 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) 07776 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) 07777 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) 07778 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) 07779 07780 /******************** Bits definition for RTC_ALRMBR register ***************/ 07781 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) 07782 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) 07783 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) 07784 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) 07785 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) 07786 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) 07787 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) 07788 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) 07789 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) 07790 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) 07791 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) 07792 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) 07793 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) 07794 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) 07795 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) 07796 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) 07797 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) 07798 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) 07799 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) 07800 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) 07801 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) 07802 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) 07803 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) 07804 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) 07805 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) 07806 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) 07807 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) 07808 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) 07809 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) 07810 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) 07811 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) 07812 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) 07813 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) 07814 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) 07815 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) 07816 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) 07817 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) 07818 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) 07819 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) 07820 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) 07821 07822 /******************** Bits definition for RTC_WPR register ******************/ 07823 #define RTC_WPR_KEY ((uint32_t)0x000000FF) 07824 07825 /******************** Bits definition for RTC_SSR register ******************/ 07826 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) 07827 07828 /******************** Bits definition for RTC_SHIFTR register ***************/ 07829 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) 07830 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) 07831 07832 /******************** Bits definition for RTC_TSTR register *****************/ 07833 #define RTC_TSTR_PM ((uint32_t)0x00400000) 07834 #define RTC_TSTR_HT ((uint32_t)0x00300000) 07835 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) 07836 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) 07837 #define RTC_TSTR_HU ((uint32_t)0x000F0000) 07838 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) 07839 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) 07840 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) 07841 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) 07842 #define RTC_TSTR_MNT ((uint32_t)0x00007000) 07843 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) 07844 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) 07845 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) 07846 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) 07847 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) 07848 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) 07849 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) 07850 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) 07851 #define RTC_TSTR_ST ((uint32_t)0x00000070) 07852 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) 07853 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) 07854 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) 07855 #define RTC_TSTR_SU ((uint32_t)0x0000000F) 07856 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) 07857 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) 07858 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) 07859 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) 07860 07861 /******************** Bits definition for RTC_TSDR register *****************/ 07862 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) 07863 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) 07864 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) 07865 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) 07866 #define RTC_TSDR_MT ((uint32_t)0x00001000) 07867 #define RTC_TSDR_MU ((uint32_t)0x00000F00) 07868 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) 07869 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) 07870 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) 07871 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) 07872 #define RTC_TSDR_DT ((uint32_t)0x00000030) 07873 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) 07874 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) 07875 #define RTC_TSDR_DU ((uint32_t)0x0000000F) 07876 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) 07877 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) 07878 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) 07879 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) 07880 07881 /******************** Bits definition for RTC_TSSSR register ****************/ 07882 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) 07883 07884 /******************** Bits definition for RTC_CAL register *****************/ 07885 #define RTC_CALR_CALP ((uint32_t)0x00008000) 07886 #define RTC_CALR_CALW8 ((uint32_t)0x00004000) 07887 #define RTC_CALR_CALW16 ((uint32_t)0x00002000) 07888 #define RTC_CALR_CALM ((uint32_t)0x000001FF) 07889 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) 07890 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) 07891 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) 07892 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) 07893 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) 07894 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) 07895 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) 07896 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) 07897 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) 07898 07899 /******************** Bits definition for RTC_TAFCR register ****************/ 07900 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) 07901 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) 07902 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) 07903 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) 07904 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) 07905 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) 07906 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) 07907 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) 07908 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) 07909 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) 07910 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) 07911 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) 07912 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) 07913 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) 07914 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) 07915 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) 07916 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) 07917 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) 07918 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) 07919 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) 07920 07921 /******************** Bits definition for RTC_ALRMASSR register *************/ 07922 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) 07923 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) 07924 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) 07925 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) 07926 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) 07927 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) 07928 07929 /******************** Bits definition for RTC_ALRMBSSR register *************/ 07930 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) 07931 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) 07932 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) 07933 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) 07934 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) 07935 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) 07936 07937 /******************** Bits definition for RTC_BKP0R register ****************/ 07938 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) 07939 07940 /******************** Bits definition for RTC_BKP1R register ****************/ 07941 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) 07942 07943 /******************** Bits definition for RTC_BKP2R register ****************/ 07944 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) 07945 07946 /******************** Bits definition for RTC_BKP3R register ****************/ 07947 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) 07948 07949 /******************** Bits definition for RTC_BKP4R register ****************/ 07950 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) 07951 07952 /******************** Bits definition for RTC_BKP5R register ****************/ 07953 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) 07954 07955 /******************** Bits definition for RTC_BKP6R register ****************/ 07956 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) 07957 07958 /******************** Bits definition for RTC_BKP7R register ****************/ 07959 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) 07960 07961 /******************** Bits definition for RTC_BKP8R register ****************/ 07962 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) 07963 07964 /******************** Bits definition for RTC_BKP9R register ****************/ 07965 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) 07966 07967 /******************** Bits definition for RTC_BKP10R register ***************/ 07968 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) 07969 07970 /******************** Bits definition for RTC_BKP11R register ***************/ 07971 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) 07972 07973 /******************** Bits definition for RTC_BKP12R register ***************/ 07974 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) 07975 07976 /******************** Bits definition for RTC_BKP13R register ***************/ 07977 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) 07978 07979 /******************** Bits definition for RTC_BKP14R register ***************/ 07980 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) 07981 07982 /******************** Bits definition for RTC_BKP15R register ***************/ 07983 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) 07984 07985 /******************************************************************************/ 07986 /* */ 07987 /* Serial Peripheral Interface (SPI) */ 07988 /* */ 07989 /******************************************************************************/ 07990 /******************* Bit definition for SPI_CR1 register ********************/ 07991 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ 07992 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ 07993 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ 07994 07995 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ 07996 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ 07997 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ 07998 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ 07999 08000 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ 08001 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ 08002 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ 08003 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ 08004 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ 08005 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */ 08006 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ 08007 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ 08008 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ 08009 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ 08010 08011 /******************* Bit definition for SPI_CR2 register ********************/ 08012 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */ 08013 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */ 08014 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */ 08015 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */ 08016 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */ 08017 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */ 08018 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */ 08019 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */ 08020 08021 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */ 08022 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */ 08023 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */ 08024 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */ 08025 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */ 08026 08027 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */ 08028 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */ 08029 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */ 08030 08031 /******************** Bit definition for SPI_SR register ********************/ 08032 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */ 08033 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */ 08034 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */ 08035 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */ 08036 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */ 08037 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */ 08038 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */ 08039 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */ 08040 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */ 08041 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */ 08042 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */ 08043 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */ 08044 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ 08045 08046 /******************** Bit definition for SPI_DR register ********************/ 08047 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ 08048 08049 /******************* Bit definition for SPI_CRCPR register ******************/ 08050 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ 08051 08052 /****************** Bit definition for SPI_RXCRCR register ******************/ 08053 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ 08054 08055 /****************** Bit definition for SPI_TXCRCR register ******************/ 08056 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ 08057 08058 /****************** Bit definition for SPI_I2SCFGR register *****************/ 08059 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ 08060 08061 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ 08062 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ 08063 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ 08064 08065 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ 08066 08067 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ 08068 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ 08069 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ 08070 08071 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ 08072 08073 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 08074 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ 08075 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ 08076 08077 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ 08078 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ 08079 08080 /****************** Bit definition for SPI_I2SPR register *******************/ 08081 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ 08082 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ 08083 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ 08084 08085 /******************************************************************************/ 08086 /* */ 08087 /* System Configuration(SYSCFG) */ 08088 /* */ 08089 /******************************************************************************/ 08090 /***************** Bit definition for SYSCFG_CFGR1 register *****************/ 08091 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */ 08092 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 08093 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 08094 #define SYSCFG_CFGR1_MEM_MODE_2 ((uint32_t)0x00000004) /*!< Bit 2 */ 08095 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */ 08096 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */ 08097 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */ 08098 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */ 08099 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ 08100 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ 08101 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */ 08102 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */ 08103 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */ 08104 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ 08105 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ 08106 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ 08107 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ 08108 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */ 08109 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */ 08110 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */ 08111 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */ 08112 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */ 08113 #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x01000000) /*!< I2C3 Fast mode plus */ 08114 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */ 08115 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */ 08116 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */ 08117 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */ 08118 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */ 08119 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */ 08120 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */ 08121 #define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Old define maintained for legacy purpose */ 08122 #define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /*!< Old define maintained for legacy purpose */ 08123 #define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /*!< Old define maintained for legacy purpose */ 08124 /***************** Bit definition for SYSCFG_RCR register *******************/ 08125 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */ 08126 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */ 08127 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */ 08128 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */ 08129 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */ 08130 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */ 08131 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */ 08132 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */ 08133 #define SYSCFG_RCR_PAGE8 ((uint32_t)0x00000100) /*!< ICODE SRAM Write protection page 8 */ 08134 #define SYSCFG_RCR_PAGE9 ((uint32_t)0x00000200) /*!< ICODE SRAM Write protection page 9 */ 08135 #define SYSCFG_RCR_PAGE10 ((uint32_t)0x00000400) /*!< ICODE SRAM Write protection page 10 */ 08136 #define SYSCFG_RCR_PAGE11 ((uint32_t)0x00000800) /*!< ICODE SRAM Write protection page 11 */ 08137 #define SYSCFG_RCR_PAGE12 ((uint32_t)0x00001000) /*!< ICODE SRAM Write protection page 12 */ 08138 #define SYSCFG_RCR_PAGE13 ((uint32_t)0x00002000) /*!< ICODE SRAM Write protection page 13 */ 08139 #define SYSCFG_RCR_PAGE14 ((uint32_t)0x00004000) /*!< ICODE SRAM Write protection page 14 */ 08140 #define SYSCFG_RCR_PAGE15 ((uint32_t)0x00008000) /*!< ICODE SRAM Write protection page 15 */ 08141 08142 08143 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 08144 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ 08145 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ 08146 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ 08147 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ 08148 08149 /** 08150 * @brief EXTI0 configuration 08151 */ 08152 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ 08153 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ 08154 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ 08155 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ 08156 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ 08157 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ 08158 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ 08159 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!< PH[0] pin */ 08160 08161 08162 /** 08163 * @brief EXTI1 configuration 08164 */ 08165 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ 08166 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ 08167 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ 08168 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ 08169 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ 08170 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ 08171 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ 08172 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!< PH[1] pin */ 08173 08174 /** 08175 * @brief EXTI2 configuration 08176 */ 08177 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ 08178 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ 08179 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ 08180 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ 08181 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ 08182 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ 08183 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ 08184 08185 /** 08186 * @brief EXTI3 configuration 08187 */ 08188 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ 08189 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ 08190 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ 08191 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ 08192 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ 08193 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PE[3] pin */ 08194 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ 08195 08196 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 08197 #define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ 08198 #define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ 08199 #define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ 08200 #define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ 08201 08202 /** 08203 * @brief EXTI4 configuration 08204 */ 08205 #define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ 08206 #define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ 08207 #define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ 08208 #define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ 08209 #define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ 08210 #define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ 08211 #define SYSCFG_EXTIRCR_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ 08212 #define SYSCFG_EXTIRCR_EXTI4_PH ((uint16_t)0x0007) /*!< PH[4] pin */ 08213 08214 /** 08215 * @brief EXTI5 configuration 08216 */ 08217 #define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ 08218 #define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ 08219 #define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ 08220 #define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ 08221 #define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ 08222 #define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ 08223 #define SYSCFG_EXTIRCR_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ 08224 08225 /** 08226 * @brief EXTI6 configuration 08227 */ 08228 #define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ 08229 #define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ 08230 #define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ 08231 #define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ 08232 #define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ 08233 #define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ 08234 #define SYSCFG_EXTIRCR_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ 08235 08236 /** 08237 * @brief EXTI7 configuration 08238 */ 08239 #define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ 08240 #define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ 08241 #define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ 08242 #define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ 08243 #define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ 08244 #define SYSCFG_EXTIRCR_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ 08245 #define SYSCFG_EXTIRCR_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ 08246 08247 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 08248 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ 08249 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ 08250 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ 08251 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ 08252 08253 /** 08254 * @brief EXTI8 configuration 08255 */ 08256 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ 08257 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ 08258 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ 08259 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ 08260 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ 08261 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ 08262 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ 08263 /** 08264 * @brief EXTI9 configuration 08265 */ 08266 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ 08267 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ 08268 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ 08269 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ 08270 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ 08271 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ 08272 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ 08273 08274 /** 08275 * @brief EXTI10 configuration 08276 */ 08277 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ 08278 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ 08279 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ 08280 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ 08281 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ 08282 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ 08283 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ 08284 08285 /** 08286 * @brief EXTI11 configuration 08287 */ 08288 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ 08289 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ 08290 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ 08291 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ 08292 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ 08293 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ 08294 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ 08295 08296 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 08297 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ 08298 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ 08299 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ 08300 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ 08301 08302 /** 08303 * @brief EXTI12 configuration 08304 */ 08305 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ 08306 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ 08307 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ 08308 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ 08309 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ 08310 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ 08311 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ 08312 08313 /** 08314 * @brief EXTI13 configuration 08315 */ 08316 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ 08317 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ 08318 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ 08319 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ 08320 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ 08321 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ 08322 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ 08323 08324 /** 08325 * @brief EXTI14 configuration 08326 */ 08327 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ 08328 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ 08329 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ 08330 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ 08331 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ 08332 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ 08333 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ 08334 08335 /** 08336 * @brief EXTI15 configuration 08337 */ 08338 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ 08339 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ 08340 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ 08341 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ 08342 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ 08343 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ 08344 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ 08345 08346 /***************** Bit definition for SYSCFG_CFGR2 register *****************/ 08347 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ 08348 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */ 08349 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */ 08350 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the address parity check on RAM */ 08351 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ 08352 08353 /***************** Bit definition for SYSCFG_CFGR3 register *****************/ 08354 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */ 08355 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */ 08356 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */ 08357 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */ 08358 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */ 08359 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */ 08360 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */ 08361 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */ 08362 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */ 08363 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */ 08364 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */ 08365 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */ 08366 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */ 08367 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */ 08368 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */ 08369 #define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */ 08370 #define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */ 08371 08372 /***************** Bit definition for SYSCFG_CFGR4 register *****************/ 08373 #define SYSCFG_CFGR4_ADC12_EXT2_RMP ((uint32_t)0x00000001) /*!< ADC12 regular channel EXT2 remap */ 08374 #define SYSCFG_CFGR4_ADC12_EXT3_RMP ((uint32_t)0x00000002) /*!< ADC12 regular channel EXT3 remap */ 08375 #define SYSCFG_CFGR4_ADC12_EXT5_RMP ((uint32_t)0x00000004) /*!< ADC12 regular channel EXT5 remap */ 08376 #define SYSCFG_CFGR4_ADC12_EXT13_RMP ((uint32_t)0x00000008) /*!< ADC12 regular channel EXT13 remap */ 08377 #define SYSCFG_CFGR4_ADC12_EXT15_RMP ((uint32_t)0x00000010) /*!< ADC12 regular channel EXT15 remap */ 08378 #define SYSCFG_CFGR4_ADC12_JEXT3_RMP ((uint32_t)0x00000020) /*!< ADC12 injected channel JEXT3 remap */ 08379 #define SYSCFG_CFGR4_ADC12_JEXT6_RMP ((uint32_t)0x00000040) /*!< ADC12 injected channel JEXT6 remap */ 08380 #define SYSCFG_CFGR4_ADC12_JEXT13_RMP ((uint32_t)0x00000080) /*!< ADC12 injected channel JEXT13 remap */ 08381 #define SYSCFG_CFGR4_ADC34_EXT5_RMP ((uint32_t)0x00000100) /*!< ADC34 regular channel EXT5 remap */ 08382 #define SYSCFG_CFGR4_ADC34_EXT6_RMP ((uint32_t)0x00000200) /*!< ADC34 regular channel EXT6 remap */ 08383 #define SYSCFG_CFGR4_ADC34_EXT15_RMP ((uint32_t)0x00000400) /*!< ADC34 regular channel EXT15 remap */ 08384 #define SYSCFG_CFGR4_ADC34_JEXT5_RMP ((uint32_t)0x00000800) /*!< ADC34 injected channel JEXT5 remap */ 08385 #define SYSCFG_CFGR4_ADC34_JEXT11_RMP ((uint32_t)0x00001000) /*!< ADC34 injected channel JEXT11 remap */ 08386 #define SYSCFG_CFGR4_ADC34_JEXT14_RMP ((uint32_t)0x00002000) /*!< ADC34 injected channel JEXT14 remap */ 08387 08388 /******************************************************************************/ 08389 /* */ 08390 /* TIM */ 08391 /* */ 08392 /******************************************************************************/ 08393 /******************* Bit definition for TIM_CR1 register ********************/ 08394 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ 08395 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ 08396 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ 08397 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ 08398 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ 08399 08400 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ 08401 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ 08402 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ 08403 08404 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ 08405 08406 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ 08407 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ 08408 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ 08409 08410 #define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */ 08411 08412 /******************* Bit definition for TIM_CR2 register ********************/ 08413 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ 08414 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ 08415 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ 08416 08417 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ 08418 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08419 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08420 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08421 08422 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ 08423 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ 08424 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ 08425 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ 08426 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ 08427 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ 08428 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ 08429 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ 08430 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */ 08431 #define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */ 08432 08433 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */ 08434 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ 08435 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ 08436 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ 08437 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */ 08438 08439 /******************* Bit definition for TIM_SMCR register *******************/ 08440 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */ 08441 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 08442 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 08443 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 08444 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 08445 08446 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ 08447 08448 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ 08449 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08450 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08451 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08452 08453 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ 08454 08455 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ 08456 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 08457 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 08458 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ 08459 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ 08460 08461 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ 08462 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 08463 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 08464 08465 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ 08466 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ 08467 08468 /******************* Bit definition for TIM_DIER register *******************/ 08469 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ 08470 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ 08471 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ 08472 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ 08473 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ 08474 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ 08475 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ 08476 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ 08477 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ 08478 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ 08479 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ 08480 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ 08481 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ 08482 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ 08483 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ 08484 08485 /******************** Bit definition for TIM_SR register ********************/ 08486 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ 08487 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ 08488 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ 08489 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ 08490 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ 08491 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ 08492 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ 08493 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ 08494 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */ 08495 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Over capture Flag */ 08496 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Over capture Flag */ 08497 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Over capture Flag */ 08498 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Over capture Flag */ 08499 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */ 08500 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */ 08501 08502 08503 /******************* Bit definition for TIM_EGR register ********************/ 08504 #define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */ 08505 #define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */ 08506 #define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */ 08507 #define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */ 08508 #define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */ 08509 #define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */ 08510 #define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */ 08511 #define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */ 08512 #define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */ 08513 08514 08515 /****************** Bit definition for TIM_CCMR1 register *******************/ 08516 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 08517 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 08518 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 08519 08520 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ 08521 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ 08522 08523 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 08524 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08525 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08526 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08527 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 08528 08529 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ 08530 08531 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 08532 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 08533 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 08534 08535 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ 08536 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ 08537 08538 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 08539 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 08540 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 08541 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 08542 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ 08543 08544 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ 08545 08546 /*----------------------------------------------------------------------------*/ 08547 08548 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 08549 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ 08550 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ 08551 08552 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 08553 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08554 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08555 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08556 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ 08557 08558 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 08559 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ 08560 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ 08561 08562 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 08563 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 08564 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 08565 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 08566 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ 08567 08568 /****************** Bit definition for TIM_CCMR2 register *******************/ 08569 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 08570 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 08571 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 08572 08573 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ 08574 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ 08575 08576 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 08577 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08578 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08579 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08580 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 08581 08582 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ 08583 08584 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 08585 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 08586 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 08587 08588 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ 08589 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ 08590 08591 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 08592 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 08593 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 08594 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 08595 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ 08596 08597 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ 08598 08599 /*----------------------------------------------------------------------------*/ 08600 08601 #define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 08602 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */ 08603 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */ 08604 08605 #define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 08606 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */ 08607 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */ 08608 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */ 08609 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */ 08610 08611 #define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 08612 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */ 08613 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */ 08614 08615 #define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 08616 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */ 08617 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */ 08618 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */ 08619 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */ 08620 08621 /******************* Bit definition for TIM_CCER register *******************/ 08622 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ 08623 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ 08624 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ 08625 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ 08626 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ 08627 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ 08628 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ 08629 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ 08630 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ 08631 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ 08632 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ 08633 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ 08634 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ 08635 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ 08636 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ 08637 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */ 08638 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */ 08639 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */ 08640 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */ 08641 /******************* Bit definition for TIM_CNT register ********************/ 08642 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ 08643 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */ 08644 /******************* Bit definition for TIM_PSC register ********************/ 08645 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ 08646 08647 /******************* Bit definition for TIM_ARR register ********************/ 08648 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ 08649 08650 /******************* Bit definition for TIM_RCR register ********************/ 08651 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ 08652 08653 /******************* Bit definition for TIM_CCR1 register *******************/ 08654 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ 08655 08656 /******************* Bit definition for TIM_CCR2 register *******************/ 08657 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ 08658 08659 /******************* Bit definition for TIM_CCR3 register *******************/ 08660 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ 08661 08662 /******************* Bit definition for TIM_CCR4 register *******************/ 08663 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ 08664 08665 /******************* Bit definition for TIM_CCR5 register *******************/ 08666 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */ 08667 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */ 08668 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */ 08669 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */ 08670 08671 /******************* Bit definition for TIM_CCR6 register *******************/ 08672 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */ 08673 08674 /******************* Bit definition for TIM_BDTR register *******************/ 08675 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 08676 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 08677 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 08678 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 08679 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 08680 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ 08681 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ 08682 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ 08683 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ 08684 08685 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ 08686 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ 08687 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ 08688 08689 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ 08690 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ 08691 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */ 08692 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */ 08693 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ 08694 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ 08695 08696 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */ 08697 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */ 08698 08699 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */ 08700 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */ 08701 08702 /******************* Bit definition for TIM_DCR register ********************/ 08703 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ 08704 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ 08705 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ 08706 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ 08707 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ 08708 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ 08709 08710 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ 08711 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ 08712 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ 08713 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ 08714 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ 08715 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ 08716 08717 /******************* Bit definition for TIM_DMAR register *******************/ 08718 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ 08719 08720 /******************* Bit definition for TIM16_OR register *********************/ 08721 #define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ 08722 #define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */ 08723 #define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */ 08724 08725 /******************* Bit definition for TIM1_OR register *********************/ 08726 #define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ 08727 #define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ 08728 #define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ 08729 #define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ 08730 #define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ 08731 08732 /******************* Bit definition for TIM8_OR register *********************/ 08733 #define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */ 08734 #define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ 08735 #define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ 08736 #define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */ 08737 #define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */ 08738 08739 /******************* Bit definition for TIM20_OR register *******************/ 08740 #define TIM20_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM20 ETR remap) */ 08741 #define TIM20_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ 08742 #define TIM20_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ 08743 #define TIM20_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */ 08744 #define TIM20_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */ 08745 08746 /****************** Bit definition for TIM_CCMR3 register *******************/ 08747 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */ 08748 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */ 08749 08750 #define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ 08751 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 08752 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 08753 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 08754 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ 08755 08756 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */ 08757 08758 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ 08759 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ 08760 08761 #define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 08762 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ 08763 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ 08764 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ 08765 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */ 08766 08767 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ 08768 08769 /******************************************************************************/ 08770 /* */ 08771 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 08772 /* */ 08773 /******************************************************************************/ 08774 /****************** Bit definition for USART_CR1 register *******************/ 08775 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ 08776 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ 08777 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ 08778 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ 08779 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ 08780 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ 08781 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ 08782 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ 08783 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ 08784 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ 08785 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ 08786 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ 08787 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ 08788 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ 08789 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ 08790 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ 08791 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 08792 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ 08793 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ 08794 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ 08795 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ 08796 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ 08797 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 08798 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ 08799 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ 08800 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ 08801 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ 08802 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ 08803 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ 08804 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ 08805 08806 /****************** Bit definition for USART_CR2 register *******************/ 08807 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ 08808 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ 08809 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ 08810 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ 08811 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ 08812 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ 08813 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ 08814 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ 08815 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 08816 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 08817 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ 08818 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ 08819 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ 08820 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ 08821 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ 08822 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ 08823 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ 08824 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 08825 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ 08826 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ 08827 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ 08828 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ 08829 08830 /****************** Bit definition for USART_CR3 register *******************/ 08831 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ 08832 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ 08833 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ 08834 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ 08835 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ 08836 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ 08837 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ 08838 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ 08839 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ 08840 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ 08841 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ 08842 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ 08843 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ 08844 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ 08845 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ 08846 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ 08847 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 08848 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ 08849 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ 08850 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ 08851 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 08852 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ 08853 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ 08854 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ 08855 08856 /****************** Bit definition for USART_BRR register *******************/ 08857 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ 08858 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ 08859 08860 /****************** Bit definition for USART_GTPR register ******************/ 08861 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ 08862 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */ 08863 08864 08865 /******************* Bit definition for USART_RTOR register *****************/ 08866 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ 08867 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ 08868 08869 /******************* Bit definition for USART_RQR register ******************/ 08870 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ 08871 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ 08872 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ 08873 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ 08874 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ 08875 08876 /******************* Bit definition for USART_ISR register ******************/ 08877 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ 08878 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ 08879 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ 08880 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ 08881 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ 08882 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ 08883 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ 08884 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ 08885 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ 08886 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ 08887 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ 08888 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ 08889 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ 08890 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ 08891 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ 08892 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ 08893 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ 08894 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ 08895 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ 08896 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ 08897 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ 08898 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ 08899 08900 /******************* Bit definition for USART_ICR register ******************/ 08901 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ 08902 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ 08903 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ 08904 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ 08905 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ 08906 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ 08907 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ 08908 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ 08909 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ 08910 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ 08911 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ 08912 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ 08913 08914 /******************* Bit definition for USART_RDR register ******************/ 08915 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ 08916 08917 /******************* Bit definition for USART_TDR register ******************/ 08918 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ 08919 08920 /******************************************************************************/ 08921 /* */ 08922 /* Window WATCHDOG */ 08923 /* */ 08924 /******************************************************************************/ 08925 /******************* Bit definition for WWDG_CR register ********************/ 08926 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ 08927 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */ 08928 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */ 08929 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */ 08930 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */ 08931 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */ 08932 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */ 08933 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */ 08934 08935 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */ 08936 08937 /******************* Bit definition for WWDG_CFR register *******************/ 08938 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */ 08939 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */ 08940 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */ 08941 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */ 08942 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */ 08943 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */ 08944 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */ 08945 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */ 08946 08947 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */ 08948 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */ 08949 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */ 08950 08951 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */ 08952 08953 /******************* Bit definition for WWDG_SR register ********************/ 08954 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */ 08955 08956 /******************************************************************************/ 08957 /* For a painless codes migration between the STM32F3xx device product */ 08958 /* lines, the aliases defined below are put in place to overcome the */ 08959 /* differences in the interrupt handlers and IRQn definitions. */ 08960 /* No need to update developed interrupt code when moving across */ 08961 /* product lines within the same STM32F3 Family */ 08962 /******************************************************************************/ 08963 #if defined (STM32F303xC) 08964 /* Aliases for __IRQn */ 08965 #define ADC1_IRQn ADC1_2_IRQn 08966 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn 08967 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn 08968 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn 08969 #define TIM7_DAC2_IRQn TIM7_IRQn 08970 #define COMP2_IRQn COMP1_2_3_IRQn 08971 #define COMP4_6_IRQn COMP4_5_6_IRQn 08972 08973 /* Aliases for __IRQHandler */ 08974 #define ADC1_IRQHandler ADC1_2_IRQHandler 08975 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler 08976 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler 08977 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler 08978 #define TIM7_DAC2_IRQHandler TIM7_IRQHandler 08979 #define COMP2_IRQHandler COMP1_2_3_IRQHandler 08980 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler 08981 08982 #elif defined (STM32F334x8) 08983 /* Aliases for __IRQn */ 08984 #define ADC1_IRQn ADC1_2_IRQn 08985 #define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn 08986 #define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn 08987 #define TIM6_DAC_IRQn TIM6_DAC1_IRQn 08988 #define TIM7_IRQn TIM7_DAC2_IRQn 08989 #define COMP1_2_3_IRQn COMP2_IRQn 08990 #define COMP4_5_6_IRQn COMP4_6_IRQn 08991 08992 /* Aliases for __IRQHandler */ 08993 #define ADC1_IRQHandler ADC1_2_IRQHandler 08994 #define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler 08995 #define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler 08996 #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler 08997 #define TIM7_IRQHandler TIM7_DAC2_IRQHandler 08998 #define COMP1_2_3_IRQHandler COMP2_IRQHandler 08999 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler 09000 09001 #elif defined (STM32F302x8) 09002 /* Aliases for __IRQn */ 09003 #define ADC1_2_IRQn ADC1_IRQn 09004 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn 09005 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn 09006 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn 09007 #define COMP1_2_3_IRQn COMP2_IRQn 09008 #define COMP4_5_6_IRQn COMP4_6_IRQn 09009 09010 /* Aliases for __IRQHandler */ 09011 #define ADC1_2_IRQHandler ADC1_IRQHandler 09012 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler 09013 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler 09014 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler 09015 #define COMP1_2_3_IRQHandler COMP2_IRQHandler 09016 #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler 09017 09018 #elif defined (STM32F303xE) 09019 /* Aliases for __IRQn */ 09020 #define ADC1_IRQn ADC1_2_IRQn 09021 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn 09022 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn 09023 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn 09024 #define TIM7_DAC2_IRQn TIM7_IRQn 09025 #define COMP2_IRQn COMP1_2_3_IRQn 09026 #define COMP4_6_IRQn COMP4_5_6_IRQn 09027 09028 /* Aliases for __IRQHandler */ 09029 #define ADC1_IRQHandler ADC1_2_IRQHandler 09030 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler 09031 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler 09032 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler 09033 #define TIM7_DAC2_IRQHandler TIM7_IRQHandler 09034 #define COMP2_IRQHandler COMP1_2_3_IRQHandler 09035 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler 09036 09037 #endif /* STM32F303xC */ 09038 /** 09039 * @} 09040 */ 09041 09042 /** 09043 * @} 09044 */ 09045 09046 #ifdef USE_STDPERIPH_DRIVER 09047 #include "stm32f30x_conf.h" 09048 #endif /*!< USE_STDPERIPH_DRIVER */ 09049 09050 /** @addtogroup Exported_macro 09051 * @{ 09052 */ 09053 09054 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 09055 09056 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 09057 09058 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 09059 09060 #define CLEAR_REG(REG) ((REG) = (0x0)) 09061 09062 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 09063 09064 #define READ_REG(REG) ((REG)) 09065 09066 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 09067 09068 /** 09069 * @} 09070 */ 09071 09072 #ifdef __cplusplus 09073 } 09074 #endif /* __cplusplus */ 09075 09076 #endif /* __STM32F30x_H */ 09077 09078 /** 09079 * @} 09080 */ 09081 09082 /** 09083 * @} 09084 */ 09085 09086 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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