system_stm32f30x.c

00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f30x.c
00004   * @author  MCD Application Team
00005   * @version V1.2.2
00006   * @date    27-February-2015
00007   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
00008   *          This file contains the system clock configuration for STM32F30x devices,
00009   *          and is generated by the clock configuration tool
00010   *          stm32f30x_Clock_Configuration_V1.0.0.xls
00011   *             
00012   * 1.  This file provides two functions and one global variable to be called from 
00013   *     user application:
00014   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00015   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
00016   *                      depending on the configuration made in the clock xls tool. 
00017   *                      This function is called at startup just after reset and 
00018   *                      before branch to main program. This call is made inside
00019   *                      the "startup_stm32f30x.s" file.
00020   *
00021   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00022   *                                  by the user application to setup the SysTick 
00023   *                                  timer or configure other parameters.
00024   *                                     
00025   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00026   *                                 be called whenever the core clock is changed
00027   *                                 during program execution.
00028   *
00029   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
00030   *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
00031   *    configure the system clock before to branch to main program.
00032   *
00033   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00034   *    function will do nothing and HSI still used as system clock source. User can 
00035   *    add some code to deal with this issue inside the SetSysClock() function.
00036   *
00037   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
00038   *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
00039   *    through PLL, and you are using different crystal you have to adapt the HSE
00040   *    value to your own configuration.
00041   *
00042   * 5. This file configures the system clock as follows:
00043   *=============================================================================
00044   *                         Supported STM32F30x device                          
00045   *-----------------------------------------------------------------------------
00046   *        System Clock source                    | PLL (HSE)
00047   *-----------------------------------------------------------------------------
00048   *        SYSCLK(Hz)                             | 72000000
00049   *-----------------------------------------------------------------------------
00050   *        HCLK(Hz)                               | 72000000
00051   *-----------------------------------------------------------------------------
00052   *        AHB Prescaler                          | 1
00053   *-----------------------------------------------------------------------------
00054   *        APB2 Prescaler                         | 1
00055   *-----------------------------------------------------------------------------
00056   *        APB1 Prescaler                         | 2
00057   *-----------------------------------------------------------------------------
00058   *        HSE Frequency(Hz)                      | 8000000
00059   *----------------------------------------------------------------------------
00060   *        PLLMUL                                 | 9
00061   *-----------------------------------------------------------------------------
00062   *        PREDIV                                 | 1
00063   *-----------------------------------------------------------------------------
00064   *        USB Clock                              | DISABLE
00065   *-----------------------------------------------------------------------------
00066   *        Flash Latency(WS)                      | 2
00067   *-----------------------------------------------------------------------------
00068   *        Prefetch Buffer                        | ON
00069   *-----------------------------------------------------------------------------
00070   *=============================================================================
00071   ******************************************************************************
00072   * @attention
00073   *
00074   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
00075   *
00076   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00077   * You may not use this file except in compliance with the License.
00078   * You may obtain a copy of the License at:
00079   *
00080   *        http://www.st.com/software_license_agreement_liberty_v2
00081   *
00082   * Unless required by applicable law or agreed to in writing, software 
00083   * distributed under the License is distributed on an "AS IS" BASIS, 
00084   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00085   * See the License for the specific language governing permissions and
00086   * limitations under the License.
00087   *
00088   ******************************************************************************
00089   */
00090 /** @addtogroup CMSIS
00091   * @{
00092   */
00093 
00094 /** @addtogroup stm32f30x_system
00095   * @{
00096   */  
00097   
00098 /** @addtogroup STM32F30x_System_Private_Includes
00099   * @{
00100   */
00101 
00102 #include "stm32f30x.h"
00103 
00104 /**
00105   * @}
00106   */
00107 
00108 /* Private typedef -----------------------------------------------------------*/
00109 
00110 /** @addtogroup STM32F30x_System_Private_Defines
00111   * @{
00112   */
00113 /*!< Uncomment the following line if you need to relocate your vector Table in
00114      Internal SRAM. */ 
00115 /* #define VECT_TAB_SRAM */
00116 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
00117                                   This value must be a multiple of 0x200. */  
00118 /**
00119   * @}
00120   */ 
00121 
00122 /* Private macro -------------------------------------------------------------*/
00123 
00124 /** @addtogroup STM32F30x_System_Private_Variables
00125   * @{
00126   */
00127 
00128   uint32_t SystemCoreClock = 72000000;
00129 
00130   __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00131 
00132 /**
00133   * @}
00134   */
00135 
00136 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
00137   * @{
00138   */
00139 
00140 static void SetSysClock(void);
00141 
00142 /**
00143   * @}
00144   */
00145 
00146 /** @addtogroup STM32F30x_System_Private_Functions
00147   * @{
00148   */
00149 
00150 /**
00151   * @brief  Setup the microcontroller system
00152   *         Initialize the Embedded Flash Interface, the PLL and update the 
00153   *         SystemFrequency variable.
00154   * @param  None
00155   * @retval None
00156   */
00157 void SystemInit(void)
00158 {
00159   /* FPU settings ------------------------------------------------------------*/
00160   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
00161     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
00162   #endif
00163 
00164   /* Reset the RCC clock configuration to the default reset state ------------*/
00165   /* Set HSION bit */
00166   RCC->CR |= (uint32_t)0x00000001;
00167 
00168   /* Reset CFGR register */
00169   RCC->CFGR &= 0xF87FC00C;
00170 
00171   /* Reset HSEON, CSSON and PLLON bits */
00172   RCC->CR &= (uint32_t)0xFEF6FFFF;
00173 
00174   /* Reset HSEBYP bit */
00175   RCC->CR &= (uint32_t)0xFFFBFFFF;
00176 
00177   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
00178   RCC->CFGR &= (uint32_t)0xFF80FFFF;
00179 
00180   /* Reset PREDIV1[3:0] bits */
00181   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
00182 
00183   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
00184   RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
00185   
00186   /* Disable all interrupts */
00187   RCC->CIR = 0x00000000;
00188 
00189   /* Configure the System clock source, PLL Multiplier and Divider factors, 
00190      AHB/APBx prescalers and Flash settings ----------------------------------*/
00191   SetSysClock();
00192   
00193 #ifdef VECT_TAB_SRAM
00194   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
00195 #else
00196   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
00197 #endif  
00198 }
00199 
00200 struct __FILE { int handle; };
00201 
00202 typedef struct __FILE FILE;
00203 
00204 FILE __stdout;
00205 FILE __stdin;
00206 
00207 static int serial_init_done=0;
00208 
00209 static void serial_init() {
00210     if(!serial_init_done) {
00211         serial_init_done=1;
00212         RCC->AHBENR |= RCC_AHBENR_GPIOCEN;
00213         RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
00214         GPIOC->AFR[0] = (GPIOC->AFR[0] & 0xff00ffff) | 0x770000; // alt funcs for GPIOC4 and 5 are 7
00215         GPIOC->OSPEEDR |= 0xf00; // speed high
00216         GPIOC->OTYPER &= ~0x30; // output type pp
00217         GPIOC->MODER = (GPIOC->MODER & ~0xf00) | 0xa00; // mode af
00218         GPIOC->PUPDR = (GPIOC->PUPDR & ~0xf00) | 0x500; // pull up
00219         USART1->CR1 &= ~USART_CR1_UE; // disable so we can change settings
00220         USART1->CR2 = (USART1->CR2 & ~USART_CR2_STOP); // 1 stop bit
00221         USART1->CR1 = (USART1->CR1 & 0xFFFFE6F3) | USART_CR1_RE | USART_CR1_TE;
00222         USART1->CR3 = (USART1->CR3 & 0xFFFFFCFF);
00223         USART1->BRR = SystemCoreClock/115200; // set baud rate
00224         USART1->CR1 |= USART_CR1_UE; // enable serial port
00225     }
00226 }
00227 
00228 int fputc(int ch, FILE *f) {
00229     serial_init();
00230     USART1->TDR = ch & 0x1ff;
00231     while (!(USART1->ISR & USART_ISR_TXE));
00232     return ch;
00233 }
00234 
00235 int fgetc(FILE *f) {
00236     serial_init();
00237     if(USART1->ISR & USART_ISR_ORE)
00238         USART1->ISR &= ~USART_ISR_ORE;
00239     while(!(USART1->ISR & USART_ISR_RXNE));
00240     return USART1->RDR & 0xff;
00241 }
00242 /**
00243    * @brief  Update SystemCoreClock variable according to Clock Register Values.
00244   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00245   *         be used by the user application to setup the SysTick timer or configure
00246   *         other parameters.
00247   *           
00248   * @note   Each time the core clock (HCLK) changes, this function must be called
00249   *         to update SystemCoreClock variable value. Otherwise, any configuration
00250   *         based on this variable will be incorrect.         
00251   *     
00252   * @note   - The system frequency computed by this function is not the real 
00253   *           frequency in the chip. It is calculated based on the predefined 
00254   *           constant and the selected clock source:
00255   *             
00256   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00257   *                                              
00258   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00259   *                          
00260   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
00261   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
00262   *         
00263   *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
00264   *             8 MHz) but the real value may vary depending on the variations
00265   *             in voltage and temperature.   
00266   *    
00267   *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
00268   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
00269   *              frequency of the crystal used. Otherwise, this function may
00270   *              have wrong result.
00271   *                
00272   *         - The result of this function could be not correct when using fractional
00273   *           value for HSE crystal.
00274   *     
00275   * @param  None
00276   * @retval None
00277   */
00278 void SystemCoreClockUpdate (void)
00279 {
00280   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
00281 
00282   /* Get SYSCLK source -------------------------------------------------------*/
00283   tmp = RCC->CFGR & RCC_CFGR_SWS;
00284   
00285   switch (tmp)
00286   {
00287     case 0x00:  /* HSI used as system clock */
00288       SystemCoreClock = HSI_VALUE;
00289       break;
00290     case 0x04:  /* HSE used as system clock */
00291       SystemCoreClock = HSE_VALUE;
00292       break;
00293     case 0x08:  /* PLL used as system clock */
00294       /* Get PLL clock source and multiplication factor ----------------------*/
00295       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00296       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00297       pllmull = ( pllmull >> 18) + 2;
00298       
00299       if (pllsource == 0x00)
00300       {
00301         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00302         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00303       }
00304       else
00305       {
00306         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00307         /* HSE oscillator clock selected as PREDIV1 clock entry */
00308         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
00309       }      
00310       break;
00311     default: /* HSI used as system clock */
00312       SystemCoreClock = HSI_VALUE;
00313       break;
00314   }
00315   /* Compute HCLK clock frequency ----------------*/
00316   /* Get HCLK prescaler */
00317   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00318   /* HCLK clock frequency */
00319   SystemCoreClock >>= tmp;  
00320 }
00321 
00322 /**
00323   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
00324   *               AHB/APBx prescalers and Flash settings
00325   * @note   This function should be called only once the RCC clock configuration  
00326   *         is reset to the default reset state (done in SystemInit() function).             
00327   * @param  None
00328   * @retval None
00329   */
00330 static void SetSysClock(void)
00331 {
00332   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00333 
00334 /******************************************************************************/
00335 /*            PLL (clocked by HSE) used as System clock source                */
00336 /******************************************************************************/
00337 
00338   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
00339   /* Enable HSE */
00340   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00341  
00342   /* Wait till HSE is ready and if Time out is reached exit */
00343   do
00344   {
00345     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00346     StartUpCounter++;
00347   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00348 
00349   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00350   {
00351     HSEStatus = (uint32_t)0x01;
00352   }
00353   else
00354   {
00355     HSEStatus = (uint32_t)0x00;
00356   }
00357 
00358   if (HSEStatus == (uint32_t)0x01)
00359   {
00360     /* Enable Prefetch Buffer and set Flash Latency */
00361     FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
00362  
00363      /* HCLK = SYSCLK / 1 */
00364      RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00365        
00366      /* PCLK2 = HCLK / 1 */
00367      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
00368      
00369      /* PCLK1 = HCLK / 2 */
00370      RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
00371 
00372     /* PLL configuration */
00373     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00374     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
00375 
00376     /* Enable PLL */
00377     RCC->CR |= RCC_CR_PLLON;
00378 
00379     /* Wait till PLL is ready */
00380     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00381     {
00382     }
00383     
00384     /* Select PLL as system clock source */
00385     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00386     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
00387 
00388     /* Wait till PLL is used as system clock source */
00389     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
00390     {
00391     }
00392   }
00393   else
00394   { /* If HSE fails to start-up, the application will have wrong clock
00395          configuration. User can add here some code to deal with this error */
00396   }
00397 }
00398 
00399 /**
00400   * @}
00401   */
00402 
00403 /**
00404   * @}
00405   */
00406 
00407 /**
00408   * @}
00409   */
00410 
00411 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
00412