Diff: video.c

Revision:

5:594c9712697c

Parent:

4:de45d218ed3c

Child:

6:f16335989076

--- a/video.c	Wed May 16 02:48:27 2018 +0000
+++ b/video.c	Thu May 17 00:59:01 2018 +0000
@@ -42,9 +42,9 @@
 
 int fboffset=0;
 
-static volatile u16 vline = 0;				/* The current line being drawn */
-static volatile u32 vflag = 0;				/* When 1, the DMA request can draw on the screen */
-static volatile u32 vdraw = 0;				/* Used to increment vline every 3 drawn lines */
+__attribute__ ((section ("ccmram"))) static volatile u16 vline = 0;				/* The current line being drawn */
+__attribute__ ((section ("ccmram"))) static volatile u32 vflag = 0;				/* When 1, the DMA request can draw on the screen */
+__attribute__ ((section ("ccmram"))) static volatile u32 vdraw = 0;				/* Used to increment vline every 3 drawn lines */
 
 #define GPIO_MODE_INPUT 0
 #define GPIO_MODE_OUTPUT 1
@@ -125,7 +125,7 @@
 
 	TimerPeriod = 2048;
 	Channel1Pulse = 144;		/* HSYNC */
-	Channel2Pulse = 364; 		/* HSYNC + BACK PORCH */
+	Channel2Pulse = 360; 		/* HSYNC + BACK PORCH */
 	
 	TIM1->CR1 &= ~TIM_CR1_CEN;
 	TIM1->PSC=0;
@@ -136,26 +136,30 @@
 	TIM1->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 	// set output compare 1 to PWM mode with preload
 	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)) | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
+	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S)) | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2CE;
 	TIM1->CCR1=Channel1Pulse;
 	TIM1->CCR2=Channel2Pulse;
-	TIM1->CCR2 |= TIM_CR2_OIS1; // output idle state set
+//	TIM1->CCR3=Channel2Pulse+100;
+	//TIM1->CCR2 |= TIM_CR2_OIS1; // output idle state set
+//	TIM1->CCR3 |= TIM_CR2_OIS1; 
 	// enable Capture and Compare 1
-	TIM1->CCER |=  TIM_CCER_CC1E |  TIM_CCER_CC2E | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
+	TIM1->CCER |=  TIM_CCER_CC1E |  TIM_CCER_CC2E  | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
 	// main output enable
     TIM1->BDTR |= TIM_BDTR_MOE; 
 	
 	TIM1->SMCR |= TIM_SMCR_MSM; // master slave mode
 	
-	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1;// TIM_TRGOSource_Update mode
+	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (3<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
 	
 	TIM8->CR1 &= ~TIM_CR1_CEN;
-	TIM8->PSC=2;
-	TIM8->ARR=2;
+	TIM8->CR1 |= TIM_CR1_ARPE;
+	TIM8->PSC=0;
+	TIM8->ARR=8;
 	TIM8->CNT=0;
 	//TIM16->CR1 |= TIM_CR1_OPM; 
 	
 	TIM8->DIER |= TIM_DIER_UDE;
-	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 4 ;
+	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 ;
 	//TIM16->SMCR |= TIM_SMCR_MSM;
 	//TIM16->CR2 = (TIM16->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1;// TIM_TRGOSource_Update mode
 	
@@ -177,7 +181,7 @@
 
 	/* VSYNC (TIM2_CH2) and VSYNC_BACKPORCH (TIM2_CH3) */
 	/* Channel 2 and 3 Configuration in PWM mode */
-	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0
+	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// triggered slave mode trigger source 0
 	
 	
 	TimerPeriod = 625;		/* Vertical lines */
@@ -203,15 +207,15 @@
 	// main output enable
     TIM2->BDTR |= TIM_BDTR_MOE; 
 
-	NVIC->IP[TIM2_IRQn]=10; // Interrupt Priority, lower is higher priority
+	NVIC->IP[TIM2_IRQn]=32; // Interrupt Priority, lower is higher priority
 	NVIC->ISER[TIM2_IRQn >> 0x05] = 1 << (TIM2_IRQn & 0x1F); // Interrupt enable
 	
 	TIM2->DIER |= TIM_DIER_CC3IE;
 	
-	NVIC->IP[TIM1_CC_IRQn]=1; // Interrupt Priority, lower is higher priority
+	NVIC->IP[TIM1_CC_IRQn]=0; // Interrupt Priority, lower is higher priority
 	NVIC->ISER[TIM1_CC_IRQn >> 0x05] = 1 << (TIM1_CC_IRQn & 0x1F); // Interrupt enable
 
-	TIM1->DIER |= TIM_DIER_CC2IE;
+//	TIM1->DIER |= TIM_DIER_CC2IE;
 
 	TIM2->CR1 |= TIM_CR1_CEN;
 	TIM1->CR1 |= TIM_CR1_CEN;
@@ -251,9 +255,11 @@
 
 __attribute__ ((section ("ccmram"))) void TIM1_CC_IRQHandler(void) {
 	if (vflag) {
-		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
+		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// 0x3093;
 //		TIM8->CNT=0;//TIM8->ARR;
+		
 		TIM8->CR1 |= TIM_CR1_CEN;
+		//TIM8->CNT=7;//4-(TIM1->CNT&7);
 	}
 	TIM1->SR = 0xFFFB; //~TIM_IT_CC2;
 }
@@ -266,9 +272,9 @@
 __attribute__ ((section ("ccmram"))) void TIM2_IRQHandler(void) {
 	vflag = 1;
 	TIM2->SR = 0xFFF7; //~TIM_IT_CC3;
-//		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
+		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
 	//	TIM8->CNT=0;
-		TIM8->CR1 |= TIM_CR1_CEN;
+	//	TIM8->CR1 |= TIM_CR1_CEN;
 
 }
 
@@ -280,12 +286,14 @@
 //__attribute__((interrupt)) 
 __attribute__ ((section ("ccmram"))) void DMA2_Channel1_IRQHandler(void) {	
 	DMA2->IFCR = DMA_ISR_TCIF1;
-	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;// 0x3093; 0x92;// | (1<<10) | (1<<8);
+	TIM8->CR1 &= ~TIM_CR1_CEN;
+	TIM8->CNT=0;
+	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;// | DMA_CCR_EN;// 0x3093; 0x92;// | (1<<10) | (1<<8);
 	DMA2_Channel1->CNDTR = HTOTAL;
-	TIM8->CR1 &= ~TIM_CR1_CEN;
+	
 	
 	vdraw++;
-	if (vdraw == 4) {
+	if (vdraw == 3) {
 		vdraw = 0;
 		vline++;
 		if (vline == VID_VSIZE) {
@@ -295,6 +303,9 @@
 			DMA2_Channel1->CMAR += HTOTAL;
 		}
 	}
+	if(vflag)
+		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
+	
 }
 __attribute__ ((section ("ccmram"))) void vidNextBuffer(void) {
 	    char *fp=(unsigned *)fb[0];