Colour_Video_Demo - Demo of low res colour vga video for stm32f3 disc…

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Demo of low res colour vga video for stm32f3 discovery board
Dependencies: STM32F3-Discovery-minimal
Fork of Space_Invaders_Demo by Martin Johnson
Diff: video.c

Revision:: 7:513afc954d6e
Parent:: 6:f16335989076
Child:: 8:34fb94209517
--- a/video.c	Thu May 17 21:27:22 2018 +0000
+++ b/video.c	Mon May 28 10:38:27 2018 +0000
@@ -123,9 +123,10 @@
 	
 	*/
 
-	TimerPeriod = 2048;
-	Channel1Pulse = 144;		/* HSYNC */
-	Channel2Pulse = 360; 		/* HSYNC + BACK PORCH */
+	TimerPeriod = 2288;//2303;
+	Channel1Pulse = 274;//274;//274;//277;		/* HSYNC */
+	//Channel2Pulse = 850;//410;//348; 		/* HSYNC + BACK PORCH */
+	Channel3Pulse = 392;//412;//394;
 	
 	TIM1->CR1 &= ~TIM_CR1_CEN;
 	TIM1->PSC=0;
@@ -133,36 +134,56 @@
 	TIM1->CNT=0;
 	
 	// disable Capture and Compare 1 and 2
-	TIM1->CCER &= ~(TIM_CCER_CC1E | TIM_CCER_CC2E);
+	TIM1->CCER &= ~(TIM_CCER_CC1E);// | TIM_CCER_CC2E);
 	// set output compare 1 to PWM mode with preload
 	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)) | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
-	TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S)) | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2CE;
+	//TIM1->CCMR1 = (TIM1->CCMR1 & ~(TIM_CCMR1_OC2M | TIM_CCMR1_CC2S)) | TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2CE;
 	TIM1->CCR1=Channel1Pulse;
-	TIM1->CCR2=Channel2Pulse;
+//	TIM1->CCR2=Channel2Pulse;
 //	TIM1->CCR3=Channel2Pulse+100;
 	//TIM1->CCR2 |= TIM_CR2_OIS1; // output idle state set
-//	TIM1->CCR3 |= TIM_CR2_OIS1; 
+	//TIM1->CR2 |= TIM_CR2_OIS1; 
 	// enable Capture and Compare 1
-	TIM1->CCER |=  TIM_CCER_CC1E |  TIM_CCER_CC2E  | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
+	TIM1->CCER |=  TIM_CCER_CC1E | TIM_CCER_CC1P ;// | TIM_CCER_CC2E  | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
 	// main output enable
     TIM1->BDTR |= TIM_BDTR_MOE; 
 	
 	TIM1->SMCR |= TIM_SMCR_MSM; // master slave mode
 	
-	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (3<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
+	TIM1->CR2 = (TIM1->CR2 & ~TIM_CR2_MMS) | (2<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
 	
 	TIM8->CR1 &= ~TIM_CR1_CEN;
 	TIM8->CR1 |= TIM_CR1_ARPE;
 	TIM8->PSC=0;
-	TIM8->ARR=8;
+	TIM8->ARR=11;
 	TIM8->CNT=0;
 	//TIM16->CR1 |= TIM_CR1_OPM; 
 	
 	TIM8->DIER |= TIM_DIER_UDE;
-	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 4 ;
+	
+	TIM8->SMCR=TIM8->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 | (3<<4); // trigger mode from itr3 (tim3)
 	//TIM16->SMCR |= TIM_SMCR_MSM;
 	//TIM16->CR2 = (TIM16->CR2 & ~TIM_CR2_MMS) | TIM_CR2_MMS_1;// TIM_TRGOSource_Update mode
 	
+	TIM3->CR1 &= ~TIM_CR1_CEN;
+	TIM3->PSC=0;
+	TIM3->ARR=Channel3Pulse;//TimerPeriod/2;
+	TIM3->CNT=0;
+	
+	// disable Capture and Compare 1 and 2
+//	TIM3->CCER &= ~(TIM_CCER_CC1E);
+	// set output compare 1 to PWM mode with preload
+//	TIM3->CCMR1 = (TIM3->CCMR1 & ~(TIM_CCMR1_OC1M | TIM_CCMR1_CC1S)) | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1;
+//	TIM3->CCR1=Channel3Pulse;
+
+	TIM3->CR1 |= TIM_CR1_OPM; 
+//	TIM3->CCER |=  TIM_CCER_CC1E | TIM_CCER_CC1P; // output polarity low
+	
+	//TIM3->SMCR |= TIM_SMCR_MSM; // master slave mode
+	TIM3->SMCR=TIM3->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 6 ; // trigger mode from itr0 (tim1)
+	
+	TIM3->CR2 = (TIM3->CR2 & ~TIM_CR2_MMS) | (2<<4); ///*TIM_CR2_MMS_2 |*/ TIM_CR2_MMS_1 /*| TIM_CR2_MMS_0*/;// TIM_TRGOSource_Update mode
+
 	/*
 		Vertical timing
 		---------------
@@ -181,12 +202,12 @@
 
 	/* VSYNC (TIM2_CH2) and VSYNC_BACKPORCH (TIM2_CH3) */
 	/* Channel 2 and 3 Configuration in PWM mode */
-	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// triggered slave mode trigger source 0
+	TIM2->SMCR=TIM2->SMCR & ~(TIM_SMCR_SMS | TIM_SMCR_TS) | 5 ;// gated slave mode trigger source 0
 	
 	
-	TimerPeriod = 625;		/* Vertical lines */
+	TimerPeriod = 525;		/* Vertical lines */
 	Channel2Pulse = 2;		/* Sync pulse */
-	Channel3Pulse = 24;		/* Sync pulse + Back porch */
+	Channel3Pulse = 35;		/* Sync pulse + Back porch */
 
 	TIM2->CR1 &= ~TIM_CR1_CEN;
 	TIM2->PSC=0;
@@ -200,7 +221,8 @@
 	TIM2->CCR2=Channel2Pulse;
 	TIM2->CCR3=Channel3Pulse;
 	
-//	TIM2->CCR2 |= TIM_CR2_OIS1; // output idle state set
+	
+	TIM2->CR2 &= ~TIM_CR2_OIS1; // output idle state set
 	// enable Capture and Compare 2 and 3
 	TIM2->CCER |=  TIM_CCER_CC2E |  TIM_CCER_CC3E | TIM_CCER_CC1P | TIM_CCER_CC2P; // output polarity low
 	
@@ -215,7 +237,7 @@
 	NVIC->IP[TIM1_CC_IRQn]=0; // Interrupt Priority, lower is higher priority
 	NVIC->ISER[TIM1_CC_IRQn >> 0x05] = 1 << (TIM1_CC_IRQn & 0x1F); // Interrupt enable
 
-	TIM1->DIER |= TIM_DIER_CC2IE;
+	//TIM1->DIER |= TIM_DIER_CC2IE;
 
 	TIM2->CR1 |= TIM_CR1_CEN;
 	TIM1->CR1 |= TIM_CR1_CEN;
@@ -224,8 +246,8 @@
 void DMA_Configuration(void) {
 	//gpio_set_af(GPIOA,7,5,GPIO_OUTPUT_PUSH_PULL, GPIO_NO_PULL, GPIO_SPEED_HIGH);
 	
-	GPIOD->PUPDR = (GPIOD->PUPDR & ~0xffff) | 0;//xaaaa; // pull down (1010)
-	GPIOD->OSPEEDR = (GPIOD->OSPEEDR & ~(0xffff)) | 0xffff;
+	GPIOD->PUPDR = (GPIOD->PUPDR & ~0xffff);//0xaaaa; // pull down (1010)
+	GPIOD->OSPEEDR = (GPIOD->OSPEEDR & ~0xffff) | 0xffff;
 	
 	
 	RCC->AHBENR |= RCC_AHBENR_DMA2EN;
@@ -233,7 +255,7 @@
     DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;
 //    DMA1_Channel3->CCR =  DMA_CCR_PINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_MEM2MEM;
     // bytes to transfer
-    DMA2_Channel1->CNDTR = HTOTAL*2;
+    DMA2_Channel1->CNDTR = HTOTAL;
     // peripheral address
     DMA2_Channel1->CPAR =(uint32_t) &GPIOD->ODR;
     // memory address
@@ -252,8 +274,11 @@
 //	and start the DMA to output a single frame buffer line through the GPIO device.
 //*****************************************************************************
 //__attribute__((interrupt)) 
-
+/*
 __attribute__ ((section ("ccmram"))) void TIM1_CC_IRQHandler(void) {
+	//GPIOD->MODER=0x5555;
+	GPIOD->MODER = (GPIOD->MODER&0xffff0000) | 0x5555; // output mode for PD0-7
+	
 	if (vflag) {
 		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// 0x3093;
 //		TIM8->CNT=0;//TIM8->ARR;
@@ -262,7 +287,10 @@
 		//TIM8->CNT=7;//4-(TIM1->CNT&7);
 	}
 	TIM1->SR = 0xFFFB; //~TIM_IT_CC2;
+	
+	TIM1->SR = 0xFFFB;
 }
+*/
 
 //*****************************************************************************
 //	This irq is generated at the end of the vertical back porch.
@@ -272,9 +300,17 @@
 __attribute__ ((section ("ccmram"))) void TIM2_IRQHandler(void) {
 	vflag = 1;
 	TIM2->SR = 0xFFF7; //~TIM_IT_CC3;
-		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;;// 0x3093;
-	//	TIM8->CNT=0;
-	//	TIM8->CR1 |= TIM_CR1_CEN;
+	TIM8->CR1 &= ~TIM_CR1_CEN;
+	//DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE ;
+	//DMA2_Channel1->CNDTR = HTOTAL;
+	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;// 0x3093;
+	//GPIOD->MODER=0;
+	//GPIOD->MODER = (GPIOD->MODER&0xffff0000); // input mode for PD0-7
+//	GPIOD->ODR=0x00;
+	//GPIOD->MODER=0xaaaa;
+		TIM8->CNT=0;
+		GPIOD->ODR=0x00;
+		
 
 }
 
@@ -288,12 +324,13 @@
 	DMA2->IFCR = DMA_ISR_TCIF1;
 	TIM8->CR1 &= ~TIM_CR1_CEN;
 	TIM8->CNT=0;
+	//while(DMA2_Channel1->CNDTR);
 	DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE;// | DMA_CCR_EN;// 0x3093; 0x92;// | (1<<10) | (1<<8);
 	DMA2_Channel1->CNDTR = HTOTAL;
 	
 	
 	vdraw++;
-	if (vdraw == 3) {
+	if (vdraw == 2) {
 		vdraw = 0;
 		vline++;
 		if (vline == VID_VSIZE) {
@@ -303,16 +340,24 @@
 			DMA2_Channel1->CMAR += HTOTAL;
 		}
 	}
-//	if(vflag)
-//		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
+	//GPIOD->ODR=0x00;
+	if(vflag)
+		DMA2_Channel1->CCR = DMA_CCR_DIR | DMA_CCR_MINC  | DMA_CCR_PL_1 | DMA_CCR_PL_0 | DMA_CCR_TCIE | DMA_CCR_EN;
+	
 	
 }
-__attribute__ ((section ("ccmram"))) void vidNextBuffer(void) {
+__attribute__ ((section ("ccmram"))) void vidNextBuffer1(void) {
 	    char *fp=(unsigned *)fb[0];
 	    for(int i=0;i<VID_VSIZE*HTOTAL;i++)
 	    	*fp++=(*fp>>4);//&0xf0f0f0f;
 }
 
+__attribute__ ((section ("ccmram"))) void vidNextBuffer(void) {
+	    unsigned *fp=(unsigned *)fb[0];
+	    for(int i=0;i<VID_VSIZE*HTOTAL/4;i++)
+	    	*fp++=(*fp>>4)&0xf0f0f0f;
+}
+
 __attribute__ ((section ("ccmram"))) void waitForRefresh(void) {
 	while(vflag) __wfi();
 }
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Type:	Program
Created:	16 May 2018
Imports:	4
Forks:	0
Commits:	18
Dependents:	0
Dependencies:	1
Followers:	1
Diff: video.c

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