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mbed-dev/cmsis/core_cm33.h@60:8399756e1ba1, 2021-01-22 (annotated)

Committer:: MartinGurtner
Date:: Fri Jan 22 13:10:37 2021 +0000
Revision:: 60:8399756e1ba1

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User	Revision	Line number	New contents of line
MartinGurtner	60:8399756e1ba1	1	/************************************************************************//
MartinGurtner	60:8399756e1ba1	2	* @file core_cm33.h
MartinGurtner	60:8399756e1ba1	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
MartinGurtner	60:8399756e1ba1	4	* @version V5.0.2
MartinGurtner	60:8399756e1ba1	5	* @date 13. February 2017
MartinGurtner	60:8399756e1ba1	6	******************************************************************************/
MartinGurtner	60:8399756e1ba1	7	/*
MartinGurtner	60:8399756e1ba1	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
MartinGurtner	60:8399756e1ba1	9	*
MartinGurtner	60:8399756e1ba1	10	* SPDX-License-Identifier: Apache-2.0
MartinGurtner	60:8399756e1ba1	11	*
MartinGurtner	60:8399756e1ba1	12	* Licensed under the Apache License, Version 2.0 (the License); you may
MartinGurtner	60:8399756e1ba1	13	* not use this file except in compliance with the License.
MartinGurtner	60:8399756e1ba1	14	* You may obtain a copy of the License at
MartinGurtner	60:8399756e1ba1	15	*
MartinGurtner	60:8399756e1ba1	16	* www.apache.org/licenses/LICENSE-2.0
MartinGurtner	60:8399756e1ba1	17	*
MartinGurtner	60:8399756e1ba1	18	* Unless required by applicable law or agreed to in writing, software
MartinGurtner	60:8399756e1ba1	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
MartinGurtner	60:8399756e1ba1	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
MartinGurtner	60:8399756e1ba1	21	* See the License for the specific language governing permissions and
MartinGurtner	60:8399756e1ba1	22	* limitations under the License.
MartinGurtner	60:8399756e1ba1	23	*/
MartinGurtner	60:8399756e1ba1	24
MartinGurtner	60:8399756e1ba1	25	#if defined ( __ICCARM__ )
MartinGurtner	60:8399756e1ba1	26	#pragma system_include /* treat file as system include file for MISRA check */
MartinGurtner	60:8399756e1ba1	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
MartinGurtner	60:8399756e1ba1	28	#pragma clang system_header /* treat file as system include file */
MartinGurtner	60:8399756e1ba1	29	#endif
MartinGurtner	60:8399756e1ba1	30
MartinGurtner	60:8399756e1ba1	31	#ifndef __CORE_CM33_H_GENERIC
MartinGurtner	60:8399756e1ba1	32	#define __CORE_CM33_H_GENERIC
MartinGurtner	60:8399756e1ba1	33
MartinGurtner	60:8399756e1ba1	34	#include <stdint.h>
MartinGurtner	60:8399756e1ba1	35
MartinGurtner	60:8399756e1ba1	36	#ifdef __cplusplus
MartinGurtner	60:8399756e1ba1	37	extern "C" {
MartinGurtner	60:8399756e1ba1	38	#endif
MartinGurtner	60:8399756e1ba1	39
MartinGurtner	60:8399756e1ba1	40	/**
MartinGurtner	60:8399756e1ba1	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
MartinGurtner	60:8399756e1ba1	42	CMSIS violates the following MISRA-C:2004 rules:
MartinGurtner	60:8399756e1ba1	43
MartinGurtner	60:8399756e1ba1	44	\li Required Rule 8.5, object/function definition in header file.<br>
MartinGurtner	60:8399756e1ba1	45	Function definitions in header files are used to allow 'inlining'.
MartinGurtner	60:8399756e1ba1	46
MartinGurtner	60:8399756e1ba1	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
MartinGurtner	60:8399756e1ba1	48	Unions are used for effective representation of core registers.
MartinGurtner	60:8399756e1ba1	49
MartinGurtner	60:8399756e1ba1	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
MartinGurtner	60:8399756e1ba1	51	Function-like macros are used to allow more efficient code.
MartinGurtner	60:8399756e1ba1	52	*/
MartinGurtner	60:8399756e1ba1	53
MartinGurtner	60:8399756e1ba1	54
MartinGurtner	60:8399756e1ba1	55	/*******************************************************************************
MartinGurtner	60:8399756e1ba1	56	* CMSIS definitions
MartinGurtner	60:8399756e1ba1	57	******************************************************************************/
MartinGurtner	60:8399756e1ba1	58	/**
MartinGurtner	60:8399756e1ba1	59	\ingroup Cortex_M33
MartinGurtner	60:8399756e1ba1	60	@{
MartinGurtner	60:8399756e1ba1	61	*/
MartinGurtner	60:8399756e1ba1	62
MartinGurtner	60:8399756e1ba1	63	/* CMSIS CM33 definitions */
MartinGurtner	60:8399756e1ba1	64	#define __CM33_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
MartinGurtner	60:8399756e1ba1	65	#define __CM33_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
MartinGurtner	60:8399756e1ba1	66	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
MartinGurtner	60:8399756e1ba1	67	__CM33_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
MartinGurtner	60:8399756e1ba1	68
MartinGurtner	60:8399756e1ba1	69	#define __CORTEX_M (33U) /!< Cortex-M Core /
MartinGurtner	60:8399756e1ba1	70
MartinGurtner	60:8399756e1ba1	71	/** __FPU_USED indicates whether an FPU is used or not.
MartinGurtner	60:8399756e1ba1	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
MartinGurtner	60:8399756e1ba1	73	*/
MartinGurtner	60:8399756e1ba1	74	#if defined ( __CC_ARM )
MartinGurtner	60:8399756e1ba1	75	#if defined __TARGET_FPU_VFP
MartinGurtner	60:8399756e1ba1	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	77	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	78	#else
MartinGurtner	60:8399756e1ba1	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	80	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	81	#endif
MartinGurtner	60:8399756e1ba1	82	#else
MartinGurtner	60:8399756e1ba1	83	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	84	#endif
MartinGurtner	60:8399756e1ba1	85
MartinGurtner	60:8399756e1ba1	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
MartinGurtner	60:8399756e1ba1	87	#if defined __ARM_PCS_VFP
MartinGurtner	60:8399756e1ba1	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	89	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	90	#else
MartinGurtner	60:8399756e1ba1	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	92	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	93	#endif
MartinGurtner	60:8399756e1ba1	94	#else
MartinGurtner	60:8399756e1ba1	95	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	96	#endif
MartinGurtner	60:8399756e1ba1	97
MartinGurtner	60:8399756e1ba1	98	#elif defined ( __GNUC__ )
MartinGurtner	60:8399756e1ba1	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
MartinGurtner	60:8399756e1ba1	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	101	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	102	#else
MartinGurtner	60:8399756e1ba1	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	104	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	105	#endif
MartinGurtner	60:8399756e1ba1	106	#else
MartinGurtner	60:8399756e1ba1	107	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	108	#endif
MartinGurtner	60:8399756e1ba1	109
MartinGurtner	60:8399756e1ba1	110	#elif defined ( __ICCARM__ )
MartinGurtner	60:8399756e1ba1	111	#if defined __ARMVFP__
MartinGurtner	60:8399756e1ba1	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	113	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	114	#else
MartinGurtner	60:8399756e1ba1	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	116	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	117	#endif
MartinGurtner	60:8399756e1ba1	118	#else
MartinGurtner	60:8399756e1ba1	119	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	120	#endif
MartinGurtner	60:8399756e1ba1	121
MartinGurtner	60:8399756e1ba1	122	#elif defined ( __TI_ARM__ )
MartinGurtner	60:8399756e1ba1	123	#if defined __TI_VFP_SUPPORT__
MartinGurtner	60:8399756e1ba1	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	125	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	126	#else
MartinGurtner	60:8399756e1ba1	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	128	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	129	#endif
MartinGurtner	60:8399756e1ba1	130	#else
MartinGurtner	60:8399756e1ba1	131	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	132	#endif
MartinGurtner	60:8399756e1ba1	133
MartinGurtner	60:8399756e1ba1	134	#elif defined ( __TASKING__ )
MartinGurtner	60:8399756e1ba1	135	#if defined __FPU_VFP__
MartinGurtner	60:8399756e1ba1	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	137	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	138	#else
MartinGurtner	60:8399756e1ba1	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	140	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	141	#endif
MartinGurtner	60:8399756e1ba1	142	#else
MartinGurtner	60:8399756e1ba1	143	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	144	#endif
MartinGurtner	60:8399756e1ba1	145
MartinGurtner	60:8399756e1ba1	146	#elif defined ( __CSMC__ )
MartinGurtner	60:8399756e1ba1	147	#if ( __CSMC__ & 0x400U)
MartinGurtner	60:8399756e1ba1	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	149	#define __FPU_USED 1U
MartinGurtner	60:8399756e1ba1	150	#else
MartinGurtner	60:8399756e1ba1	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
MartinGurtner	60:8399756e1ba1	152	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	153	#endif
MartinGurtner	60:8399756e1ba1	154	#else
MartinGurtner	60:8399756e1ba1	155	#define __FPU_USED 0U
MartinGurtner	60:8399756e1ba1	156	#endif
MartinGurtner	60:8399756e1ba1	157
MartinGurtner	60:8399756e1ba1	158	#endif
MartinGurtner	60:8399756e1ba1	159
MartinGurtner	60:8399756e1ba1	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
MartinGurtner	60:8399756e1ba1	161
MartinGurtner	60:8399756e1ba1	162
MartinGurtner	60:8399756e1ba1	163	#ifdef __cplusplus
MartinGurtner	60:8399756e1ba1	164	}
MartinGurtner	60:8399756e1ba1	165	#endif
MartinGurtner	60:8399756e1ba1	166
MartinGurtner	60:8399756e1ba1	167	#endif /* __CORE_CM33_H_GENERIC */
MartinGurtner	60:8399756e1ba1	168
MartinGurtner	60:8399756e1ba1	169	#ifndef __CMSIS_GENERIC
MartinGurtner	60:8399756e1ba1	170
MartinGurtner	60:8399756e1ba1	171	#ifndef __CORE_CM33_H_DEPENDANT
MartinGurtner	60:8399756e1ba1	172	#define __CORE_CM33_H_DEPENDANT
MartinGurtner	60:8399756e1ba1	173
MartinGurtner	60:8399756e1ba1	174	#ifdef __cplusplus
MartinGurtner	60:8399756e1ba1	175	extern "C" {
MartinGurtner	60:8399756e1ba1	176	#endif
MartinGurtner	60:8399756e1ba1	177
MartinGurtner	60:8399756e1ba1	178	/* check device defines and use defaults */
MartinGurtner	60:8399756e1ba1	179	#if defined __CHECK_DEVICE_DEFINES
MartinGurtner	60:8399756e1ba1	180	#ifndef __CM33_REV
MartinGurtner	60:8399756e1ba1	181	#define __CM33_REV 0x0000U
MartinGurtner	60:8399756e1ba1	182	#warning "__CM33_REV not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	183	#endif
MartinGurtner	60:8399756e1ba1	184
MartinGurtner	60:8399756e1ba1	185	#ifndef __FPU_PRESENT
MartinGurtner	60:8399756e1ba1	186	#define __FPU_PRESENT 0U
MartinGurtner	60:8399756e1ba1	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	188	#endif
MartinGurtner	60:8399756e1ba1	189
MartinGurtner	60:8399756e1ba1	190	#ifndef __MPU_PRESENT
MartinGurtner	60:8399756e1ba1	191	#define __MPU_PRESENT 0U
MartinGurtner	60:8399756e1ba1	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	193	#endif
MartinGurtner	60:8399756e1ba1	194
MartinGurtner	60:8399756e1ba1	195	#ifndef __SAUREGION_PRESENT
MartinGurtner	60:8399756e1ba1	196	#define __SAUREGION_PRESENT 0U
MartinGurtner	60:8399756e1ba1	197	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	198	#endif
MartinGurtner	60:8399756e1ba1	199
MartinGurtner	60:8399756e1ba1	200	#ifndef __DSP_PRESENT
MartinGurtner	60:8399756e1ba1	201	#define __DSP_PRESENT 0U
MartinGurtner	60:8399756e1ba1	202	#warning "__DSP_PRESENT not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	203	#endif
MartinGurtner	60:8399756e1ba1	204
MartinGurtner	60:8399756e1ba1	205	#ifndef __NVIC_PRIO_BITS
MartinGurtner	60:8399756e1ba1	206	#define __NVIC_PRIO_BITS 3U
MartinGurtner	60:8399756e1ba1	207	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	208	#endif
MartinGurtner	60:8399756e1ba1	209
MartinGurtner	60:8399756e1ba1	210	#ifndef __Vendor_SysTickConfig
MartinGurtner	60:8399756e1ba1	211	#define __Vendor_SysTickConfig 0U
MartinGurtner	60:8399756e1ba1	212	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
MartinGurtner	60:8399756e1ba1	213	#endif
MartinGurtner	60:8399756e1ba1	214	#endif
MartinGurtner	60:8399756e1ba1	215
MartinGurtner	60:8399756e1ba1	216	/* IO definitions (access restrictions to peripheral registers) */
MartinGurtner	60:8399756e1ba1	217	/**
MartinGurtner	60:8399756e1ba1	218	\defgroup CMSIS_glob_defs CMSIS Global Defines
MartinGurtner	60:8399756e1ba1	219
MartinGurtner	60:8399756e1ba1	220	<strong>IO Type Qualifiers</strong> are used
MartinGurtner	60:8399756e1ba1	221	\li to specify the access to peripheral variables.
MartinGurtner	60:8399756e1ba1	222	\li for automatic generation of peripheral register debug information.
MartinGurtner	60:8399756e1ba1	223	*/
MartinGurtner	60:8399756e1ba1	224	#ifdef __cplusplus
MartinGurtner	60:8399756e1ba1	225	#define __I volatile /!< Defines 'read only' permissions /
MartinGurtner	60:8399756e1ba1	226	#else
MartinGurtner	60:8399756e1ba1	227	#define __I volatile const /!< Defines 'read only' permissions /
MartinGurtner	60:8399756e1ba1	228	#endif
MartinGurtner	60:8399756e1ba1	229	#define __O volatile /!< Defines 'write only' permissions /
MartinGurtner	60:8399756e1ba1	230	#define __IO volatile /!< Defines 'read / write' permissions /
MartinGurtner	60:8399756e1ba1	231
MartinGurtner	60:8399756e1ba1	232	/* following defines should be used for structure members */
MartinGurtner	60:8399756e1ba1	233	#define __IM volatile const /! Defines 'read only' structure member permissions /
MartinGurtner	60:8399756e1ba1	234	#define __OM volatile /! Defines 'write only' structure member permissions /
MartinGurtner	60:8399756e1ba1	235	#define __IOM volatile /! Defines 'read / write' structure member permissions /
MartinGurtner	60:8399756e1ba1	236
MartinGurtner	60:8399756e1ba1	237	/@} end of group Cortex_M33 /
MartinGurtner	60:8399756e1ba1	238
MartinGurtner	60:8399756e1ba1	239
MartinGurtner	60:8399756e1ba1	240
MartinGurtner	60:8399756e1ba1	241	/*******************************************************************************
MartinGurtner	60:8399756e1ba1	242	* Register Abstraction
MartinGurtner	60:8399756e1ba1	243	Core Register contain:
MartinGurtner	60:8399756e1ba1	244	- Core Register
MartinGurtner	60:8399756e1ba1	245	- Core NVIC Register
MartinGurtner	60:8399756e1ba1	246	- Core SCB Register
MartinGurtner	60:8399756e1ba1	247	- Core SysTick Register
MartinGurtner	60:8399756e1ba1	248	- Core Debug Register
MartinGurtner	60:8399756e1ba1	249	- Core MPU Register
MartinGurtner	60:8399756e1ba1	250	- Core SAU Register
MartinGurtner	60:8399756e1ba1	251	- Core FPU Register
MartinGurtner	60:8399756e1ba1	252	******************************************************************************/
MartinGurtner	60:8399756e1ba1	253	/**
MartinGurtner	60:8399756e1ba1	254	\defgroup CMSIS_core_register Defines and Type Definitions
MartinGurtner	60:8399756e1ba1	255	\brief Type definitions and defines for Cortex-M processor based devices.
MartinGurtner	60:8399756e1ba1	256	*/
MartinGurtner	60:8399756e1ba1	257
MartinGurtner	60:8399756e1ba1	258	/**
MartinGurtner	60:8399756e1ba1	259	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	260	\defgroup CMSIS_CORE Status and Control Registers
MartinGurtner	60:8399756e1ba1	261	\brief Core Register type definitions.
MartinGurtner	60:8399756e1ba1	262	@{
MartinGurtner	60:8399756e1ba1	263	*/
MartinGurtner	60:8399756e1ba1	264
MartinGurtner	60:8399756e1ba1	265	/**
MartinGurtner	60:8399756e1ba1	266	\brief Union type to access the Application Program Status Register (APSR).
MartinGurtner	60:8399756e1ba1	267	*/
MartinGurtner	60:8399756e1ba1	268	typedef union
MartinGurtner	60:8399756e1ba1	269	{
MartinGurtner	60:8399756e1ba1	270	struct
MartinGurtner	60:8399756e1ba1	271	{
MartinGurtner	60:8399756e1ba1	272	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
MartinGurtner	60:8399756e1ba1	273	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MartinGurtner	60:8399756e1ba1	274	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
MartinGurtner	60:8399756e1ba1	275	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MartinGurtner	60:8399756e1ba1	276	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MartinGurtner	60:8399756e1ba1	277	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MartinGurtner	60:8399756e1ba1	278	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MartinGurtner	60:8399756e1ba1	279	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MartinGurtner	60:8399756e1ba1	280	} b; /!< Structure used for bit access /
MartinGurtner	60:8399756e1ba1	281	uint32_t w; /!< Type used for word access /
MartinGurtner	60:8399756e1ba1	282	} APSR_Type;
MartinGurtner	60:8399756e1ba1	283
MartinGurtner	60:8399756e1ba1	284	/* APSR Register Definitions */
MartinGurtner	60:8399756e1ba1	285	#define APSR_N_Pos 31U /!< APSR: N Position /
MartinGurtner	60:8399756e1ba1	286	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
MartinGurtner	60:8399756e1ba1	287
MartinGurtner	60:8399756e1ba1	288	#define APSR_Z_Pos 30U /!< APSR: Z Position /
MartinGurtner	60:8399756e1ba1	289	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
MartinGurtner	60:8399756e1ba1	290
MartinGurtner	60:8399756e1ba1	291	#define APSR_C_Pos 29U /!< APSR: C Position /
MartinGurtner	60:8399756e1ba1	292	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
MartinGurtner	60:8399756e1ba1	293
MartinGurtner	60:8399756e1ba1	294	#define APSR_V_Pos 28U /!< APSR: V Position /
MartinGurtner	60:8399756e1ba1	295	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
MartinGurtner	60:8399756e1ba1	296
MartinGurtner	60:8399756e1ba1	297	#define APSR_Q_Pos 27U /!< APSR: Q Position /
MartinGurtner	60:8399756e1ba1	298	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
MartinGurtner	60:8399756e1ba1	299
MartinGurtner	60:8399756e1ba1	300	#define APSR_GE_Pos 16U /!< APSR: GE Position /
MartinGurtner	60:8399756e1ba1	301	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
MartinGurtner	60:8399756e1ba1	302
MartinGurtner	60:8399756e1ba1	303
MartinGurtner	60:8399756e1ba1	304	/**
MartinGurtner	60:8399756e1ba1	305	\brief Union type to access the Interrupt Program Status Register (IPSR).
MartinGurtner	60:8399756e1ba1	306	*/
MartinGurtner	60:8399756e1ba1	307	typedef union
MartinGurtner	60:8399756e1ba1	308	{
MartinGurtner	60:8399756e1ba1	309	struct
MartinGurtner	60:8399756e1ba1	310	{
MartinGurtner	60:8399756e1ba1	311	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MartinGurtner	60:8399756e1ba1	312	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
MartinGurtner	60:8399756e1ba1	313	} b; /!< Structure used for bit access /
MartinGurtner	60:8399756e1ba1	314	uint32_t w; /!< Type used for word access /
MartinGurtner	60:8399756e1ba1	315	} IPSR_Type;
MartinGurtner	60:8399756e1ba1	316
MartinGurtner	60:8399756e1ba1	317	/* IPSR Register Definitions */
MartinGurtner	60:8399756e1ba1	318	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
MartinGurtner	60:8399756e1ba1	319	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
MartinGurtner	60:8399756e1ba1	320
MartinGurtner	60:8399756e1ba1	321
MartinGurtner	60:8399756e1ba1	322	/**
MartinGurtner	60:8399756e1ba1	323	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
MartinGurtner	60:8399756e1ba1	324	*/
MartinGurtner	60:8399756e1ba1	325	typedef union
MartinGurtner	60:8399756e1ba1	326	{
MartinGurtner	60:8399756e1ba1	327	struct
MartinGurtner	60:8399756e1ba1	328	{
MartinGurtner	60:8399756e1ba1	329	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
MartinGurtner	60:8399756e1ba1	330	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
MartinGurtner	60:8399756e1ba1	331	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
MartinGurtner	60:8399756e1ba1	332	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
MartinGurtner	60:8399756e1ba1	333	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
MartinGurtner	60:8399756e1ba1	334	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
MartinGurtner	60:8399756e1ba1	335	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
MartinGurtner	60:8399756e1ba1	336	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
MartinGurtner	60:8399756e1ba1	337	uint32_t C:1; /!< bit: 29 Carry condition code flag /
MartinGurtner	60:8399756e1ba1	338	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
MartinGurtner	60:8399756e1ba1	339	uint32_t N:1; /!< bit: 31 Negative condition code flag /
MartinGurtner	60:8399756e1ba1	340	} b; /!< Structure used for bit access /
MartinGurtner	60:8399756e1ba1	341	uint32_t w; /!< Type used for word access /
MartinGurtner	60:8399756e1ba1	342	} xPSR_Type;
MartinGurtner	60:8399756e1ba1	343
MartinGurtner	60:8399756e1ba1	344	/* xPSR Register Definitions */
MartinGurtner	60:8399756e1ba1	345	#define xPSR_N_Pos 31U /!< xPSR: N Position /
MartinGurtner	60:8399756e1ba1	346	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
MartinGurtner	60:8399756e1ba1	347
MartinGurtner	60:8399756e1ba1	348	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
MartinGurtner	60:8399756e1ba1	349	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
MartinGurtner	60:8399756e1ba1	350
MartinGurtner	60:8399756e1ba1	351	#define xPSR_C_Pos 29U /!< xPSR: C Position /
MartinGurtner	60:8399756e1ba1	352	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
MartinGurtner	60:8399756e1ba1	353
MartinGurtner	60:8399756e1ba1	354	#define xPSR_V_Pos 28U /!< xPSR: V Position /
MartinGurtner	60:8399756e1ba1	355	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
MartinGurtner	60:8399756e1ba1	356
MartinGurtner	60:8399756e1ba1	357	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
MartinGurtner	60:8399756e1ba1	358	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
MartinGurtner	60:8399756e1ba1	359
MartinGurtner	60:8399756e1ba1	360	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
MartinGurtner	60:8399756e1ba1	361	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
MartinGurtner	60:8399756e1ba1	362
MartinGurtner	60:8399756e1ba1	363	#define xPSR_T_Pos 24U /!< xPSR: T Position /
MartinGurtner	60:8399756e1ba1	364	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
MartinGurtner	60:8399756e1ba1	365
MartinGurtner	60:8399756e1ba1	366	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
MartinGurtner	60:8399756e1ba1	367	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
MartinGurtner	60:8399756e1ba1	368
MartinGurtner	60:8399756e1ba1	369	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
MartinGurtner	60:8399756e1ba1	370	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
MartinGurtner	60:8399756e1ba1	371
MartinGurtner	60:8399756e1ba1	372
MartinGurtner	60:8399756e1ba1	373	/**
MartinGurtner	60:8399756e1ba1	374	\brief Union type to access the Control Registers (CONTROL).
MartinGurtner	60:8399756e1ba1	375	*/
MartinGurtner	60:8399756e1ba1	376	typedef union
MartinGurtner	60:8399756e1ba1	377	{
MartinGurtner	60:8399756e1ba1	378	struct
MartinGurtner	60:8399756e1ba1	379	{
MartinGurtner	60:8399756e1ba1	380	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
MartinGurtner	60:8399756e1ba1	381	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
MartinGurtner	60:8399756e1ba1	382	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
MartinGurtner	60:8399756e1ba1	383	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
MartinGurtner	60:8399756e1ba1	384	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
MartinGurtner	60:8399756e1ba1	385	} b; /!< Structure used for bit access /
MartinGurtner	60:8399756e1ba1	386	uint32_t w; /!< Type used for word access /
MartinGurtner	60:8399756e1ba1	387	} CONTROL_Type;
MartinGurtner	60:8399756e1ba1	388
MartinGurtner	60:8399756e1ba1	389	/* CONTROL Register Definitions */
MartinGurtner	60:8399756e1ba1	390	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
MartinGurtner	60:8399756e1ba1	391	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
MartinGurtner	60:8399756e1ba1	392
MartinGurtner	60:8399756e1ba1	393	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
MartinGurtner	60:8399756e1ba1	394	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
MartinGurtner	60:8399756e1ba1	395
MartinGurtner	60:8399756e1ba1	396	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
MartinGurtner	60:8399756e1ba1	397	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
MartinGurtner	60:8399756e1ba1	398
MartinGurtner	60:8399756e1ba1	399	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
MartinGurtner	60:8399756e1ba1	400	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
MartinGurtner	60:8399756e1ba1	401
MartinGurtner	60:8399756e1ba1	402	/@} end of group CMSIS_CORE /
MartinGurtner	60:8399756e1ba1	403
MartinGurtner	60:8399756e1ba1	404
MartinGurtner	60:8399756e1ba1	405	/**
MartinGurtner	60:8399756e1ba1	406	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	407	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
MartinGurtner	60:8399756e1ba1	408	\brief Type definitions for the NVIC Registers
MartinGurtner	60:8399756e1ba1	409	@{
MartinGurtner	60:8399756e1ba1	410	*/
MartinGurtner	60:8399756e1ba1	411
MartinGurtner	60:8399756e1ba1	412	/**
MartinGurtner	60:8399756e1ba1	413	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
MartinGurtner	60:8399756e1ba1	414	*/
MartinGurtner	60:8399756e1ba1	415	typedef struct
MartinGurtner	60:8399756e1ba1	416	{
MartinGurtner	60:8399756e1ba1	417	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
MartinGurtner	60:8399756e1ba1	418	uint32_t RESERVED0[16U];
MartinGurtner	60:8399756e1ba1	419	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
MartinGurtner	60:8399756e1ba1	420	uint32_t RSERVED1[16U];
MartinGurtner	60:8399756e1ba1	421	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
MartinGurtner	60:8399756e1ba1	422	uint32_t RESERVED2[16U];
MartinGurtner	60:8399756e1ba1	423	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
MartinGurtner	60:8399756e1ba1	424	uint32_t RESERVED3[16U];
MartinGurtner	60:8399756e1ba1	425	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
MartinGurtner	60:8399756e1ba1	426	uint32_t RESERVED4[16U];
MartinGurtner	60:8399756e1ba1	427	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
MartinGurtner	60:8399756e1ba1	428	uint32_t RESERVED5[16U];
MartinGurtner	60:8399756e1ba1	429	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
MartinGurtner	60:8399756e1ba1	430	uint32_t RESERVED6[580U];
MartinGurtner	60:8399756e1ba1	431	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
MartinGurtner	60:8399756e1ba1	432	} NVIC_Type;
MartinGurtner	60:8399756e1ba1	433
MartinGurtner	60:8399756e1ba1	434	/* Software Triggered Interrupt Register Definitions */
MartinGurtner	60:8399756e1ba1	435	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
MartinGurtner	60:8399756e1ba1	436	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
MartinGurtner	60:8399756e1ba1	437
MartinGurtner	60:8399756e1ba1	438	/@} end of group CMSIS_NVIC /
MartinGurtner	60:8399756e1ba1	439
MartinGurtner	60:8399756e1ba1	440
MartinGurtner	60:8399756e1ba1	441	/**
MartinGurtner	60:8399756e1ba1	442	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	443	\defgroup CMSIS_SCB System Control Block (SCB)
MartinGurtner	60:8399756e1ba1	444	\brief Type definitions for the System Control Block Registers
MartinGurtner	60:8399756e1ba1	445	@{
MartinGurtner	60:8399756e1ba1	446	*/
MartinGurtner	60:8399756e1ba1	447
MartinGurtner	60:8399756e1ba1	448	/**
MartinGurtner	60:8399756e1ba1	449	\brief Structure type to access the System Control Block (SCB).
MartinGurtner	60:8399756e1ba1	450	*/
MartinGurtner	60:8399756e1ba1	451	typedef struct
MartinGurtner	60:8399756e1ba1	452	{
MartinGurtner	60:8399756e1ba1	453	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
MartinGurtner	60:8399756e1ba1	454	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
MartinGurtner	60:8399756e1ba1	455	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
MartinGurtner	60:8399756e1ba1	456	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
MartinGurtner	60:8399756e1ba1	457	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
MartinGurtner	60:8399756e1ba1	458	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
MartinGurtner	60:8399756e1ba1	459	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
MartinGurtner	60:8399756e1ba1	460	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
MartinGurtner	60:8399756e1ba1	461	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
MartinGurtner	60:8399756e1ba1	462	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
MartinGurtner	60:8399756e1ba1	463	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
MartinGurtner	60:8399756e1ba1	464	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
MartinGurtner	60:8399756e1ba1	465	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
MartinGurtner	60:8399756e1ba1	466	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
MartinGurtner	60:8399756e1ba1	467	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
MartinGurtner	60:8399756e1ba1	468	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
MartinGurtner	60:8399756e1ba1	469	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
MartinGurtner	60:8399756e1ba1	470	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
MartinGurtner	60:8399756e1ba1	471	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
MartinGurtner	60:8399756e1ba1	472	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
MartinGurtner	60:8399756e1ba1	473	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
MartinGurtner	60:8399756e1ba1	474	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
MartinGurtner	60:8399756e1ba1	475	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
MartinGurtner	60:8399756e1ba1	476	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
MartinGurtner	60:8399756e1ba1	477	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
MartinGurtner	60:8399756e1ba1	478	uint32_t RESERVED3[92U];
MartinGurtner	60:8399756e1ba1	479	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
MartinGurtner	60:8399756e1ba1	480	uint32_t RESERVED4[15U];
MartinGurtner	60:8399756e1ba1	481	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
MartinGurtner	60:8399756e1ba1	482	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
MartinGurtner	60:8399756e1ba1	483	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
MartinGurtner	60:8399756e1ba1	484	uint32_t RESERVED5[1U];
MartinGurtner	60:8399756e1ba1	485	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
MartinGurtner	60:8399756e1ba1	486	uint32_t RESERVED6[1U];
MartinGurtner	60:8399756e1ba1	487	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
MartinGurtner	60:8399756e1ba1	488	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
MartinGurtner	60:8399756e1ba1	489	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
MartinGurtner	60:8399756e1ba1	490	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
MartinGurtner	60:8399756e1ba1	491	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
MartinGurtner	60:8399756e1ba1	492	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
MartinGurtner	60:8399756e1ba1	493	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
MartinGurtner	60:8399756e1ba1	494	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
MartinGurtner	60:8399756e1ba1	495	uint32_t RESERVED7[6U];
MartinGurtner	60:8399756e1ba1	496	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
MartinGurtner	60:8399756e1ba1	497	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
MartinGurtner	60:8399756e1ba1	498	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
MartinGurtner	60:8399756e1ba1	499	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
MartinGurtner	60:8399756e1ba1	500	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
MartinGurtner	60:8399756e1ba1	501	uint32_t RESERVED8[1U];
MartinGurtner	60:8399756e1ba1	502	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
MartinGurtner	60:8399756e1ba1	503	} SCB_Type;
MartinGurtner	60:8399756e1ba1	504
MartinGurtner	60:8399756e1ba1	505	/* SCB CPUID Register Definitions */
MartinGurtner	60:8399756e1ba1	506	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
MartinGurtner	60:8399756e1ba1	507	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
MartinGurtner	60:8399756e1ba1	508
MartinGurtner	60:8399756e1ba1	509	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
MartinGurtner	60:8399756e1ba1	510	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
MartinGurtner	60:8399756e1ba1	511
MartinGurtner	60:8399756e1ba1	512	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
MartinGurtner	60:8399756e1ba1	513	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
MartinGurtner	60:8399756e1ba1	514
MartinGurtner	60:8399756e1ba1	515	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
MartinGurtner	60:8399756e1ba1	516	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
MartinGurtner	60:8399756e1ba1	517
MartinGurtner	60:8399756e1ba1	518	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
MartinGurtner	60:8399756e1ba1	519	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
MartinGurtner	60:8399756e1ba1	520
MartinGurtner	60:8399756e1ba1	521	/* SCB Interrupt Control State Register Definitions */
MartinGurtner	60:8399756e1ba1	522	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
MartinGurtner	60:8399756e1ba1	523	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
MartinGurtner	60:8399756e1ba1	524
MartinGurtner	60:8399756e1ba1	525	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
MartinGurtner	60:8399756e1ba1	526	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
MartinGurtner	60:8399756e1ba1	527
MartinGurtner	60:8399756e1ba1	528	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
MartinGurtner	60:8399756e1ba1	529	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
MartinGurtner	60:8399756e1ba1	530
MartinGurtner	60:8399756e1ba1	531	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
MartinGurtner	60:8399756e1ba1	532	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
MartinGurtner	60:8399756e1ba1	533
MartinGurtner	60:8399756e1ba1	534	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
MartinGurtner	60:8399756e1ba1	535	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
MartinGurtner	60:8399756e1ba1	536
MartinGurtner	60:8399756e1ba1	537	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
MartinGurtner	60:8399756e1ba1	538	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
MartinGurtner	60:8399756e1ba1	539
MartinGurtner	60:8399756e1ba1	540	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
MartinGurtner	60:8399756e1ba1	541	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
MartinGurtner	60:8399756e1ba1	542
MartinGurtner	60:8399756e1ba1	543	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
MartinGurtner	60:8399756e1ba1	544	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
MartinGurtner	60:8399756e1ba1	545
MartinGurtner	60:8399756e1ba1	546	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
MartinGurtner	60:8399756e1ba1	547	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
MartinGurtner	60:8399756e1ba1	548
MartinGurtner	60:8399756e1ba1	549	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
MartinGurtner	60:8399756e1ba1	550	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
MartinGurtner	60:8399756e1ba1	551
MartinGurtner	60:8399756e1ba1	552	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
MartinGurtner	60:8399756e1ba1	553	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
MartinGurtner	60:8399756e1ba1	554
MartinGurtner	60:8399756e1ba1	555	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
MartinGurtner	60:8399756e1ba1	556	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
MartinGurtner	60:8399756e1ba1	557
MartinGurtner	60:8399756e1ba1	558	/* SCB Vector Table Offset Register Definitions */
MartinGurtner	60:8399756e1ba1	559	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
MartinGurtner	60:8399756e1ba1	560	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
MartinGurtner	60:8399756e1ba1	561
MartinGurtner	60:8399756e1ba1	562	/* SCB Application Interrupt and Reset Control Register Definitions */
MartinGurtner	60:8399756e1ba1	563	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
MartinGurtner	60:8399756e1ba1	564	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
MartinGurtner	60:8399756e1ba1	565
MartinGurtner	60:8399756e1ba1	566	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
MartinGurtner	60:8399756e1ba1	567	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
MartinGurtner	60:8399756e1ba1	568
MartinGurtner	60:8399756e1ba1	569	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
MartinGurtner	60:8399756e1ba1	570	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
MartinGurtner	60:8399756e1ba1	571
MartinGurtner	60:8399756e1ba1	572	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
MartinGurtner	60:8399756e1ba1	573	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
MartinGurtner	60:8399756e1ba1	574
MartinGurtner	60:8399756e1ba1	575	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
MartinGurtner	60:8399756e1ba1	576	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
MartinGurtner	60:8399756e1ba1	577
MartinGurtner	60:8399756e1ba1	578	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
MartinGurtner	60:8399756e1ba1	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
MartinGurtner	60:8399756e1ba1	580
MartinGurtner	60:8399756e1ba1	581	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
MartinGurtner	60:8399756e1ba1	582	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
MartinGurtner	60:8399756e1ba1	583
MartinGurtner	60:8399756e1ba1	584	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
MartinGurtner	60:8399756e1ba1	585	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
MartinGurtner	60:8399756e1ba1	586
MartinGurtner	60:8399756e1ba1	587	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
MartinGurtner	60:8399756e1ba1	588	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
MartinGurtner	60:8399756e1ba1	589
MartinGurtner	60:8399756e1ba1	590	/* SCB System Control Register Definitions */
MartinGurtner	60:8399756e1ba1	591	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
MartinGurtner	60:8399756e1ba1	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
MartinGurtner	60:8399756e1ba1	593
MartinGurtner	60:8399756e1ba1	594	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
MartinGurtner	60:8399756e1ba1	595	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
MartinGurtner	60:8399756e1ba1	596
MartinGurtner	60:8399756e1ba1	597	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
MartinGurtner	60:8399756e1ba1	598	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
MartinGurtner	60:8399756e1ba1	599
MartinGurtner	60:8399756e1ba1	600	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
MartinGurtner	60:8399756e1ba1	601	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
MartinGurtner	60:8399756e1ba1	602
MartinGurtner	60:8399756e1ba1	603	/* SCB Configuration Control Register Definitions */
MartinGurtner	60:8399756e1ba1	604	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
MartinGurtner	60:8399756e1ba1	605	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
MartinGurtner	60:8399756e1ba1	606
MartinGurtner	60:8399756e1ba1	607	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
MartinGurtner	60:8399756e1ba1	608	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
MartinGurtner	60:8399756e1ba1	609
MartinGurtner	60:8399756e1ba1	610	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
MartinGurtner	60:8399756e1ba1	611	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
MartinGurtner	60:8399756e1ba1	612
MartinGurtner	60:8399756e1ba1	613	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
MartinGurtner	60:8399756e1ba1	614	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
MartinGurtner	60:8399756e1ba1	615
MartinGurtner	60:8399756e1ba1	616	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
MartinGurtner	60:8399756e1ba1	617	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
MartinGurtner	60:8399756e1ba1	618
MartinGurtner	60:8399756e1ba1	619	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
MartinGurtner	60:8399756e1ba1	620	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
MartinGurtner	60:8399756e1ba1	621
MartinGurtner	60:8399756e1ba1	622	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
MartinGurtner	60:8399756e1ba1	623	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
MartinGurtner	60:8399756e1ba1	624
MartinGurtner	60:8399756e1ba1	625	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
MartinGurtner	60:8399756e1ba1	626	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
MartinGurtner	60:8399756e1ba1	627
MartinGurtner	60:8399756e1ba1	628	/* SCB System Handler Control and State Register Definitions */
MartinGurtner	60:8399756e1ba1	629	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
MartinGurtner	60:8399756e1ba1	630	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
MartinGurtner	60:8399756e1ba1	631
MartinGurtner	60:8399756e1ba1	632	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
MartinGurtner	60:8399756e1ba1	633	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
MartinGurtner	60:8399756e1ba1	634
MartinGurtner	60:8399756e1ba1	635	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
MartinGurtner	60:8399756e1ba1	636	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
MartinGurtner	60:8399756e1ba1	637
MartinGurtner	60:8399756e1ba1	638	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
MartinGurtner	60:8399756e1ba1	639	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
MartinGurtner	60:8399756e1ba1	640
MartinGurtner	60:8399756e1ba1	641	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
MartinGurtner	60:8399756e1ba1	642	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
MartinGurtner	60:8399756e1ba1	643
MartinGurtner	60:8399756e1ba1	644	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
MartinGurtner	60:8399756e1ba1	645	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
MartinGurtner	60:8399756e1ba1	646
MartinGurtner	60:8399756e1ba1	647	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
MartinGurtner	60:8399756e1ba1	648	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
MartinGurtner	60:8399756e1ba1	649
MartinGurtner	60:8399756e1ba1	650	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
MartinGurtner	60:8399756e1ba1	651	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
MartinGurtner	60:8399756e1ba1	652
MartinGurtner	60:8399756e1ba1	653	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
MartinGurtner	60:8399756e1ba1	654	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
MartinGurtner	60:8399756e1ba1	655
MartinGurtner	60:8399756e1ba1	656	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
MartinGurtner	60:8399756e1ba1	657	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
MartinGurtner	60:8399756e1ba1	658
MartinGurtner	60:8399756e1ba1	659	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
MartinGurtner	60:8399756e1ba1	660	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
MartinGurtner	60:8399756e1ba1	661
MartinGurtner	60:8399756e1ba1	662	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
MartinGurtner	60:8399756e1ba1	663	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
MartinGurtner	60:8399756e1ba1	664
MartinGurtner	60:8399756e1ba1	665	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
MartinGurtner	60:8399756e1ba1	666	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
MartinGurtner	60:8399756e1ba1	667
MartinGurtner	60:8399756e1ba1	668	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
MartinGurtner	60:8399756e1ba1	669	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
MartinGurtner	60:8399756e1ba1	670
MartinGurtner	60:8399756e1ba1	671	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
MartinGurtner	60:8399756e1ba1	672	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
MartinGurtner	60:8399756e1ba1	673
MartinGurtner	60:8399756e1ba1	674	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
MartinGurtner	60:8399756e1ba1	675	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
MartinGurtner	60:8399756e1ba1	676
MartinGurtner	60:8399756e1ba1	677	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
MartinGurtner	60:8399756e1ba1	678	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
MartinGurtner	60:8399756e1ba1	679
MartinGurtner	60:8399756e1ba1	680	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
MartinGurtner	60:8399756e1ba1	681	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
MartinGurtner	60:8399756e1ba1	682
MartinGurtner	60:8399756e1ba1	683	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
MartinGurtner	60:8399756e1ba1	684	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
MartinGurtner	60:8399756e1ba1	685
MartinGurtner	60:8399756e1ba1	686	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
MartinGurtner	60:8399756e1ba1	687	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
MartinGurtner	60:8399756e1ba1	688
MartinGurtner	60:8399756e1ba1	689	/* SCB Configurable Fault Status Register Definitions */
MartinGurtner	60:8399756e1ba1	690	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
MartinGurtner	60:8399756e1ba1	691	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
MartinGurtner	60:8399756e1ba1	692
MartinGurtner	60:8399756e1ba1	693	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
MartinGurtner	60:8399756e1ba1	694	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
MartinGurtner	60:8399756e1ba1	695
MartinGurtner	60:8399756e1ba1	696	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
MartinGurtner	60:8399756e1ba1	697	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
MartinGurtner	60:8399756e1ba1	698
MartinGurtner	60:8399756e1ba1	699	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
MartinGurtner	60:8399756e1ba1	700	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
MartinGurtner	60:8399756e1ba1	701	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
MartinGurtner	60:8399756e1ba1	702
MartinGurtner	60:8399756e1ba1	703	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
MartinGurtner	60:8399756e1ba1	704	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
MartinGurtner	60:8399756e1ba1	705
MartinGurtner	60:8399756e1ba1	706	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
MartinGurtner	60:8399756e1ba1	707	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
MartinGurtner	60:8399756e1ba1	708
MartinGurtner	60:8399756e1ba1	709	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
MartinGurtner	60:8399756e1ba1	710	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
MartinGurtner	60:8399756e1ba1	711
MartinGurtner	60:8399756e1ba1	712	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
MartinGurtner	60:8399756e1ba1	713	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
MartinGurtner	60:8399756e1ba1	714
MartinGurtner	60:8399756e1ba1	715	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
MartinGurtner	60:8399756e1ba1	716	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
MartinGurtner	60:8399756e1ba1	717
MartinGurtner	60:8399756e1ba1	718	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
MartinGurtner	60:8399756e1ba1	719	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
MartinGurtner	60:8399756e1ba1	720	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
MartinGurtner	60:8399756e1ba1	721
MartinGurtner	60:8399756e1ba1	722	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
MartinGurtner	60:8399756e1ba1	723	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
MartinGurtner	60:8399756e1ba1	724
MartinGurtner	60:8399756e1ba1	725	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
MartinGurtner	60:8399756e1ba1	726	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
MartinGurtner	60:8399756e1ba1	727
MartinGurtner	60:8399756e1ba1	728	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
MartinGurtner	60:8399756e1ba1	729	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
MartinGurtner	60:8399756e1ba1	730
MartinGurtner	60:8399756e1ba1	731	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
MartinGurtner	60:8399756e1ba1	732	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
MartinGurtner	60:8399756e1ba1	733
MartinGurtner	60:8399756e1ba1	734	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
MartinGurtner	60:8399756e1ba1	735	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
MartinGurtner	60:8399756e1ba1	736
MartinGurtner	60:8399756e1ba1	737	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
MartinGurtner	60:8399756e1ba1	738	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
MartinGurtner	60:8399756e1ba1	739
MartinGurtner	60:8399756e1ba1	740	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
MartinGurtner	60:8399756e1ba1	741	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
MartinGurtner	60:8399756e1ba1	742	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
MartinGurtner	60:8399756e1ba1	743
MartinGurtner	60:8399756e1ba1	744	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
MartinGurtner	60:8399756e1ba1	745	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
MartinGurtner	60:8399756e1ba1	746
MartinGurtner	60:8399756e1ba1	747	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
MartinGurtner	60:8399756e1ba1	748	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
MartinGurtner	60:8399756e1ba1	749
MartinGurtner	60:8399756e1ba1	750	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
MartinGurtner	60:8399756e1ba1	751	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
MartinGurtner	60:8399756e1ba1	752
MartinGurtner	60:8399756e1ba1	753	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
MartinGurtner	60:8399756e1ba1	754	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
MartinGurtner	60:8399756e1ba1	755
MartinGurtner	60:8399756e1ba1	756	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
MartinGurtner	60:8399756e1ba1	757	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
MartinGurtner	60:8399756e1ba1	758
MartinGurtner	60:8399756e1ba1	759	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
MartinGurtner	60:8399756e1ba1	760	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
MartinGurtner	60:8399756e1ba1	761
MartinGurtner	60:8399756e1ba1	762	/* SCB Hard Fault Status Register Definitions */
MartinGurtner	60:8399756e1ba1	763	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
MartinGurtner	60:8399756e1ba1	764	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
MartinGurtner	60:8399756e1ba1	765
MartinGurtner	60:8399756e1ba1	766	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
MartinGurtner	60:8399756e1ba1	767	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
MartinGurtner	60:8399756e1ba1	768
MartinGurtner	60:8399756e1ba1	769	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
MartinGurtner	60:8399756e1ba1	770	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
MartinGurtner	60:8399756e1ba1	771
MartinGurtner	60:8399756e1ba1	772	/* SCB Debug Fault Status Register Definitions */
MartinGurtner	60:8399756e1ba1	773	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
MartinGurtner	60:8399756e1ba1	774	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
MartinGurtner	60:8399756e1ba1	775
MartinGurtner	60:8399756e1ba1	776	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
MartinGurtner	60:8399756e1ba1	777	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
MartinGurtner	60:8399756e1ba1	778
MartinGurtner	60:8399756e1ba1	779	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
MartinGurtner	60:8399756e1ba1	780	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
MartinGurtner	60:8399756e1ba1	781
MartinGurtner	60:8399756e1ba1	782	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
MartinGurtner	60:8399756e1ba1	783	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
MartinGurtner	60:8399756e1ba1	784
MartinGurtner	60:8399756e1ba1	785	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
MartinGurtner	60:8399756e1ba1	786	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
MartinGurtner	60:8399756e1ba1	787
MartinGurtner	60:8399756e1ba1	788	/* SCB Non-Secure Access Control Register Definitions */
MartinGurtner	60:8399756e1ba1	789	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
MartinGurtner	60:8399756e1ba1	790	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
MartinGurtner	60:8399756e1ba1	791
MartinGurtner	60:8399756e1ba1	792	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
MartinGurtner	60:8399756e1ba1	793	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
MartinGurtner	60:8399756e1ba1	794
MartinGurtner	60:8399756e1ba1	795	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
MartinGurtner	60:8399756e1ba1	796	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
MartinGurtner	60:8399756e1ba1	797
MartinGurtner	60:8399756e1ba1	798	/* SCB Cache Level ID Register Definitions */
MartinGurtner	60:8399756e1ba1	799	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
MartinGurtner	60:8399756e1ba1	800	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
MartinGurtner	60:8399756e1ba1	801
MartinGurtner	60:8399756e1ba1	802	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
MartinGurtner	60:8399756e1ba1	803	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
MartinGurtner	60:8399756e1ba1	804
MartinGurtner	60:8399756e1ba1	805	/* SCB Cache Type Register Definitions */
MartinGurtner	60:8399756e1ba1	806	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
MartinGurtner	60:8399756e1ba1	807	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
MartinGurtner	60:8399756e1ba1	808
MartinGurtner	60:8399756e1ba1	809	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
MartinGurtner	60:8399756e1ba1	810	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
MartinGurtner	60:8399756e1ba1	811
MartinGurtner	60:8399756e1ba1	812	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
MartinGurtner	60:8399756e1ba1	813	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
MartinGurtner	60:8399756e1ba1	814
MartinGurtner	60:8399756e1ba1	815	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
MartinGurtner	60:8399756e1ba1	816	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
MartinGurtner	60:8399756e1ba1	817
MartinGurtner	60:8399756e1ba1	818	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
MartinGurtner	60:8399756e1ba1	819	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
MartinGurtner	60:8399756e1ba1	820
MartinGurtner	60:8399756e1ba1	821	/* SCB Cache Size ID Register Definitions */
MartinGurtner	60:8399756e1ba1	822	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
MartinGurtner	60:8399756e1ba1	823	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
MartinGurtner	60:8399756e1ba1	824
MartinGurtner	60:8399756e1ba1	825	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
MartinGurtner	60:8399756e1ba1	826	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
MartinGurtner	60:8399756e1ba1	827
MartinGurtner	60:8399756e1ba1	828	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
MartinGurtner	60:8399756e1ba1	829	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
MartinGurtner	60:8399756e1ba1	830
MartinGurtner	60:8399756e1ba1	831	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
MartinGurtner	60:8399756e1ba1	832	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
MartinGurtner	60:8399756e1ba1	833
MartinGurtner	60:8399756e1ba1	834	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
MartinGurtner	60:8399756e1ba1	835	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
MartinGurtner	60:8399756e1ba1	836
MartinGurtner	60:8399756e1ba1	837	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
MartinGurtner	60:8399756e1ba1	838	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
MartinGurtner	60:8399756e1ba1	839
MartinGurtner	60:8399756e1ba1	840	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
MartinGurtner	60:8399756e1ba1	841	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
MartinGurtner	60:8399756e1ba1	842
MartinGurtner	60:8399756e1ba1	843	/* SCB Cache Size Selection Register Definitions */
MartinGurtner	60:8399756e1ba1	844	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
MartinGurtner	60:8399756e1ba1	845	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
MartinGurtner	60:8399756e1ba1	846
MartinGurtner	60:8399756e1ba1	847	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
MartinGurtner	60:8399756e1ba1	848	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
MartinGurtner	60:8399756e1ba1	849
MartinGurtner	60:8399756e1ba1	850	/* SCB Software Triggered Interrupt Register Definitions */
MartinGurtner	60:8399756e1ba1	851	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
MartinGurtner	60:8399756e1ba1	852	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
MartinGurtner	60:8399756e1ba1	853
MartinGurtner	60:8399756e1ba1	854	/* SCB D-Cache Invalidate by Set-way Register Definitions */
MartinGurtner	60:8399756e1ba1	855	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
MartinGurtner	60:8399756e1ba1	856	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
MartinGurtner	60:8399756e1ba1	857
MartinGurtner	60:8399756e1ba1	858	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
MartinGurtner	60:8399756e1ba1	859	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
MartinGurtner	60:8399756e1ba1	860
MartinGurtner	60:8399756e1ba1	861	/* SCB D-Cache Clean by Set-way Register Definitions */
MartinGurtner	60:8399756e1ba1	862	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
MartinGurtner	60:8399756e1ba1	863	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
MartinGurtner	60:8399756e1ba1	864
MartinGurtner	60:8399756e1ba1	865	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
MartinGurtner	60:8399756e1ba1	866	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
MartinGurtner	60:8399756e1ba1	867
MartinGurtner	60:8399756e1ba1	868	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
MartinGurtner	60:8399756e1ba1	869	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
MartinGurtner	60:8399756e1ba1	870	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
MartinGurtner	60:8399756e1ba1	871
MartinGurtner	60:8399756e1ba1	872	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
MartinGurtner	60:8399756e1ba1	873	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
MartinGurtner	60:8399756e1ba1	874
MartinGurtner	60:8399756e1ba1	875	/* Instruction Tightly-Coupled Memory Control Register Definitions */
MartinGurtner	60:8399756e1ba1	876	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
MartinGurtner	60:8399756e1ba1	877	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
MartinGurtner	60:8399756e1ba1	878
MartinGurtner	60:8399756e1ba1	879	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
MartinGurtner	60:8399756e1ba1	880	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
MartinGurtner	60:8399756e1ba1	881
MartinGurtner	60:8399756e1ba1	882	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
MartinGurtner	60:8399756e1ba1	883	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
MartinGurtner	60:8399756e1ba1	884
MartinGurtner	60:8399756e1ba1	885	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
MartinGurtner	60:8399756e1ba1	886	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
MartinGurtner	60:8399756e1ba1	887
MartinGurtner	60:8399756e1ba1	888	/* Data Tightly-Coupled Memory Control Register Definitions */
MartinGurtner	60:8399756e1ba1	889	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
MartinGurtner	60:8399756e1ba1	890	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
MartinGurtner	60:8399756e1ba1	891
MartinGurtner	60:8399756e1ba1	892	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
MartinGurtner	60:8399756e1ba1	893	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
MartinGurtner	60:8399756e1ba1	894
MartinGurtner	60:8399756e1ba1	895	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
MartinGurtner	60:8399756e1ba1	896	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
MartinGurtner	60:8399756e1ba1	897
MartinGurtner	60:8399756e1ba1	898	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
MartinGurtner	60:8399756e1ba1	899	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
MartinGurtner	60:8399756e1ba1	900
MartinGurtner	60:8399756e1ba1	901	/* AHBP Control Register Definitions */
MartinGurtner	60:8399756e1ba1	902	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
MartinGurtner	60:8399756e1ba1	903	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
MartinGurtner	60:8399756e1ba1	904
MartinGurtner	60:8399756e1ba1	905	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
MartinGurtner	60:8399756e1ba1	906	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
MartinGurtner	60:8399756e1ba1	907
MartinGurtner	60:8399756e1ba1	908	/* L1 Cache Control Register Definitions */
MartinGurtner	60:8399756e1ba1	909	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
MartinGurtner	60:8399756e1ba1	910	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
MartinGurtner	60:8399756e1ba1	911
MartinGurtner	60:8399756e1ba1	912	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
MartinGurtner	60:8399756e1ba1	913	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
MartinGurtner	60:8399756e1ba1	914
MartinGurtner	60:8399756e1ba1	915	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
MartinGurtner	60:8399756e1ba1	916	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
MartinGurtner	60:8399756e1ba1	917
MartinGurtner	60:8399756e1ba1	918	/* AHBS Control Register Definitions */
MartinGurtner	60:8399756e1ba1	919	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
MartinGurtner	60:8399756e1ba1	920	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
MartinGurtner	60:8399756e1ba1	921
MartinGurtner	60:8399756e1ba1	922	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
MartinGurtner	60:8399756e1ba1	923	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
MartinGurtner	60:8399756e1ba1	924
MartinGurtner	60:8399756e1ba1	925	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
MartinGurtner	60:8399756e1ba1	926	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
MartinGurtner	60:8399756e1ba1	927
MartinGurtner	60:8399756e1ba1	928	/* Auxiliary Bus Fault Status Register Definitions */
MartinGurtner	60:8399756e1ba1	929	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
MartinGurtner	60:8399756e1ba1	930	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
MartinGurtner	60:8399756e1ba1	931
MartinGurtner	60:8399756e1ba1	932	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
MartinGurtner	60:8399756e1ba1	933	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
MartinGurtner	60:8399756e1ba1	934
MartinGurtner	60:8399756e1ba1	935	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
MartinGurtner	60:8399756e1ba1	936	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
MartinGurtner	60:8399756e1ba1	937
MartinGurtner	60:8399756e1ba1	938	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
MartinGurtner	60:8399756e1ba1	939	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
MartinGurtner	60:8399756e1ba1	940
MartinGurtner	60:8399756e1ba1	941	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
MartinGurtner	60:8399756e1ba1	942	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
MartinGurtner	60:8399756e1ba1	943
MartinGurtner	60:8399756e1ba1	944	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
MartinGurtner	60:8399756e1ba1	945	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
MartinGurtner	60:8399756e1ba1	946
MartinGurtner	60:8399756e1ba1	947	/@} end of group CMSIS_SCB /
MartinGurtner	60:8399756e1ba1	948
MartinGurtner	60:8399756e1ba1	949
MartinGurtner	60:8399756e1ba1	950	/**
MartinGurtner	60:8399756e1ba1	951	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	952	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
MartinGurtner	60:8399756e1ba1	953	\brief Type definitions for the System Control and ID Register not in the SCB
MartinGurtner	60:8399756e1ba1	954	@{
MartinGurtner	60:8399756e1ba1	955	*/
MartinGurtner	60:8399756e1ba1	956
MartinGurtner	60:8399756e1ba1	957	/**
MartinGurtner	60:8399756e1ba1	958	\brief Structure type to access the System Control and ID Register not in the SCB.
MartinGurtner	60:8399756e1ba1	959	*/
MartinGurtner	60:8399756e1ba1	960	typedef struct
MartinGurtner	60:8399756e1ba1	961	{
MartinGurtner	60:8399756e1ba1	962	uint32_t RESERVED0[1U];
MartinGurtner	60:8399756e1ba1	963	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
MartinGurtner	60:8399756e1ba1	964	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
MartinGurtner	60:8399756e1ba1	965	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
MartinGurtner	60:8399756e1ba1	966	} SCnSCB_Type;
MartinGurtner	60:8399756e1ba1	967
MartinGurtner	60:8399756e1ba1	968	/* Interrupt Controller Type Register Definitions */
MartinGurtner	60:8399756e1ba1	969	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
MartinGurtner	60:8399756e1ba1	970	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
MartinGurtner	60:8399756e1ba1	971
MartinGurtner	60:8399756e1ba1	972	/@} end of group CMSIS_SCnotSCB /
MartinGurtner	60:8399756e1ba1	973
MartinGurtner	60:8399756e1ba1	974
MartinGurtner	60:8399756e1ba1	975	/**
MartinGurtner	60:8399756e1ba1	976	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	977	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
MartinGurtner	60:8399756e1ba1	978	\brief Type definitions for the System Timer Registers.
MartinGurtner	60:8399756e1ba1	979	@{
MartinGurtner	60:8399756e1ba1	980	*/
MartinGurtner	60:8399756e1ba1	981
MartinGurtner	60:8399756e1ba1	982	/**
MartinGurtner	60:8399756e1ba1	983	\brief Structure type to access the System Timer (SysTick).
MartinGurtner	60:8399756e1ba1	984	*/
MartinGurtner	60:8399756e1ba1	985	typedef struct
MartinGurtner	60:8399756e1ba1	986	{
MartinGurtner	60:8399756e1ba1	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
MartinGurtner	60:8399756e1ba1	988	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
MartinGurtner	60:8399756e1ba1	989	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
MartinGurtner	60:8399756e1ba1	990	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
MartinGurtner	60:8399756e1ba1	991	} SysTick_Type;
MartinGurtner	60:8399756e1ba1	992
MartinGurtner	60:8399756e1ba1	993	/* SysTick Control / Status Register Definitions */
MartinGurtner	60:8399756e1ba1	994	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
MartinGurtner	60:8399756e1ba1	995	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
MartinGurtner	60:8399756e1ba1	996
MartinGurtner	60:8399756e1ba1	997	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
MartinGurtner	60:8399756e1ba1	998	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
MartinGurtner	60:8399756e1ba1	999
MartinGurtner	60:8399756e1ba1	1000	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
MartinGurtner	60:8399756e1ba1	1001	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
MartinGurtner	60:8399756e1ba1	1002
MartinGurtner	60:8399756e1ba1	1003	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
MartinGurtner	60:8399756e1ba1	1004	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
MartinGurtner	60:8399756e1ba1	1005
MartinGurtner	60:8399756e1ba1	1006	/* SysTick Reload Register Definitions */
MartinGurtner	60:8399756e1ba1	1007	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
MartinGurtner	60:8399756e1ba1	1008	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
MartinGurtner	60:8399756e1ba1	1009
MartinGurtner	60:8399756e1ba1	1010	/* SysTick Current Register Definitions */
MartinGurtner	60:8399756e1ba1	1011	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
MartinGurtner	60:8399756e1ba1	1012	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
MartinGurtner	60:8399756e1ba1	1013
MartinGurtner	60:8399756e1ba1	1014	/* SysTick Calibration Register Definitions */
MartinGurtner	60:8399756e1ba1	1015	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
MartinGurtner	60:8399756e1ba1	1016	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
MartinGurtner	60:8399756e1ba1	1017
MartinGurtner	60:8399756e1ba1	1018	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
MartinGurtner	60:8399756e1ba1	1019	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
MartinGurtner	60:8399756e1ba1	1020
MartinGurtner	60:8399756e1ba1	1021	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
MartinGurtner	60:8399756e1ba1	1022	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
MartinGurtner	60:8399756e1ba1	1023
MartinGurtner	60:8399756e1ba1	1024	/@} end of group CMSIS_SysTick /
MartinGurtner	60:8399756e1ba1	1025
MartinGurtner	60:8399756e1ba1	1026
MartinGurtner	60:8399756e1ba1	1027	/**
MartinGurtner	60:8399756e1ba1	1028	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1029	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
MartinGurtner	60:8399756e1ba1	1030	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
MartinGurtner	60:8399756e1ba1	1031	@{
MartinGurtner	60:8399756e1ba1	1032	*/
MartinGurtner	60:8399756e1ba1	1033
MartinGurtner	60:8399756e1ba1	1034	/**
MartinGurtner	60:8399756e1ba1	1035	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
MartinGurtner	60:8399756e1ba1	1036	*/
MartinGurtner	60:8399756e1ba1	1037	typedef struct
MartinGurtner	60:8399756e1ba1	1038	{
MartinGurtner	60:8399756e1ba1	1039	__OM union
MartinGurtner	60:8399756e1ba1	1040	{
MartinGurtner	60:8399756e1ba1	1041	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
MartinGurtner	60:8399756e1ba1	1042	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
MartinGurtner	60:8399756e1ba1	1043	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
MartinGurtner	60:8399756e1ba1	1044	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
MartinGurtner	60:8399756e1ba1	1045	uint32_t RESERVED0[864U];
MartinGurtner	60:8399756e1ba1	1046	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
MartinGurtner	60:8399756e1ba1	1047	uint32_t RESERVED1[15U];
MartinGurtner	60:8399756e1ba1	1048	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
MartinGurtner	60:8399756e1ba1	1049	uint32_t RESERVED2[15U];
MartinGurtner	60:8399756e1ba1	1050	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
MartinGurtner	60:8399756e1ba1	1051	uint32_t RESERVED3[29U];
MartinGurtner	60:8399756e1ba1	1052	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
MartinGurtner	60:8399756e1ba1	1053	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
MartinGurtner	60:8399756e1ba1	1054	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
MartinGurtner	60:8399756e1ba1	1055	uint32_t RESERVED4[43U];
MartinGurtner	60:8399756e1ba1	1056	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
MartinGurtner	60:8399756e1ba1	1057	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
MartinGurtner	60:8399756e1ba1	1058	uint32_t RESERVED5[1U];
MartinGurtner	60:8399756e1ba1	1059	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
MartinGurtner	60:8399756e1ba1	1060	uint32_t RESERVED6[4U];
MartinGurtner	60:8399756e1ba1	1061	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
MartinGurtner	60:8399756e1ba1	1062	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
MartinGurtner	60:8399756e1ba1	1063	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
MartinGurtner	60:8399756e1ba1	1064	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
MartinGurtner	60:8399756e1ba1	1065	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
MartinGurtner	60:8399756e1ba1	1066	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
MartinGurtner	60:8399756e1ba1	1067	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
MartinGurtner	60:8399756e1ba1	1068	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
MartinGurtner	60:8399756e1ba1	1069	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
MartinGurtner	60:8399756e1ba1	1070	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
MartinGurtner	60:8399756e1ba1	1071	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
MartinGurtner	60:8399756e1ba1	1072	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
MartinGurtner	60:8399756e1ba1	1073	} ITM_Type;
MartinGurtner	60:8399756e1ba1	1074
MartinGurtner	60:8399756e1ba1	1075	/* ITM Stimulus Port Register Definitions */
MartinGurtner	60:8399756e1ba1	1076	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
MartinGurtner	60:8399756e1ba1	1077	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
MartinGurtner	60:8399756e1ba1	1078
MartinGurtner	60:8399756e1ba1	1079	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
MartinGurtner	60:8399756e1ba1	1080	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
MartinGurtner	60:8399756e1ba1	1081
MartinGurtner	60:8399756e1ba1	1082	/* ITM Trace Privilege Register Definitions */
MartinGurtner	60:8399756e1ba1	1083	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
MartinGurtner	60:8399756e1ba1	1084	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
MartinGurtner	60:8399756e1ba1	1085
MartinGurtner	60:8399756e1ba1	1086	/* ITM Trace Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1087	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
MartinGurtner	60:8399756e1ba1	1088	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
MartinGurtner	60:8399756e1ba1	1089
MartinGurtner	60:8399756e1ba1	1090	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
MartinGurtner	60:8399756e1ba1	1091	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
MartinGurtner	60:8399756e1ba1	1092
MartinGurtner	60:8399756e1ba1	1093	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
MartinGurtner	60:8399756e1ba1	1094	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
MartinGurtner	60:8399756e1ba1	1095
MartinGurtner	60:8399756e1ba1	1096	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
MartinGurtner	60:8399756e1ba1	1097	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
MartinGurtner	60:8399756e1ba1	1098
MartinGurtner	60:8399756e1ba1	1099	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
MartinGurtner	60:8399756e1ba1	1100	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
MartinGurtner	60:8399756e1ba1	1101
MartinGurtner	60:8399756e1ba1	1102	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
MartinGurtner	60:8399756e1ba1	1103	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
MartinGurtner	60:8399756e1ba1	1104
MartinGurtner	60:8399756e1ba1	1105	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
MartinGurtner	60:8399756e1ba1	1106	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
MartinGurtner	60:8399756e1ba1	1107
MartinGurtner	60:8399756e1ba1	1108	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
MartinGurtner	60:8399756e1ba1	1109	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
MartinGurtner	60:8399756e1ba1	1110
MartinGurtner	60:8399756e1ba1	1111	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
MartinGurtner	60:8399756e1ba1	1112	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
MartinGurtner	60:8399756e1ba1	1113
MartinGurtner	60:8399756e1ba1	1114	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
MartinGurtner	60:8399756e1ba1	1115	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
MartinGurtner	60:8399756e1ba1	1116
MartinGurtner	60:8399756e1ba1	1117	/* ITM Integration Write Register Definitions */
MartinGurtner	60:8399756e1ba1	1118	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
MartinGurtner	60:8399756e1ba1	1119	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
MartinGurtner	60:8399756e1ba1	1120
MartinGurtner	60:8399756e1ba1	1121	/* ITM Integration Read Register Definitions */
MartinGurtner	60:8399756e1ba1	1122	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
MartinGurtner	60:8399756e1ba1	1123	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
MartinGurtner	60:8399756e1ba1	1124
MartinGurtner	60:8399756e1ba1	1125	/* ITM Integration Mode Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1126	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
MartinGurtner	60:8399756e1ba1	1127	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
MartinGurtner	60:8399756e1ba1	1128
MartinGurtner	60:8399756e1ba1	1129	/* ITM Lock Status Register Definitions */
MartinGurtner	60:8399756e1ba1	1130	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
MartinGurtner	60:8399756e1ba1	1131	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
MartinGurtner	60:8399756e1ba1	1132
MartinGurtner	60:8399756e1ba1	1133	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
MartinGurtner	60:8399756e1ba1	1134	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
MartinGurtner	60:8399756e1ba1	1135
MartinGurtner	60:8399756e1ba1	1136	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
MartinGurtner	60:8399756e1ba1	1137	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
MartinGurtner	60:8399756e1ba1	1138
MartinGurtner	60:8399756e1ba1	1139	/@}/ /* end of group CMSIS_ITM */
MartinGurtner	60:8399756e1ba1	1140
MartinGurtner	60:8399756e1ba1	1141
MartinGurtner	60:8399756e1ba1	1142	/**
MartinGurtner	60:8399756e1ba1	1143	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1144	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
MartinGurtner	60:8399756e1ba1	1145	\brief Type definitions for the Data Watchpoint and Trace (DWT)
MartinGurtner	60:8399756e1ba1	1146	@{
MartinGurtner	60:8399756e1ba1	1147	*/
MartinGurtner	60:8399756e1ba1	1148
MartinGurtner	60:8399756e1ba1	1149	/**
MartinGurtner	60:8399756e1ba1	1150	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
MartinGurtner	60:8399756e1ba1	1151	*/
MartinGurtner	60:8399756e1ba1	1152	typedef struct
MartinGurtner	60:8399756e1ba1	1153	{
MartinGurtner	60:8399756e1ba1	1154	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
MartinGurtner	60:8399756e1ba1	1155	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
MartinGurtner	60:8399756e1ba1	1156	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
MartinGurtner	60:8399756e1ba1	1157	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
MartinGurtner	60:8399756e1ba1	1158	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
MartinGurtner	60:8399756e1ba1	1159	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
MartinGurtner	60:8399756e1ba1	1160	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
MartinGurtner	60:8399756e1ba1	1161	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
MartinGurtner	60:8399756e1ba1	1162	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
MartinGurtner	60:8399756e1ba1	1163	uint32_t RESERVED1[1U];
MartinGurtner	60:8399756e1ba1	1164	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
MartinGurtner	60:8399756e1ba1	1165	uint32_t RESERVED2[1U];
MartinGurtner	60:8399756e1ba1	1166	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
MartinGurtner	60:8399756e1ba1	1167	uint32_t RESERVED3[1U];
MartinGurtner	60:8399756e1ba1	1168	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
MartinGurtner	60:8399756e1ba1	1169	uint32_t RESERVED4[1U];
MartinGurtner	60:8399756e1ba1	1170	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
MartinGurtner	60:8399756e1ba1	1171	uint32_t RESERVED5[1U];
MartinGurtner	60:8399756e1ba1	1172	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
MartinGurtner	60:8399756e1ba1	1173	uint32_t RESERVED6[1U];
MartinGurtner	60:8399756e1ba1	1174	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
MartinGurtner	60:8399756e1ba1	1175	uint32_t RESERVED7[1U];
MartinGurtner	60:8399756e1ba1	1176	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
MartinGurtner	60:8399756e1ba1	1177	uint32_t RESERVED8[1U];
MartinGurtner	60:8399756e1ba1	1178	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
MartinGurtner	60:8399756e1ba1	1179	uint32_t RESERVED9[1U];
MartinGurtner	60:8399756e1ba1	1180	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
MartinGurtner	60:8399756e1ba1	1181	uint32_t RESERVED10[1U];
MartinGurtner	60:8399756e1ba1	1182	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
MartinGurtner	60:8399756e1ba1	1183	uint32_t RESERVED11[1U];
MartinGurtner	60:8399756e1ba1	1184	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
MartinGurtner	60:8399756e1ba1	1185	uint32_t RESERVED12[1U];
MartinGurtner	60:8399756e1ba1	1186	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
MartinGurtner	60:8399756e1ba1	1187	uint32_t RESERVED13[1U];
MartinGurtner	60:8399756e1ba1	1188	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
MartinGurtner	60:8399756e1ba1	1189	uint32_t RESERVED14[1U];
MartinGurtner	60:8399756e1ba1	1190	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
MartinGurtner	60:8399756e1ba1	1191	uint32_t RESERVED15[1U];
MartinGurtner	60:8399756e1ba1	1192	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
MartinGurtner	60:8399756e1ba1	1193	uint32_t RESERVED16[1U];
MartinGurtner	60:8399756e1ba1	1194	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
MartinGurtner	60:8399756e1ba1	1195	uint32_t RESERVED17[1U];
MartinGurtner	60:8399756e1ba1	1196	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
MartinGurtner	60:8399756e1ba1	1197	uint32_t RESERVED18[1U];
MartinGurtner	60:8399756e1ba1	1198	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
MartinGurtner	60:8399756e1ba1	1199	uint32_t RESERVED19[1U];
MartinGurtner	60:8399756e1ba1	1200	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
MartinGurtner	60:8399756e1ba1	1201	uint32_t RESERVED20[1U];
MartinGurtner	60:8399756e1ba1	1202	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
MartinGurtner	60:8399756e1ba1	1203	uint32_t RESERVED21[1U];
MartinGurtner	60:8399756e1ba1	1204	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
MartinGurtner	60:8399756e1ba1	1205	uint32_t RESERVED22[1U];
MartinGurtner	60:8399756e1ba1	1206	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
MartinGurtner	60:8399756e1ba1	1207	uint32_t RESERVED23[1U];
MartinGurtner	60:8399756e1ba1	1208	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
MartinGurtner	60:8399756e1ba1	1209	uint32_t RESERVED24[1U];
MartinGurtner	60:8399756e1ba1	1210	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
MartinGurtner	60:8399756e1ba1	1211	uint32_t RESERVED25[1U];
MartinGurtner	60:8399756e1ba1	1212	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
MartinGurtner	60:8399756e1ba1	1213	uint32_t RESERVED26[1U];
MartinGurtner	60:8399756e1ba1	1214	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
MartinGurtner	60:8399756e1ba1	1215	uint32_t RESERVED27[1U];
MartinGurtner	60:8399756e1ba1	1216	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
MartinGurtner	60:8399756e1ba1	1217	uint32_t RESERVED28[1U];
MartinGurtner	60:8399756e1ba1	1218	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
MartinGurtner	60:8399756e1ba1	1219	uint32_t RESERVED29[1U];
MartinGurtner	60:8399756e1ba1	1220	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
MartinGurtner	60:8399756e1ba1	1221	uint32_t RESERVED30[1U];
MartinGurtner	60:8399756e1ba1	1222	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
MartinGurtner	60:8399756e1ba1	1223	uint32_t RESERVED31[1U];
MartinGurtner	60:8399756e1ba1	1224	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
MartinGurtner	60:8399756e1ba1	1225	uint32_t RESERVED32[934U];
MartinGurtner	60:8399756e1ba1	1226	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
MartinGurtner	60:8399756e1ba1	1227	uint32_t RESERVED33[1U];
MartinGurtner	60:8399756e1ba1	1228	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
MartinGurtner	60:8399756e1ba1	1229	} DWT_Type;
MartinGurtner	60:8399756e1ba1	1230
MartinGurtner	60:8399756e1ba1	1231	/* DWT Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1232	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
MartinGurtner	60:8399756e1ba1	1233	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
MartinGurtner	60:8399756e1ba1	1234
MartinGurtner	60:8399756e1ba1	1235	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
MartinGurtner	60:8399756e1ba1	1236	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
MartinGurtner	60:8399756e1ba1	1237
MartinGurtner	60:8399756e1ba1	1238	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
MartinGurtner	60:8399756e1ba1	1239	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
MartinGurtner	60:8399756e1ba1	1240
MartinGurtner	60:8399756e1ba1	1241	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
MartinGurtner	60:8399756e1ba1	1242	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
MartinGurtner	60:8399756e1ba1	1243
MartinGurtner	60:8399756e1ba1	1244	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
MartinGurtner	60:8399756e1ba1	1245	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
MartinGurtner	60:8399756e1ba1	1246
MartinGurtner	60:8399756e1ba1	1247	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
MartinGurtner	60:8399756e1ba1	1248	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
MartinGurtner	60:8399756e1ba1	1249
MartinGurtner	60:8399756e1ba1	1250	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
MartinGurtner	60:8399756e1ba1	1251	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1252
MartinGurtner	60:8399756e1ba1	1253	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
MartinGurtner	60:8399756e1ba1	1254	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1255
MartinGurtner	60:8399756e1ba1	1256	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
MartinGurtner	60:8399756e1ba1	1257	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1258
MartinGurtner	60:8399756e1ba1	1259	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
MartinGurtner	60:8399756e1ba1	1260	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1261
MartinGurtner	60:8399756e1ba1	1262	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
MartinGurtner	60:8399756e1ba1	1263	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1264
MartinGurtner	60:8399756e1ba1	1265	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
MartinGurtner	60:8399756e1ba1	1266	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
MartinGurtner	60:8399756e1ba1	1267
MartinGurtner	60:8399756e1ba1	1268	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
MartinGurtner	60:8399756e1ba1	1269	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
MartinGurtner	60:8399756e1ba1	1270
MartinGurtner	60:8399756e1ba1	1271	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
MartinGurtner	60:8399756e1ba1	1272	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
MartinGurtner	60:8399756e1ba1	1273
MartinGurtner	60:8399756e1ba1	1274	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
MartinGurtner	60:8399756e1ba1	1275	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
MartinGurtner	60:8399756e1ba1	1276
MartinGurtner	60:8399756e1ba1	1277	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
MartinGurtner	60:8399756e1ba1	1278	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
MartinGurtner	60:8399756e1ba1	1279
MartinGurtner	60:8399756e1ba1	1280	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
MartinGurtner	60:8399756e1ba1	1281	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
MartinGurtner	60:8399756e1ba1	1282
MartinGurtner	60:8399756e1ba1	1283	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
MartinGurtner	60:8399756e1ba1	1284	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
MartinGurtner	60:8399756e1ba1	1285
MartinGurtner	60:8399756e1ba1	1286	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
MartinGurtner	60:8399756e1ba1	1287	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
MartinGurtner	60:8399756e1ba1	1288
MartinGurtner	60:8399756e1ba1	1289	/* DWT CPI Count Register Definitions */
MartinGurtner	60:8399756e1ba1	1290	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
MartinGurtner	60:8399756e1ba1	1291	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
MartinGurtner	60:8399756e1ba1	1292
MartinGurtner	60:8399756e1ba1	1293	/* DWT Exception Overhead Count Register Definitions */
MartinGurtner	60:8399756e1ba1	1294	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
MartinGurtner	60:8399756e1ba1	1295	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
MartinGurtner	60:8399756e1ba1	1296
MartinGurtner	60:8399756e1ba1	1297	/* DWT Sleep Count Register Definitions */
MartinGurtner	60:8399756e1ba1	1298	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
MartinGurtner	60:8399756e1ba1	1299	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
MartinGurtner	60:8399756e1ba1	1300
MartinGurtner	60:8399756e1ba1	1301	/* DWT LSU Count Register Definitions */
MartinGurtner	60:8399756e1ba1	1302	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
MartinGurtner	60:8399756e1ba1	1303	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
MartinGurtner	60:8399756e1ba1	1304
MartinGurtner	60:8399756e1ba1	1305	/* DWT Folded-instruction Count Register Definitions */
MartinGurtner	60:8399756e1ba1	1306	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
MartinGurtner	60:8399756e1ba1	1307	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
MartinGurtner	60:8399756e1ba1	1308
MartinGurtner	60:8399756e1ba1	1309	/* DWT Comparator Function Register Definitions */
MartinGurtner	60:8399756e1ba1	1310	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
MartinGurtner	60:8399756e1ba1	1311	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
MartinGurtner	60:8399756e1ba1	1312
MartinGurtner	60:8399756e1ba1	1313	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
MartinGurtner	60:8399756e1ba1	1314	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
MartinGurtner	60:8399756e1ba1	1315
MartinGurtner	60:8399756e1ba1	1316	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
MartinGurtner	60:8399756e1ba1	1317	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
MartinGurtner	60:8399756e1ba1	1318
MartinGurtner	60:8399756e1ba1	1319	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
MartinGurtner	60:8399756e1ba1	1320	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
MartinGurtner	60:8399756e1ba1	1321
MartinGurtner	60:8399756e1ba1	1322	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
MartinGurtner	60:8399756e1ba1	1323	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
MartinGurtner	60:8399756e1ba1	1324
MartinGurtner	60:8399756e1ba1	1325	/@}/ /* end of group CMSIS_DWT */
MartinGurtner	60:8399756e1ba1	1326
MartinGurtner	60:8399756e1ba1	1327
MartinGurtner	60:8399756e1ba1	1328	/**
MartinGurtner	60:8399756e1ba1	1329	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1330	\defgroup CMSIS_TPI Trace Port Interface (TPI)
MartinGurtner	60:8399756e1ba1	1331	\brief Type definitions for the Trace Port Interface (TPI)
MartinGurtner	60:8399756e1ba1	1332	@{
MartinGurtner	60:8399756e1ba1	1333	*/
MartinGurtner	60:8399756e1ba1	1334
MartinGurtner	60:8399756e1ba1	1335	/**
MartinGurtner	60:8399756e1ba1	1336	\brief Structure type to access the Trace Port Interface Register (TPI).
MartinGurtner	60:8399756e1ba1	1337	*/
MartinGurtner	60:8399756e1ba1	1338	typedef struct
MartinGurtner	60:8399756e1ba1	1339	{
MartinGurtner	60:8399756e1ba1	1340	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
MartinGurtner	60:8399756e1ba1	1341	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
MartinGurtner	60:8399756e1ba1	1342	uint32_t RESERVED0[2U];
MartinGurtner	60:8399756e1ba1	1343	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
MartinGurtner	60:8399756e1ba1	1344	uint32_t RESERVED1[55U];
MartinGurtner	60:8399756e1ba1	1345	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
MartinGurtner	60:8399756e1ba1	1346	uint32_t RESERVED2[131U];
MartinGurtner	60:8399756e1ba1	1347	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
MartinGurtner	60:8399756e1ba1	1348	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
MartinGurtner	60:8399756e1ba1	1349	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
MartinGurtner	60:8399756e1ba1	1350	uint32_t RESERVED3[759U];
MartinGurtner	60:8399756e1ba1	1351	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
MartinGurtner	60:8399756e1ba1	1352	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
MartinGurtner	60:8399756e1ba1	1353	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
MartinGurtner	60:8399756e1ba1	1354	uint32_t RESERVED4[1U];
MartinGurtner	60:8399756e1ba1	1355	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
MartinGurtner	60:8399756e1ba1	1356	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
MartinGurtner	60:8399756e1ba1	1357	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
MartinGurtner	60:8399756e1ba1	1358	uint32_t RESERVED5[39U];
MartinGurtner	60:8399756e1ba1	1359	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
MartinGurtner	60:8399756e1ba1	1360	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
MartinGurtner	60:8399756e1ba1	1361	uint32_t RESERVED7[8U];
MartinGurtner	60:8399756e1ba1	1362	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
MartinGurtner	60:8399756e1ba1	1363	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
MartinGurtner	60:8399756e1ba1	1364	} TPI_Type;
MartinGurtner	60:8399756e1ba1	1365
MartinGurtner	60:8399756e1ba1	1366	/* TPI Asynchronous Clock Prescaler Register Definitions */
MartinGurtner	60:8399756e1ba1	1367	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
MartinGurtner	60:8399756e1ba1	1368	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
MartinGurtner	60:8399756e1ba1	1369
MartinGurtner	60:8399756e1ba1	1370	/* TPI Selected Pin Protocol Register Definitions */
MartinGurtner	60:8399756e1ba1	1371	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
MartinGurtner	60:8399756e1ba1	1372	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
MartinGurtner	60:8399756e1ba1	1373
MartinGurtner	60:8399756e1ba1	1374	/* TPI Formatter and Flush Status Register Definitions */
MartinGurtner	60:8399756e1ba1	1375	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
MartinGurtner	60:8399756e1ba1	1376	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
MartinGurtner	60:8399756e1ba1	1377
MartinGurtner	60:8399756e1ba1	1378	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
MartinGurtner	60:8399756e1ba1	1379	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
MartinGurtner	60:8399756e1ba1	1380
MartinGurtner	60:8399756e1ba1	1381	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
MartinGurtner	60:8399756e1ba1	1382	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
MartinGurtner	60:8399756e1ba1	1383
MartinGurtner	60:8399756e1ba1	1384	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
MartinGurtner	60:8399756e1ba1	1385	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
MartinGurtner	60:8399756e1ba1	1386
MartinGurtner	60:8399756e1ba1	1387	/* TPI Formatter and Flush Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1388	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
MartinGurtner	60:8399756e1ba1	1389	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
MartinGurtner	60:8399756e1ba1	1390
MartinGurtner	60:8399756e1ba1	1391	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
MartinGurtner	60:8399756e1ba1	1392	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
MartinGurtner	60:8399756e1ba1	1393
MartinGurtner	60:8399756e1ba1	1394	/* TPI TRIGGER Register Definitions */
MartinGurtner	60:8399756e1ba1	1395	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
MartinGurtner	60:8399756e1ba1	1396	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
MartinGurtner	60:8399756e1ba1	1397
MartinGurtner	60:8399756e1ba1	1398	/* TPI Integration ETM Data Register Definitions (FIFO0) */
MartinGurtner	60:8399756e1ba1	1399	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
MartinGurtner	60:8399756e1ba1	1400	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
MartinGurtner	60:8399756e1ba1	1401
MartinGurtner	60:8399756e1ba1	1402	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
MartinGurtner	60:8399756e1ba1	1403	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
MartinGurtner	60:8399756e1ba1	1404
MartinGurtner	60:8399756e1ba1	1405	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
MartinGurtner	60:8399756e1ba1	1406	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
MartinGurtner	60:8399756e1ba1	1407
MartinGurtner	60:8399756e1ba1	1408	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
MartinGurtner	60:8399756e1ba1	1409	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
MartinGurtner	60:8399756e1ba1	1410
MartinGurtner	60:8399756e1ba1	1411	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
MartinGurtner	60:8399756e1ba1	1412	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
MartinGurtner	60:8399756e1ba1	1413
MartinGurtner	60:8399756e1ba1	1414	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
MartinGurtner	60:8399756e1ba1	1415	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
MartinGurtner	60:8399756e1ba1	1416
MartinGurtner	60:8399756e1ba1	1417	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
MartinGurtner	60:8399756e1ba1	1418	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
MartinGurtner	60:8399756e1ba1	1419
MartinGurtner	60:8399756e1ba1	1420	/* TPI ITATBCTR2 Register Definitions */
MartinGurtner	60:8399756e1ba1	1421	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
MartinGurtner	60:8399756e1ba1	1422	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
MartinGurtner	60:8399756e1ba1	1423
MartinGurtner	60:8399756e1ba1	1424	/* TPI Integration ITM Data Register Definitions (FIFO1) */
MartinGurtner	60:8399756e1ba1	1425	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
MartinGurtner	60:8399756e1ba1	1426	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
MartinGurtner	60:8399756e1ba1	1427
MartinGurtner	60:8399756e1ba1	1428	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
MartinGurtner	60:8399756e1ba1	1429	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
MartinGurtner	60:8399756e1ba1	1430
MartinGurtner	60:8399756e1ba1	1431	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
MartinGurtner	60:8399756e1ba1	1432	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
MartinGurtner	60:8399756e1ba1	1433
MartinGurtner	60:8399756e1ba1	1434	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
MartinGurtner	60:8399756e1ba1	1435	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
MartinGurtner	60:8399756e1ba1	1436
MartinGurtner	60:8399756e1ba1	1437	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
MartinGurtner	60:8399756e1ba1	1438	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
MartinGurtner	60:8399756e1ba1	1439
MartinGurtner	60:8399756e1ba1	1440	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
MartinGurtner	60:8399756e1ba1	1441	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
MartinGurtner	60:8399756e1ba1	1442
MartinGurtner	60:8399756e1ba1	1443	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
MartinGurtner	60:8399756e1ba1	1444	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
MartinGurtner	60:8399756e1ba1	1445
MartinGurtner	60:8399756e1ba1	1446	/* TPI ITATBCTR0 Register Definitions */
MartinGurtner	60:8399756e1ba1	1447	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
MartinGurtner	60:8399756e1ba1	1448	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
MartinGurtner	60:8399756e1ba1	1449
MartinGurtner	60:8399756e1ba1	1450	/* TPI Integration Mode Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1451	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
MartinGurtner	60:8399756e1ba1	1452	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
MartinGurtner	60:8399756e1ba1	1453
MartinGurtner	60:8399756e1ba1	1454	/* TPI DEVID Register Definitions */
MartinGurtner	60:8399756e1ba1	1455	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
MartinGurtner	60:8399756e1ba1	1456	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
MartinGurtner	60:8399756e1ba1	1457
MartinGurtner	60:8399756e1ba1	1458	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
MartinGurtner	60:8399756e1ba1	1459	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
MartinGurtner	60:8399756e1ba1	1460
MartinGurtner	60:8399756e1ba1	1461	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
MartinGurtner	60:8399756e1ba1	1462	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
MartinGurtner	60:8399756e1ba1	1463
MartinGurtner	60:8399756e1ba1	1464	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
MartinGurtner	60:8399756e1ba1	1465	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
MartinGurtner	60:8399756e1ba1	1466
MartinGurtner	60:8399756e1ba1	1467	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
MartinGurtner	60:8399756e1ba1	1468	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
MartinGurtner	60:8399756e1ba1	1469
MartinGurtner	60:8399756e1ba1	1470	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
MartinGurtner	60:8399756e1ba1	1471	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
MartinGurtner	60:8399756e1ba1	1472
MartinGurtner	60:8399756e1ba1	1473	/* TPI DEVTYPE Register Definitions */
MartinGurtner	60:8399756e1ba1	1474	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
MartinGurtner	60:8399756e1ba1	1475	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
MartinGurtner	60:8399756e1ba1	1476
MartinGurtner	60:8399756e1ba1	1477	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
MartinGurtner	60:8399756e1ba1	1478	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
MartinGurtner	60:8399756e1ba1	1479
MartinGurtner	60:8399756e1ba1	1480	/@}/ /* end of group CMSIS_TPI */
MartinGurtner	60:8399756e1ba1	1481
MartinGurtner	60:8399756e1ba1	1482
MartinGurtner	60:8399756e1ba1	1483	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	1484	/**
MartinGurtner	60:8399756e1ba1	1485	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1486	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
MartinGurtner	60:8399756e1ba1	1487	\brief Type definitions for the Memory Protection Unit (MPU)
MartinGurtner	60:8399756e1ba1	1488	@{
MartinGurtner	60:8399756e1ba1	1489	*/
MartinGurtner	60:8399756e1ba1	1490
MartinGurtner	60:8399756e1ba1	1491	/**
MartinGurtner	60:8399756e1ba1	1492	\brief Structure type to access the Memory Protection Unit (MPU).
MartinGurtner	60:8399756e1ba1	1493	*/
MartinGurtner	60:8399756e1ba1	1494	typedef struct
MartinGurtner	60:8399756e1ba1	1495	{
MartinGurtner	60:8399756e1ba1	1496	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
MartinGurtner	60:8399756e1ba1	1497	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
MartinGurtner	60:8399756e1ba1	1498	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
MartinGurtner	60:8399756e1ba1	1499	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
MartinGurtner	60:8399756e1ba1	1500	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
MartinGurtner	60:8399756e1ba1	1501	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
MartinGurtner	60:8399756e1ba1	1502	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
MartinGurtner	60:8399756e1ba1	1503	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
MartinGurtner	60:8399756e1ba1	1504	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
MartinGurtner	60:8399756e1ba1	1505	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
MartinGurtner	60:8399756e1ba1	1506	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
MartinGurtner	60:8399756e1ba1	1507	uint32_t RESERVED0[1];
MartinGurtner	60:8399756e1ba1	1508	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
MartinGurtner	60:8399756e1ba1	1509	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
MartinGurtner	60:8399756e1ba1	1510	} MPU_Type;
MartinGurtner	60:8399756e1ba1	1511
MartinGurtner	60:8399756e1ba1	1512	/* MPU Type Register Definitions */
MartinGurtner	60:8399756e1ba1	1513	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
MartinGurtner	60:8399756e1ba1	1514	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
MartinGurtner	60:8399756e1ba1	1515
MartinGurtner	60:8399756e1ba1	1516	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
MartinGurtner	60:8399756e1ba1	1517	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
MartinGurtner	60:8399756e1ba1	1518
MartinGurtner	60:8399756e1ba1	1519	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
MartinGurtner	60:8399756e1ba1	1520	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
MartinGurtner	60:8399756e1ba1	1521
MartinGurtner	60:8399756e1ba1	1522	/* MPU Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1523	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
MartinGurtner	60:8399756e1ba1	1524	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
MartinGurtner	60:8399756e1ba1	1525
MartinGurtner	60:8399756e1ba1	1526	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
MartinGurtner	60:8399756e1ba1	1527	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
MartinGurtner	60:8399756e1ba1	1528
MartinGurtner	60:8399756e1ba1	1529	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
MartinGurtner	60:8399756e1ba1	1530	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
MartinGurtner	60:8399756e1ba1	1531
MartinGurtner	60:8399756e1ba1	1532	/* MPU Region Number Register Definitions */
MartinGurtner	60:8399756e1ba1	1533	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
MartinGurtner	60:8399756e1ba1	1534	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
MartinGurtner	60:8399756e1ba1	1535
MartinGurtner	60:8399756e1ba1	1536	/* MPU Region Base Address Register Definitions */
MartinGurtner	60:8399756e1ba1	1537	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
MartinGurtner	60:8399756e1ba1	1538	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
MartinGurtner	60:8399756e1ba1	1539
MartinGurtner	60:8399756e1ba1	1540	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
MartinGurtner	60:8399756e1ba1	1541	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
MartinGurtner	60:8399756e1ba1	1542
MartinGurtner	60:8399756e1ba1	1543	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
MartinGurtner	60:8399756e1ba1	1544	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
MartinGurtner	60:8399756e1ba1	1545
MartinGurtner	60:8399756e1ba1	1546	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
MartinGurtner	60:8399756e1ba1	1547	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
MartinGurtner	60:8399756e1ba1	1548
MartinGurtner	60:8399756e1ba1	1549	/* MPU Region Limit Address Register Definitions */
MartinGurtner	60:8399756e1ba1	1550	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
MartinGurtner	60:8399756e1ba1	1551	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
MartinGurtner	60:8399756e1ba1	1552
MartinGurtner	60:8399756e1ba1	1553	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
MartinGurtner	60:8399756e1ba1	1554	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
MartinGurtner	60:8399756e1ba1	1555
MartinGurtner	60:8399756e1ba1	1556	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
MartinGurtner	60:8399756e1ba1	1557	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
MartinGurtner	60:8399756e1ba1	1558
MartinGurtner	60:8399756e1ba1	1559	/* MPU Memory Attribute Indirection Register 0 Definitions */
MartinGurtner	60:8399756e1ba1	1560	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
MartinGurtner	60:8399756e1ba1	1561	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
MartinGurtner	60:8399756e1ba1	1562
MartinGurtner	60:8399756e1ba1	1563	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
MartinGurtner	60:8399756e1ba1	1564	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
MartinGurtner	60:8399756e1ba1	1565
MartinGurtner	60:8399756e1ba1	1566	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
MartinGurtner	60:8399756e1ba1	1567	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
MartinGurtner	60:8399756e1ba1	1568
MartinGurtner	60:8399756e1ba1	1569	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
MartinGurtner	60:8399756e1ba1	1570	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
MartinGurtner	60:8399756e1ba1	1571
MartinGurtner	60:8399756e1ba1	1572	/* MPU Memory Attribute Indirection Register 1 Definitions */
MartinGurtner	60:8399756e1ba1	1573	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
MartinGurtner	60:8399756e1ba1	1574	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
MartinGurtner	60:8399756e1ba1	1575
MartinGurtner	60:8399756e1ba1	1576	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
MartinGurtner	60:8399756e1ba1	1577	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
MartinGurtner	60:8399756e1ba1	1578
MartinGurtner	60:8399756e1ba1	1579	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
MartinGurtner	60:8399756e1ba1	1580	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
MartinGurtner	60:8399756e1ba1	1581
MartinGurtner	60:8399756e1ba1	1582	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
MartinGurtner	60:8399756e1ba1	1583	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
MartinGurtner	60:8399756e1ba1	1584
MartinGurtner	60:8399756e1ba1	1585	/@} end of group CMSIS_MPU /
MartinGurtner	60:8399756e1ba1	1586	#endif
MartinGurtner	60:8399756e1ba1	1587
MartinGurtner	60:8399756e1ba1	1588
MartinGurtner	60:8399756e1ba1	1589	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	1590	/**
MartinGurtner	60:8399756e1ba1	1591	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1592	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
MartinGurtner	60:8399756e1ba1	1593	\brief Type definitions for the Security Attribution Unit (SAU)
MartinGurtner	60:8399756e1ba1	1594	@{
MartinGurtner	60:8399756e1ba1	1595	*/
MartinGurtner	60:8399756e1ba1	1596
MartinGurtner	60:8399756e1ba1	1597	/**
MartinGurtner	60:8399756e1ba1	1598	\brief Structure type to access the Security Attribution Unit (SAU).
MartinGurtner	60:8399756e1ba1	1599	*/
MartinGurtner	60:8399756e1ba1	1600	typedef struct
MartinGurtner	60:8399756e1ba1	1601	{
MartinGurtner	60:8399756e1ba1	1602	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
MartinGurtner	60:8399756e1ba1	1603	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
MartinGurtner	60:8399756e1ba1	1604	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	1605	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
MartinGurtner	60:8399756e1ba1	1606	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
MartinGurtner	60:8399756e1ba1	1607	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
MartinGurtner	60:8399756e1ba1	1608	#else
MartinGurtner	60:8399756e1ba1	1609	uint32_t RESERVED0[3];
MartinGurtner	60:8399756e1ba1	1610	#endif
MartinGurtner	60:8399756e1ba1	1611	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
MartinGurtner	60:8399756e1ba1	1612	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
MartinGurtner	60:8399756e1ba1	1613	} SAU_Type;
MartinGurtner	60:8399756e1ba1	1614
MartinGurtner	60:8399756e1ba1	1615	/* SAU Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1616	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
MartinGurtner	60:8399756e1ba1	1617	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
MartinGurtner	60:8399756e1ba1	1618
MartinGurtner	60:8399756e1ba1	1619	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
MartinGurtner	60:8399756e1ba1	1620	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
MartinGurtner	60:8399756e1ba1	1621
MartinGurtner	60:8399756e1ba1	1622	/* SAU Type Register Definitions */
MartinGurtner	60:8399756e1ba1	1623	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
MartinGurtner	60:8399756e1ba1	1624	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
MartinGurtner	60:8399756e1ba1	1625
MartinGurtner	60:8399756e1ba1	1626	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	1627	/* SAU Region Number Register Definitions */
MartinGurtner	60:8399756e1ba1	1628	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
MartinGurtner	60:8399756e1ba1	1629	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
MartinGurtner	60:8399756e1ba1	1630
MartinGurtner	60:8399756e1ba1	1631	/* SAU Region Base Address Register Definitions */
MartinGurtner	60:8399756e1ba1	1632	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
MartinGurtner	60:8399756e1ba1	1633	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
MartinGurtner	60:8399756e1ba1	1634
MartinGurtner	60:8399756e1ba1	1635	/* SAU Region Limit Address Register Definitions */
MartinGurtner	60:8399756e1ba1	1636	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
MartinGurtner	60:8399756e1ba1	1637	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
MartinGurtner	60:8399756e1ba1	1638
MartinGurtner	60:8399756e1ba1	1639	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
MartinGurtner	60:8399756e1ba1	1640	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
MartinGurtner	60:8399756e1ba1	1641
MartinGurtner	60:8399756e1ba1	1642	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
MartinGurtner	60:8399756e1ba1	1643	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
MartinGurtner	60:8399756e1ba1	1644
MartinGurtner	60:8399756e1ba1	1645	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
MartinGurtner	60:8399756e1ba1	1646
MartinGurtner	60:8399756e1ba1	1647	/* Secure Fault Status Register Definitions */
MartinGurtner	60:8399756e1ba1	1648	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
MartinGurtner	60:8399756e1ba1	1649	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
MartinGurtner	60:8399756e1ba1	1650
MartinGurtner	60:8399756e1ba1	1651	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
MartinGurtner	60:8399756e1ba1	1652	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
MartinGurtner	60:8399756e1ba1	1653
MartinGurtner	60:8399756e1ba1	1654	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
MartinGurtner	60:8399756e1ba1	1655	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
MartinGurtner	60:8399756e1ba1	1656
MartinGurtner	60:8399756e1ba1	1657	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
MartinGurtner	60:8399756e1ba1	1658	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
MartinGurtner	60:8399756e1ba1	1659
MartinGurtner	60:8399756e1ba1	1660	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
MartinGurtner	60:8399756e1ba1	1661	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
MartinGurtner	60:8399756e1ba1	1662
MartinGurtner	60:8399756e1ba1	1663	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
MartinGurtner	60:8399756e1ba1	1664	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
MartinGurtner	60:8399756e1ba1	1665
MartinGurtner	60:8399756e1ba1	1666	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
MartinGurtner	60:8399756e1ba1	1667	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
MartinGurtner	60:8399756e1ba1	1668
MartinGurtner	60:8399756e1ba1	1669	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
MartinGurtner	60:8399756e1ba1	1670	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
MartinGurtner	60:8399756e1ba1	1671
MartinGurtner	60:8399756e1ba1	1672	/@} end of group CMSIS_SAU /
MartinGurtner	60:8399756e1ba1	1673	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	1674
MartinGurtner	60:8399756e1ba1	1675
MartinGurtner	60:8399756e1ba1	1676	/**
MartinGurtner	60:8399756e1ba1	1677	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1678	\defgroup CMSIS_FPU Floating Point Unit (FPU)
MartinGurtner	60:8399756e1ba1	1679	\brief Type definitions for the Floating Point Unit (FPU)
MartinGurtner	60:8399756e1ba1	1680	@{
MartinGurtner	60:8399756e1ba1	1681	*/
MartinGurtner	60:8399756e1ba1	1682
MartinGurtner	60:8399756e1ba1	1683	/**
MartinGurtner	60:8399756e1ba1	1684	\brief Structure type to access the Floating Point Unit (FPU).
MartinGurtner	60:8399756e1ba1	1685	*/
MartinGurtner	60:8399756e1ba1	1686	typedef struct
MartinGurtner	60:8399756e1ba1	1687	{
MartinGurtner	60:8399756e1ba1	1688	uint32_t RESERVED0[1U];
MartinGurtner	60:8399756e1ba1	1689	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
MartinGurtner	60:8399756e1ba1	1690	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
MartinGurtner	60:8399756e1ba1	1691	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
MartinGurtner	60:8399756e1ba1	1692	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
MartinGurtner	60:8399756e1ba1	1693	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
MartinGurtner	60:8399756e1ba1	1694	} FPU_Type;
MartinGurtner	60:8399756e1ba1	1695
MartinGurtner	60:8399756e1ba1	1696	/* Floating-Point Context Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1697	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
MartinGurtner	60:8399756e1ba1	1698	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
MartinGurtner	60:8399756e1ba1	1699
MartinGurtner	60:8399756e1ba1	1700	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
MartinGurtner	60:8399756e1ba1	1701	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
MartinGurtner	60:8399756e1ba1	1702
MartinGurtner	60:8399756e1ba1	1703	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
MartinGurtner	60:8399756e1ba1	1704	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
MartinGurtner	60:8399756e1ba1	1705
MartinGurtner	60:8399756e1ba1	1706	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
MartinGurtner	60:8399756e1ba1	1707	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
MartinGurtner	60:8399756e1ba1	1708
MartinGurtner	60:8399756e1ba1	1709	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
MartinGurtner	60:8399756e1ba1	1710	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
MartinGurtner	60:8399756e1ba1	1711
MartinGurtner	60:8399756e1ba1	1712	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
MartinGurtner	60:8399756e1ba1	1713	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
MartinGurtner	60:8399756e1ba1	1714
MartinGurtner	60:8399756e1ba1	1715	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
MartinGurtner	60:8399756e1ba1	1716	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1717
MartinGurtner	60:8399756e1ba1	1718	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
MartinGurtner	60:8399756e1ba1	1719	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
MartinGurtner	60:8399756e1ba1	1720
MartinGurtner	60:8399756e1ba1	1721	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
MartinGurtner	60:8399756e1ba1	1722	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1723
MartinGurtner	60:8399756e1ba1	1724	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
MartinGurtner	60:8399756e1ba1	1725	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1726
MartinGurtner	60:8399756e1ba1	1727	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
MartinGurtner	60:8399756e1ba1	1728	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1729
MartinGurtner	60:8399756e1ba1	1730	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
MartinGurtner	60:8399756e1ba1	1731	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1732
MartinGurtner	60:8399756e1ba1	1733	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
MartinGurtner	60:8399756e1ba1	1734	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
MartinGurtner	60:8399756e1ba1	1735
MartinGurtner	60:8399756e1ba1	1736	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
MartinGurtner	60:8399756e1ba1	1737	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
MartinGurtner	60:8399756e1ba1	1738
MartinGurtner	60:8399756e1ba1	1739	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
MartinGurtner	60:8399756e1ba1	1740	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
MartinGurtner	60:8399756e1ba1	1741
MartinGurtner	60:8399756e1ba1	1742	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
MartinGurtner	60:8399756e1ba1	1743	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
MartinGurtner	60:8399756e1ba1	1744
MartinGurtner	60:8399756e1ba1	1745	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
MartinGurtner	60:8399756e1ba1	1746	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
MartinGurtner	60:8399756e1ba1	1747
MartinGurtner	60:8399756e1ba1	1748	/* Floating-Point Context Address Register Definitions */
MartinGurtner	60:8399756e1ba1	1749	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
MartinGurtner	60:8399756e1ba1	1750	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
MartinGurtner	60:8399756e1ba1	1751
MartinGurtner	60:8399756e1ba1	1752	/* Floating-Point Default Status Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1753	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
MartinGurtner	60:8399756e1ba1	1754	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
MartinGurtner	60:8399756e1ba1	1755
MartinGurtner	60:8399756e1ba1	1756	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
MartinGurtner	60:8399756e1ba1	1757	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
MartinGurtner	60:8399756e1ba1	1758
MartinGurtner	60:8399756e1ba1	1759	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
MartinGurtner	60:8399756e1ba1	1760	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
MartinGurtner	60:8399756e1ba1	1761
MartinGurtner	60:8399756e1ba1	1762	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
MartinGurtner	60:8399756e1ba1	1763	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
MartinGurtner	60:8399756e1ba1	1764
MartinGurtner	60:8399756e1ba1	1765	/* Media and FP Feature Register 0 Definitions */
MartinGurtner	60:8399756e1ba1	1766	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
MartinGurtner	60:8399756e1ba1	1767	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
MartinGurtner	60:8399756e1ba1	1768
MartinGurtner	60:8399756e1ba1	1769	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
MartinGurtner	60:8399756e1ba1	1770	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
MartinGurtner	60:8399756e1ba1	1771
MartinGurtner	60:8399756e1ba1	1772	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
MartinGurtner	60:8399756e1ba1	1773	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
MartinGurtner	60:8399756e1ba1	1774
MartinGurtner	60:8399756e1ba1	1775	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
MartinGurtner	60:8399756e1ba1	1776	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
MartinGurtner	60:8399756e1ba1	1777
MartinGurtner	60:8399756e1ba1	1778	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
MartinGurtner	60:8399756e1ba1	1779	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
MartinGurtner	60:8399756e1ba1	1780
MartinGurtner	60:8399756e1ba1	1781	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
MartinGurtner	60:8399756e1ba1	1782	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
MartinGurtner	60:8399756e1ba1	1783
MartinGurtner	60:8399756e1ba1	1784	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
MartinGurtner	60:8399756e1ba1	1785	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
MartinGurtner	60:8399756e1ba1	1786
MartinGurtner	60:8399756e1ba1	1787	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
MartinGurtner	60:8399756e1ba1	1788	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
MartinGurtner	60:8399756e1ba1	1789
MartinGurtner	60:8399756e1ba1	1790	/* Media and FP Feature Register 1 Definitions */
MartinGurtner	60:8399756e1ba1	1791	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
MartinGurtner	60:8399756e1ba1	1792	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
MartinGurtner	60:8399756e1ba1	1793
MartinGurtner	60:8399756e1ba1	1794	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
MartinGurtner	60:8399756e1ba1	1795	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
MartinGurtner	60:8399756e1ba1	1796
MartinGurtner	60:8399756e1ba1	1797	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
MartinGurtner	60:8399756e1ba1	1798	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
MartinGurtner	60:8399756e1ba1	1799
MartinGurtner	60:8399756e1ba1	1800	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
MartinGurtner	60:8399756e1ba1	1801	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
MartinGurtner	60:8399756e1ba1	1802
MartinGurtner	60:8399756e1ba1	1803	/@} end of group CMSIS_FPU /
MartinGurtner	60:8399756e1ba1	1804
MartinGurtner	60:8399756e1ba1	1805
MartinGurtner	60:8399756e1ba1	1806	/**
MartinGurtner	60:8399756e1ba1	1807	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1808	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
MartinGurtner	60:8399756e1ba1	1809	\brief Type definitions for the Core Debug Registers
MartinGurtner	60:8399756e1ba1	1810	@{
MartinGurtner	60:8399756e1ba1	1811	*/
MartinGurtner	60:8399756e1ba1	1812
MartinGurtner	60:8399756e1ba1	1813	/**
MartinGurtner	60:8399756e1ba1	1814	\brief Structure type to access the Core Debug Register (CoreDebug).
MartinGurtner	60:8399756e1ba1	1815	*/
MartinGurtner	60:8399756e1ba1	1816	typedef struct
MartinGurtner	60:8399756e1ba1	1817	{
MartinGurtner	60:8399756e1ba1	1818	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
MartinGurtner	60:8399756e1ba1	1819	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
MartinGurtner	60:8399756e1ba1	1820	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
MartinGurtner	60:8399756e1ba1	1821	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
MartinGurtner	60:8399756e1ba1	1822	uint32_t RESERVED4[1U];
MartinGurtner	60:8399756e1ba1	1823	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
MartinGurtner	60:8399756e1ba1	1824	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
MartinGurtner	60:8399756e1ba1	1825	} CoreDebug_Type;
MartinGurtner	60:8399756e1ba1	1826
MartinGurtner	60:8399756e1ba1	1827	/* Debug Halting Control and Status Register Definitions */
MartinGurtner	60:8399756e1ba1	1828	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
MartinGurtner	60:8399756e1ba1	1829	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
MartinGurtner	60:8399756e1ba1	1830
MartinGurtner	60:8399756e1ba1	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
MartinGurtner	60:8399756e1ba1	1832	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
MartinGurtner	60:8399756e1ba1	1833
MartinGurtner	60:8399756e1ba1	1834	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
MartinGurtner	60:8399756e1ba1	1835	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
MartinGurtner	60:8399756e1ba1	1836
MartinGurtner	60:8399756e1ba1	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
MartinGurtner	60:8399756e1ba1	1838	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
MartinGurtner	60:8399756e1ba1	1839
MartinGurtner	60:8399756e1ba1	1840	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
MartinGurtner	60:8399756e1ba1	1841	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
MartinGurtner	60:8399756e1ba1	1842
MartinGurtner	60:8399756e1ba1	1843	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
MartinGurtner	60:8399756e1ba1	1844	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
MartinGurtner	60:8399756e1ba1	1845
MartinGurtner	60:8399756e1ba1	1846	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
MartinGurtner	60:8399756e1ba1	1847	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
MartinGurtner	60:8399756e1ba1	1848
MartinGurtner	60:8399756e1ba1	1849	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
MartinGurtner	60:8399756e1ba1	1850	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
MartinGurtner	60:8399756e1ba1	1851
MartinGurtner	60:8399756e1ba1	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
MartinGurtner	60:8399756e1ba1	1853	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
MartinGurtner	60:8399756e1ba1	1854
MartinGurtner	60:8399756e1ba1	1855	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
MartinGurtner	60:8399756e1ba1	1856	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
MartinGurtner	60:8399756e1ba1	1857
MartinGurtner	60:8399756e1ba1	1858	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
MartinGurtner	60:8399756e1ba1	1859	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
MartinGurtner	60:8399756e1ba1	1860
MartinGurtner	60:8399756e1ba1	1861	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
MartinGurtner	60:8399756e1ba1	1862	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
MartinGurtner	60:8399756e1ba1	1863
MartinGurtner	60:8399756e1ba1	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
MartinGurtner	60:8399756e1ba1	1865	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
MartinGurtner	60:8399756e1ba1	1866
MartinGurtner	60:8399756e1ba1	1867	/* Debug Core Register Selector Register Definitions */
MartinGurtner	60:8399756e1ba1	1868	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
MartinGurtner	60:8399756e1ba1	1869	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
MartinGurtner	60:8399756e1ba1	1870
MartinGurtner	60:8399756e1ba1	1871	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
MartinGurtner	60:8399756e1ba1	1872	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
MartinGurtner	60:8399756e1ba1	1873
MartinGurtner	60:8399756e1ba1	1874	/* Debug Exception and Monitor Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1875	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
MartinGurtner	60:8399756e1ba1	1876	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
MartinGurtner	60:8399756e1ba1	1877
MartinGurtner	60:8399756e1ba1	1878	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
MartinGurtner	60:8399756e1ba1	1879	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
MartinGurtner	60:8399756e1ba1	1880
MartinGurtner	60:8399756e1ba1	1881	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
MartinGurtner	60:8399756e1ba1	1882	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
MartinGurtner	60:8399756e1ba1	1883
MartinGurtner	60:8399756e1ba1	1884	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
MartinGurtner	60:8399756e1ba1	1885	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
MartinGurtner	60:8399756e1ba1	1886
MartinGurtner	60:8399756e1ba1	1887	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
MartinGurtner	60:8399756e1ba1	1888	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
MartinGurtner	60:8399756e1ba1	1889
MartinGurtner	60:8399756e1ba1	1890	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
MartinGurtner	60:8399756e1ba1	1891	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
MartinGurtner	60:8399756e1ba1	1892
MartinGurtner	60:8399756e1ba1	1893	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
MartinGurtner	60:8399756e1ba1	1894	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
MartinGurtner	60:8399756e1ba1	1895
MartinGurtner	60:8399756e1ba1	1896	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
MartinGurtner	60:8399756e1ba1	1897	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
MartinGurtner	60:8399756e1ba1	1898
MartinGurtner	60:8399756e1ba1	1899	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
MartinGurtner	60:8399756e1ba1	1900	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
MartinGurtner	60:8399756e1ba1	1901
MartinGurtner	60:8399756e1ba1	1902	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
MartinGurtner	60:8399756e1ba1	1903	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
MartinGurtner	60:8399756e1ba1	1904
MartinGurtner	60:8399756e1ba1	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
MartinGurtner	60:8399756e1ba1	1906	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
MartinGurtner	60:8399756e1ba1	1907
MartinGurtner	60:8399756e1ba1	1908	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
MartinGurtner	60:8399756e1ba1	1909	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
MartinGurtner	60:8399756e1ba1	1910
MartinGurtner	60:8399756e1ba1	1911	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
MartinGurtner	60:8399756e1ba1	1912	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
MartinGurtner	60:8399756e1ba1	1913
MartinGurtner	60:8399756e1ba1	1914	/* Debug Authentication Control Register Definitions */
MartinGurtner	60:8399756e1ba1	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
MartinGurtner	60:8399756e1ba1	1916	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
MartinGurtner	60:8399756e1ba1	1917
MartinGurtner	60:8399756e1ba1	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
MartinGurtner	60:8399756e1ba1	1919	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
MartinGurtner	60:8399756e1ba1	1920
MartinGurtner	60:8399756e1ba1	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
MartinGurtner	60:8399756e1ba1	1922	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
MartinGurtner	60:8399756e1ba1	1923
MartinGurtner	60:8399756e1ba1	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
MartinGurtner	60:8399756e1ba1	1925	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
MartinGurtner	60:8399756e1ba1	1926
MartinGurtner	60:8399756e1ba1	1927	/* Debug Security Control and Status Register Definitions */
MartinGurtner	60:8399756e1ba1	1928	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
MartinGurtner	60:8399756e1ba1	1929	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
MartinGurtner	60:8399756e1ba1	1930
MartinGurtner	60:8399756e1ba1	1931	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
MartinGurtner	60:8399756e1ba1	1932	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
MartinGurtner	60:8399756e1ba1	1933
MartinGurtner	60:8399756e1ba1	1934	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
MartinGurtner	60:8399756e1ba1	1935	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
MartinGurtner	60:8399756e1ba1	1936
MartinGurtner	60:8399756e1ba1	1937	/@} end of group CMSIS_CoreDebug /
MartinGurtner	60:8399756e1ba1	1938
MartinGurtner	60:8399756e1ba1	1939
MartinGurtner	60:8399756e1ba1	1940	/**
MartinGurtner	60:8399756e1ba1	1941	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1942	\defgroup CMSIS_core_bitfield Core register bit field macros
MartinGurtner	60:8399756e1ba1	1943	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
MartinGurtner	60:8399756e1ba1	1944	@{
MartinGurtner	60:8399756e1ba1	1945	*/
MartinGurtner	60:8399756e1ba1	1946
MartinGurtner	60:8399756e1ba1	1947	/**
MartinGurtner	60:8399756e1ba1	1948	\brief Mask and shift a bit field value for use in a register bit range.
MartinGurtner	60:8399756e1ba1	1949	\param[in] field Name of the register bit field.
MartinGurtner	60:8399756e1ba1	1950	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
MartinGurtner	60:8399756e1ba1	1951	\return Masked and shifted value.
MartinGurtner	60:8399756e1ba1	1952	*/
MartinGurtner	60:8399756e1ba1	1953	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
MartinGurtner	60:8399756e1ba1	1954
MartinGurtner	60:8399756e1ba1	1955	/**
MartinGurtner	60:8399756e1ba1	1956	\brief Mask and shift a register value to extract a bit filed value.
MartinGurtner	60:8399756e1ba1	1957	\param[in] field Name of the register bit field.
MartinGurtner	60:8399756e1ba1	1958	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
MartinGurtner	60:8399756e1ba1	1959	\return Masked and shifted bit field value.
MartinGurtner	60:8399756e1ba1	1960	*/
MartinGurtner	60:8399756e1ba1	1961	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
MartinGurtner	60:8399756e1ba1	1962
MartinGurtner	60:8399756e1ba1	1963	/@} end of group CMSIS_core_bitfield /
MartinGurtner	60:8399756e1ba1	1964
MartinGurtner	60:8399756e1ba1	1965
MartinGurtner	60:8399756e1ba1	1966	/**
MartinGurtner	60:8399756e1ba1	1967	\ingroup CMSIS_core_register
MartinGurtner	60:8399756e1ba1	1968	\defgroup CMSIS_core_base Core Definitions
MartinGurtner	60:8399756e1ba1	1969	\brief Definitions for base addresses, unions, and structures.
MartinGurtner	60:8399756e1ba1	1970	@{
MartinGurtner	60:8399756e1ba1	1971	*/
MartinGurtner	60:8399756e1ba1	1972
MartinGurtner	60:8399756e1ba1	1973	/* Memory mapping of Core Hardware */
MartinGurtner	60:8399756e1ba1	1974	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
MartinGurtner	60:8399756e1ba1	1975	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
MartinGurtner	60:8399756e1ba1	1976	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
MartinGurtner	60:8399756e1ba1	1977	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
MartinGurtner	60:8399756e1ba1	1978	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
MartinGurtner	60:8399756e1ba1	1979	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
MartinGurtner	60:8399756e1ba1	1980	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
MartinGurtner	60:8399756e1ba1	1981	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
MartinGurtner	60:8399756e1ba1	1982
MartinGurtner	60:8399756e1ba1	1983	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
MartinGurtner	60:8399756e1ba1	1984	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
MartinGurtner	60:8399756e1ba1	1985	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
MartinGurtner	60:8399756e1ba1	1986	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
MartinGurtner	60:8399756e1ba1	1987	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
MartinGurtner	60:8399756e1ba1	1988	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
MartinGurtner	60:8399756e1ba1	1989	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
MartinGurtner	60:8399756e1ba1	1990	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
MartinGurtner	60:8399756e1ba1	1991
MartinGurtner	60:8399756e1ba1	1992	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	1993	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
MartinGurtner	60:8399756e1ba1	1994	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
MartinGurtner	60:8399756e1ba1	1995	#endif
MartinGurtner	60:8399756e1ba1	1996
MartinGurtner	60:8399756e1ba1	1997	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	1998	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
MartinGurtner	60:8399756e1ba1	1999	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
MartinGurtner	60:8399756e1ba1	2000	#endif
MartinGurtner	60:8399756e1ba1	2001
MartinGurtner	60:8399756e1ba1	2002	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
MartinGurtner	60:8399756e1ba1	2003	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
MartinGurtner	60:8399756e1ba1	2004
MartinGurtner	60:8399756e1ba1	2005	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	2006	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2007	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2008	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2009	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2010	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2011
MartinGurtner	60:8399756e1ba1	2012	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
MartinGurtner	60:8399756e1ba1	2013	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2014	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2015	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2016	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2017
MartinGurtner	60:8399756e1ba1	2018	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
MartinGurtner	60:8399756e1ba1	2019	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2020	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2021	#endif
MartinGurtner	60:8399756e1ba1	2022
MartinGurtner	60:8399756e1ba1	2023	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
MartinGurtner	60:8399756e1ba1	2024	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
MartinGurtner	60:8399756e1ba1	2025
MartinGurtner	60:8399756e1ba1	2026	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	2027	/@} /
MartinGurtner	60:8399756e1ba1	2028
MartinGurtner	60:8399756e1ba1	2029
MartinGurtner	60:8399756e1ba1	2030
MartinGurtner	60:8399756e1ba1	2031	/*******************************************************************************
MartinGurtner	60:8399756e1ba1	2032	* Hardware Abstraction Layer
MartinGurtner	60:8399756e1ba1	2033	Core Function Interface contains:
MartinGurtner	60:8399756e1ba1	2034	- Core NVIC Functions
MartinGurtner	60:8399756e1ba1	2035	- Core SysTick Functions
MartinGurtner	60:8399756e1ba1	2036	- Core Debug Functions
MartinGurtner	60:8399756e1ba1	2037	- Core Register Access Functions
MartinGurtner	60:8399756e1ba1	2038	******************************************************************************/
MartinGurtner	60:8399756e1ba1	2039	/**
MartinGurtner	60:8399756e1ba1	2040	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
MartinGurtner	60:8399756e1ba1	2041	*/
MartinGurtner	60:8399756e1ba1	2042
MartinGurtner	60:8399756e1ba1	2043
MartinGurtner	60:8399756e1ba1	2044
MartinGurtner	60:8399756e1ba1	2045	/* ########################## NVIC functions #################################### */
MartinGurtner	60:8399756e1ba1	2046	/**
MartinGurtner	60:8399756e1ba1	2047	\ingroup CMSIS_Core_FunctionInterface
MartinGurtner	60:8399756e1ba1	2048	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
MartinGurtner	60:8399756e1ba1	2049	\brief Functions that manage interrupts and exceptions via the NVIC.
MartinGurtner	60:8399756e1ba1	2050	@{
MartinGurtner	60:8399756e1ba1	2051	*/
MartinGurtner	60:8399756e1ba1	2052
MartinGurtner	60:8399756e1ba1	2053	#ifdef CMSIS_NVIC_VIRTUAL
MartinGurtner	60:8399756e1ba1	2054	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
MartinGurtner	60:8399756e1ba1	2055	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
MartinGurtner	60:8399756e1ba1	2056	#endif
MartinGurtner	60:8399756e1ba1	2057	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
MartinGurtner	60:8399756e1ba1	2058	#else
MartinGurtner	60:8399756e1ba1	2059	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
MartinGurtner	60:8399756e1ba1	2060	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
MartinGurtner	60:8399756e1ba1	2061	#define NVIC_EnableIRQ __NVIC_EnableIRQ
MartinGurtner	60:8399756e1ba1	2062	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
MartinGurtner	60:8399756e1ba1	2063	#define NVIC_DisableIRQ __NVIC_DisableIRQ
MartinGurtner	60:8399756e1ba1	2064	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
MartinGurtner	60:8399756e1ba1	2065	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
MartinGurtner	60:8399756e1ba1	2066	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
MartinGurtner	60:8399756e1ba1	2067	#define NVIC_GetActive __NVIC_GetActive
MartinGurtner	60:8399756e1ba1	2068	#define NVIC_SetPriority __NVIC_SetPriority
MartinGurtner	60:8399756e1ba1	2069	#define NVIC_GetPriority __NVIC_GetPriority
MartinGurtner	60:8399756e1ba1	2070	#define NVIC_SystemReset __NVIC_SystemReset
MartinGurtner	60:8399756e1ba1	2071	#endif /* CMSIS_NVIC_VIRTUAL */
MartinGurtner	60:8399756e1ba1	2072
MartinGurtner	60:8399756e1ba1	2073	#ifdef CMSIS_VECTAB_VIRTUAL
MartinGurtner	60:8399756e1ba1	2074	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
MartinGurtner	60:8399756e1ba1	2075	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
MartinGurtner	60:8399756e1ba1	2076	#endif
MartinGurtner	60:8399756e1ba1	2077	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
MartinGurtner	60:8399756e1ba1	2078	#else
MartinGurtner	60:8399756e1ba1	2079	#define NVIC_SetVector __NVIC_SetVector
MartinGurtner	60:8399756e1ba1	2080	#define NVIC_GetVector __NVIC_GetVector
MartinGurtner	60:8399756e1ba1	2081	#endif /* (CMSIS_VECTAB_VIRTUAL) */
MartinGurtner	60:8399756e1ba1	2082
MartinGurtner	60:8399756e1ba1	2083	#define NVIC_USER_IRQ_OFFSET 16
MartinGurtner	60:8399756e1ba1	2084
MartinGurtner	60:8399756e1ba1	2085
MartinGurtner	60:8399756e1ba1	2086
MartinGurtner	60:8399756e1ba1	2087	/**
MartinGurtner	60:8399756e1ba1	2088	\brief Set Priority Grouping
MartinGurtner	60:8399756e1ba1	2089	\details Sets the priority grouping field using the required unlock sequence.
MartinGurtner	60:8399756e1ba1	2090	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MartinGurtner	60:8399756e1ba1	2091	Only values from 0..7 are used.
MartinGurtner	60:8399756e1ba1	2092	In case of a conflict between priority grouping and available
MartinGurtner	60:8399756e1ba1	2093	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MartinGurtner	60:8399756e1ba1	2094	\param [in] PriorityGroup Priority grouping field.
MartinGurtner	60:8399756e1ba1	2095	*/
MartinGurtner	60:8399756e1ba1	2096	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
MartinGurtner	60:8399756e1ba1	2097	{
MartinGurtner	60:8399756e1ba1	2098	uint32_t reg_value;
MartinGurtner	60:8399756e1ba1	2099	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MartinGurtner	60:8399756e1ba1	2100
MartinGurtner	60:8399756e1ba1	2101	reg_value = SCB->AIRCR; /* read old register configuration */
MartinGurtner	60:8399756e1ba1	2102	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MartinGurtner	60:8399756e1ba1	2103	reg_value = (reg_value \|
MartinGurtner	60:8399756e1ba1	2104	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MartinGurtner	60:8399756e1ba1	2105	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
MartinGurtner	60:8399756e1ba1	2106	SCB->AIRCR = reg_value;
MartinGurtner	60:8399756e1ba1	2107	}
MartinGurtner	60:8399756e1ba1	2108
MartinGurtner	60:8399756e1ba1	2109
MartinGurtner	60:8399756e1ba1	2110	/**
MartinGurtner	60:8399756e1ba1	2111	\brief Get Priority Grouping
MartinGurtner	60:8399756e1ba1	2112	\details Reads the priority grouping field from the NVIC Interrupt Controller.
MartinGurtner	60:8399756e1ba1	2113	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MartinGurtner	60:8399756e1ba1	2114	*/
MartinGurtner	60:8399756e1ba1	2115	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
MartinGurtner	60:8399756e1ba1	2116	{
MartinGurtner	60:8399756e1ba1	2117	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MartinGurtner	60:8399756e1ba1	2118	}
MartinGurtner	60:8399756e1ba1	2119
MartinGurtner	60:8399756e1ba1	2120
MartinGurtner	60:8399756e1ba1	2121	/**
MartinGurtner	60:8399756e1ba1	2122	\brief Enable Interrupt
MartinGurtner	60:8399756e1ba1	2123	\details Enables a device specific interrupt in the NVIC interrupt controller.
MartinGurtner	60:8399756e1ba1	2124	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2125	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2126	*/
MartinGurtner	60:8399756e1ba1	2127	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2128	{
MartinGurtner	60:8399756e1ba1	2129	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2130	{
MartinGurtner	60:8399756e1ba1	2131	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2132	}
MartinGurtner	60:8399756e1ba1	2133	}
MartinGurtner	60:8399756e1ba1	2134
MartinGurtner	60:8399756e1ba1	2135
MartinGurtner	60:8399756e1ba1	2136	/**
MartinGurtner	60:8399756e1ba1	2137	\brief Get Interrupt Enable status
MartinGurtner	60:8399756e1ba1	2138	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
MartinGurtner	60:8399756e1ba1	2139	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2140	\return 0 Interrupt is not enabled.
MartinGurtner	60:8399756e1ba1	2141	\return 1 Interrupt is enabled.
MartinGurtner	60:8399756e1ba1	2142	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2143	*/
MartinGurtner	60:8399756e1ba1	2144	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2145	{
MartinGurtner	60:8399756e1ba1	2146	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2147	{
MartinGurtner	60:8399756e1ba1	2148	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2149	}
MartinGurtner	60:8399756e1ba1	2150	else
MartinGurtner	60:8399756e1ba1	2151	{
MartinGurtner	60:8399756e1ba1	2152	return(0U);
MartinGurtner	60:8399756e1ba1	2153	}
MartinGurtner	60:8399756e1ba1	2154	}
MartinGurtner	60:8399756e1ba1	2155
MartinGurtner	60:8399756e1ba1	2156
MartinGurtner	60:8399756e1ba1	2157	/**
MartinGurtner	60:8399756e1ba1	2158	\brief Disable Interrupt
MartinGurtner	60:8399756e1ba1	2159	\details Disables a device specific interrupt in the NVIC interrupt controller.
MartinGurtner	60:8399756e1ba1	2160	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2161	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2162	*/
MartinGurtner	60:8399756e1ba1	2163	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2164	{
MartinGurtner	60:8399756e1ba1	2165	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2166	{
MartinGurtner	60:8399756e1ba1	2167	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2168	__DSB();
MartinGurtner	60:8399756e1ba1	2169	__ISB();
MartinGurtner	60:8399756e1ba1	2170	}
MartinGurtner	60:8399756e1ba1	2171	}
MartinGurtner	60:8399756e1ba1	2172
MartinGurtner	60:8399756e1ba1	2173
MartinGurtner	60:8399756e1ba1	2174	/**
MartinGurtner	60:8399756e1ba1	2175	\brief Get Pending Interrupt
MartinGurtner	60:8399756e1ba1	2176	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
MartinGurtner	60:8399756e1ba1	2177	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2178	\return 0 Interrupt status is not pending.
MartinGurtner	60:8399756e1ba1	2179	\return 1 Interrupt status is pending.
MartinGurtner	60:8399756e1ba1	2180	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2181	*/
MartinGurtner	60:8399756e1ba1	2182	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2183	{
MartinGurtner	60:8399756e1ba1	2184	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2185	{
MartinGurtner	60:8399756e1ba1	2186	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2187	}
MartinGurtner	60:8399756e1ba1	2188	else
MartinGurtner	60:8399756e1ba1	2189	{
MartinGurtner	60:8399756e1ba1	2190	return(0U);
MartinGurtner	60:8399756e1ba1	2191	}
MartinGurtner	60:8399756e1ba1	2192	}
MartinGurtner	60:8399756e1ba1	2193
MartinGurtner	60:8399756e1ba1	2194
MartinGurtner	60:8399756e1ba1	2195	/**
MartinGurtner	60:8399756e1ba1	2196	\brief Set Pending Interrupt
MartinGurtner	60:8399756e1ba1	2197	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
MartinGurtner	60:8399756e1ba1	2198	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2199	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2200	*/
MartinGurtner	60:8399756e1ba1	2201	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2202	{
MartinGurtner	60:8399756e1ba1	2203	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2204	{
MartinGurtner	60:8399756e1ba1	2205	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2206	}
MartinGurtner	60:8399756e1ba1	2207	}
MartinGurtner	60:8399756e1ba1	2208
MartinGurtner	60:8399756e1ba1	2209
MartinGurtner	60:8399756e1ba1	2210	/**
MartinGurtner	60:8399756e1ba1	2211	\brief Clear Pending Interrupt
MartinGurtner	60:8399756e1ba1	2212	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
MartinGurtner	60:8399756e1ba1	2213	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2214	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2215	*/
MartinGurtner	60:8399756e1ba1	2216	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2217	{
MartinGurtner	60:8399756e1ba1	2218	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2219	{
MartinGurtner	60:8399756e1ba1	2220	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2221	}
MartinGurtner	60:8399756e1ba1	2222	}
MartinGurtner	60:8399756e1ba1	2223
MartinGurtner	60:8399756e1ba1	2224
MartinGurtner	60:8399756e1ba1	2225	/**
MartinGurtner	60:8399756e1ba1	2226	\brief Get Active Interrupt
MartinGurtner	60:8399756e1ba1	2227	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
MartinGurtner	60:8399756e1ba1	2228	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2229	\return 0 Interrupt status is not active.
MartinGurtner	60:8399756e1ba1	2230	\return 1 Interrupt status is active.
MartinGurtner	60:8399756e1ba1	2231	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2232	*/
MartinGurtner	60:8399756e1ba1	2233	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2234	{
MartinGurtner	60:8399756e1ba1	2235	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2236	{
MartinGurtner	60:8399756e1ba1	2237	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2238	}
MartinGurtner	60:8399756e1ba1	2239	else
MartinGurtner	60:8399756e1ba1	2240	{
MartinGurtner	60:8399756e1ba1	2241	return(0U);
MartinGurtner	60:8399756e1ba1	2242	}
MartinGurtner	60:8399756e1ba1	2243	}
MartinGurtner	60:8399756e1ba1	2244
MartinGurtner	60:8399756e1ba1	2245
MartinGurtner	60:8399756e1ba1	2246	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	2247	/**
MartinGurtner	60:8399756e1ba1	2248	\brief Get Interrupt Target State
MartinGurtner	60:8399756e1ba1	2249	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
MartinGurtner	60:8399756e1ba1	2250	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2251	\return 0 if interrupt is assigned to Secure
MartinGurtner	60:8399756e1ba1	2252	\return 1 if interrupt is assigned to Non Secure
MartinGurtner	60:8399756e1ba1	2253	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2254	*/
MartinGurtner	60:8399756e1ba1	2255	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2256	{
MartinGurtner	60:8399756e1ba1	2257	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2258	{
MartinGurtner	60:8399756e1ba1	2259	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2260	}
MartinGurtner	60:8399756e1ba1	2261	else
MartinGurtner	60:8399756e1ba1	2262	{
MartinGurtner	60:8399756e1ba1	2263	return(0U);
MartinGurtner	60:8399756e1ba1	2264	}
MartinGurtner	60:8399756e1ba1	2265	}
MartinGurtner	60:8399756e1ba1	2266
MartinGurtner	60:8399756e1ba1	2267
MartinGurtner	60:8399756e1ba1	2268	/**
MartinGurtner	60:8399756e1ba1	2269	\brief Set Interrupt Target State
MartinGurtner	60:8399756e1ba1	2270	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
MartinGurtner	60:8399756e1ba1	2271	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2272	\return 0 if interrupt is assigned to Secure
MartinGurtner	60:8399756e1ba1	2273	1 if interrupt is assigned to Non Secure
MartinGurtner	60:8399756e1ba1	2274	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2275	*/
MartinGurtner	60:8399756e1ba1	2276	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2277	{
MartinGurtner	60:8399756e1ba1	2278	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2279	{
MartinGurtner	60:8399756e1ba1	2280	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
MartinGurtner	60:8399756e1ba1	2281	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2282	}
MartinGurtner	60:8399756e1ba1	2283	else
MartinGurtner	60:8399756e1ba1	2284	{
MartinGurtner	60:8399756e1ba1	2285	return(0U);
MartinGurtner	60:8399756e1ba1	2286	}
MartinGurtner	60:8399756e1ba1	2287	}
MartinGurtner	60:8399756e1ba1	2288
MartinGurtner	60:8399756e1ba1	2289
MartinGurtner	60:8399756e1ba1	2290	/**
MartinGurtner	60:8399756e1ba1	2291	\brief Clear Interrupt Target State
MartinGurtner	60:8399756e1ba1	2292	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
MartinGurtner	60:8399756e1ba1	2293	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2294	\return 0 if interrupt is assigned to Secure
MartinGurtner	60:8399756e1ba1	2295	1 if interrupt is assigned to Non Secure
MartinGurtner	60:8399756e1ba1	2296	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2297	*/
MartinGurtner	60:8399756e1ba1	2298	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2299	{
MartinGurtner	60:8399756e1ba1	2300	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2301	{
MartinGurtner	60:8399756e1ba1	2302	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
MartinGurtner	60:8399756e1ba1	2303	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2304	}
MartinGurtner	60:8399756e1ba1	2305	else
MartinGurtner	60:8399756e1ba1	2306	{
MartinGurtner	60:8399756e1ba1	2307	return(0U);
MartinGurtner	60:8399756e1ba1	2308	}
MartinGurtner	60:8399756e1ba1	2309	}
MartinGurtner	60:8399756e1ba1	2310	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	2311
MartinGurtner	60:8399756e1ba1	2312
MartinGurtner	60:8399756e1ba1	2313	/**
MartinGurtner	60:8399756e1ba1	2314	\brief Set Interrupt Priority
MartinGurtner	60:8399756e1ba1	2315	\details Sets the priority of a device specific interrupt or a processor exception.
MartinGurtner	60:8399756e1ba1	2316	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2317	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2318	\param [in] IRQn Interrupt number.
MartinGurtner	60:8399756e1ba1	2319	\param [in] priority Priority to set.
MartinGurtner	60:8399756e1ba1	2320	\note The priority cannot be set for every processor exception.
MartinGurtner	60:8399756e1ba1	2321	*/
MartinGurtner	60:8399756e1ba1	2322	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
MartinGurtner	60:8399756e1ba1	2323	{
MartinGurtner	60:8399756e1ba1	2324	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2325	{
MartinGurtner	60:8399756e1ba1	2326	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MartinGurtner	60:8399756e1ba1	2327	}
MartinGurtner	60:8399756e1ba1	2328	else
MartinGurtner	60:8399756e1ba1	2329	{
MartinGurtner	60:8399756e1ba1	2330	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MartinGurtner	60:8399756e1ba1	2331	}
MartinGurtner	60:8399756e1ba1	2332	}
MartinGurtner	60:8399756e1ba1	2333
MartinGurtner	60:8399756e1ba1	2334
MartinGurtner	60:8399756e1ba1	2335	/**
MartinGurtner	60:8399756e1ba1	2336	\brief Get Interrupt Priority
MartinGurtner	60:8399756e1ba1	2337	\details Reads the priority of a device specific interrupt or a processor exception.
MartinGurtner	60:8399756e1ba1	2338	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2339	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2340	\param [in] IRQn Interrupt number.
MartinGurtner	60:8399756e1ba1	2341	\return Interrupt Priority.
MartinGurtner	60:8399756e1ba1	2342	Value is aligned automatically to the implemented priority bits of the microcontroller.
MartinGurtner	60:8399756e1ba1	2343	*/
MartinGurtner	60:8399756e1ba1	2344	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2345	{
MartinGurtner	60:8399756e1ba1	2346
MartinGurtner	60:8399756e1ba1	2347	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2348	{
MartinGurtner	60:8399756e1ba1	2349	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
MartinGurtner	60:8399756e1ba1	2350	}
MartinGurtner	60:8399756e1ba1	2351	else
MartinGurtner	60:8399756e1ba1	2352	{
MartinGurtner	60:8399756e1ba1	2353	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
MartinGurtner	60:8399756e1ba1	2354	}
MartinGurtner	60:8399756e1ba1	2355	}
MartinGurtner	60:8399756e1ba1	2356
MartinGurtner	60:8399756e1ba1	2357
MartinGurtner	60:8399756e1ba1	2358	/**
MartinGurtner	60:8399756e1ba1	2359	\brief Encode Priority
MartinGurtner	60:8399756e1ba1	2360	\details Encodes the priority for an interrupt with the given priority group,
MartinGurtner	60:8399756e1ba1	2361	preemptive priority value, and subpriority value.
MartinGurtner	60:8399756e1ba1	2362	In case of a conflict between priority grouping and available
MartinGurtner	60:8399756e1ba1	2363	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MartinGurtner	60:8399756e1ba1	2364	\param [in] PriorityGroup Used priority group.
MartinGurtner	60:8399756e1ba1	2365	\param [in] PreemptPriority Preemptive priority value (starting from 0).
MartinGurtner	60:8399756e1ba1	2366	\param [in] SubPriority Subpriority value (starting from 0).
MartinGurtner	60:8399756e1ba1	2367	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
MartinGurtner	60:8399756e1ba1	2368	*/
MartinGurtner	60:8399756e1ba1	2369	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
MartinGurtner	60:8399756e1ba1	2370	{
MartinGurtner	60:8399756e1ba1	2371	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MartinGurtner	60:8399756e1ba1	2372	uint32_t PreemptPriorityBits;
MartinGurtner	60:8399756e1ba1	2373	uint32_t SubPriorityBits;
MartinGurtner	60:8399756e1ba1	2374
MartinGurtner	60:8399756e1ba1	2375	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MartinGurtner	60:8399756e1ba1	2376	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MartinGurtner	60:8399756e1ba1	2377
MartinGurtner	60:8399756e1ba1	2378	return (
MartinGurtner	60:8399756e1ba1	2379	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
MartinGurtner	60:8399756e1ba1	2380	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
MartinGurtner	60:8399756e1ba1	2381	);
MartinGurtner	60:8399756e1ba1	2382	}
MartinGurtner	60:8399756e1ba1	2383
MartinGurtner	60:8399756e1ba1	2384
MartinGurtner	60:8399756e1ba1	2385	/**
MartinGurtner	60:8399756e1ba1	2386	\brief Decode Priority
MartinGurtner	60:8399756e1ba1	2387	\details Decodes an interrupt priority value with a given priority group to
MartinGurtner	60:8399756e1ba1	2388	preemptive priority value and subpriority value.
MartinGurtner	60:8399756e1ba1	2389	In case of a conflict between priority grouping and available
MartinGurtner	60:8399756e1ba1	2390	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
MartinGurtner	60:8399756e1ba1	2391	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
MartinGurtner	60:8399756e1ba1	2392	\param [in] PriorityGroup Used priority group.
MartinGurtner	60:8399756e1ba1	2393	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
MartinGurtner	60:8399756e1ba1	2394	\param [out] pSubPriority Subpriority value (starting from 0).
MartinGurtner	60:8399756e1ba1	2395	*/
MartinGurtner	60:8399756e1ba1	2396	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
MartinGurtner	60:8399756e1ba1	2397	{
MartinGurtner	60:8399756e1ba1	2398	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MartinGurtner	60:8399756e1ba1	2399	uint32_t PreemptPriorityBits;
MartinGurtner	60:8399756e1ba1	2400	uint32_t SubPriorityBits;
MartinGurtner	60:8399756e1ba1	2401
MartinGurtner	60:8399756e1ba1	2402	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
MartinGurtner	60:8399756e1ba1	2403	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
MartinGurtner	60:8399756e1ba1	2404
MartinGurtner	60:8399756e1ba1	2405	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
MartinGurtner	60:8399756e1ba1	2406	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
MartinGurtner	60:8399756e1ba1	2407	}
MartinGurtner	60:8399756e1ba1	2408
MartinGurtner	60:8399756e1ba1	2409
MartinGurtner	60:8399756e1ba1	2410	/**
MartinGurtner	60:8399756e1ba1	2411	\brief Set Interrupt Vector
MartinGurtner	60:8399756e1ba1	2412	\details Sets an interrupt vector in SRAM based interrupt vector table.
MartinGurtner	60:8399756e1ba1	2413	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2414	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2415	VTOR must been relocated to SRAM before.
MartinGurtner	60:8399756e1ba1	2416	\param [in] IRQn Interrupt number
MartinGurtner	60:8399756e1ba1	2417	\param [in] vector Address of interrupt handler function
MartinGurtner	60:8399756e1ba1	2418	*/
MartinGurtner	60:8399756e1ba1	2419	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
MartinGurtner	60:8399756e1ba1	2420	{
MartinGurtner	60:8399756e1ba1	2421	uint32_t vectors = (uint32_t )SCB->VTOR;
MartinGurtner	60:8399756e1ba1	2422	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
MartinGurtner	60:8399756e1ba1	2423	}
MartinGurtner	60:8399756e1ba1	2424
MartinGurtner	60:8399756e1ba1	2425
MartinGurtner	60:8399756e1ba1	2426	/**
MartinGurtner	60:8399756e1ba1	2427	\brief Get Interrupt Vector
MartinGurtner	60:8399756e1ba1	2428	\details Reads an interrupt vector from interrupt vector table.
MartinGurtner	60:8399756e1ba1	2429	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2430	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2431	\param [in] IRQn Interrupt number.
MartinGurtner	60:8399756e1ba1	2432	\return Address of interrupt handler function
MartinGurtner	60:8399756e1ba1	2433	*/
MartinGurtner	60:8399756e1ba1	2434	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2435	{
MartinGurtner	60:8399756e1ba1	2436	uint32_t vectors = (uint32_t )SCB->VTOR;
MartinGurtner	60:8399756e1ba1	2437	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
MartinGurtner	60:8399756e1ba1	2438	}
MartinGurtner	60:8399756e1ba1	2439
MartinGurtner	60:8399756e1ba1	2440
MartinGurtner	60:8399756e1ba1	2441	/**
MartinGurtner	60:8399756e1ba1	2442	\brief System Reset
MartinGurtner	60:8399756e1ba1	2443	\details Initiates a system reset request to reset the MCU.
MartinGurtner	60:8399756e1ba1	2444	*/
MartinGurtner	60:8399756e1ba1	2445	__STATIC_INLINE void __NVIC_SystemReset(void)
MartinGurtner	60:8399756e1ba1	2446	{
MartinGurtner	60:8399756e1ba1	2447	__DSB(); /* Ensure all outstanding memory accesses included
MartinGurtner	60:8399756e1ba1	2448	buffered write are completed before reset */
MartinGurtner	60:8399756e1ba1	2449	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MartinGurtner	60:8399756e1ba1	2450	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
MartinGurtner	60:8399756e1ba1	2451	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
MartinGurtner	60:8399756e1ba1	2452	__DSB(); /* Ensure completion of memory access */
MartinGurtner	60:8399756e1ba1	2453
MartinGurtner	60:8399756e1ba1	2454	for(;;) /* wait until reset */
MartinGurtner	60:8399756e1ba1	2455	{
MartinGurtner	60:8399756e1ba1	2456	__NOP();
MartinGurtner	60:8399756e1ba1	2457	}
MartinGurtner	60:8399756e1ba1	2458	}
MartinGurtner	60:8399756e1ba1	2459
MartinGurtner	60:8399756e1ba1	2460	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	2461	/**
MartinGurtner	60:8399756e1ba1	2462	\brief Set Priority Grouping (non-secure)
MartinGurtner	60:8399756e1ba1	2463	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
MartinGurtner	60:8399756e1ba1	2464	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
MartinGurtner	60:8399756e1ba1	2465	Only values from 0..7 are used.
MartinGurtner	60:8399756e1ba1	2466	In case of a conflict between priority grouping and available
MartinGurtner	60:8399756e1ba1	2467	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
MartinGurtner	60:8399756e1ba1	2468	\param [in] PriorityGroup Priority grouping field.
MartinGurtner	60:8399756e1ba1	2469	*/
MartinGurtner	60:8399756e1ba1	2470	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
MartinGurtner	60:8399756e1ba1	2471	{
MartinGurtner	60:8399756e1ba1	2472	uint32_t reg_value;
MartinGurtner	60:8399756e1ba1	2473	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
MartinGurtner	60:8399756e1ba1	2474
MartinGurtner	60:8399756e1ba1	2475	reg_value = SCB_NS->AIRCR; /* read old register configuration */
MartinGurtner	60:8399756e1ba1	2476	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
MartinGurtner	60:8399756e1ba1	2477	reg_value = (reg_value \|
MartinGurtner	60:8399756e1ba1	2478	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
MartinGurtner	60:8399756e1ba1	2479	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
MartinGurtner	60:8399756e1ba1	2480	SCB_NS->AIRCR = reg_value;
MartinGurtner	60:8399756e1ba1	2481	}
MartinGurtner	60:8399756e1ba1	2482
MartinGurtner	60:8399756e1ba1	2483
MartinGurtner	60:8399756e1ba1	2484	/**
MartinGurtner	60:8399756e1ba1	2485	\brief Get Priority Grouping (non-secure)
MartinGurtner	60:8399756e1ba1	2486	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
MartinGurtner	60:8399756e1ba1	2487	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
MartinGurtner	60:8399756e1ba1	2488	*/
MartinGurtner	60:8399756e1ba1	2489	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
MartinGurtner	60:8399756e1ba1	2490	{
MartinGurtner	60:8399756e1ba1	2491	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
MartinGurtner	60:8399756e1ba1	2492	}
MartinGurtner	60:8399756e1ba1	2493
MartinGurtner	60:8399756e1ba1	2494
MartinGurtner	60:8399756e1ba1	2495	/**
MartinGurtner	60:8399756e1ba1	2496	\brief Enable Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2497	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
MartinGurtner	60:8399756e1ba1	2498	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2499	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2500	*/
MartinGurtner	60:8399756e1ba1	2501	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2502	{
MartinGurtner	60:8399756e1ba1	2503	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2504	{
MartinGurtner	60:8399756e1ba1	2505	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2506	}
MartinGurtner	60:8399756e1ba1	2507	}
MartinGurtner	60:8399756e1ba1	2508
MartinGurtner	60:8399756e1ba1	2509
MartinGurtner	60:8399756e1ba1	2510	/**
MartinGurtner	60:8399756e1ba1	2511	\brief Get Interrupt Enable status (non-secure)
MartinGurtner	60:8399756e1ba1	2512	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
MartinGurtner	60:8399756e1ba1	2513	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2514	\return 0 Interrupt is not enabled.
MartinGurtner	60:8399756e1ba1	2515	\return 1 Interrupt is enabled.
MartinGurtner	60:8399756e1ba1	2516	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2517	*/
MartinGurtner	60:8399756e1ba1	2518	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2519	{
MartinGurtner	60:8399756e1ba1	2520	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2521	{
MartinGurtner	60:8399756e1ba1	2522	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2523	}
MartinGurtner	60:8399756e1ba1	2524	else
MartinGurtner	60:8399756e1ba1	2525	{
MartinGurtner	60:8399756e1ba1	2526	return(0U);
MartinGurtner	60:8399756e1ba1	2527	}
MartinGurtner	60:8399756e1ba1	2528	}
MartinGurtner	60:8399756e1ba1	2529
MartinGurtner	60:8399756e1ba1	2530
MartinGurtner	60:8399756e1ba1	2531	/**
MartinGurtner	60:8399756e1ba1	2532	\brief Disable Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2533	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
MartinGurtner	60:8399756e1ba1	2534	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2535	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2536	*/
MartinGurtner	60:8399756e1ba1	2537	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2538	{
MartinGurtner	60:8399756e1ba1	2539	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2540	{
MartinGurtner	60:8399756e1ba1	2541	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2542	}
MartinGurtner	60:8399756e1ba1	2543	}
MartinGurtner	60:8399756e1ba1	2544
MartinGurtner	60:8399756e1ba1	2545
MartinGurtner	60:8399756e1ba1	2546	/**
MartinGurtner	60:8399756e1ba1	2547	\brief Get Pending Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2548	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
MartinGurtner	60:8399756e1ba1	2549	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2550	\return 0 Interrupt status is not pending.
MartinGurtner	60:8399756e1ba1	2551	\return 1 Interrupt status is pending.
MartinGurtner	60:8399756e1ba1	2552	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2553	*/
MartinGurtner	60:8399756e1ba1	2554	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2555	{
MartinGurtner	60:8399756e1ba1	2556	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2557	{
MartinGurtner	60:8399756e1ba1	2558	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2559	}
MartinGurtner	60:8399756e1ba1	2560	}
MartinGurtner	60:8399756e1ba1	2561
MartinGurtner	60:8399756e1ba1	2562
MartinGurtner	60:8399756e1ba1	2563	/**
MartinGurtner	60:8399756e1ba1	2564	\brief Set Pending Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2565	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
MartinGurtner	60:8399756e1ba1	2566	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2567	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2568	*/
MartinGurtner	60:8399756e1ba1	2569	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2570	{
MartinGurtner	60:8399756e1ba1	2571	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2572	{
MartinGurtner	60:8399756e1ba1	2573	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2574	}
MartinGurtner	60:8399756e1ba1	2575	}
MartinGurtner	60:8399756e1ba1	2576
MartinGurtner	60:8399756e1ba1	2577
MartinGurtner	60:8399756e1ba1	2578	/**
MartinGurtner	60:8399756e1ba1	2579	\brief Clear Pending Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2580	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
MartinGurtner	60:8399756e1ba1	2581	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2582	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2583	*/
MartinGurtner	60:8399756e1ba1	2584	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2585	{
MartinGurtner	60:8399756e1ba1	2586	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2587	{
MartinGurtner	60:8399756e1ba1	2588	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
MartinGurtner	60:8399756e1ba1	2589	}
MartinGurtner	60:8399756e1ba1	2590	}
MartinGurtner	60:8399756e1ba1	2591
MartinGurtner	60:8399756e1ba1	2592
MartinGurtner	60:8399756e1ba1	2593	/**
MartinGurtner	60:8399756e1ba1	2594	\brief Get Active Interrupt (non-secure)
MartinGurtner	60:8399756e1ba1	2595	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
MartinGurtner	60:8399756e1ba1	2596	\param [in] IRQn Device specific interrupt number.
MartinGurtner	60:8399756e1ba1	2597	\return 0 Interrupt status is not active.
MartinGurtner	60:8399756e1ba1	2598	\return 1 Interrupt status is active.
MartinGurtner	60:8399756e1ba1	2599	\note IRQn must not be negative.
MartinGurtner	60:8399756e1ba1	2600	*/
MartinGurtner	60:8399756e1ba1	2601	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2602	{
MartinGurtner	60:8399756e1ba1	2603	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2604	{
MartinGurtner	60:8399756e1ba1	2605	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
MartinGurtner	60:8399756e1ba1	2606	}
MartinGurtner	60:8399756e1ba1	2607	else
MartinGurtner	60:8399756e1ba1	2608	{
MartinGurtner	60:8399756e1ba1	2609	return(0U);
MartinGurtner	60:8399756e1ba1	2610	}
MartinGurtner	60:8399756e1ba1	2611	}
MartinGurtner	60:8399756e1ba1	2612
MartinGurtner	60:8399756e1ba1	2613
MartinGurtner	60:8399756e1ba1	2614	/**
MartinGurtner	60:8399756e1ba1	2615	\brief Set Interrupt Priority (non-secure)
MartinGurtner	60:8399756e1ba1	2616	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
MartinGurtner	60:8399756e1ba1	2617	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2618	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2619	\param [in] IRQn Interrupt number.
MartinGurtner	60:8399756e1ba1	2620	\param [in] priority Priority to set.
MartinGurtner	60:8399756e1ba1	2621	\note The priority cannot be set for every non-secure processor exception.
MartinGurtner	60:8399756e1ba1	2622	*/
MartinGurtner	60:8399756e1ba1	2623	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
MartinGurtner	60:8399756e1ba1	2624	{
MartinGurtner	60:8399756e1ba1	2625	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2626	{
MartinGurtner	60:8399756e1ba1	2627	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MartinGurtner	60:8399756e1ba1	2628	}
MartinGurtner	60:8399756e1ba1	2629	else
MartinGurtner	60:8399756e1ba1	2630	{
MartinGurtner	60:8399756e1ba1	2631	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
MartinGurtner	60:8399756e1ba1	2632	}
MartinGurtner	60:8399756e1ba1	2633	}
MartinGurtner	60:8399756e1ba1	2634
MartinGurtner	60:8399756e1ba1	2635
MartinGurtner	60:8399756e1ba1	2636	/**
MartinGurtner	60:8399756e1ba1	2637	\brief Get Interrupt Priority (non-secure)
MartinGurtner	60:8399756e1ba1	2638	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
MartinGurtner	60:8399756e1ba1	2639	The interrupt number can be positive to specify a device specific interrupt,
MartinGurtner	60:8399756e1ba1	2640	or negative to specify a processor exception.
MartinGurtner	60:8399756e1ba1	2641	\param [in] IRQn Interrupt number.
MartinGurtner	60:8399756e1ba1	2642	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
MartinGurtner	60:8399756e1ba1	2643	*/
MartinGurtner	60:8399756e1ba1	2644	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
MartinGurtner	60:8399756e1ba1	2645	{
MartinGurtner	60:8399756e1ba1	2646
MartinGurtner	60:8399756e1ba1	2647	if ((int32_t)(IRQn) >= 0)
MartinGurtner	60:8399756e1ba1	2648	{
MartinGurtner	60:8399756e1ba1	2649	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
MartinGurtner	60:8399756e1ba1	2650	}
MartinGurtner	60:8399756e1ba1	2651	else
MartinGurtner	60:8399756e1ba1	2652	{
MartinGurtner	60:8399756e1ba1	2653	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
MartinGurtner	60:8399756e1ba1	2654	}
MartinGurtner	60:8399756e1ba1	2655	}
MartinGurtner	60:8399756e1ba1	2656	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	2657
MartinGurtner	60:8399756e1ba1	2658	/@} end of CMSIS_Core_NVICFunctions /
MartinGurtner	60:8399756e1ba1	2659
MartinGurtner	60:8399756e1ba1	2660
MartinGurtner	60:8399756e1ba1	2661	/* ########################## FPU functions #################################### */
MartinGurtner	60:8399756e1ba1	2662	/**
MartinGurtner	60:8399756e1ba1	2663	\ingroup CMSIS_Core_FunctionInterface
MartinGurtner	60:8399756e1ba1	2664	\defgroup CMSIS_Core_FpuFunctions FPU Functions
MartinGurtner	60:8399756e1ba1	2665	\brief Function that provides FPU type.
MartinGurtner	60:8399756e1ba1	2666	@{
MartinGurtner	60:8399756e1ba1	2667	*/
MartinGurtner	60:8399756e1ba1	2668
MartinGurtner	60:8399756e1ba1	2669	/**
MartinGurtner	60:8399756e1ba1	2670	\brief get FPU type
MartinGurtner	60:8399756e1ba1	2671	\details returns the FPU type
MartinGurtner	60:8399756e1ba1	2672	\returns
MartinGurtner	60:8399756e1ba1	2673	- \b 0: No FPU
MartinGurtner	60:8399756e1ba1	2674	- \b 1: Single precision FPU
MartinGurtner	60:8399756e1ba1	2675	- \b 2: Double + Single precision FPU
MartinGurtner	60:8399756e1ba1	2676	*/
MartinGurtner	60:8399756e1ba1	2677	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
MartinGurtner	60:8399756e1ba1	2678	{
MartinGurtner	60:8399756e1ba1	2679	uint32_t mvfr0;
MartinGurtner	60:8399756e1ba1	2680
MartinGurtner	60:8399756e1ba1	2681	mvfr0 = FPU->MVFR0;
MartinGurtner	60:8399756e1ba1	2682	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
MartinGurtner	60:8399756e1ba1	2683	{
MartinGurtner	60:8399756e1ba1	2684	return 2U; /* Double + Single precision FPU */
MartinGurtner	60:8399756e1ba1	2685	}
MartinGurtner	60:8399756e1ba1	2686	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
MartinGurtner	60:8399756e1ba1	2687	{
MartinGurtner	60:8399756e1ba1	2688	return 1U; /* Single precision FPU */
MartinGurtner	60:8399756e1ba1	2689	}
MartinGurtner	60:8399756e1ba1	2690	else
MartinGurtner	60:8399756e1ba1	2691	{
MartinGurtner	60:8399756e1ba1	2692	return 0U; /* No FPU */
MartinGurtner	60:8399756e1ba1	2693	}
MartinGurtner	60:8399756e1ba1	2694	}
MartinGurtner	60:8399756e1ba1	2695
MartinGurtner	60:8399756e1ba1	2696
MartinGurtner	60:8399756e1ba1	2697	/@} end of CMSIS_Core_FpuFunctions /
MartinGurtner	60:8399756e1ba1	2698
MartinGurtner	60:8399756e1ba1	2699
MartinGurtner	60:8399756e1ba1	2700
MartinGurtner	60:8399756e1ba1	2701	/* ########################## SAU functions #################################### */
MartinGurtner	60:8399756e1ba1	2702	/**
MartinGurtner	60:8399756e1ba1	2703	\ingroup CMSIS_Core_FunctionInterface
MartinGurtner	60:8399756e1ba1	2704	\defgroup CMSIS_Core_SAUFunctions SAU Functions
MartinGurtner	60:8399756e1ba1	2705	\brief Functions that configure the SAU.
MartinGurtner	60:8399756e1ba1	2706	@{
MartinGurtner	60:8399756e1ba1	2707	*/
MartinGurtner	60:8399756e1ba1	2708
MartinGurtner	60:8399756e1ba1	2709	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	2710
MartinGurtner	60:8399756e1ba1	2711	/**
MartinGurtner	60:8399756e1ba1	2712	\brief Enable SAU
MartinGurtner	60:8399756e1ba1	2713	\details Enables the Security Attribution Unit (SAU).
MartinGurtner	60:8399756e1ba1	2714	*/
MartinGurtner	60:8399756e1ba1	2715	__STATIC_INLINE void TZ_SAU_Enable(void)
MartinGurtner	60:8399756e1ba1	2716	{
MartinGurtner	60:8399756e1ba1	2717	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
MartinGurtner	60:8399756e1ba1	2718	}
MartinGurtner	60:8399756e1ba1	2719
MartinGurtner	60:8399756e1ba1	2720
MartinGurtner	60:8399756e1ba1	2721
MartinGurtner	60:8399756e1ba1	2722	/**
MartinGurtner	60:8399756e1ba1	2723	\brief Disable SAU
MartinGurtner	60:8399756e1ba1	2724	\details Disables the Security Attribution Unit (SAU).
MartinGurtner	60:8399756e1ba1	2725	*/
MartinGurtner	60:8399756e1ba1	2726	__STATIC_INLINE void TZ_SAU_Disable(void)
MartinGurtner	60:8399756e1ba1	2727	{
MartinGurtner	60:8399756e1ba1	2728	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
MartinGurtner	60:8399756e1ba1	2729	}
MartinGurtner	60:8399756e1ba1	2730
MartinGurtner	60:8399756e1ba1	2731	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	2732
MartinGurtner	60:8399756e1ba1	2733	/@} end of CMSIS_Core_SAUFunctions /
MartinGurtner	60:8399756e1ba1	2734
MartinGurtner	60:8399756e1ba1	2735
MartinGurtner	60:8399756e1ba1	2736
MartinGurtner	60:8399756e1ba1	2737
MartinGurtner	60:8399756e1ba1	2738	/* ################################## SysTick function ############################################ */
MartinGurtner	60:8399756e1ba1	2739	/**
MartinGurtner	60:8399756e1ba1	2740	\ingroup CMSIS_Core_FunctionInterface
MartinGurtner	60:8399756e1ba1	2741	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
MartinGurtner	60:8399756e1ba1	2742	\brief Functions that configure the System.
MartinGurtner	60:8399756e1ba1	2743	@{
MartinGurtner	60:8399756e1ba1	2744	*/
MartinGurtner	60:8399756e1ba1	2745
MartinGurtner	60:8399756e1ba1	2746	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
MartinGurtner	60:8399756e1ba1	2747
MartinGurtner	60:8399756e1ba1	2748	/**
MartinGurtner	60:8399756e1ba1	2749	\brief System Tick Configuration
MartinGurtner	60:8399756e1ba1	2750	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
MartinGurtner	60:8399756e1ba1	2751	Counter is in free running mode to generate periodic interrupts.
MartinGurtner	60:8399756e1ba1	2752	\param [in] ticks Number of ticks between two interrupts.
MartinGurtner	60:8399756e1ba1	2753	\return 0 Function succeeded.
MartinGurtner	60:8399756e1ba1	2754	\return 1 Function failed.
MartinGurtner	60:8399756e1ba1	2755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MartinGurtner	60:8399756e1ba1	2756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
MartinGurtner	60:8399756e1ba1	2757	must contain a vendor-specific implementation of this function.
MartinGurtner	60:8399756e1ba1	2758	*/
MartinGurtner	60:8399756e1ba1	2759	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
MartinGurtner	60:8399756e1ba1	2760	{
MartinGurtner	60:8399756e1ba1	2761	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
MartinGurtner	60:8399756e1ba1	2762	{
MartinGurtner	60:8399756e1ba1	2763	return (1UL); /* Reload value impossible */
MartinGurtner	60:8399756e1ba1	2764	}
MartinGurtner	60:8399756e1ba1	2765
MartinGurtner	60:8399756e1ba1	2766	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MartinGurtner	60:8399756e1ba1	2767	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MartinGurtner	60:8399756e1ba1	2768	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
MartinGurtner	60:8399756e1ba1	2769	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
MartinGurtner	60:8399756e1ba1	2770	SysTick_CTRL_TICKINT_Msk \|
MartinGurtner	60:8399756e1ba1	2771	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MartinGurtner	60:8399756e1ba1	2772	return (0UL); /* Function successful */
MartinGurtner	60:8399756e1ba1	2773	}
MartinGurtner	60:8399756e1ba1	2774
MartinGurtner	60:8399756e1ba1	2775	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
MartinGurtner	60:8399756e1ba1	2776	/**
MartinGurtner	60:8399756e1ba1	2777	\brief System Tick Configuration (non-secure)
MartinGurtner	60:8399756e1ba1	2778	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
MartinGurtner	60:8399756e1ba1	2779	Counter is in free running mode to generate periodic interrupts.
MartinGurtner	60:8399756e1ba1	2780	\param [in] ticks Number of ticks between two interrupts.
MartinGurtner	60:8399756e1ba1	2781	\return 0 Function succeeded.
MartinGurtner	60:8399756e1ba1	2782	\return 1 Function failed.
MartinGurtner	60:8399756e1ba1	2783	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
MartinGurtner	60:8399756e1ba1	2784	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
MartinGurtner	60:8399756e1ba1	2785	must contain a vendor-specific implementation of this function.
MartinGurtner	60:8399756e1ba1	2786
MartinGurtner	60:8399756e1ba1	2787	*/
MartinGurtner	60:8399756e1ba1	2788	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
MartinGurtner	60:8399756e1ba1	2789	{
MartinGurtner	60:8399756e1ba1	2790	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
MartinGurtner	60:8399756e1ba1	2791	{
MartinGurtner	60:8399756e1ba1	2792	return (1UL); /* Reload value impossible */
MartinGurtner	60:8399756e1ba1	2793	}
MartinGurtner	60:8399756e1ba1	2794
MartinGurtner	60:8399756e1ba1	2795	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
MartinGurtner	60:8399756e1ba1	2796	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
MartinGurtner	60:8399756e1ba1	2797	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
MartinGurtner	60:8399756e1ba1	2798	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
MartinGurtner	60:8399756e1ba1	2799	SysTick_CTRL_TICKINT_Msk \|
MartinGurtner	60:8399756e1ba1	2800	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
MartinGurtner	60:8399756e1ba1	2801	return (0UL); /* Function successful */
MartinGurtner	60:8399756e1ba1	2802	}
MartinGurtner	60:8399756e1ba1	2803	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
MartinGurtner	60:8399756e1ba1	2804
MartinGurtner	60:8399756e1ba1	2805	#endif
MartinGurtner	60:8399756e1ba1	2806
MartinGurtner	60:8399756e1ba1	2807	/@} end of CMSIS_Core_SysTickFunctions /
MartinGurtner	60:8399756e1ba1	2808
MartinGurtner	60:8399756e1ba1	2809
MartinGurtner	60:8399756e1ba1	2810
MartinGurtner	60:8399756e1ba1	2811	/* ##################################### Debug In/Output function ########################################### */
MartinGurtner	60:8399756e1ba1	2812	/**
MartinGurtner	60:8399756e1ba1	2813	\ingroup CMSIS_Core_FunctionInterface
MartinGurtner	60:8399756e1ba1	2814	\defgroup CMSIS_core_DebugFunctions ITM Functions
MartinGurtner	60:8399756e1ba1	2815	\brief Functions that access the ITM debug interface.
MartinGurtner	60:8399756e1ba1	2816	@{
MartinGurtner	60:8399756e1ba1	2817	*/
MartinGurtner	60:8399756e1ba1	2818
MartinGurtner	60:8399756e1ba1	2819	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
MartinGurtner	60:8399756e1ba1	2820	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
MartinGurtner	60:8399756e1ba1	2821
MartinGurtner	60:8399756e1ba1	2822
MartinGurtner	60:8399756e1ba1	2823	/**
MartinGurtner	60:8399756e1ba1	2824	\brief ITM Send Character
MartinGurtner	60:8399756e1ba1	2825	\details Transmits a character via the ITM channel 0, and
MartinGurtner	60:8399756e1ba1	2826	\li Just returns when no debugger is connected that has booked the output.
MartinGurtner	60:8399756e1ba1	2827	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
MartinGurtner	60:8399756e1ba1	2828	\param [in] ch Character to transmit.
MartinGurtner	60:8399756e1ba1	2829	\returns Character to transmit.
MartinGurtner	60:8399756e1ba1	2830	*/
MartinGurtner	60:8399756e1ba1	2831	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
MartinGurtner	60:8399756e1ba1	2832	{
MartinGurtner	60:8399756e1ba1	2833	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
MartinGurtner	60:8399756e1ba1	2834	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
MartinGurtner	60:8399756e1ba1	2835	{
MartinGurtner	60:8399756e1ba1	2836	while (ITM->PORT[0U].u32 == 0UL)
MartinGurtner	60:8399756e1ba1	2837	{
MartinGurtner	60:8399756e1ba1	2838	__NOP();
MartinGurtner	60:8399756e1ba1	2839	}
MartinGurtner	60:8399756e1ba1	2840	ITM->PORT[0U].u8 = (uint8_t)ch;
MartinGurtner	60:8399756e1ba1	2841	}
MartinGurtner	60:8399756e1ba1	2842	return (ch);
MartinGurtner	60:8399756e1ba1	2843	}
MartinGurtner	60:8399756e1ba1	2844
MartinGurtner	60:8399756e1ba1	2845
MartinGurtner	60:8399756e1ba1	2846	/**
MartinGurtner	60:8399756e1ba1	2847	\brief ITM Receive Character
MartinGurtner	60:8399756e1ba1	2848	\details Inputs a character via the external variable \ref ITM_RxBuffer.
MartinGurtner	60:8399756e1ba1	2849	\return Received character.
MartinGurtner	60:8399756e1ba1	2850	\return -1 No character pending.
MartinGurtner	60:8399756e1ba1	2851	*/
MartinGurtner	60:8399756e1ba1	2852	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
MartinGurtner	60:8399756e1ba1	2853	{
MartinGurtner	60:8399756e1ba1	2854	int32_t ch = -1; /* no character available */
MartinGurtner	60:8399756e1ba1	2855
MartinGurtner	60:8399756e1ba1	2856	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
MartinGurtner	60:8399756e1ba1	2857	{
MartinGurtner	60:8399756e1ba1	2858	ch = ITM_RxBuffer;
MartinGurtner	60:8399756e1ba1	2859	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
MartinGurtner	60:8399756e1ba1	2860	}
MartinGurtner	60:8399756e1ba1	2861
MartinGurtner	60:8399756e1ba1	2862	return (ch);
MartinGurtner	60:8399756e1ba1	2863	}
MartinGurtner	60:8399756e1ba1	2864
MartinGurtner	60:8399756e1ba1	2865
MartinGurtner	60:8399756e1ba1	2866	/**
MartinGurtner	60:8399756e1ba1	2867	\brief ITM Check Character
MartinGurtner	60:8399756e1ba1	2868	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
MartinGurtner	60:8399756e1ba1	2869	\return 0 No character available.
MartinGurtner	60:8399756e1ba1	2870	\return 1 Character available.
MartinGurtner	60:8399756e1ba1	2871	*/
MartinGurtner	60:8399756e1ba1	2872	__STATIC_INLINE int32_t ITM_CheckChar (void)
MartinGurtner	60:8399756e1ba1	2873	{
MartinGurtner	60:8399756e1ba1	2874
MartinGurtner	60:8399756e1ba1	2875	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
MartinGurtner	60:8399756e1ba1	2876	{
MartinGurtner	60:8399756e1ba1	2877	return (0); /* no character available */
MartinGurtner	60:8399756e1ba1	2878	}
MartinGurtner	60:8399756e1ba1	2879	else
MartinGurtner	60:8399756e1ba1	2880	{
MartinGurtner	60:8399756e1ba1	2881	return (1); /* character available */
MartinGurtner	60:8399756e1ba1	2882	}
MartinGurtner	60:8399756e1ba1	2883	}
MartinGurtner	60:8399756e1ba1	2884
MartinGurtner	60:8399756e1ba1	2885	/@} end of CMSIS_core_DebugFunctions /
MartinGurtner	60:8399756e1ba1	2886
MartinGurtner	60:8399756e1ba1	2887
MartinGurtner	60:8399756e1ba1	2888
MartinGurtner	60:8399756e1ba1	2889
MartinGurtner	60:8399756e1ba1	2890	#ifdef __cplusplus
MartinGurtner	60:8399756e1ba1	2891	}
MartinGurtner	60:8399756e1ba1	2892	#endif
MartinGurtner	60:8399756e1ba1	2893
MartinGurtner	60:8399756e1ba1	2894	#endif /* __CORE_CM33_H_DEPENDANT */
MartinGurtner	60:8399756e1ba1	2895
MartinGurtner	60:8399756e1ba1	2896	#endif /* __CMSIS_GENERIC */

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Created:	01 Dec 2020
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Commits:	61
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mbed-dev/cmsis/core_cm33.h@60:8399756e1ba1, 2021-01-22 (annotated)

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