nmi_wlan.h

00001 #ifndef NMI_WLAN_H
00002 #define NMI_WLAN_H
00003 
00004 #include "nmi_type.h"
00005 
00006 /********************************************
00007 
00008     Endian Conversion 
00009 
00010 ********************************************/
00011 
00012 #define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
00013                                         (((val) & 0x0000FF00) << 8)  + \
00014                                         (((val) & 0x00FF0000) >> 8)   + \
00015                                         (((val) & 0xFF000000) >> 24))
00016 
00017 
00018 /********************************************
00019 
00020     Macro Defines 
00021 
00022 ********************************************/
00023 #define SINGLE_TX_QUEUE 
00024 #define HOST_PS
00025 #define STATIC_TX_BUFFER
00026 
00027 /********************************************
00028 
00029     Register Defines
00030 
00031 ********************************************/
00032 #define NMI_PERIPH_REG_BASE 0x1000
00033 #define NMI_CHIPID  (NMI_PERIPH_REG_BASE)
00034 #define NMI_GLB_RESET_0 (NMI_PERIPH_REG_BASE + 0x400)
00035 #define NMI_PIN_MUX_0 (NMI_PERIPH_REG_BASE + 0x408)
00036 #define NMI_MISC    (NMI_PERIPH_REG_BASE+0x428)
00037 #define NMI_INTR_REG_BASE (NMI_PERIPH_REG_BASE+0xa00)
00038 #define NMI_INTR_ENABLE (NMI_INTR_REG_BASE)
00039 #define NMI_INTR_POLARITY (NMI_INTR_REG_BASE+0x10)
00040 #define NMI_INTR_TYPE (NMI_INTR_REG_BASE+0x20)
00041 #define NMI_INTR_CLEAR (NMI_INTR_REG_BASE+0x30)
00042 #define NMI_INTR_STATUS (NMI_INTR_REG_BASE+0x40)
00043 
00044 #define NMI_VMM_TBL_SIZE 64
00045 #define NMI_VMM_TX_TBL_BASE (0x150400)
00046 #define NMI_VMM_RX_TBL_BASE (0x150500)
00047 
00048 #define NMI_VMM_BASE 0x150000
00049 #define NMI_VMM_CORE_CTL (NMI_VMM_BASE)
00050 #define NMI_VMM_TBL_CTL (NMI_VMM_BASE+0x4)
00051 #define NMI_VMM_TBL_ENTRY (NMI_VMM_BASE+0x8)
00052 #define NMI_VMM_TBL0_SIZE (NMI_VMM_BASE+0xc)
00053 #define NMI_VMM_TO_HOST_SIZE (NMI_VMM_BASE+0x10)
00054 #define NMI_VMM_CORE_CFG (NMI_VMM_BASE+0x14)
00055 #define NMI_VMM_TBL_ACTIVE (NMI_VMM_BASE+040)
00056 #define NMI_VMM_TBL_STATUS (NMI_VMM_BASE+0x44)
00057 
00058 #define NMI_SPI_REG_BASE 0xe800
00059 #define NMI_SPI_CTL (NMI_SPI_REG_BASE)
00060 #define NMI_SPI_MASTER_DMA_ADDR (NMI_SPI_REG_BASE+0x4)
00061 #define NMI_SPI_MASTER_DMA_COUNT (NMI_SPI_REG_BASE+0x8)
00062 #define NMI_SPI_SLAVE_DMA_ADDR (NMI_SPI_REG_BASE+0xc)
00063 #define NMI_SPI_SLAVE_DMA_COUNT (NMI_SPI_REG_BASE+0x10)
00064 #define NMI_SPI_TX_MODE (NMI_SPI_REG_BASE+0x20)
00065 #define NMI_SPI_PROTOCOL_CONFIG (NMI_SPI_REG_BASE+0x24)
00066 #define NMI_SPI_INTR_CTL (NMI_SPI_REG_BASE+0x2c)
00067 
00068 #define NMI_SPI_PROTOCOL_OFFSET (NMI_SPI_PROTOCOL_CONFIG-NMI_SPI_REG_BASE)
00069 
00070 #define NMI_AHB_DATA_MEM_BASE 0x30000
00071 #define NMI_AHB_SHARE_MEM_BASE 0xd0000
00072 #define NMI_AHB_DMA_ADDR (NMI_AHB_DATA_MEM_BASE + 0xe000)
00073 
00074 #define NMI_CLR_RX_INTR_REG     (NMI_PERIPH_REG_BASE+0xc8)
00075 #define NMI_TX_SET_INTR_REG     (NMI_PERIPH_REG_BASE+0x78)  /*0xa8*/
00076 
00077 #define NMI_SDIO_INTR_TYPE_REG  (NMI_PERIPH_REG_BASE+0x8c)
00078 
00079 /********************************************
00080 
00081     FW State Defines
00082 
00083 ********************************************/
00084 
00085 #define FW_TX_OK                0x1
00086 #define FW_SYNC                 0x2
00087 #define FW_SLEEP                0x4
00088 /********************************************
00089 
00090     Size
00091 
00092 ********************************************/
00093 
00094 #define CFG_MSG_HDR_LEN 4
00095 #define N_MAX_TX_SIZE (2*1024)//(8*1024)
00096 #define N_HDR_SIZE 4
00097 #define N_ALIGN_SIZE 4
00098 #define N_GRP_HDR_SIZE 4
00099 
00100 /********************************************
00101 
00102     List Helper
00103 
00104 ********************************************/
00105 
00106 struct wl_list {    
00107     struct wl_list *prev;   
00108     struct wl_list *next;
00109 };
00110 
00111 #define wl_get_list_entry(ptr, type, member) \
00112     ((type *)((char *)(ptr)-(unsigned long)(&((type *)0)->member)))
00113 
00114 #define wl_list_for_each(pos, head) \
00115     for (pos = (head)->next; pos != (head); pos = pos->next)
00116 
00117 #define wl_list_for_each_prev(pos, head) \
00118     for (pos = (head)->prev; pos != (head); pos = pos->prev)
00119 
00120 #define wl_list_for_each_safe(pos, n, head) \
00121     for (pos = (head)->next, n = pos->next; pos != (head); pos = n, n = pos->next)
00122 
00123 #if defined(_LINUX_) 
00124 static inline void wl_init_list_head(struct wl_list *list)
00125 {   
00126     list->next = list;  
00127     list->prev = list;
00128 }
00129 
00130 static inline void wl_list_add(struct wl_list *ne, struct wl_list *prev, struct wl_list *next)
00131 {   
00132     next->prev = ne;    
00133     ne->next = next;    
00134     ne->prev = prev;    
00135     prev->next = ne;
00136 }
00137 
00138 static inline void wl_list_add_head(struct wl_list *ne, struct wl_list *head)
00139 {   
00140     wl_list_add(ne, head, head->next);
00141 }
00142 
00143 static inline void wl_list_add_tail(struct wl_list *ne, struct wl_list *head)
00144 {   
00145     wl_list_add(ne, head->prev, head);
00146 }
00147 
00148 static inline void wl_list_del(struct wl_list *entry)
00149 {   
00150     struct wl_list *prev = entry->prev;
00151     struct wl_list *next = entry->next;
00152 
00153     next->prev = prev;  
00154     prev->next = next;
00155 }
00156 
00157 static inline int wl_list_empty(const struct wl_list *head)
00158 {   
00159     return head->next == head;
00160 }
00161 
00162 #else
00163 static void wl_init_list_head(struct wl_list *list);
00164 static void wl_list_add(struct wl_list *ne, struct wl_list *prev, struct wl_list *next);
00165 static void wl_list_add_head(struct wl_list *ne, struct wl_list *head);
00166 static void wl_list_add_tail(struct wl_list *ne, struct wl_list *head);
00167 static void wl_list_del(struct wl_list *entry);
00168 static int wl_list_empty(const struct wl_list *head);
00169 
00170 
00171 #endif
00172 /********************************************
00173 
00174     Mac State Defines
00175 
00176 ********************************************/
00177 
00178 typedef enum {
00179     MAC_DISCONNECTED = 1, //0,  /* ksong 2013.5.9 */
00180     MAC_CONNECTED,
00181     MAC_ALIVE, //MAC_UPDATE_PLL,
00182     MAC_UPDATE_PLL_DONE,
00183     MAC_SLEEP,
00184     MAC_WAKE,
00185     MAC_READY,
00186     MAC_TX_DONE,
00187     MAC_TX_STOP,
00188 } MAC_STATUS_T;
00189 
00190 typedef enum {
00191     MLME_SCAN_RSP   = 0,
00192     MLME_START_RSP  = 1,
00193     MLME_JOIN_RSP   = 2,
00194     MLME_AUTH_RSP   = 3,
00195     MLME_ASOC_RSP   = 4,
00196     MLME_EAPOL_RSP  = 5,        /* Atmel: 1-15-2015 */  
00197     MLME_UNEXPECT_RSP = 6,  /* ksong 2013-8-9 */
00198 } MLME_RSP_TYPE_T;
00199 
00200 /********************************************
00201 
00202     Comamnd Parameters
00203 
00204 ********************************************/
00205 
00206 typedef enum {
00207     B_ONLY_MODE = 0,                /* basic rate: 1, 2 Mbps, otherwise: 5, 11 Mbps */
00208     G_ONLY_MODE,                    /* basic rate: 6, 12, 24 Mbps, otherwise: 9, 18, 36, 48, 54 Mbps */
00209     G_MIXED_11B_1_MODE,     /* basic rate: 1, 2, 5.5, 11 Mbps, otherwise: all on */
00210     G_MIXED_11B_2_MODE,     /* basic rate: 1, 2, 5, 11, 6, 12, 24 Mbps, otherwise: all on */
00211 } G_OPERATING_MODE_T;
00212 
00213 typedef enum{
00214     RATE_AUTO = 0,
00215     RATE_1MB = 1,
00216     RATE_2MB = 2,
00217     RATE_5MB = 5,
00218     RATE_6MB = 6,
00219     RATE_9MB = 9,
00220     RATE_11MB = 11,
00221     RATE_12MB = 12,
00222     RATE_18MB = 18,
00223     RATE_24MB = 24,
00224     RATE_26MB = 36,
00225     RATE_48MB = 48,
00226     RATE_54MB = 54
00227 } TX_RATE_T;
00228 
00229 typedef enum {
00230     G_SHORT_PREAMBLE = 0,   /* Short Preamble          */
00231     G_LONG_PREAMBLE  = 1,       /* Long Preamble           */
00232     G_AUTO_PREAMBLE  = 2,       /* Auto Preamble Selection */
00233 } G_PREAMBLE_T;
00234 
00235 typedef enum {
00236     AUTO_PROT = 0,  /* Auto */
00237     NO_PROT,            /* Do not use any protection       */
00238     ERP_PROT,           /* Protect all ERP frame exchanges */
00239     HT_PROT,            /* Protect all HT frame exchanges  */
00240     GF_PROT,            /* Protect all GF frame exchanges  */
00241 } N_PROTECTION_MODE_T;
00242 
00243 typedef enum {
00244     SITE_SURVEY_1CH    = 0,
00245     SITE_SURVEY_ALL_CH = 1,
00246     SITE_SURVEY_OFF    = 2
00247 } SITE_SURVEY_T;
00248 
00249 typedef enum {
00250     NORMAL_ACK = 0,
00251     NO_ACK,
00252 } ACK_POLICY_T;
00253 
00254 typedef enum {
00255     G_SELF_CTS_PROT,
00256     G_RTS_CTS_PROT,
00257 } G_PROTECTION_MODE_T;
00258 
00259 typedef enum {
00260     HT_MIXED_MODE = 1,
00261     HT_ONLY_20MHZ_MODE,
00262     HT_ONLY_20_40MHZ_MODE,
00263 } N_OPERATING_MODE_T;
00264 
00265 /********************************************
00266 
00267     Command ID Defines
00268 
00269 ********************************************/
00270 
00271 typedef enum {
00272     WID_CHAR     = 0,
00273     WID_SHORT    = 1,
00274     WID_INT      = 2,
00275     WID_STR      = 3,
00276     WID_BIN = 4
00277 } WID_TYPE_T;
00278 
00279 typedef enum {
00280 WID_NIL                            = -1,
00281 
00282     /* Character WID list */
00283     WID_BSS_TYPE                       = 0x0000,
00284     WID_CURRENT_TX_RATE                = 0x0001,
00285     WID_CURRENT_CHANNEL                = 0x0002,
00286     WID_PREAMBLE                       = 0x0003,
00287     WID_11G_OPERATING_MODE             = 0x0004,
00288     WID_STATUS                         = 0x0005,
00289     WID_SCAN_TYPE                      = 0x0007,
00290     WID_PRIVACY_INVOKED                = 0x0008,
00291     WID_KEY_ID                         = 0x0009,
00292     WID_QOS_ENABLE                     = 0x000A,
00293     WID_POWER_MANAGEMENT               = 0x000B,
00294     WID_11I_MODE                       = 0x000C,
00295     WID_AUTH_TYPE                      = 0x000D,
00296     WID_SITE_SURVEY                    = 0x000E,
00297     WID_LISTEN_INTERVAL                = 0x000F,
00298     WID_DTIM_PERIOD                    = 0x0010,
00299     WID_ACK_POLICY                     = 0x0011,
00300     WID_RESET                          = 0x0012,
00301     WID_BCAST_SSID                     = 0x0015,
00302     WID_DISCONNECT                     = 0x0016,
00303     WID_READ_ADDR_SDRAM                = 0x0017,
00304     WID_TX_POWER_LEVEL_11A             = 0x0018,
00305     WID_REKEY_POLICY                   = 0x0019,
00306     WID_SHORT_SLOT_ALLOWED             = 0x001A,
00307     WID_PHY_ACTIVE_REG                 = 0x001B,
00308     WID_TX_POWER_LEVEL_11B             = 0x001D,
00309     WID_START_SCAN_REQ                 = 0x001E,
00310     WID_RSSI                           = 0x001F,
00311     WID_JOIN_REQ                       = 0x0020,
00312 #ifdef MAC_ANTENNA_DIVERSITY_FEATURE
00313     WID_ANTENNA_SELECTION              = 0x0021,
00314 #endif /* MAC_ANTENNA_DIVERSITY_FEATURE */
00315     WID_USER_CONTROL_ON_TX_POWER       = 0x0027,
00316     WID_MEMORY_ACCESS_8BIT             = 0x0029,
00317     WID_UAPSD_SUPPORT_AP               = 0x002A,
00318     WID_CURRENT_MAC_STATUS             = 0x0031,
00319     WID_AUTO_RX_SENSITIVITY            = 0x0032,
00320     WID_DATAFLOW_CONTROL               = 0x0033,
00321     WID_SCAN_FILTER                    = 0x0036,
00322     WID_LINK_LOSS_THRESHOLD            = 0x0037,
00323     WID_AUTORATE_TYPE                  = 0x0038,
00324     WID_802_11H_DFS_MODE               = 0x003B,
00325     WID_802_11H_TPC_MODE               = 0x003C,
00326 
00327     /* Character WID list */
00328     WID_11N_PROT_MECH                  = 0x0080,
00329     WID_11N_ERP_PROT_TYPE              = 0x0081,
00330     WID_11N_ENABLE                     = 0x0082,
00331     WID_11N_OPERATING_MODE             = 0x0083,
00332     WID_11N_OBSS_NONHT_DETECTION       = 0x0084,
00333     WID_11N_HT_PROT_TYPE               = 0x0085,
00334     WID_11N_RIFS_PROT_ENABLE           = 0x0086,
00335     WID_11N_SMPS_MODE                  = 0x0087,
00336     WID_11N_CURRENT_TX_MCS             = 0x0088,
00337     WID_11N_PRINT_STATS                = 0x0089,
00338     WID_HUT_FCS_CORRUPT_MODE           = 0x008A,
00339     WID_HUT_RESTART                    = 0x008B,
00340     WID_HUT_TX_FORMAT                  = 0x008C,
00341     WID_11N_SHORT_GI_ENABLE            = 0x008D,
00342     WID_HUT_BANDWIDTH                  = 0x008E,
00343     WID_HUT_OP_BAND                    = 0x008F,
00344     WID_HUT_STBC                       = 0x0090,
00345     WID_HUT_ESS                        = 0x0091,
00346     WID_HUT_ANTSET                     = 0x0092,
00347     WID_HUT_HT_OP_MODE                 = 0x0093,
00348     WID_RIFS_MODE                      = 0x0094,
00349     WID_HUT_SMOOTHING_REC              = 0x0095,
00350     WID_HUT_SOUNDING_PKT               = 0x0096,
00351     WID_HUT_HT_CODING                  = 0x0097,
00352     WID_HUT_TEST_DIR                   = 0x0098,
00353     WID_HUT_PHY_TEST_MODE              = 0x009A,
00354     WID_HUT_PHY_TEST_RATE_HI           = 0x009B,
00355     WID_HUT_PHY_TEST_RATE_LO           = 0x009C,
00356     WID_HUT_DISABLE_RXQ_REPLENISH      = 0x009D,
00357     WID_HUT_KEY_ORIGIN                 = 0x009E,
00358     WID_HUT_BCST_PERCENT               = 0x009F,
00359     WID_HUT_GROUP_CIPHER_TYPE          = 0x00A0,
00360     WID_TX_ABORT_CONFIG                = 0x00A1,
00361     WID_HOST_DATA_IF_TYPE              = 0x00A2,
00362     WID_HOST_CONFIG_IF_TYPE            = 0x00A3,
00363     WID_HUT_TSF_TEST_MODE              = 0x00A4,
00364     WID_HUT_PKT_TSSI_VALUE             = 0x00A5,
00365     WID_REG_TSSI_11B_VALUE             = 0x00A6,
00366     WID_REG_TSSI_11G_VALUE             = 0x00A7,
00367     WID_REG_TSSI_11N_VALUE             = 0x00A8,
00368     WID_TX_CALIBRATION                 = 0x00A9,
00369     WID_DSCR_TSSI_11B_VALUE            = 0x00AA,
00370     WID_DSCR_TSSI_11G_VALUE            = 0x00AB,
00371     WID_DSCR_TSSI_11N_VALUE            = 0x00AC,
00372     WID_HUT_RSSI_EX                    = 0x00AD,
00373     WID_HUT_ADJ_RSSI_EX                = 0x00AE,
00374     WID_11N_IMMEDIATE_BA_ENABLED       = 0x00AF,
00375     WID_11N_TXOP_PROT_DISABLE          = 0x00B0,
00376     WID_TX_POWER_LEVEL_11N             = 0x00B1,
00377     WID_USER_SEC_CHANNEL_OFFSET        = 0x00C0,
00378     WID_2040_COEXISTENCE               = 0x00C1,
00379     WID_HUT_FC_TXOP_MOD                = 0x00C2,
00380     WID_HUT_FC_PROT_TYPE               = 0x00C3,
00381     WID_HUT_SEC_CCA_ASSERT             = 0x00C4,
00382     WID_2040_ENABLE                    = 0x00C5,
00383     WID_2040_CURR_CHANNEL_OFFSET       = 0x00C6,
00384     WID_2040_40MHZ_INTOLERANT          = 0x00C7,
00385     WID_HOST_PLATFORM                            = 0x00C8,      /* ykk */
00386     WID_MLME_RSP                             = 0x00C9,      /* ykk */
00387     WID_RX_TEST                     = 0x00CA,     /* ksong 2013-7-16 */
00388     WID_DOZE_TIME                          = 0x00CB,        /* ksong 2013-7-22 */
00389   /* Character WID list */
00390 
00391   /* Short WID list */
00392   WID_RTS_THRESHOLD                  = 0x1000,
00393   WID_FRAG_THRESHOLD                 = 0x1001,
00394   WID_SHORT_RETRY_LIMIT              = 0x1002,
00395   WID_LONG_RETRY_LIMIT               = 0x1003,
00396   WID_BEACON_INTERVAL                = 0x1006,
00397   WID_MEMORY_ACCESS_16BIT            = 0x1008,
00398   WID_RX_SENSE                       = 0x100B,
00399   WID_ACTIVE_SCAN_TIME               = 0x100C,
00400   WID_PASSIVE_SCAN_TIME              = 0x100D,
00401   WID_SITE_SURVEY_SCAN_TIME          = 0x100E,
00402   WID_JOIN_START_TIMEOUT             = 0x100F,
00403   WID_AUTH_TIMEOUT                   = 0x1010,
00404   WID_ASOC_TIMEOUT                   = 0x1011,
00405   WID_11I_PROTOCOL_TIMEOUT           = 0x1012,
00406   WID_EAPOL_RESPONSE_TIMEOUT         = 0x1013,
00407 
00408   /* Short WID list */
00409   WID_11N_RF_REG_VAL                 = 0x1080,
00410   WID_HUT_FRAME_LEN                  = 0x1081,
00411   WID_HUT_TXOP_LIMIT                 = 0x1082,
00412   WID_HUT_SIG_QUAL_AVG               = 0x1083,
00413   WID_HUT_SIG_QUAL_AVG_CNT           = 0x1084,
00414   WID_11N_SIG_QUAL_VAL               = 0x1085,
00415   WID_HUT_RSSI_EX_COUNT              = 0x1086,
00416   WID_CCA_THRESHOLD                  = 0x1087,
00417   WID_CLK_26M_SETTLE_TIME           = 0x1088,    /* ksong */
00418 
00419   /* Short WID list */
00420 
00421     /* Integer WID list */
00422     WID_FAILED_COUNT                   = 0x2000,
00423     WID_RETRY_COUNT                    = 0x2001,
00424     WID_MULTIPLE_RETRY_COUNT           = 0x2002,
00425     WID_FRAME_DUPLICATE_COUNT          = 0x2003,
00426     WID_ACK_FAILURE_COUNT              = 0x2004,
00427     WID_RECEIVED_FRAGMENT_COUNT        = 0x2005,
00428     WID_MCAST_RECEIVED_FRAME_COUNT     = 0x2006,
00429     WID_FCS_ERROR_COUNT                = 0x2007,
00430     WID_SUCCESS_FRAME_COUNT            = 0x2008,
00431     WID_HUT_TX_COUNT                   = 0x200A,
00432     WID_TX_FRAGMENT_COUNT              = 0x200B,
00433     WID_TX_MULTICAST_FRAME_COUNT       = 0x200C,
00434     WID_RTS_SUCCESS_COUNT              = 0x200D,
00435     WID_RTS_FAILURE_COUNT              = 0x200E,
00436     WID_WEP_UNDECRYPTABLE_COUNT        = 0x200F,
00437     WID_REKEY_PERIOD                   = 0x2010,
00438     WID_REKEY_PACKET_COUNT             = 0x2011,
00439     WID_1X_SERV_ADDR                   = 0x2012,
00440     WID_STACK_IP_ADDR                  = 0x2013,
00441     WID_STACK_NETMASK_ADDR             = 0x2014,
00442     WID_HW_RX_COUNT                    = 0x2015,
00443     WID_MEMORY_ADDRESS                 = 0x201E,
00444     WID_MEMORY_ACCESS_32BIT            = 0x201F,
00445     WID_RF_REG_VAL                     = 0x2021,
00446 
00447     /* Integer WID list */
00448     WID_11N_PHY_ACTIVE_REG_VAL         = 0x2080,
00449     WID_HUT_NUM_TX_PKTS                = 0x2081,
00450     WID_HUT_TX_TIME_TAKEN              = 0x2082,
00451     WID_HUT_TX_TEST_TIME               = 0x2083,
00452 
00453     /* Integer WID list */
00454   WID_FW_DEBUG_FLAG                     = 0x2084,
00455 
00456     /* String WID list */
00457     WID_SSID                           = 0x3000,
00458     WID_FIRMWARE_VERSION               = 0x3001,
00459     WID_OPERATIONAL_RATE_SET           = 0x3002,
00460     WID_BSSID                          = 0x3003,
00461     WID_WEP_KEY_VALUE                  = 0x3004,
00462     WID_11I_PSK                        = 0x3008,
00463     WID_11E_P_ACTION_REQ               = 0x3009,
00464     WID_1X_KEY                         = 0x300A,
00465     WID_HARDWARE_VERSION               = 0x300B,
00466     WID_MAC_ADDR                       = 0x300C,
00467     WID_HUT_DEST_ADDR                  = 0x300D,
00468     WID_MISC_TEST_MODES                = 0x300E,
00469     WID_PHY_VERSION                    = 0x300F,
00470     WID_SUPP_USERNAME                  = 0x3010,
00471     WID_SUPP_PASSWORD                  = 0x3011,
00472     WID_SITE_SURVEY_RESULTS            = 0x3012,    
00473     WID_RX_POWER_LEVEL                 = 0x3013,
00474     WID_ADD_WEP_KEY                    = 0x3019,
00475     WID_REMOVE_WEP_KEY                 = 0x301A,
00476     WID_ADD_PTK                        = 0x301B,
00477     WID_ADD_RX_GTK                     = 0x301C,
00478     WID_ADD_TX_GTK                     = 0x301D,
00479     WID_REMOVE_KEY                     = 0x301E,
00480     WID_ASSOC_REQ_INFO                 = 0x301F,
00481     WID_ASSOC_RES_INFO                 = 0x3020,
00482     WID_UPDATE_RF_SUPPORTED_INFO       = 0x3021,
00483 
00484   /* String WID list */
00485   WID_11N_P_ACTION_REQ               = 0x3080,
00486   WID_HUT_TEST_ID                    = 0x3081,
00487   WID_PMKID_INFO                     = 0x3082,
00488   WID_FIRMWARE_INFO                  = 0x3083,
00489   WID_HOST_SCAN_SSID                        = 0x3084,
00490 
00491   /* String WID list */
00492   WID_FIXED_IP_ADDR                  = 0x3090,//Ryan
00493 
00494   /* Binary WID list */
00495   WID_UAPSD_CONFIG                   = 0x4001,
00496   WID_UAPSD_STATUS                   = 0x4002,
00497   WID_WMM_AP_AC_PARAMS               = 0x4003,
00498   WID_WMM_STA_AC_PARAMS              = 0x4004,
00499   WID_NETWORK_INFO                   = 0x4005,
00500   WID_STA_JOIN_INFO                  = 0x4006,
00501   WID_CONNECTED_STA_LIST             = 0x4007,
00502     WID_SCAN_BSS_INFO                                               = 0x4008,
00503 
00504   /* Binary WID list */
00505   WID_11N_AUTORATE_TABLE             = 0x4080,
00506   WID_HUT_TX_PATTERN                 = 0x4081,
00507   WID_HUT_STATS                      = 0x4082,
00508   WID_HUT_LOG_STATS                  = 0x4083,
00509 
00510     WID_HOST_PROBE_IE                                   = 0x4084,
00511     WID_HOST_SCAN_CHANNEL                           = 0x4085,   
00512  
00513     /* Atmel, 1-15-2015*/ 
00514   WID_PMK_CACHE_INFO                    = 0x4088,
00515 
00516  
00517  /* Miscellaneous WIDs */
00518   WID_ALL                            = 0x7FFE,
00519   WID_MAX                            = 0xFFFF
00520 } WID_T;
00521 
00522 /********************************************
00523 
00524     Tx/Rx Queue Structure
00525 
00526 ********************************************/
00527 
00528 #ifdef SINGLE_TX_QUEUE
00529 typedef enum {
00530     CFG_W = 1,
00531     CFG_Q,
00532     NET_D,
00533 } TX_PACKET_ID_T;
00534 #endif
00535 
00536 typedef struct que_h {
00537     int bytes_in_queue; 
00538     int count;
00539     LOCK_ID_T lock_id;
00540     struct wl_list list;
00541 } que_hdr_t;
00542 
00543 typedef struct que_e {
00544     u8 *buffer; 
00545     u32 buffer_size;    
00546     struct wl_list list;
00547 } que_e_common_t;
00548 
00549 #ifdef SINGLE_TX_QUEUE
00550 typedef struct tx_que_common {
00551     u8 *buffer; 
00552     u32 buffer_size;
00553     struct wl_list list;
00554     TX_PACKET_ID_T id;
00555 } tx_que_common_t;
00556 #endif
00557 
00558 typedef struct txq_e {
00559     u8 *buffer; 
00560     u32 buffer_size;
00561     struct wl_list list;
00562 #ifdef SINGLE_TX_QUEUE
00563     TX_PACKET_ID_T id;
00564 #endif
00565     void *priv;
00566     free_txb_cb_fun_t free_txb_cb;  
00567 } txq_e_t;
00568 
00569 typedef struct rxq_e {
00570     u8 *buffer; 
00571     u32 buffer_size;    
00572     struct wl_list list;
00573 } rxq_e_t;
00574 
00575 typedef struct set_cfg_e {  
00576     u8 *buffer; 
00577     u32 buffer_size;    
00578     struct wl_list list;
00579 #ifdef SINGLE_TX_QUEUE
00580     TX_PACKET_ID_T id;
00581 #endif
00582 } cfg_w_e_t;
00583 
00584 typedef struct query_cfg_e {
00585     u8 *buffer; 
00586     u32 buffer_size;
00587     struct wl_list list;
00588 #ifdef SINGLE_TX_QUEUE
00589     TX_PACKET_ID_T id;
00590 #endif
00591 } cfg_q_e_t;
00592 
00593 /* Atmel: 1-15-2015
00594         Move to nmi_wlan_if.h
00595 */
00596 //typedef void (*query_cb_fun_t)(u32, u32);
00597 
00598 typedef struct query_rsp_e {
00599     u16 wid;    
00600     query_cb_fun_t query_cb;
00601     struct wl_list list;
00602 } cfg_q_rsp_e_t;
00603 
00604 typedef struct {
00605     u8  type;
00606     u8  id;
00607     u16     len;
00608 } cfg_msg_hdr_t; 
00609 
00610 
00611 typedef struct {
00612     int (*read_reg)(u32, u32 *);
00613     int (*write_reg)(u32, u32);
00614     int (*block_rx)(u32, u8 *, u32);
00615     int (*block_tx)(u32, u8 *, u32);    
00616     int (*hw_cfg)(void);
00617     int (*clear_intr)(void);    
00618 } nmi_wl_if_t;
00619 
00620 #ifdef __cplusplus
00621 extern "C" {
00622 #endif
00623 extern int nmi_hif_init(nmi_wl_io_t *, nmi_wl_if_t *);
00624 extern void DPRINT(u32, char *fmt, ...);
00625 extern void DPRINT_HEX(u32 grp, char *title, u8 *buf, u32 len);
00626 void set_FW_TX_OK(void);//Tsungta
00627 void get_FW_TX_OK(void);//Tsungta
00628 u32 FW_TX_is_OK(void);
00629 #ifdef __cplusplus
00630 }
00631 #endif
00632 
00633 #endif
00634 
00635