Toyomasa Watarai / mbed-src

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targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/system_LPC11Uxx.h@412:ea78ced42a1f, 2014-11-27 (annotated)

Committer:
MACRUM
Date:
Thu Nov 27 06:27:12 2014 +0000
Revision:
412:ea78ced42a1f
Parent:
13:0645d8841f51 
Fixed I2C issue (temporary) in RZ/A1H

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /**************************************************************************//**
emilmont 10:3bc89ef62ce7 2 * @file system_LPC11Uxx.h
emilmont 10:3bc89ef62ce7 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
emilmont 10:3bc89ef62ce7 4 * for the NXP LPC11Uxx Device Series
emilmont 10:3bc89ef62ce7 5 * @version V1.10
emilmont 10:3bc89ef62ce7 6 * @date 24. November 2010
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * @note
emilmont 10:3bc89ef62ce7 9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 10 *
emilmont 10:3bc89ef62ce7 11 * @par
emilmont 10:3bc89ef62ce7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 10:3bc89ef62ce7 13 * processor based microcontrollers. This file can be freely distributed
emilmont 10:3bc89ef62ce7 14 * within development tools that are supporting such ARM based processors.
emilmont 10:3bc89ef62ce7 15 *
emilmont 10:3bc89ef62ce7 16 * @par
emilmont 10:3bc89ef62ce7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 10:3bc89ef62ce7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 10:3bc89ef62ce7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 10:3bc89ef62ce7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 10:3bc89ef62ce7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 10:3bc89ef62ce7 22 *
emilmont 10:3bc89ef62ce7 23 ******************************************************************************/
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25
emilmont 10:3bc89ef62ce7 26 #ifndef __SYSTEM_LPC11Uxx_H
emilmont 10:3bc89ef62ce7 27 #define __SYSTEM_LPC11Uxx_H
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 30 extern "C" {
emilmont 10:3bc89ef62ce7 31 #endif
emilmont 10:3bc89ef62ce7 32
emilmont 10:3bc89ef62ce7 33 #include <stdint.h>
emilmont 10:3bc89ef62ce7 34
emilmont 10:3bc89ef62ce7 35 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37
emilmont 10:3bc89ef62ce7 38 /**
emilmont 10:3bc89ef62ce7 39 * Initialize the system
emilmont 10:3bc89ef62ce7 40 *
emilmont 10:3bc89ef62ce7 41 * @param none
emilmont 10:3bc89ef62ce7 42 * @return none
emilmont 10:3bc89ef62ce7 43 *
emilmont 10:3bc89ef62ce7 44 * @brief Setup the microcontroller system.
emilmont 10:3bc89ef62ce7 45 * Initialize the System and update the SystemCoreClock variable.
emilmont 10:3bc89ef62ce7 46 */
emilmont 10:3bc89ef62ce7 47 extern void SystemInit (void);
emilmont 10:3bc89ef62ce7 48
emilmont 10:3bc89ef62ce7 49 /**
emilmont 10:3bc89ef62ce7 50 * Update SystemCoreClock variable
emilmont 10:3bc89ef62ce7 51 *
emilmont 10:3bc89ef62ce7 52 * @param none
emilmont 10:3bc89ef62ce7 53 * @return none
emilmont 10:3bc89ef62ce7 54 *
emilmont 10:3bc89ef62ce7 55 * @brief Updates the SystemCoreClock with current core Clock
emilmont 10:3bc89ef62ce7 56 * retrieved from cpu registers.
emilmont 10:3bc89ef62ce7 57 */
emilmont 10:3bc89ef62ce7 58 extern void SystemCoreClockUpdate (void);
emilmont 10:3bc89ef62ce7 59
emilmont 10:3bc89ef62ce7 60 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 61 }
emilmont 10:3bc89ef62ce7 62 #endif
emilmont 10:3bc89ef62ce7 63
emilmont 10:3bc89ef62ce7 64 #endif /* __SYSTEM_LPC11Uxx_H */