Toyomasa Watarai / mbed-dev

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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.c@68:53d4cfd70523, 2016-02-19 (annotated)

Committer:
MACRUM
Date:
Fri Feb 19 06:16:11 2016 +0000
Revision:
68:53d4cfd70523
Parent:
0:9b334a45a8ff 
Add state reset code in analogin_init() for Nucleo F303K8 target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f30x_syscfg.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 27-February-2014
bogdanm 0:9b334a45a8ff 7 * @brief This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 8 * functionalities of the SYSCFG peripheral:
bogdanm 0:9b334a45a8ff 9 * + Remapping the memory mapped at 0x00000000
bogdanm 0:9b334a45a8ff 10 * + Remapping the DMA channels
bogdanm 0:9b334a45a8ff 11 * + Enabling I2C fast mode plus driving capability for I2C plus
bogdanm 0:9b334a45a8ff 12 * + Remapping USB interrupt line
bogdanm 0:9b334a45a8ff 13 * + Configuring the EXTI lines connection to the GPIO port
bogdanm 0:9b334a45a8ff 14 * + Configuring the CLASSB requirements
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 @verbatim
bogdanm 0:9b334a45a8ff 17
bogdanm 0:9b334a45a8ff 18 ===============================================================================
bogdanm 0:9b334a45a8ff 19 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 20 ===============================================================================
bogdanm 0:9b334a45a8ff 21 [..] The SYSCFG registers can be accessed only when the SYSCFG
bogdanm 0:9b334a45a8ff 22 interface APB clock is enabled.
bogdanm 0:9b334a45a8ff 23 [..] To enable SYSCFG APB clock use:
bogdanm 0:9b334a45a8ff 24 RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 @endverbatim
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 ******************************************************************************
bogdanm 0:9b334a45a8ff 29 * @attention
bogdanm 0:9b334a45a8ff 30 *
bogdanm 0:9b334a45a8ff 31 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 32 *
bogdanm 0:9b334a45a8ff 33 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 34 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 35 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 36 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 37 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 38 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 39 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 40 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 41 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 42 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 43 *
bogdanm 0:9b334a45a8ff 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 47 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 50 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 51 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 54 *
bogdanm 0:9b334a45a8ff 55 ******************************************************************************
bogdanm 0:9b334a45a8ff 56 */
bogdanm 0:9b334a45a8ff 57
bogdanm 0:9b334a45a8ff 58 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 #include "stm32f30x_syscfg.h"
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm 0:9b334a45a8ff 62 * @{
bogdanm 0:9b334a45a8ff 63 */
bogdanm 0:9b334a45a8ff 64
bogdanm 0:9b334a45a8ff 65 /** @defgroup SYSCFG
bogdanm 0:9b334a45a8ff 66 * @brief SYSCFG driver modules
bogdanm 0:9b334a45a8ff 67 * @{
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 71 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 72 /* Reset value od SYSCFG_CFGR1 register */
bogdanm 0:9b334a45a8ff 73 #define CFGR1_CLEAR_MASK ((uint32_t)0x7C000000)
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 /* ------------ SYSCFG registers bit address in the alias region -------------*/
bogdanm 0:9b334a45a8ff 76 #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 /* --- CFGR1 Register ---*/
bogdanm 0:9b334a45a8ff 79 /* Alias word address of USB_IT_RMP bit */
bogdanm 0:9b334a45a8ff 80 #define CFGR1_OFFSET (SYSCFG_OFFSET + 0x00)
bogdanm 0:9b334a45a8ff 81 #define USBITRMP_BitNumber 0x05
bogdanm 0:9b334a45a8ff 82 #define CFGR1_USBITRMP_BB (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /* --- CFGR2 Register ---*/
bogdanm 0:9b334a45a8ff 85 /* Alias word address of BYP_ADDR_PAR bit */
bogdanm 0:9b334a45a8ff 86 #define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18)
bogdanm 0:9b334a45a8ff 87 #define BYPADDRPAR_BitNumber 0x04
bogdanm 0:9b334a45a8ff 88 #define CFGR1_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 91 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 92 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 93 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /** @defgroup SYSCFG_Private_Functions
bogdanm 0:9b334a45a8ff 96 * @{
bogdanm 0:9b334a45a8ff 97 */
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 100 * @brief SYSCFG Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 101 *
bogdanm 0:9b334a45a8ff 102 @verbatim
bogdanm 0:9b334a45a8ff 103 ===============================================================================
bogdanm 0:9b334a45a8ff 104 ##### SYSCFG Initialization and Configuration functions #####
bogdanm 0:9b334a45a8ff 105 ===============================================================================
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 @endverbatim
bogdanm 0:9b334a45a8ff 108 * @{
bogdanm 0:9b334a45a8ff 109 */
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 /**
bogdanm 0:9b334a45a8ff 112 * @brief Deinitializes the SYSCFG registers to their default reset values.
bogdanm 0:9b334a45a8ff 113 * @param None
bogdanm 0:9b334a45a8ff 114 * @retval None
bogdanm 0:9b334a45a8ff 115 * @note MEM_MODE bits are not affected by APB reset.
bogdanm 0:9b334a45a8ff 116 * MEM_MODE bits took the value from the user option bytes.
bogdanm 0:9b334a45a8ff 117 */
bogdanm 0:9b334a45a8ff 118 void SYSCFG_DeInit(void)
bogdanm 0:9b334a45a8ff 119 {
bogdanm 0:9b334a45a8ff 120 /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
bogdanm 0:9b334a45a8ff 121 SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
bogdanm 0:9b334a45a8ff 122 /* Set FPU Interrupt Enable bits to default value */
bogdanm 0:9b334a45a8ff 123 SYSCFG->CFGR1 |= 0x7C000000;
bogdanm 0:9b334a45a8ff 124 /* Reset RAM Write protection bits to default value */
bogdanm 0:9b334a45a8ff 125 SYSCFG->RCR = 0x00000000;
bogdanm 0:9b334a45a8ff 126 /* Set EXTICRx registers to reset value */
bogdanm 0:9b334a45a8ff 127 SYSCFG->EXTICR[0] = 0;
bogdanm 0:9b334a45a8ff 128 SYSCFG->EXTICR[1] = 0;
bogdanm 0:9b334a45a8ff 129 SYSCFG->EXTICR[2] = 0;
bogdanm 0:9b334a45a8ff 130 SYSCFG->EXTICR[3] = 0;
bogdanm 0:9b334a45a8ff 131 /* Set CFGR2 register to reset value */
bogdanm 0:9b334a45a8ff 132 SYSCFG->CFGR2 = 0;
bogdanm 0:9b334a45a8ff 133 /* Set CFGR3 register to reset value */
bogdanm 0:9b334a45a8ff 134 SYSCFG->CFGR3 = 0;
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /**
bogdanm 0:9b334a45a8ff 138 * @brief Configures the memory mapping at address 0x00000000.
bogdanm 0:9b334a45a8ff 139 * @param SYSCFG_MemoryRemap: selects the memory remapping.
bogdanm 0:9b334a45a8ff 140 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 141 * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
bogdanm 0:9b334a45a8ff 142 * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
bogdanm 0:9b334a45a8ff 143 * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
bogdanm 0:9b334a45a8ff 144 * @retval None
bogdanm 0:9b334a45a8ff 145 */
bogdanm 0:9b334a45a8ff 146 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
bogdanm 0:9b334a45a8ff 147 {
bogdanm 0:9b334a45a8ff 148 uint32_t tmpcfgr1 = 0;
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* Check the parameter */
bogdanm 0:9b334a45a8ff 151 assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* Get CFGR1 register value */
bogdanm 0:9b334a45a8ff 154 tmpcfgr1 = SYSCFG->CFGR1;
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /* Clear MEM_MODE bits */
bogdanm 0:9b334a45a8ff 157 tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* Set the new MEM_MODE bits value */
bogdanm 0:9b334a45a8ff 160 tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /* Set CFGR1 register with the new memory remap configuration */
bogdanm 0:9b334a45a8ff 163 SYSCFG->CFGR1 = tmpcfgr1;
bogdanm 0:9b334a45a8ff 164 }
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /**
bogdanm 0:9b334a45a8ff 167 * @brief Configures the DMA channels remapping.
bogdanm 0:9b334a45a8ff 168 * @param SYSCFG_DMARemap: selects the DMA channels remap.
bogdanm 0:9b334a45a8ff 169 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 170 * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
bogdanm 0:9b334a45a8ff 171 * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
bogdanm 0:9b334a45a8ff 172 * @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
bogdanm 0:9b334a45a8ff 173 * @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
bogdanm 0:9b334a45a8ff 174 * @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
bogdanm 0:9b334a45a8ff 175 * @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
bogdanm 0:9b334a45a8ff 176 * @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
bogdanm 0:9b334a45a8ff 177 * @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
bogdanm 0:9b334a45a8ff 178 * @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
bogdanm 0:9b334a45a8ff 179 * @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
bogdanm 0:9b334a45a8ff 180 * @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
bogdanm 0:9b334a45a8ff 181 * @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
bogdanm 0:9b334a45a8ff 182 * @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
bogdanm 0:9b334a45a8ff 183 * @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
bogdanm 0:9b334a45a8ff 184 * @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
bogdanm 0:9b334a45a8ff 185 * @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
bogdanm 0:9b334a45a8ff 186 * @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
bogdanm 0:9b334a45a8ff 187 * @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
bogdanm 0:9b334a45a8ff 188 * @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
bogdanm 0:9b334a45a8ff 189 * @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
bogdanm 0:9b334a45a8ff 190 * @param NewState: new state of the DMA channel remapping.
bogdanm 0:9b334a45a8ff 191 * This parameter can be: Enable or Disable.
bogdanm 0:9b334a45a8ff 192 * @note When enabled, DMA channel of the selected peripheral is remapped
bogdanm 0:9b334a45a8ff 193 * @note When disabled, Default DMA channel is mapped to the selected peripheral
bogdanm 0:9b334a45a8ff 194 * @note
bogdanm 0:9b334a45a8ff 195 * By default TIM17 DMA requests is mapped to channel 1
bogdanm 0:9b334a45a8ff 196 * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
bogdanm 0:9b334a45a8ff 197 * to remap TIM17 DMA requests to DMA1 channel 2
bogdanm 0:9b334a45a8ff 198 * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
bogdanm 0:9b334a45a8ff 199 * to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
bogdanm 0:9b334a45a8ff 200 * @retval None
bogdanm 0:9b334a45a8ff 201 */
bogdanm 0:9b334a45a8ff 202 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 203 {
bogdanm 0:9b334a45a8ff 204 /* Check the parameters */
bogdanm 0:9b334a45a8ff 205 assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
bogdanm 0:9b334a45a8ff 206 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
bogdanm 0:9b334a45a8ff 209 {
bogdanm 0:9b334a45a8ff 210 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 /* Remap the DMA channel */
bogdanm 0:9b334a45a8ff 213 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
bogdanm 0:9b334a45a8ff 214 }
bogdanm 0:9b334a45a8ff 215 else
bogdanm 0:9b334a45a8ff 216 {
bogdanm 0:9b334a45a8ff 217 /* use the default DMA channel mapping */
bogdanm 0:9b334a45a8ff 218 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
bogdanm 0:9b334a45a8ff 219 }
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221 else
bogdanm 0:9b334a45a8ff 222 {
bogdanm 0:9b334a45a8ff 223 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 224 {
bogdanm 0:9b334a45a8ff 225 /* Remap the DMA channel */
bogdanm 0:9b334a45a8ff 226 SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
bogdanm 0:9b334a45a8ff 227 }
bogdanm 0:9b334a45a8ff 228 else
bogdanm 0:9b334a45a8ff 229 {
bogdanm 0:9b334a45a8ff 230 /* use the default DMA channel mapping */
bogdanm 0:9b334a45a8ff 231 SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /**
bogdanm 0:9b334a45a8ff 237 * @brief Configures the remapping capabilities of DAC/TIM triggers.
bogdanm 0:9b334a45a8ff 238 * @param SYSCFG_TriggerRemap: selects the trigger to be remapped.
bogdanm 0:9b334a45a8ff 239 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 240 * @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
bogdanm 0:9b334a45a8ff 241 * @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
bogdanm 0:9b334a45a8ff 242 * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
bogdanm 0:9b334a45a8ff 243 * @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
bogdanm 0:9b334a45a8ff 244 * @param NewState: new state of the trigger mapping.
bogdanm 0:9b334a45a8ff 245 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 246 * @note ENABLE: Enable fast mode plus driving capability for selected pin
bogdanm 0:9b334a45a8ff 247 * @note DISABLE: Disable fast mode plus driving capability for selected pin
bogdanm 0:9b334a45a8ff 248 * @retval None
bogdanm 0:9b334a45a8ff 249 */
bogdanm 0:9b334a45a8ff 250 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 251 {
bogdanm 0:9b334a45a8ff 252 /* Check the parameters */
bogdanm 0:9b334a45a8ff 253 assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
bogdanm 0:9b334a45a8ff 254 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
bogdanm 0:9b334a45a8ff 257 {
bogdanm 0:9b334a45a8ff 258 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 259 {
bogdanm 0:9b334a45a8ff 260 /* Remap the trigger */
bogdanm 0:9b334a45a8ff 261 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 else
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* Use the default trigger mapping */
bogdanm 0:9b334a45a8ff 266 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
bogdanm 0:9b334a45a8ff 267 }
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269 else
bogdanm 0:9b334a45a8ff 270 {
bogdanm 0:9b334a45a8ff 271 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 272 {
bogdanm 0:9b334a45a8ff 273 /* Remap the trigger */
bogdanm 0:9b334a45a8ff 274 SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276 else
bogdanm 0:9b334a45a8ff 277 {
bogdanm 0:9b334a45a8ff 278 /* Use the default trigger mapping */
bogdanm 0:9b334a45a8ff 279 SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /**
bogdanm 0:9b334a45a8ff 285 * @brief Configures the remapping capabilities of encoder mode.
bogdanm 0:9b334a45a8ff 286 * @ note This feature implement the so-called M/T method for measuring speed
bogdanm 0:9b334a45a8ff 287 * and position using quadrature encoders.
bogdanm 0:9b334a45a8ff 288 * @param SYSCFG_EncoderRemap: selects the remap option for encoder mode.
bogdanm 0:9b334a45a8ff 289 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 290 * @arg SYSCFG_EncoderRemap_No: No remap
bogdanm 0:9b334a45a8ff 291 * @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
bogdanm 0:9b334a45a8ff 292 * @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
bogdanm 0:9b334a45a8ff 293 * @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
bogdanm 0:9b334a45a8ff 294 * @retval None
bogdanm 0:9b334a45a8ff 295 */
bogdanm 0:9b334a45a8ff 296 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
bogdanm 0:9b334a45a8ff 297 {
bogdanm 0:9b334a45a8ff 298 /* Check the parameter */
bogdanm 0:9b334a45a8ff 299 assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
bogdanm 0:9b334a45a8ff 300
bogdanm 0:9b334a45a8ff 301 /* Reset the encoder mode remapping bits */
bogdanm 0:9b334a45a8ff 302 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Set the selected configuration */
bogdanm 0:9b334a45a8ff 305 SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /**
bogdanm 0:9b334a45a8ff 309 * @brief Remaps the USB interrupt lines.
bogdanm 0:9b334a45a8ff 310 * @param NewState: new state of the mapping of USB interrupt lines.
bogdanm 0:9b334a45a8ff 311 * This parameter can be:
bogdanm 0:9b334a45a8ff 312 * @param ENABLE: Remap the USB interrupt line as following:
bogdanm 0:9b334a45a8ff 313 * @arg USB Device High Priority (USB_HP) interrupt mapped to line 74.
bogdanm 0:9b334a45a8ff 314 * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 75.
bogdanm 0:9b334a45a8ff 315 * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
bogdanm 0:9b334a45a8ff 316 * @param DISABLE: Use the default USB interrupt line:
bogdanm 0:9b334a45a8ff 317 * @arg USB Device High Priority (USB_HP) interrupt mapped to line 19.
bogdanm 0:9b334a45a8ff 318 * @arg USB Device Low Priority (USB_LP) interrupt mapped to line 20.
bogdanm 0:9b334a45a8ff 319 * @arg USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
bogdanm 0:9b334a45a8ff 320 * @retval None
bogdanm 0:9b334a45a8ff 321 */
bogdanm 0:9b334a45a8ff 322 void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
bogdanm 0:9b334a45a8ff 323 {
bogdanm 0:9b334a45a8ff 324 /* Check the parameter */
bogdanm 0:9b334a45a8ff 325 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Remap the USB interupt lines */
bogdanm 0:9b334a45a8ff 328 *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
bogdanm 0:9b334a45a8ff 329 }
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /**
bogdanm 0:9b334a45a8ff 332 * @brief Configures the I2C fast mode plus driving capability.
bogdanm 0:9b334a45a8ff 333 * @param SYSCFG_I2CFastModePlus: selects the pin.
bogdanm 0:9b334a45a8ff 334 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 335 * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
bogdanm 0:9b334a45a8ff 336 * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
bogdanm 0:9b334a45a8ff 337 * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
bogdanm 0:9b334a45a8ff 338 * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
bogdanm 0:9b334a45a8ff 339 * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
bogdanm 0:9b334a45a8ff 340 * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
bogdanm 0:9b334a45a8ff 341 * @param NewState: new state of the DMA channel remapping.
bogdanm 0:9b334a45a8ff 342 * This parameter can be:
bogdanm 0:9b334a45a8ff 343 * @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
bogdanm 0:9b334a45a8ff 344 * @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
bogdanm 0:9b334a45a8ff 345 * @note For I2C1, fast mode plus driving capability can be enabled on all selected
bogdanm 0:9b334a45a8ff 346 * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
bogdanm 0:9b334a45a8ff 347 * on each one of the following pins PB6, PB7, PB8 and PB9.
bogdanm 0:9b334a45a8ff 348 * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
bogdanm 0:9b334a45a8ff 349 * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
bogdanm 0:9b334a45a8ff 350 * @note For all I2C2 pins fast mode plus driving capability can be enabled
bogdanm 0:9b334a45a8ff 351 * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
bogdanm 0:9b334a45a8ff 352 * @retval None
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 355 {
bogdanm 0:9b334a45a8ff 356 /* Check the parameters */
bogdanm 0:9b334a45a8ff 357 assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
bogdanm 0:9b334a45a8ff 358 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 /* Enable fast mode plus driving capability for selected I2C pin */
bogdanm 0:9b334a45a8ff 363 SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
bogdanm 0:9b334a45a8ff 364 }
bogdanm 0:9b334a45a8ff 365 else
bogdanm 0:9b334a45a8ff 366 {
bogdanm 0:9b334a45a8ff 367 /* Disable fast mode plus driving capability for selected I2C pin */
bogdanm 0:9b334a45a8ff 368 SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
bogdanm 0:9b334a45a8ff 369 }
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371
bogdanm 0:9b334a45a8ff 372 /**
bogdanm 0:9b334a45a8ff 373 * @brief Enables or disables the selected SYSCFG interrupts.
bogdanm 0:9b334a45a8ff 374 * @param SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 375 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 376 * @arg SYSCFG_IT_IXC: Inexact Interrupt
bogdanm 0:9b334a45a8ff 377 * @arg SYSCFG_IT_IDC: Input denormal Interrupt
bogdanm 0:9b334a45a8ff 378 * @arg SYSCFG_IT_OFC: Overflow Interrupt
bogdanm 0:9b334a45a8ff 379 * @arg SYSCFG_IT_UFC: Underflow Interrupt
bogdanm 0:9b334a45a8ff 380 * @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
bogdanm 0:9b334a45a8ff 381 * @arg SYSCFG_IT_IOC: Invalid operation Interrupt
bogdanm 0:9b334a45a8ff 382 * @param NewState: new state of the specified SYSCFG interrupts.
bogdanm 0:9b334a45a8ff 383 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 384 * @retval None
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 387 {
bogdanm 0:9b334a45a8ff 388 /* Check the parameters */
bogdanm 0:9b334a45a8ff 389 assert_param(IS_FUNCTIONAL_STATE(NewState));
bogdanm 0:9b334a45a8ff 390 assert_param(IS_SYSCFG_IT(SYSCFG_IT));
bogdanm 0:9b334a45a8ff 391
bogdanm 0:9b334a45a8ff 392 if (NewState != DISABLE)
bogdanm 0:9b334a45a8ff 393 {
bogdanm 0:9b334a45a8ff 394 /* Enable the selected SYSCFG interrupts */
bogdanm 0:9b334a45a8ff 395 SYSCFG->CFGR1 |= SYSCFG_IT;
bogdanm 0:9b334a45a8ff 396 }
bogdanm 0:9b334a45a8ff 397 else
bogdanm 0:9b334a45a8ff 398 {
bogdanm 0:9b334a45a8ff 399 /* Disable the selected SYSCFG interrupts */
bogdanm 0:9b334a45a8ff 400 SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
bogdanm 0:9b334a45a8ff 401 }
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 /**
bogdanm 0:9b334a45a8ff 405 * @brief Selects the GPIO pin used as EXTI Line.
bogdanm 0:9b334a45a8ff 406 * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
bogdanm 0:9b334a45a8ff 407 * for EXTI lines where x can be (A, B, C, D, E or F).
bogdanm 0:9b334a45a8ff 408 * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
bogdanm 0:9b334a45a8ff 409 * This parameter can be EXTI_PinSourcex where x can be (0..15)
bogdanm 0:9b334a45a8ff 410 * @retval None
bogdanm 0:9b334a45a8ff 411 */
bogdanm 0:9b334a45a8ff 412 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 uint32_t tmp = 0x00;
bogdanm 0:9b334a45a8ff 415
bogdanm 0:9b334a45a8ff 416 /* Check the parameters */
bogdanm 0:9b334a45a8ff 417 assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
bogdanm 0:9b334a45a8ff 418 assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
bogdanm 0:9b334a45a8ff 421 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
bogdanm 0:9b334a45a8ff 422 SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425 /**
bogdanm 0:9b334a45a8ff 426 * @brief Connects the selected parameter to the break input of TIM1.
bogdanm 0:9b334a45a8ff 427 * @note The selected configuration is locked and can be unlocked by system reset
bogdanm 0:9b334a45a8ff 428 * @param SYSCFG_Break: selects the configuration to be connected to break
bogdanm 0:9b334a45a8ff 429 * input of TIM1
bogdanm 0:9b334a45a8ff 430 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 431 * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
bogdanm 0:9b334a45a8ff 432 * @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
bogdanm 0:9b334a45a8ff 433 * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
bogdanm 0:9b334a45a8ff 434 * @retval None
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
bogdanm 0:9b334a45a8ff 437 {
bogdanm 0:9b334a45a8ff 438 /* Check the parameter */
bogdanm 0:9b334a45a8ff 439 assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443
bogdanm 0:9b334a45a8ff 444 /**
bogdanm 0:9b334a45a8ff 445 * @brief Disables the parity check on RAM.
bogdanm 0:9b334a45a8ff 446 * @note Disabling the parity check on RAM locks the configuration bit.
bogdanm 0:9b334a45a8ff 447 * To re-enable the parity check on RAM perform a system reset.
bogdanm 0:9b334a45a8ff 448 * @param None
bogdanm 0:9b334a45a8ff 449 * @retval None
bogdanm 0:9b334a45a8ff 450 */
bogdanm 0:9b334a45a8ff 451 void SYSCFG_BypassParityCheckDisable(void)
bogdanm 0:9b334a45a8ff 452 {
bogdanm 0:9b334a45a8ff 453 /* Disable the adddress parity check on RAM */
bogdanm 0:9b334a45a8ff 454 *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 455 }
bogdanm 0:9b334a45a8ff 456
bogdanm 0:9b334a45a8ff 457 /**
bogdanm 0:9b334a45a8ff 458 * @brief Enables the ICODE SRAM write protection.
bogdanm 0:9b334a45a8ff 459 * @note Enabling the ICODE SRAM write protection locks the configuration bit.
bogdanm 0:9b334a45a8ff 460 * To disable the ICODE SRAM write protection perform a system reset.
bogdanm 0:9b334a45a8ff 461 * @param None
bogdanm 0:9b334a45a8ff 462 * @retval None
bogdanm 0:9b334a45a8ff 463 */
bogdanm 0:9b334a45a8ff 464 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
bogdanm 0:9b334a45a8ff 465 {
bogdanm 0:9b334a45a8ff 466 /* Check the parameter */
bogdanm 0:9b334a45a8ff 467 assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
bogdanm 0:9b334a45a8ff 468
bogdanm 0:9b334a45a8ff 469 /* Enable the write-protection on the selected ICODE SRAM page */
bogdanm 0:9b334a45a8ff 470 SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
bogdanm 0:9b334a45a8ff 471 }
bogdanm 0:9b334a45a8ff 472
bogdanm 0:9b334a45a8ff 473 /**
bogdanm 0:9b334a45a8ff 474 * @brief Checks whether the specified SYSCFG flag is set or not.
bogdanm 0:9b334a45a8ff 475 * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
bogdanm 0:9b334a45a8ff 476 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 477 * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
bogdanm 0:9b334a45a8ff 478 * @retval The new state of SYSCFG_Flag (SET or RESET).
bogdanm 0:9b334a45a8ff 479 */
bogdanm 0:9b334a45a8ff 480 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
bogdanm 0:9b334a45a8ff 481 {
bogdanm 0:9b334a45a8ff 482 FlagStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Check the parameter */
bogdanm 0:9b334a45a8ff 485 assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /* Check the status of the specified SPI flag */
bogdanm 0:9b334a45a8ff 488 if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
bogdanm 0:9b334a45a8ff 489 {
bogdanm 0:9b334a45a8ff 490 /* SYSCFG_Flag is set */
bogdanm 0:9b334a45a8ff 491 bitstatus = SET;
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493 else
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 /* SYSCFG_Flag is reset */
bogdanm 0:9b334a45a8ff 496 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 497 }
bogdanm 0:9b334a45a8ff 498 /* Return the SYSCFG_Flag status */
bogdanm 0:9b334a45a8ff 499 return bitstatus;
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /**
bogdanm 0:9b334a45a8ff 503 * @brief Clears the selected SYSCFG flag.
bogdanm 0:9b334a45a8ff 504 * @param SYSCFG_Flag: selects the flag to be cleared.
bogdanm 0:9b334a45a8ff 505 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 506 * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
bogdanm 0:9b334a45a8ff 507 * @retval None
bogdanm 0:9b334a45a8ff 508 */
bogdanm 0:9b334a45a8ff 509 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
bogdanm 0:9b334a45a8ff 510 {
bogdanm 0:9b334a45a8ff 511 /* Check the parameter */
bogdanm 0:9b334a45a8ff 512 assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
bogdanm 0:9b334a45a8ff 513
bogdanm 0:9b334a45a8ff 514 SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
bogdanm 0:9b334a45a8ff 515 }
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /**
bogdanm 0:9b334a45a8ff 518 * @}
bogdanm 0:9b334a45a8ff 519 */
bogdanm 0:9b334a45a8ff 520
bogdanm 0:9b334a45a8ff 521 /**
bogdanm 0:9b334a45a8ff 522 * @}
bogdanm 0:9b334a45a8ff 523 */
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /**
bogdanm 0:9b334a45a8ff 526 * @}
bogdanm 0:9b334a45a8ff 527 */
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /**
bogdanm 0:9b334a45a8ff 530 * @}
bogdanm 0:9b334a45a8ff 531 */
bogdanm 0:9b334a45a8ff 532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 533