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mbed-dev
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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.c@68:53d4cfd70523, 2016-02-19 (annotated)
- Committer:
- MACRUM
- Date:
- Fri Feb 19 06:16:11 2016 +0000
- Revision:
- 68:53d4cfd70523
- Parent:
- 0:9b334a45a8ff
Add state reset code in analogin_init() for Nucleo F303K8 target
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f30x_dma.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.1.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 27-February-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief This file provides firmware functions to manage the following |
| bogdanm | 0:9b334a45a8ff | 8 | * functionalities of the Direct Memory Access controller (DMA): |
| bogdanm | 0:9b334a45a8ff | 9 | * + Initialization and Configuration |
| bogdanm | 0:9b334a45a8ff | 10 | * + Data Counter |
| bogdanm | 0:9b334a45a8ff | 11 | * + Interrupts and flags management |
| bogdanm | 0:9b334a45a8ff | 12 | * |
| bogdanm | 0:9b334a45a8ff | 13 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 14 | |
| bogdanm | 0:9b334a45a8ff | 15 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 16 | ##### How to use this driver ##### |
| bogdanm | 0:9b334a45a8ff | 17 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 18 | [..] |
| bogdanm | 0:9b334a45a8ff | 19 | (#) Enable The DMA controller clock using |
| bogdanm | 0:9b334a45a8ff | 20 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or |
| bogdanm | 0:9b334a45a8ff | 21 | using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2. |
| bogdanm | 0:9b334a45a8ff | 22 | (#) Enable and configure the peripheral to be connected to the DMA channel |
| bogdanm | 0:9b334a45a8ff | 23 | (except for internal SRAM / FLASH memories: no initialization is necessary). |
| bogdanm | 0:9b334a45a8ff | 24 | (#) For a given Channel, program the Source and Destination addresses, |
| bogdanm | 0:9b334a45a8ff | 25 | the transfer Direction, the Buffer Size, the Peripheral and Memory |
| bogdanm | 0:9b334a45a8ff | 26 | Incrementation mode and Data Size, the Circular or Normal mode, |
| bogdanm | 0:9b334a45a8ff | 27 | the channel transfer Priority and the Memory-to-Memory transfer |
| bogdanm | 0:9b334a45a8ff | 28 | mode (if needed) using the DMA_Init() function. |
| bogdanm | 0:9b334a45a8ff | 29 | (#) Enable the NVIC and the corresponding interrupt(s) using the function |
| bogdanm | 0:9b334a45a8ff | 30 | DMA_ITConfig() if you need to use DMA interrupts. |
| bogdanm | 0:9b334a45a8ff | 31 | (#) Enable the DMA channel using the DMA_Cmd() function. |
| bogdanm | 0:9b334a45a8ff | 32 | (#) Activate the needed channel Request using PPP_DMACmd() function for |
| bogdanm | 0:9b334a45a8ff | 33 | any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) |
| bogdanm | 0:9b334a45a8ff | 34 | The function allowing this operation is provided in each PPP peripheral |
| bogdanm | 0:9b334a45a8ff | 35 | driver (ie. SPI_DMACmd for SPI peripheral). |
| bogdanm | 0:9b334a45a8ff | 36 | (#) Optionally, you can configure the number of data to be transferred |
| bogdanm | 0:9b334a45a8ff | 37 | when the channel is disabled (ie. after each Transfer Complete event |
| bogdanm | 0:9b334a45a8ff | 38 | or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). |
| bogdanm | 0:9b334a45a8ff | 39 | And you can get the number of remaining data to be transferred using |
| bogdanm | 0:9b334a45a8ff | 40 | the function DMA_GetCurrDataCounter() at run time (when the DMA channel is |
| bogdanm | 0:9b334a45a8ff | 41 | enabled and running). |
| bogdanm | 0:9b334a45a8ff | 42 | (#) To control DMA events you can use one of the following two methods: |
| bogdanm | 0:9b334a45a8ff | 43 | (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). |
| bogdanm | 0:9b334a45a8ff | 44 | (##) Use DMA interrupts through the function DMA_ITConfig() at initialization |
| bogdanm | 0:9b334a45a8ff | 45 | phase and DMA_GetITStatus() function into interrupt routines in |
| bogdanm | 0:9b334a45a8ff | 46 | communication phase. |
| bogdanm | 0:9b334a45a8ff | 47 | After checking on a flag you should clear it using DMA_ClearFlag() |
| bogdanm | 0:9b334a45a8ff | 48 | function. And after checking on an interrupt event you should |
| bogdanm | 0:9b334a45a8ff | 49 | clear it using DMA_ClearITPendingBit() function. |
| bogdanm | 0:9b334a45a8ff | 50 | |
| bogdanm | 0:9b334a45a8ff | 51 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 52 | |
| bogdanm | 0:9b334a45a8ff | 53 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 54 | * @attention |
| bogdanm | 0:9b334a45a8ff | 55 | * |
| bogdanm | 0:9b334a45a8ff | 56 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 57 | * |
| bogdanm | 0:9b334a45a8ff | 58 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 59 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 60 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 61 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 62 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 63 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 64 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 65 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 66 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 67 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 68 | * |
| bogdanm | 0:9b334a45a8ff | 69 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 70 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 71 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 72 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 73 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 74 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 75 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 76 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 77 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 78 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 79 | * |
| bogdanm | 0:9b334a45a8ff | 80 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 81 | */ |
| bogdanm | 0:9b334a45a8ff | 82 | |
| bogdanm | 0:9b334a45a8ff | 83 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 84 | #include "stm32f30x_dma.h" |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | /** @addtogroup STM32F30x_StdPeriph_Driver |
| bogdanm | 0:9b334a45a8ff | 87 | * @{ |
| bogdanm | 0:9b334a45a8ff | 88 | */ |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | /** @defgroup DMA |
| bogdanm | 0:9b334a45a8ff | 91 | * @brief DMA driver modules |
| bogdanm | 0:9b334a45a8ff | 92 | * @{ |
| bogdanm | 0:9b334a45a8ff | 93 | */ |
| bogdanm | 0:9b334a45a8ff | 94 | |
| bogdanm | 0:9b334a45a8ff | 95 | /* Private typedef -----------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 96 | /* Private define ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 97 | #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */ |
| bogdanm | 0:9b334a45a8ff | 99 | |
| bogdanm | 0:9b334a45a8ff | 100 | |
| bogdanm | 0:9b334a45a8ff | 101 | /* DMA1 Channelx interrupt pending bit masks */ |
| bogdanm | 0:9b334a45a8ff | 102 | #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
| bogdanm | 0:9b334a45a8ff | 103 | #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
| bogdanm | 0:9b334a45a8ff | 104 | #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
| bogdanm | 0:9b334a45a8ff | 105 | #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
| bogdanm | 0:9b334a45a8ff | 106 | #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
| bogdanm | 0:9b334a45a8ff | 107 | #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) |
| bogdanm | 0:9b334a45a8ff | 108 | #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) |
| bogdanm | 0:9b334a45a8ff | 109 | |
| bogdanm | 0:9b334a45a8ff | 110 | /* DMA2 Channelx interrupt pending bit masks */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
| bogdanm | 0:9b334a45a8ff | 112 | #define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
| bogdanm | 0:9b334a45a8ff | 113 | #define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
| bogdanm | 0:9b334a45a8ff | 114 | #define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
| bogdanm | 0:9b334a45a8ff | 115 | #define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
| bogdanm | 0:9b334a45a8ff | 116 | |
| bogdanm | 0:9b334a45a8ff | 117 | /* Private macro -------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 118 | /* Private variables ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 119 | /* Private function prototypes -----------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 120 | /* Private functions ---------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 121 | |
| bogdanm | 0:9b334a45a8ff | 122 | /** @defgroup DMA_Private_Functions |
| bogdanm | 0:9b334a45a8ff | 123 | * @{ |
| bogdanm | 0:9b334a45a8ff | 124 | */ |
| bogdanm | 0:9b334a45a8ff | 125 | |
| bogdanm | 0:9b334a45a8ff | 126 | /** @defgroup DMA_Group1 Initialization and Configuration functions |
| bogdanm | 0:9b334a45a8ff | 127 | * @brief Initialization and Configuration functions |
| bogdanm | 0:9b334a45a8ff | 128 | * |
| bogdanm | 0:9b334a45a8ff | 129 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 130 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 131 | ##### Initialization and Configuration functions ##### |
| bogdanm | 0:9b334a45a8ff | 132 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 133 | [..] This subsection provides functions allowing to initialize the DMA channel |
| bogdanm | 0:9b334a45a8ff | 134 | source and destination addresses, incrementation and data sizes, transfer |
| bogdanm | 0:9b334a45a8ff | 135 | direction, buffer size, circular/normal mode selection, memory-to-memory |
| bogdanm | 0:9b334a45a8ff | 136 | mode selection and channel priority value. |
| bogdanm | 0:9b334a45a8ff | 137 | [..] The DMA_Init() function follows the DMA configuration procedures as described |
| bogdanm | 0:9b334a45a8ff | 138 | in reference manual (RM00316). |
| bogdanm | 0:9b334a45a8ff | 139 | |
| bogdanm | 0:9b334a45a8ff | 140 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 141 | * @{ |
| bogdanm | 0:9b334a45a8ff | 142 | */ |
| bogdanm | 0:9b334a45a8ff | 143 | |
| bogdanm | 0:9b334a45a8ff | 144 | /** |
| bogdanm | 0:9b334a45a8ff | 145 | * @brief Deinitializes the DMAy Channelx registers to their default reset |
| bogdanm | 0:9b334a45a8ff | 146 | * values. |
| bogdanm | 0:9b334a45a8ff | 147 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 148 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 149 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 150 | */ |
| bogdanm | 0:9b334a45a8ff | 151 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) |
| bogdanm | 0:9b334a45a8ff | 152 | { |
| bogdanm | 0:9b334a45a8ff | 153 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 154 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 155 | |
| bogdanm | 0:9b334a45a8ff | 156 | /* Disable the selected DMAy Channelx */ |
| bogdanm | 0:9b334a45a8ff | 157 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); |
| bogdanm | 0:9b334a45a8ff | 158 | |
| bogdanm | 0:9b334a45a8ff | 159 | /* Reset DMAy Channelx control register */ |
| bogdanm | 0:9b334a45a8ff | 160 | DMAy_Channelx->CCR = 0; |
| bogdanm | 0:9b334a45a8ff | 161 | |
| bogdanm | 0:9b334a45a8ff | 162 | /* Reset DMAy Channelx remaining bytes register */ |
| bogdanm | 0:9b334a45a8ff | 163 | DMAy_Channelx->CNDTR = 0; |
| bogdanm | 0:9b334a45a8ff | 164 | |
| bogdanm | 0:9b334a45a8ff | 165 | /* Reset DMAy Channelx peripheral address register */ |
| bogdanm | 0:9b334a45a8ff | 166 | DMAy_Channelx->CPAR = 0; |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | /* Reset DMAy Channelx memory address register */ |
| bogdanm | 0:9b334a45a8ff | 169 | DMAy_Channelx->CMAR = 0; |
| bogdanm | 0:9b334a45a8ff | 170 | |
| bogdanm | 0:9b334a45a8ff | 171 | if (DMAy_Channelx == DMA1_Channel1) |
| bogdanm | 0:9b334a45a8ff | 172 | { |
| bogdanm | 0:9b334a45a8ff | 173 | /* Reset interrupt pending bits for DMA1 Channel1 */ |
| bogdanm | 0:9b334a45a8ff | 174 | DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 175 | } |
| bogdanm | 0:9b334a45a8ff | 176 | else if (DMAy_Channelx == DMA1_Channel2) |
| bogdanm | 0:9b334a45a8ff | 177 | { |
| bogdanm | 0:9b334a45a8ff | 178 | /* Reset interrupt pending bits for DMA1 Channel2 */ |
| bogdanm | 0:9b334a45a8ff | 179 | DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 180 | } |
| bogdanm | 0:9b334a45a8ff | 181 | else if (DMAy_Channelx == DMA1_Channel3) |
| bogdanm | 0:9b334a45a8ff | 182 | { |
| bogdanm | 0:9b334a45a8ff | 183 | /* Reset interrupt pending bits for DMA1 Channel3 */ |
| bogdanm | 0:9b334a45a8ff | 184 | DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 185 | } |
| bogdanm | 0:9b334a45a8ff | 186 | else if (DMAy_Channelx == DMA1_Channel4) |
| bogdanm | 0:9b334a45a8ff | 187 | { |
| bogdanm | 0:9b334a45a8ff | 188 | /* Reset interrupt pending bits for DMA1 Channel4 */ |
| bogdanm | 0:9b334a45a8ff | 189 | DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 190 | } |
| bogdanm | 0:9b334a45a8ff | 191 | else if (DMAy_Channelx == DMA1_Channel5) |
| bogdanm | 0:9b334a45a8ff | 192 | { |
| bogdanm | 0:9b334a45a8ff | 193 | /* Reset interrupt pending bits for DMA1 Channel5 */ |
| bogdanm | 0:9b334a45a8ff | 194 | DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 195 | } |
| bogdanm | 0:9b334a45a8ff | 196 | else if (DMAy_Channelx == DMA1_Channel6) |
| bogdanm | 0:9b334a45a8ff | 197 | { |
| bogdanm | 0:9b334a45a8ff | 198 | /* Reset interrupt pending bits for DMA1 Channel6 */ |
| bogdanm | 0:9b334a45a8ff | 199 | DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 200 | } |
| bogdanm | 0:9b334a45a8ff | 201 | else if (DMAy_Channelx == DMA1_Channel7) |
| bogdanm | 0:9b334a45a8ff | 202 | { |
| bogdanm | 0:9b334a45a8ff | 203 | /* Reset interrupt pending bits for DMA1 Channel7 */ |
| bogdanm | 0:9b334a45a8ff | 204 | DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 205 | } |
| bogdanm | 0:9b334a45a8ff | 206 | else if (DMAy_Channelx == DMA2_Channel1) |
| bogdanm | 0:9b334a45a8ff | 207 | { |
| bogdanm | 0:9b334a45a8ff | 208 | /* Reset interrupt pending bits for DMA2 Channel1 */ |
| bogdanm | 0:9b334a45a8ff | 209 | DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 210 | } |
| bogdanm | 0:9b334a45a8ff | 211 | else if (DMAy_Channelx == DMA2_Channel2) |
| bogdanm | 0:9b334a45a8ff | 212 | { |
| bogdanm | 0:9b334a45a8ff | 213 | /* Reset interrupt pending bits for DMA2 Channel2 */ |
| bogdanm | 0:9b334a45a8ff | 214 | DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 215 | } |
| bogdanm | 0:9b334a45a8ff | 216 | else if (DMAy_Channelx == DMA2_Channel3) |
| bogdanm | 0:9b334a45a8ff | 217 | { |
| bogdanm | 0:9b334a45a8ff | 218 | /* Reset interrupt pending bits for DMA2 Channel3 */ |
| bogdanm | 0:9b334a45a8ff | 219 | DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 220 | } |
| bogdanm | 0:9b334a45a8ff | 221 | else if (DMAy_Channelx == DMA2_Channel4) |
| bogdanm | 0:9b334a45a8ff | 222 | { |
| bogdanm | 0:9b334a45a8ff | 223 | /* Reset interrupt pending bits for DMA2 Channel4 */ |
| bogdanm | 0:9b334a45a8ff | 224 | DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 225 | } |
| bogdanm | 0:9b334a45a8ff | 226 | else |
| bogdanm | 0:9b334a45a8ff | 227 | { |
| bogdanm | 0:9b334a45a8ff | 228 | if (DMAy_Channelx == DMA2_Channel5) |
| bogdanm | 0:9b334a45a8ff | 229 | { |
| bogdanm | 0:9b334a45a8ff | 230 | /* Reset interrupt pending bits for DMA2 Channel5 */ |
| bogdanm | 0:9b334a45a8ff | 231 | DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; |
| bogdanm | 0:9b334a45a8ff | 232 | } |
| bogdanm | 0:9b334a45a8ff | 233 | } |
| bogdanm | 0:9b334a45a8ff | 234 | } |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | /** |
| bogdanm | 0:9b334a45a8ff | 237 | * @brief Initializes the DMAy Channelx according to the specified parameters |
| bogdanm | 0:9b334a45a8ff | 238 | * in the DMA_InitStruct. |
| bogdanm | 0:9b334a45a8ff | 239 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 240 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 241 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains |
| bogdanm | 0:9b334a45a8ff | 242 | * the configuration information for the specified DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 243 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 244 | */ |
| bogdanm | 0:9b334a45a8ff | 245 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) |
| bogdanm | 0:9b334a45a8ff | 246 | { |
| bogdanm | 0:9b334a45a8ff | 247 | uint32_t tmpreg = 0; |
| bogdanm | 0:9b334a45a8ff | 248 | |
| bogdanm | 0:9b334a45a8ff | 249 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 250 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 251 | assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); |
| bogdanm | 0:9b334a45a8ff | 252 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); |
| bogdanm | 0:9b334a45a8ff | 253 | assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); |
| bogdanm | 0:9b334a45a8ff | 254 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); |
| bogdanm | 0:9b334a45a8ff | 255 | assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); |
| bogdanm | 0:9b334a45a8ff | 256 | assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); |
| bogdanm | 0:9b334a45a8ff | 257 | assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); |
| bogdanm | 0:9b334a45a8ff | 258 | assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); |
| bogdanm | 0:9b334a45a8ff | 259 | |
| bogdanm | 0:9b334a45a8ff | 260 | /*--------------------------- DMAy Channelx CCR Configuration ----------------*/ |
| bogdanm | 0:9b334a45a8ff | 261 | /* Get the DMAy_Channelx CCR value */ |
| bogdanm | 0:9b334a45a8ff | 262 | tmpreg = DMAy_Channelx->CCR; |
| bogdanm | 0:9b334a45a8ff | 263 | |
| bogdanm | 0:9b334a45a8ff | 264 | /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
| bogdanm | 0:9b334a45a8ff | 265 | tmpreg &= CCR_CLEAR_MASK; |
| bogdanm | 0:9b334a45a8ff | 266 | |
| bogdanm | 0:9b334a45a8ff | 267 | /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ |
| bogdanm | 0:9b334a45a8ff | 268 | /* Set DIR bit according to DMA_DIR value */ |
| bogdanm | 0:9b334a45a8ff | 269 | /* Set CIRC bit according to DMA_Mode value */ |
| bogdanm | 0:9b334a45a8ff | 270 | /* Set PINC bit according to DMA_PeripheralInc value */ |
| bogdanm | 0:9b334a45a8ff | 271 | /* Set MINC bit according to DMA_MemoryInc value */ |
| bogdanm | 0:9b334a45a8ff | 272 | /* Set PSIZE bits according to DMA_PeripheralDataSize value */ |
| bogdanm | 0:9b334a45a8ff | 273 | /* Set MSIZE bits according to DMA_MemoryDataSize value */ |
| bogdanm | 0:9b334a45a8ff | 274 | /* Set PL bits according to DMA_Priority value */ |
| bogdanm | 0:9b334a45a8ff | 275 | /* Set the MEM2MEM bit according to DMA_M2M value */ |
| bogdanm | 0:9b334a45a8ff | 276 | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | |
| bogdanm | 0:9b334a45a8ff | 277 | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | |
| bogdanm | 0:9b334a45a8ff | 278 | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | |
| bogdanm | 0:9b334a45a8ff | 279 | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; |
| bogdanm | 0:9b334a45a8ff | 280 | |
| bogdanm | 0:9b334a45a8ff | 281 | /* Write to DMAy Channelx CCR */ |
| bogdanm | 0:9b334a45a8ff | 282 | DMAy_Channelx->CCR = tmpreg; |
| bogdanm | 0:9b334a45a8ff | 283 | |
| bogdanm | 0:9b334a45a8ff | 284 | /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ |
| bogdanm | 0:9b334a45a8ff | 285 | /* Write to DMAy Channelx CNDTR */ |
| bogdanm | 0:9b334a45a8ff | 286 | DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; |
| bogdanm | 0:9b334a45a8ff | 287 | |
| bogdanm | 0:9b334a45a8ff | 288 | /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ |
| bogdanm | 0:9b334a45a8ff | 289 | /* Write to DMAy Channelx CPAR */ |
| bogdanm | 0:9b334a45a8ff | 290 | DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ |
| bogdanm | 0:9b334a45a8ff | 293 | /* Write to DMAy Channelx CMAR */ |
| bogdanm | 0:9b334a45a8ff | 294 | DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; |
| bogdanm | 0:9b334a45a8ff | 295 | } |
| bogdanm | 0:9b334a45a8ff | 296 | |
| bogdanm | 0:9b334a45a8ff | 297 | /** |
| bogdanm | 0:9b334a45a8ff | 298 | * @brief Fills each DMA_InitStruct member with its default value. |
| bogdanm | 0:9b334a45a8ff | 299 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will |
| bogdanm | 0:9b334a45a8ff | 300 | * be initialized. |
| bogdanm | 0:9b334a45a8ff | 301 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 302 | */ |
| bogdanm | 0:9b334a45a8ff | 303 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) |
| bogdanm | 0:9b334a45a8ff | 304 | { |
| bogdanm | 0:9b334a45a8ff | 305 | /*-------------- Reset DMA init structure parameters values ------------------*/ |
| bogdanm | 0:9b334a45a8ff | 306 | /* Initialize the DMA_PeripheralBaseAddr member */ |
| bogdanm | 0:9b334a45a8ff | 307 | DMA_InitStruct->DMA_PeripheralBaseAddr = 0; |
| bogdanm | 0:9b334a45a8ff | 308 | /* Initialize the DMA_MemoryBaseAddr member */ |
| bogdanm | 0:9b334a45a8ff | 309 | DMA_InitStruct->DMA_MemoryBaseAddr = 0; |
| bogdanm | 0:9b334a45a8ff | 310 | /* Initialize the DMA_DIR member */ |
| bogdanm | 0:9b334a45a8ff | 311 | DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; |
| bogdanm | 0:9b334a45a8ff | 312 | /* Initialize the DMA_BufferSize member */ |
| bogdanm | 0:9b334a45a8ff | 313 | DMA_InitStruct->DMA_BufferSize = 0; |
| bogdanm | 0:9b334a45a8ff | 314 | /* Initialize the DMA_PeripheralInc member */ |
| bogdanm | 0:9b334a45a8ff | 315 | DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; |
| bogdanm | 0:9b334a45a8ff | 316 | /* Initialize the DMA_MemoryInc member */ |
| bogdanm | 0:9b334a45a8ff | 317 | DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; |
| bogdanm | 0:9b334a45a8ff | 318 | /* Initialize the DMA_PeripheralDataSize member */ |
| bogdanm | 0:9b334a45a8ff | 319 | DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; |
| bogdanm | 0:9b334a45a8ff | 320 | /* Initialize the DMA_MemoryDataSize member */ |
| bogdanm | 0:9b334a45a8ff | 321 | DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; |
| bogdanm | 0:9b334a45a8ff | 322 | /* Initialize the DMA_Mode member */ |
| bogdanm | 0:9b334a45a8ff | 323 | DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; |
| bogdanm | 0:9b334a45a8ff | 324 | /* Initialize the DMA_Priority member */ |
| bogdanm | 0:9b334a45a8ff | 325 | DMA_InitStruct->DMA_Priority = DMA_Priority_Low; |
| bogdanm | 0:9b334a45a8ff | 326 | /* Initialize the DMA_M2M member */ |
| bogdanm | 0:9b334a45a8ff | 327 | DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; |
| bogdanm | 0:9b334a45a8ff | 328 | } |
| bogdanm | 0:9b334a45a8ff | 329 | |
| bogdanm | 0:9b334a45a8ff | 330 | /** |
| bogdanm | 0:9b334a45a8ff | 331 | * @brief Enables or disables the specified DMAy Channelx. |
| bogdanm | 0:9b334a45a8ff | 332 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 333 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 334 | * @param NewState: new state of the DMAy Channelx. |
| bogdanm | 0:9b334a45a8ff | 335 | * This parameter can be: ENABLE or DISABLE. |
| bogdanm | 0:9b334a45a8ff | 336 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 337 | */ |
| bogdanm | 0:9b334a45a8ff | 338 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) |
| bogdanm | 0:9b334a45a8ff | 339 | { |
| bogdanm | 0:9b334a45a8ff | 340 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 341 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 342 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| bogdanm | 0:9b334a45a8ff | 343 | |
| bogdanm | 0:9b334a45a8ff | 344 | if (NewState != DISABLE) |
| bogdanm | 0:9b334a45a8ff | 345 | { |
| bogdanm | 0:9b334a45a8ff | 346 | /* Enable the selected DMAy Channelx */ |
| bogdanm | 0:9b334a45a8ff | 347 | DMAy_Channelx->CCR |= DMA_CCR_EN; |
| bogdanm | 0:9b334a45a8ff | 348 | } |
| bogdanm | 0:9b334a45a8ff | 349 | else |
| bogdanm | 0:9b334a45a8ff | 350 | { |
| bogdanm | 0:9b334a45a8ff | 351 | /* Disable the selected DMAy Channelx */ |
| bogdanm | 0:9b334a45a8ff | 352 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); |
| bogdanm | 0:9b334a45a8ff | 353 | } |
| bogdanm | 0:9b334a45a8ff | 354 | } |
| bogdanm | 0:9b334a45a8ff | 355 | |
| bogdanm | 0:9b334a45a8ff | 356 | /** |
| bogdanm | 0:9b334a45a8ff | 357 | * @} |
| bogdanm | 0:9b334a45a8ff | 358 | */ |
| bogdanm | 0:9b334a45a8ff | 359 | |
| bogdanm | 0:9b334a45a8ff | 360 | /** @defgroup DMA_Group2 Data Counter functions |
| bogdanm | 0:9b334a45a8ff | 361 | * @brief Data Counter functions |
| bogdanm | 0:9b334a45a8ff | 362 | * |
| bogdanm | 0:9b334a45a8ff | 363 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 364 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 365 | ##### Data Counter functions ##### |
| bogdanm | 0:9b334a45a8ff | 366 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 367 | [..] This subsection provides function allowing to configure and read the buffer |
| bogdanm | 0:9b334a45a8ff | 368 | size (number of data to be transferred).The DMA data counter can be written |
| bogdanm | 0:9b334a45a8ff | 369 | only when the DMA channel is disabled (ie. after transfer complete event). |
| bogdanm | 0:9b334a45a8ff | 370 | [..] The following function can be used to write the Channel data counter value: |
| bogdanm | 0:9b334a45a8ff | 371 | (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber). |
| bogdanm | 0:9b334a45a8ff | 372 | [..] |
| bogdanm | 0:9b334a45a8ff | 373 | (@) It is advised to use this function rather than DMA_Init() in situations |
| bogdanm | 0:9b334a45a8ff | 374 | where only the Data buffer needs to be reloaded. |
| bogdanm | 0:9b334a45a8ff | 375 | [..] The DMA data counter can be read to indicate the number of remaining transfers |
| bogdanm | 0:9b334a45a8ff | 376 | for the relative DMA channel. This counter is decremented at the end of each |
| bogdanm | 0:9b334a45a8ff | 377 | data transfer and when the transfer is complete: |
| bogdanm | 0:9b334a45a8ff | 378 | (+) If Normal mode is selected: the counter is set to 0. |
| bogdanm | 0:9b334a45a8ff | 379 | (+) If Circular mode is selected: the counter is reloaded with the initial |
| bogdanm | 0:9b334a45a8ff | 380 | value(configured before enabling the DMA channel). |
| bogdanm | 0:9b334a45a8ff | 381 | [..] The following function can be used to read the Channel data counter value: |
| bogdanm | 0:9b334a45a8ff | 382 | (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). |
| bogdanm | 0:9b334a45a8ff | 383 | |
| bogdanm | 0:9b334a45a8ff | 384 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 385 | * @{ |
| bogdanm | 0:9b334a45a8ff | 386 | */ |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | /** |
| bogdanm | 0:9b334a45a8ff | 389 | * @brief Sets the number of data units in the current DMAy Channelx transfer. |
| bogdanm | 0:9b334a45a8ff | 390 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 391 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 392 | * @param DataNumber: The number of data units in the current DMAy Channelx |
| bogdanm | 0:9b334a45a8ff | 393 | * transfer. |
| bogdanm | 0:9b334a45a8ff | 394 | * @note This function can only be used when the DMAy_Channelx is disabled. |
| bogdanm | 0:9b334a45a8ff | 395 | * @retval None. |
| bogdanm | 0:9b334a45a8ff | 396 | */ |
| bogdanm | 0:9b334a45a8ff | 397 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) |
| bogdanm | 0:9b334a45a8ff | 398 | { |
| bogdanm | 0:9b334a45a8ff | 399 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 400 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 401 | |
| bogdanm | 0:9b334a45a8ff | 402 | /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ |
| bogdanm | 0:9b334a45a8ff | 403 | /* Write to DMAy Channelx CNDTR */ |
| bogdanm | 0:9b334a45a8ff | 404 | DMAy_Channelx->CNDTR = DataNumber; |
| bogdanm | 0:9b334a45a8ff | 405 | } |
| bogdanm | 0:9b334a45a8ff | 406 | |
| bogdanm | 0:9b334a45a8ff | 407 | /** |
| bogdanm | 0:9b334a45a8ff | 408 | * @brief Returns the number of remaining data units in the current |
| bogdanm | 0:9b334a45a8ff | 409 | * DMAy Channelx transfer. |
| bogdanm | 0:9b334a45a8ff | 410 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 411 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 412 | * @retval The number of remaining data units in the current DMAy Channelx |
| bogdanm | 0:9b334a45a8ff | 413 | * transfer. |
| bogdanm | 0:9b334a45a8ff | 414 | */ |
| bogdanm | 0:9b334a45a8ff | 415 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) |
| bogdanm | 0:9b334a45a8ff | 416 | { |
| bogdanm | 0:9b334a45a8ff | 417 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 418 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 419 | /* Return the number of remaining data units for DMAy Channelx */ |
| bogdanm | 0:9b334a45a8ff | 420 | return ((uint16_t)(DMAy_Channelx->CNDTR)); |
| bogdanm | 0:9b334a45a8ff | 421 | } |
| bogdanm | 0:9b334a45a8ff | 422 | |
| bogdanm | 0:9b334a45a8ff | 423 | /** |
| bogdanm | 0:9b334a45a8ff | 424 | * @} |
| bogdanm | 0:9b334a45a8ff | 425 | */ |
| bogdanm | 0:9b334a45a8ff | 426 | |
| bogdanm | 0:9b334a45a8ff | 427 | /** @defgroup DMA_Group3 Interrupts and flags management functions |
| bogdanm | 0:9b334a45a8ff | 428 | * @brief Interrupts and flags management functions |
| bogdanm | 0:9b334a45a8ff | 429 | * |
| bogdanm | 0:9b334a45a8ff | 430 | @verbatim |
| bogdanm | 0:9b334a45a8ff | 431 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 432 | ##### Interrupts and flags management functions ##### |
| bogdanm | 0:9b334a45a8ff | 433 | =============================================================================== |
| bogdanm | 0:9b334a45a8ff | 434 | [..] This subsection provides functions allowing to configure the DMA Interrupt |
| bogdanm | 0:9b334a45a8ff | 435 | sources and check or clear the flags or pending bits status. |
| bogdanm | 0:9b334a45a8ff | 436 | The user should identify which mode will be used in his application to manage |
| bogdanm | 0:9b334a45a8ff | 437 | the DMA controller events: Polling mode or Interrupt mode. |
| bogdanm | 0:9b334a45a8ff | 438 | |
| bogdanm | 0:9b334a45a8ff | 439 | *** Polling Mode *** |
| bogdanm | 0:9b334a45a8ff | 440 | ==================== |
| bogdanm | 0:9b334a45a8ff | 441 | [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller |
| bogdanm | 0:9b334a45a8ff | 442 | number, x : DMA channel number): |
| bogdanm | 0:9b334a45a8ff | 443 | (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. |
| bogdanm | 0:9b334a45a8ff | 444 | (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. |
| bogdanm | 0:9b334a45a8ff | 445 | (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. |
| bogdanm | 0:9b334a45a8ff | 446 | (#) DMAy_FLAG_GLx : to indicate that at least one of the events described |
| bogdanm | 0:9b334a45a8ff | 447 | above occurred. |
| bogdanm | 0:9b334a45a8ff | 448 | [..] |
| bogdanm | 0:9b334a45a8ff | 449 | (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the |
| bogdanm | 0:9b334a45a8ff | 450 | same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
| bogdanm | 0:9b334a45a8ff | 451 | [..] In this Mode it is advised to use the following functions: |
| bogdanm | 0:9b334a45a8ff | 452 | (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); |
| bogdanm | 0:9b334a45a8ff | 453 | (+) void DMA_ClearFlag(uint32_t DMA_FLAG); |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | *** Interrupt Mode *** |
| bogdanm | 0:9b334a45a8ff | 456 | ====================== |
| bogdanm | 0:9b334a45a8ff | 457 | [..] Each DMA channel can be managed through 4 Interrupts: |
| bogdanm | 0:9b334a45a8ff | 458 | (+) Interrupt Source |
| bogdanm | 0:9b334a45a8ff | 459 | (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete |
| bogdanm | 0:9b334a45a8ff | 460 | event. |
| bogdanm | 0:9b334a45a8ff | 461 | (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete |
| bogdanm | 0:9b334a45a8ff | 462 | event. |
| bogdanm | 0:9b334a45a8ff | 463 | (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event. |
| bogdanm | 0:9b334a45a8ff | 464 | (##) DMA_IT_GL: to indicate that at least one of the interrupts described |
| bogdanm | 0:9b334a45a8ff | 465 | above occurred. |
| bogdanm | 0:9b334a45a8ff | 466 | -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of |
| bogdanm | 0:9b334a45a8ff | 467 | the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). |
| bogdanm | 0:9b334a45a8ff | 468 | [..] In this Mode it is advised to use the following functions: |
| bogdanm | 0:9b334a45a8ff | 469 | (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 470 | (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); |
| bogdanm | 0:9b334a45a8ff | 471 | (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); |
| bogdanm | 0:9b334a45a8ff | 472 | |
| bogdanm | 0:9b334a45a8ff | 473 | @endverbatim |
| bogdanm | 0:9b334a45a8ff | 474 | * @{ |
| bogdanm | 0:9b334a45a8ff | 475 | */ |
| bogdanm | 0:9b334a45a8ff | 476 | |
| bogdanm | 0:9b334a45a8ff | 477 | /** |
| bogdanm | 0:9b334a45a8ff | 478 | * @brief Enables or disables the specified DMAy Channelx interrupts. |
| bogdanm | 0:9b334a45a8ff | 479 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and |
| bogdanm | 0:9b334a45a8ff | 480 | * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
| bogdanm | 0:9b334a45a8ff | 481 | * @param DMA_IT: specifies the DMA interrupts sources to be enabled |
| bogdanm | 0:9b334a45a8ff | 482 | * or disabled. |
| bogdanm | 0:9b334a45a8ff | 483 | * This parameter can be any combination of the following values: |
| bogdanm | 0:9b334a45a8ff | 484 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
| bogdanm | 0:9b334a45a8ff | 485 | * @arg DMA_IT_HT: Half transfer interrupt mask |
| bogdanm | 0:9b334a45a8ff | 486 | * @arg DMA_IT_TE: Transfer error interrupt mask |
| bogdanm | 0:9b334a45a8ff | 487 | * @param NewState: new state of the specified DMA interrupts. |
| bogdanm | 0:9b334a45a8ff | 488 | * This parameter can be: ENABLE or DISABLE. |
| bogdanm | 0:9b334a45a8ff | 489 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 490 | */ |
| bogdanm | 0:9b334a45a8ff | 491 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) |
| bogdanm | 0:9b334a45a8ff | 492 | { |
| bogdanm | 0:9b334a45a8ff | 493 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 494 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
| bogdanm | 0:9b334a45a8ff | 495 | assert_param(IS_DMA_CONFIG_IT(DMA_IT)); |
| bogdanm | 0:9b334a45a8ff | 496 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
| bogdanm | 0:9b334a45a8ff | 497 | |
| bogdanm | 0:9b334a45a8ff | 498 | if (NewState != DISABLE) |
| bogdanm | 0:9b334a45a8ff | 499 | { |
| bogdanm | 0:9b334a45a8ff | 500 | /* Enable the selected DMA interrupts */ |
| bogdanm | 0:9b334a45a8ff | 501 | DMAy_Channelx->CCR |= DMA_IT; |
| bogdanm | 0:9b334a45a8ff | 502 | } |
| bogdanm | 0:9b334a45a8ff | 503 | else |
| bogdanm | 0:9b334a45a8ff | 504 | { |
| bogdanm | 0:9b334a45a8ff | 505 | /* Disable the selected DMA interrupts */ |
| bogdanm | 0:9b334a45a8ff | 506 | DMAy_Channelx->CCR &= ~DMA_IT; |
| bogdanm | 0:9b334a45a8ff | 507 | } |
| bogdanm | 0:9b334a45a8ff | 508 | } |
| bogdanm | 0:9b334a45a8ff | 509 | |
| bogdanm | 0:9b334a45a8ff | 510 | /** |
| bogdanm | 0:9b334a45a8ff | 511 | * @brief Checks whether the specified DMAy Channelx flag is set or not. |
| bogdanm | 0:9b334a45a8ff | 512 | * @param DMAy_FLAG: specifies the flag to check. |
| bogdanm | 0:9b334a45a8ff | 513 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 514 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
| bogdanm | 0:9b334a45a8ff | 515 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 516 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 517 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 518 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
| bogdanm | 0:9b334a45a8ff | 519 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 520 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 521 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 522 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
| bogdanm | 0:9b334a45a8ff | 523 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 524 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 525 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 526 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
| bogdanm | 0:9b334a45a8ff | 527 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 528 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 529 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 530 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
| bogdanm | 0:9b334a45a8ff | 531 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 532 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 533 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 534 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
| bogdanm | 0:9b334a45a8ff | 535 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 536 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 537 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 538 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
| bogdanm | 0:9b334a45a8ff | 539 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 540 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 541 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 542 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
| bogdanm | 0:9b334a45a8ff | 543 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 544 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 545 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 546 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
| bogdanm | 0:9b334a45a8ff | 547 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 548 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 549 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 550 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
| bogdanm | 0:9b334a45a8ff | 551 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 552 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 553 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 554 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
| bogdanm | 0:9b334a45a8ff | 555 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 556 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 557 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 558 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
| bogdanm | 0:9b334a45a8ff | 559 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 560 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 561 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 562 | * |
| bogdanm | 0:9b334a45a8ff | 563 | * @note |
| bogdanm | 0:9b334a45a8ff | 564 | * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags |
| bogdanm | 0:9b334a45a8ff | 565 | * relative to the same channel is set (Transfer Complete, Half-transfer |
| bogdanm | 0:9b334a45a8ff | 566 | * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or |
| bogdanm | 0:9b334a45a8ff | 567 | * DMAy_FLAG_TEx). |
| bogdanm | 0:9b334a45a8ff | 568 | * |
| bogdanm | 0:9b334a45a8ff | 569 | * @retval The new state of DMAy_FLAG (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 570 | */ |
| bogdanm | 0:9b334a45a8ff | 571 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) |
| bogdanm | 0:9b334a45a8ff | 572 | { |
| bogdanm | 0:9b334a45a8ff | 573 | FlagStatus bitstatus = RESET; |
| bogdanm | 0:9b334a45a8ff | 574 | uint32_t tmpreg = 0; |
| bogdanm | 0:9b334a45a8ff | 575 | |
| bogdanm | 0:9b334a45a8ff | 576 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 577 | assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); |
| bogdanm | 0:9b334a45a8ff | 578 | |
| bogdanm | 0:9b334a45a8ff | 579 | /* Calculate the used DMAy */ |
| bogdanm | 0:9b334a45a8ff | 580 | if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 581 | { |
| bogdanm | 0:9b334a45a8ff | 582 | /* Get DMA2 ISR register value */ |
| bogdanm | 0:9b334a45a8ff | 583 | tmpreg = DMA2->ISR ; |
| bogdanm | 0:9b334a45a8ff | 584 | } |
| bogdanm | 0:9b334a45a8ff | 585 | else |
| bogdanm | 0:9b334a45a8ff | 586 | { |
| bogdanm | 0:9b334a45a8ff | 587 | /* Get DMA1 ISR register value */ |
| bogdanm | 0:9b334a45a8ff | 588 | tmpreg = DMA1->ISR ; |
| bogdanm | 0:9b334a45a8ff | 589 | } |
| bogdanm | 0:9b334a45a8ff | 590 | |
| bogdanm | 0:9b334a45a8ff | 591 | /* Check the status of the specified DMAy flag */ |
| bogdanm | 0:9b334a45a8ff | 592 | if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 593 | { |
| bogdanm | 0:9b334a45a8ff | 594 | /* DMAy_FLAG is set */ |
| bogdanm | 0:9b334a45a8ff | 595 | bitstatus = SET; |
| bogdanm | 0:9b334a45a8ff | 596 | } |
| bogdanm | 0:9b334a45a8ff | 597 | else |
| bogdanm | 0:9b334a45a8ff | 598 | { |
| bogdanm | 0:9b334a45a8ff | 599 | /* DMAy_FLAG is reset */ |
| bogdanm | 0:9b334a45a8ff | 600 | bitstatus = RESET; |
| bogdanm | 0:9b334a45a8ff | 601 | } |
| bogdanm | 0:9b334a45a8ff | 602 | |
| bogdanm | 0:9b334a45a8ff | 603 | /* Return the DMAy_FLAG status */ |
| bogdanm | 0:9b334a45a8ff | 604 | return bitstatus; |
| bogdanm | 0:9b334a45a8ff | 605 | } |
| bogdanm | 0:9b334a45a8ff | 606 | |
| bogdanm | 0:9b334a45a8ff | 607 | /** |
| bogdanm | 0:9b334a45a8ff | 608 | * @brief Clears the DMAy Channelx's pending flags. |
| bogdanm | 0:9b334a45a8ff | 609 | * @param DMAy_FLAG: specifies the flag to clear. |
| bogdanm | 0:9b334a45a8ff | 610 | * This parameter can be any combination (for the same DMA) of the following values: |
| bogdanm | 0:9b334a45a8ff | 611 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
| bogdanm | 0:9b334a45a8ff | 612 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 613 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 614 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 615 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
| bogdanm | 0:9b334a45a8ff | 616 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 617 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 618 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 619 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
| bogdanm | 0:9b334a45a8ff | 620 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 621 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 622 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 623 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
| bogdanm | 0:9b334a45a8ff | 624 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 625 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 626 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 627 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
| bogdanm | 0:9b334a45a8ff | 628 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 629 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 630 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 631 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
| bogdanm | 0:9b334a45a8ff | 632 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 633 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 634 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 635 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
| bogdanm | 0:9b334a45a8ff | 636 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 637 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 638 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 639 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
| bogdanm | 0:9b334a45a8ff | 640 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 641 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 642 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 643 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
| bogdanm | 0:9b334a45a8ff | 644 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 645 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 646 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 647 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
| bogdanm | 0:9b334a45a8ff | 648 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 649 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 650 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 651 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
| bogdanm | 0:9b334a45a8ff | 652 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 653 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 654 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 655 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
| bogdanm | 0:9b334a45a8ff | 656 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
| bogdanm | 0:9b334a45a8ff | 657 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
| bogdanm | 0:9b334a45a8ff | 658 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
| bogdanm | 0:9b334a45a8ff | 659 | * |
| bogdanm | 0:9b334a45a8ff | 660 | * @note |
| bogdanm | 0:9b334a45a8ff | 661 | * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags |
| bogdanm | 0:9b334a45a8ff | 662 | * relative to the same channel (Transfer Complete, Half-transfer Complete and |
| bogdanm | 0:9b334a45a8ff | 663 | * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
| bogdanm | 0:9b334a45a8ff | 664 | * |
| bogdanm | 0:9b334a45a8ff | 665 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 666 | */ |
| bogdanm | 0:9b334a45a8ff | 667 | void DMA_ClearFlag(uint32_t DMAy_FLAG) |
| bogdanm | 0:9b334a45a8ff | 668 | { |
| bogdanm | 0:9b334a45a8ff | 669 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 670 | assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); |
| bogdanm | 0:9b334a45a8ff | 671 | |
| bogdanm | 0:9b334a45a8ff | 672 | /* Calculate the used DMAy */ |
| bogdanm | 0:9b334a45a8ff | 673 | if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 674 | { |
| bogdanm | 0:9b334a45a8ff | 675 | /* Clear the selected DMAy flags */ |
| bogdanm | 0:9b334a45a8ff | 676 | DMA2->IFCR = DMAy_FLAG; |
| bogdanm | 0:9b334a45a8ff | 677 | } |
| bogdanm | 0:9b334a45a8ff | 678 | else |
| bogdanm | 0:9b334a45a8ff | 679 | { |
| bogdanm | 0:9b334a45a8ff | 680 | /* Clear the selected DMAy flags */ |
| bogdanm | 0:9b334a45a8ff | 681 | DMA1->IFCR = DMAy_FLAG; |
| bogdanm | 0:9b334a45a8ff | 682 | } |
| bogdanm | 0:9b334a45a8ff | 683 | } |
| bogdanm | 0:9b334a45a8ff | 684 | |
| bogdanm | 0:9b334a45a8ff | 685 | /** |
| bogdanm | 0:9b334a45a8ff | 686 | * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. |
| bogdanm | 0:9b334a45a8ff | 687 | * @param DMAy_IT: specifies the DMAy interrupt source to check. |
| bogdanm | 0:9b334a45a8ff | 688 | * This parameter can be one of the following values: |
| bogdanm | 0:9b334a45a8ff | 689 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 690 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 691 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 692 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 693 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 694 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 695 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 696 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 697 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 698 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 699 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 700 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 701 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 702 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 703 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 704 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 705 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 706 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 707 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 708 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 709 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 710 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 711 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 712 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 713 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 714 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 715 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 716 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 717 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 718 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 719 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 720 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 721 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 722 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 723 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 724 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 725 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 726 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 727 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 728 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 729 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 730 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 731 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 732 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 733 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 734 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 735 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 736 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 737 | * |
| bogdanm | 0:9b334a45a8ff | 738 | * @note |
| bogdanm | 0:9b334a45a8ff | 739 | * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other |
| bogdanm | 0:9b334a45a8ff | 740 | * interrupts relative to the same channel is set (Transfer Complete, |
| bogdanm | 0:9b334a45a8ff | 741 | * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, |
| bogdanm | 0:9b334a45a8ff | 742 | * DMAy_IT_HTx or DMAy_IT_TEx). |
| bogdanm | 0:9b334a45a8ff | 743 | * |
| bogdanm | 0:9b334a45a8ff | 744 | * @retval The new state of DMAy_IT (SET or RESET). |
| bogdanm | 0:9b334a45a8ff | 745 | */ |
| bogdanm | 0:9b334a45a8ff | 746 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT) |
| bogdanm | 0:9b334a45a8ff | 747 | { |
| bogdanm | 0:9b334a45a8ff | 748 | ITStatus bitstatus = RESET; |
| bogdanm | 0:9b334a45a8ff | 749 | uint32_t tmpreg = 0; |
| bogdanm | 0:9b334a45a8ff | 750 | |
| bogdanm | 0:9b334a45a8ff | 751 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 752 | assert_param(IS_DMA_GET_IT(DMAy_IT)); |
| bogdanm | 0:9b334a45a8ff | 753 | |
| bogdanm | 0:9b334a45a8ff | 754 | /* Calculate the used DMA */ |
| bogdanm | 0:9b334a45a8ff | 755 | if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 756 | { |
| bogdanm | 0:9b334a45a8ff | 757 | /* Get DMA2 ISR register value */ |
| bogdanm | 0:9b334a45a8ff | 758 | tmpreg = DMA2->ISR; |
| bogdanm | 0:9b334a45a8ff | 759 | } |
| bogdanm | 0:9b334a45a8ff | 760 | else |
| bogdanm | 0:9b334a45a8ff | 761 | { |
| bogdanm | 0:9b334a45a8ff | 762 | /* Get DMA1 ISR register value */ |
| bogdanm | 0:9b334a45a8ff | 763 | tmpreg = DMA1->ISR; |
| bogdanm | 0:9b334a45a8ff | 764 | } |
| bogdanm | 0:9b334a45a8ff | 765 | |
| bogdanm | 0:9b334a45a8ff | 766 | /* Check the status of the specified DMAy interrupt */ |
| bogdanm | 0:9b334a45a8ff | 767 | if ((tmpreg & DMAy_IT) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 768 | { |
| bogdanm | 0:9b334a45a8ff | 769 | /* DMAy_IT is set */ |
| bogdanm | 0:9b334a45a8ff | 770 | bitstatus = SET; |
| bogdanm | 0:9b334a45a8ff | 771 | } |
| bogdanm | 0:9b334a45a8ff | 772 | else |
| bogdanm | 0:9b334a45a8ff | 773 | { |
| bogdanm | 0:9b334a45a8ff | 774 | /* DMAy_IT is reset */ |
| bogdanm | 0:9b334a45a8ff | 775 | bitstatus = RESET; |
| bogdanm | 0:9b334a45a8ff | 776 | } |
| bogdanm | 0:9b334a45a8ff | 777 | /* Return the DMAy_IT status */ |
| bogdanm | 0:9b334a45a8ff | 778 | return bitstatus; |
| bogdanm | 0:9b334a45a8ff | 779 | } |
| bogdanm | 0:9b334a45a8ff | 780 | |
| bogdanm | 0:9b334a45a8ff | 781 | /** |
| bogdanm | 0:9b334a45a8ff | 782 | * @brief Clears the DMAy Channelx's interrupt pending bits. |
| bogdanm | 0:9b334a45a8ff | 783 | * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. |
| bogdanm | 0:9b334a45a8ff | 784 | * This parameter can be any combination (for the same DMA) of the following values: |
| bogdanm | 0:9b334a45a8ff | 785 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 786 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 787 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 788 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 789 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 790 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 791 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 792 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 793 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 794 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 795 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 796 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 797 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 798 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 799 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 800 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 801 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 802 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 803 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 804 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 805 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 806 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 807 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 808 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 809 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 810 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 811 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 812 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 813 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 814 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 815 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 816 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 817 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 818 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 819 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 820 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 821 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 822 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 823 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 824 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 825 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 826 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 827 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 828 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 829 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
| bogdanm | 0:9b334a45a8ff | 830 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
| bogdanm | 0:9b334a45a8ff | 831 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
| bogdanm | 0:9b334a45a8ff | 832 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
| bogdanm | 0:9b334a45a8ff | 833 | * |
| bogdanm | 0:9b334a45a8ff | 834 | * @note |
| bogdanm | 0:9b334a45a8ff | 835 | * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other |
| bogdanm | 0:9b334a45a8ff | 836 | * interrupts relative to the same channel (Transfer Complete, Half-transfer |
| bogdanm | 0:9b334a45a8ff | 837 | * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and |
| bogdanm | 0:9b334a45a8ff | 838 | * DMAy_IT_TEx). |
| bogdanm | 0:9b334a45a8ff | 839 | * |
| bogdanm | 0:9b334a45a8ff | 840 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 841 | */ |
| bogdanm | 0:9b334a45a8ff | 842 | void DMA_ClearITPendingBit(uint32_t DMAy_IT) |
| bogdanm | 0:9b334a45a8ff | 843 | { |
| bogdanm | 0:9b334a45a8ff | 844 | /* Check the parameters */ |
| bogdanm | 0:9b334a45a8ff | 845 | assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); |
| bogdanm | 0:9b334a45a8ff | 846 | |
| bogdanm | 0:9b334a45a8ff | 847 | /* Calculate the used DMAy */ |
| bogdanm | 0:9b334a45a8ff | 848 | if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) |
| bogdanm | 0:9b334a45a8ff | 849 | { |
| bogdanm | 0:9b334a45a8ff | 850 | /* Clear the selected DMAy interrupt pending bits */ |
| bogdanm | 0:9b334a45a8ff | 851 | DMA2->IFCR = DMAy_IT; |
| bogdanm | 0:9b334a45a8ff | 852 | } |
| bogdanm | 0:9b334a45a8ff | 853 | else |
| bogdanm | 0:9b334a45a8ff | 854 | { |
| bogdanm | 0:9b334a45a8ff | 855 | /* Clear the selected DMAy interrupt pending bits */ |
| bogdanm | 0:9b334a45a8ff | 856 | DMA1->IFCR = DMAy_IT; |
| bogdanm | 0:9b334a45a8ff | 857 | } |
| bogdanm | 0:9b334a45a8ff | 858 | } |
| bogdanm | 0:9b334a45a8ff | 859 | |
| bogdanm | 0:9b334a45a8ff | 860 | /** |
| bogdanm | 0:9b334a45a8ff | 861 | * @} |
| bogdanm | 0:9b334a45a8ff | 862 | */ |
| bogdanm | 0:9b334a45a8ff | 863 | |
| bogdanm | 0:9b334a45a8ff | 864 | /** |
| bogdanm | 0:9b334a45a8ff | 865 | * @} |
| bogdanm | 0:9b334a45a8ff | 866 | */ |
| bogdanm | 0:9b334a45a8ff | 867 | |
| bogdanm | 0:9b334a45a8ff | 868 | /** |
| bogdanm | 0:9b334a45a8ff | 869 | * @} |
| bogdanm | 0:9b334a45a8ff | 870 | */ |
| bogdanm | 0:9b334a45a8ff | 871 | |
| bogdanm | 0:9b334a45a8ff | 872 | /** |
| bogdanm | 0:9b334a45a8ff | 873 | * @} |
| bogdanm | 0:9b334a45a8ff | 874 | */ |
| bogdanm | 0:9b334a45a8ff | 875 | |
| bogdanm | 0:9b334a45a8ff | 876 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |