Toyomasa Watarai / mbed-dev-lpcx1769

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Dependents:   LPCXpresso1769_blinky

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c@148:341accce5a58, 2016-09-19 (annotated)

Committer:
MACRUM
Date:
Mon Sep 19 14:20:24 2016 +0000
Revision:
148:341accce5a58
Parent:
144:ef7eb2e8f9f7 
Modified pin names and clock config for LPCXpresso1769

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l1xx_hal_adc_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 04-March-2016
<> 144:ef7eb2e8f9f7 7 * @brief This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 8 * functionalities of the Analog to Digital Convertor (ADC)
<> 144:ef7eb2e8f9f7 9 * peripheral:
<> 144:ef7eb2e8f9f7 10 * + Operation functions
<> 144:ef7eb2e8f9f7 11 * ++ Start, stop, get result of conversions of injected
<> 144:ef7eb2e8f9f7 12 * group, using 2 possible modes: polling, interruption.
<> 144:ef7eb2e8f9f7 13 * ++ Calibration (ADC automatic self-calibration)
<> 144:ef7eb2e8f9f7 14 * + Control functions
<> 144:ef7eb2e8f9f7 15 * ++ Channels configuration on injected group
<> 144:ef7eb2e8f9f7 16 * Other functions (generic functions) are available in file
<> 144:ef7eb2e8f9f7 17 * "stm32l1xx_hal_adc.c".
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 @verbatim
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 (@) Sections "ADC peripheral features" and "How to use this driver" are
<> 144:ef7eb2e8f9f7 22 available in file of generic functions "stm32l1xx_hal_adc.c".
<> 144:ef7eb2e8f9f7 23 [..]
<> 144:ef7eb2e8f9f7 24 @endverbatim
<> 144:ef7eb2e8f9f7 25 ******************************************************************************
<> 144:ef7eb2e8f9f7 26 * @attention
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 31 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 32 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 33 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 35 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 36 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 38 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 39 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 51 *
<> 144:ef7eb2e8f9f7 52 ******************************************************************************
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 #include "stm32l1xx_hal.h"
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup STM32L1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @defgroup ADCEx ADCEx
<> 144:ef7eb2e8f9f7 63 * @brief ADC Extension HAL module driver
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #ifdef HAL_ADC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 70 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 71 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
<> 144:ef7eb2e8f9f7 72 * @{
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* ADC conversion cycles (unit: ADC clock cycles) */
<> 144:ef7eb2e8f9f7 76 /* (selected sampling time + conversion time of 12 ADC clock cycles, with */
<> 144:ef7eb2e8f9f7 77 /* resolution 12 bits) */
<> 144:ef7eb2e8f9f7 78 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ((uint32_t) 16)
<> 144:ef7eb2e8f9f7 79 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ((uint32_t) 21)
<> 144:ef7eb2e8f9f7 80 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ((uint32_t) 28)
<> 144:ef7eb2e8f9f7 81 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ((uint32_t) 36)
<> 144:ef7eb2e8f9f7 82 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ((uint32_t) 60)
<> 144:ef7eb2e8f9f7 83 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES ((uint32_t)108)
<> 144:ef7eb2e8f9f7 84 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204)
<> 144:ef7eb2e8f9f7 85 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396)
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* Delay for temperature sensor stabilization time. */
<> 144:ef7eb2e8f9f7 88 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
<> 144:ef7eb2e8f9f7 89 /* Unit: us */
<> 144:ef7eb2e8f9f7 90 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @}
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 97 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup ADCEx_Exported_Functions_Group1 ADC Extended IO operation functions
<> 144:ef7eb2e8f9f7 106 * @brief ADC Extended Input and Output operation functions
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 @verbatim
<> 144:ef7eb2e8f9f7 109 ===============================================================================
<> 144:ef7eb2e8f9f7 110 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 111 ===============================================================================
<> 144:ef7eb2e8f9f7 112 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 113 (+) Start conversion of injected group.
<> 144:ef7eb2e8f9f7 114 (+) Stop conversion of injected group.
<> 144:ef7eb2e8f9f7 115 (+) Poll for conversion complete on injected group.
<> 144:ef7eb2e8f9f7 116 (+) Get result of injected channel conversion.
<> 144:ef7eb2e8f9f7 117 (+) Start conversion of injected group and enable interruptions.
<> 144:ef7eb2e8f9f7 118 (+) Stop conversion of injected group and disable interruptions.
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 @endverbatim
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief Enables ADC, starts conversion of injected group.
<> 144:ef7eb2e8f9f7 126 * Interruptions enabled in this function: None.
<> 144:ef7eb2e8f9f7 127 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 128 * @retval HAL status
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 131 {
<> 144:ef7eb2e8f9f7 132 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /* Check the parameters */
<> 144:ef7eb2e8f9f7 135 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Process locked */
<> 144:ef7eb2e8f9f7 138 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 141 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 144 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Set ADC state */
<> 144:ef7eb2e8f9f7 147 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 148 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 149 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 150 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 151 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 154 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 155 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 156 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 157 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 160 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Process unlocked */
<> 144:ef7eb2e8f9f7 164 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 165 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 166 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 169 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 170 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /* Enable conversion of injected group. */
<> 144:ef7eb2e8f9f7 173 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 174 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 175 /* trigger event. */
<> 144:ef7eb2e8f9f7 176 /* If automatic injected conversion is enabled, conversion will start */
<> 144:ef7eb2e8f9f7 177 /* after next regular group conversion. */
<> 144:ef7eb2e8f9f7 178 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 179 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 /* Enable ADC software conversion for injected channels */
<> 144:ef7eb2e8f9f7 182 SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Return function status */
<> 144:ef7eb2e8f9f7 187 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Stop conversion of injected channels. Disable ADC peripheral if
<> 144:ef7eb2e8f9f7 192 * no regular conversion is on going.
<> 144:ef7eb2e8f9f7 193 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 194 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 195 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 196 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 197 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 198 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 199 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 200 * @retval None
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Check the parameters */
<> 144:ef7eb2e8f9f7 207 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Process locked */
<> 144:ef7eb2e8f9f7 210 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 213 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 214 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 215 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 216 /* are common) */
<> 144:ef7eb2e8f9f7 217 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 218 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 219 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 222 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 223 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 226 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 /* Set ADC state */
<> 144:ef7eb2e8f9f7 229 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 230 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 231 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234 else
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 237 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 240 }
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Process unlocked */
<> 144:ef7eb2e8f9f7 243 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Return function status */
<> 144:ef7eb2e8f9f7 246 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 247 }
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @brief Wait for injected group conversion to be completed.
<> 144:ef7eb2e8f9f7 251 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 252 * @param Timeout: Timeout value in millisecond.
<> 144:ef7eb2e8f9f7 253 * @retval HAL status
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 uint32_t tickstart;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Variables for polling in case of scan mode enabled and polling for each */
<> 144:ef7eb2e8f9f7 260 /* conversion. */
<> 144:ef7eb2e8f9f7 261 /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU */
<> 144:ef7eb2e8f9f7 262 /* cycles to compensate number of CPU cycles for processing of variable */
<> 144:ef7eb2e8f9f7 263 /* "conversion_timeout_cpu_cycles_max" */
<> 144:ef7eb2e8f9f7 264 uint32_t conversion_timeout_cpu_cycles = 28;
<> 144:ef7eb2e8f9f7 265 uint32_t conversion_timeout_cpu_cycles_max = 0;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* Check the parameters */
<> 144:ef7eb2e8f9f7 268 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Get timeout */
<> 144:ef7eb2e8f9f7 271 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* Polling for end of conversion: differentiation if single/sequence */
<> 144:ef7eb2e8f9f7 274 /* conversion. */
<> 144:ef7eb2e8f9f7 275 /* For injected group, flag JEOC is set only at the end of the sequence, */
<> 144:ef7eb2e8f9f7 276 /* not for each conversion within the sequence. */
<> 144:ef7eb2e8f9f7 277 /* If setting "EOCSelection" is set to poll for each single conversion, */
<> 144:ef7eb2e8f9f7 278 /* management of polling depends on setting of injected group sequencer: */
<> 144:ef7eb2e8f9f7 279 /* - If single conversion for injected group (scan mode disabled or */
<> 144:ef7eb2e8f9f7 280 /* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
<> 144:ef7eb2e8f9f7 281 /* conversion completion. */
<> 144:ef7eb2e8f9f7 282 /* - If sequence conversion for injected group (scan mode enabled and */
<> 144:ef7eb2e8f9f7 283 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
<> 144:ef7eb2e8f9f7 284 /* sequence. */
<> 144:ef7eb2e8f9f7 285 /* To poll for each conversion, the maximum conversion time is computed */
<> 144:ef7eb2e8f9f7 286 /* from ADC conversion time (selected sampling time + conversion time of */
<> 144:ef7eb2e8f9f7 287 /* 12 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
<> 144:ef7eb2e8f9f7 288 /* settings, conversion time range can vary from 8 to several thousands */
<> 144:ef7eb2e8f9f7 289 /* of CPU cycles). */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Note: On STM32L1, setting "EOCSelection" is related to regular group */
<> 144:ef7eb2e8f9f7 292 /* only, by hardware. For compatibility with other STM32 devices, */
<> 144:ef7eb2e8f9f7 293 /* this setting is related also to injected group by software. */
<> 144:ef7eb2e8f9f7 294 if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) ||
<> 144:ef7eb2e8f9f7 295 (hadc->Init.EOCSelection != ADC_EOC_SINGLE_CONV) )
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Wait until End of Conversion flag is raised */
<> 144:ef7eb2e8f9f7 298 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 301 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 306 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Process unlocked */
<> 144:ef7eb2e8f9f7 309 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316 else
<> 144:ef7eb2e8f9f7 317 {
<> 144:ef7eb2e8f9f7 318 /* Computation of CPU cycles corresponding to ADC conversion cycles. */
<> 144:ef7eb2e8f9f7 319 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
<> 144:ef7eb2e8f9f7 320 /* channels. */
<> 144:ef7eb2e8f9f7 321 conversion_timeout_cpu_cycles_max = ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc);
<> 144:ef7eb2e8f9f7 322 conversion_timeout_cpu_cycles_max *= ADC_CONVCYCLES_MAX_RANGE(hadc);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Poll with maximum conversion time */
<> 144:ef7eb2e8f9f7 325 while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 /* Check if timeout is disabled (set to infinite wait) */
<> 144:ef7eb2e8f9f7 328 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 329 {
<> 144:ef7eb2e8f9f7 330 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 331 {
<> 144:ef7eb2e8f9f7 332 /* Update ADC state machine to timeout */
<> 144:ef7eb2e8f9f7 333 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /* Process unlocked */
<> 144:ef7eb2e8f9f7 336 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 conversion_timeout_cpu_cycles ++;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /* Clear end of conversion flag of injected group if low power feature */
<> 144:ef7eb2e8f9f7 346 /* "Auto Wait" is disabled, to not interfere with this feature until data */
<> 144:ef7eb2e8f9f7 347 /* register is read using function HAL_ADCEx_InjectedGetValue(). */
<> 144:ef7eb2e8f9f7 348 if (hadc->Init.LowPowerAutoWait == DISABLE)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 351 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Update ADC state machine */
<> 144:ef7eb2e8f9f7 355 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Determine whether any further conversion upcoming on group injected */
<> 144:ef7eb2e8f9f7 358 /* by external trigger, continuous mode or scan sequence on going. */
<> 144:ef7eb2e8f9f7 359 /* Note: On STM32L1, there is no independent flag of end of sequence. */
<> 144:ef7eb2e8f9f7 360 /* The test of scan sequence on going is done either with scan */
<> 144:ef7eb2e8f9f7 361 /* sequence disabled or with end of conversion flag set to */
<> 144:ef7eb2e8f9f7 362 /* of end of sequence. */
<> 144:ef7eb2e8f9f7 363 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 364 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
<> 144:ef7eb2e8f9f7 365 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) &&
<> 144:ef7eb2e8f9f7 366 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
<> 144:ef7eb2e8f9f7 367 (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
<> 144:ef7eb2e8f9f7 368 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Set ADC state */
<> 144:ef7eb2e8f9f7 371 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377 }
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Return ADC state */
<> 144:ef7eb2e8f9f7 380 return HAL_OK;
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Enables ADC, starts conversion of injected group with interruption.
<> 144:ef7eb2e8f9f7 385 * - JEOC (end of conversion of injected group)
<> 144:ef7eb2e8f9f7 386 * Each of these interruptions has its dedicated callback function.
<> 144:ef7eb2e8f9f7 387 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 388 * @retval HAL status.
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /* Check the parameters */
<> 144:ef7eb2e8f9f7 395 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Process locked */
<> 144:ef7eb2e8f9f7 398 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Enable the ADC peripheral */
<> 144:ef7eb2e8f9f7 401 tmp_hal_status = ADC_Enable(hadc);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* Start conversion if ADC is effectively enabled */
<> 144:ef7eb2e8f9f7 404 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 /* Set ADC state */
<> 144:ef7eb2e8f9f7 407 /* - Clear state bitfield related to injected group conversion results */
<> 144:ef7eb2e8f9f7 408 /* - Set state bitfield related to injected operation */
<> 144:ef7eb2e8f9f7 409 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 410 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
<> 144:ef7eb2e8f9f7 411 HAL_ADC_STATE_INJ_BUSY);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Check if a regular conversion is ongoing */
<> 144:ef7eb2e8f9f7 414 /* Note: On this device, there is no ADC error code fields related to */
<> 144:ef7eb2e8f9f7 415 /* conversions on group injected only. In case of conversion on */
<> 144:ef7eb2e8f9f7 416 /* going on group regular, no error code is reset. */
<> 144:ef7eb2e8f9f7 417 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 /* Reset ADC all error code fields */
<> 144:ef7eb2e8f9f7 420 ADC_CLEAR_ERRORCODE(hadc);
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Process unlocked */
<> 144:ef7eb2e8f9f7 424 /* Unlock before starting ADC conversions: in case of potential */
<> 144:ef7eb2e8f9f7 425 /* interruption, to let the process to ADC IRQ Handler. */
<> 144:ef7eb2e8f9f7 426 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Clear injected group conversion flag */
<> 144:ef7eb2e8f9f7 429 /* (To ensure of no unknown state from potential previous ADC operations) */
<> 144:ef7eb2e8f9f7 430 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Enable end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 433 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Enable conversion of injected group. */
<> 144:ef7eb2e8f9f7 436 /* If software start has been selected, conversion starts immediately. */
<> 144:ef7eb2e8f9f7 437 /* If external trigger has been selected, conversion will start at next */
<> 144:ef7eb2e8f9f7 438 /* trigger event. */
<> 144:ef7eb2e8f9f7 439 /* If automatic injected conversion is enabled, conversion will start */
<> 144:ef7eb2e8f9f7 440 /* after next regular group conversion. */
<> 144:ef7eb2e8f9f7 441 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
<> 144:ef7eb2e8f9f7 442 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 /* Enable ADC software conversion for injected channels */
<> 144:ef7eb2e8f9f7 445 SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Return function status */
<> 144:ef7eb2e8f9f7 450 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 451 }
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @brief Stop conversion of injected channels, disable interruption of
<> 144:ef7eb2e8f9f7 455 * end-of-conversion. Disable ADC peripheral if no regular conversion
<> 144:ef7eb2e8f9f7 456 * is on going.
<> 144:ef7eb2e8f9f7 457 * @note If ADC must be disabled and if conversion is on going on
<> 144:ef7eb2e8f9f7 458 * regular group, function HAL_ADC_Stop must be used to stop both
<> 144:ef7eb2e8f9f7 459 * injected and regular groups, and disable the ADC.
<> 144:ef7eb2e8f9f7 460 * @note If injected group mode auto-injection is enabled,
<> 144:ef7eb2e8f9f7 461 * function HAL_ADC_Stop must be used.
<> 144:ef7eb2e8f9f7 462 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 463 * @retval None
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Check the parameters */
<> 144:ef7eb2e8f9f7 470 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Process locked */
<> 144:ef7eb2e8f9f7 473 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 /* Stop potential conversion and disable ADC peripheral */
<> 144:ef7eb2e8f9f7 476 /* Conditioned to: */
<> 144:ef7eb2e8f9f7 477 /* - No conversion on the other group (regular group) is intended to */
<> 144:ef7eb2e8f9f7 478 /* continue (injected and regular groups stop conversion and ADC disable */
<> 144:ef7eb2e8f9f7 479 /* are common) */
<> 144:ef7eb2e8f9f7 480 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
<> 144:ef7eb2e8f9f7 481 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
<> 144:ef7eb2e8f9f7 482 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Stop potential conversion on going, on regular and injected groups */
<> 144:ef7eb2e8f9f7 485 /* Disable ADC peripheral */
<> 144:ef7eb2e8f9f7 486 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 /* Check if ADC is effectively disabled */
<> 144:ef7eb2e8f9f7 489 if (tmp_hal_status == HAL_OK)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Disable ADC end of conversion interrupt for injected channels */
<> 144:ef7eb2e8f9f7 492 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Set ADC state */
<> 144:ef7eb2e8f9f7 495 ADC_STATE_CLR_SET(hadc->State,
<> 144:ef7eb2e8f9f7 496 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
<> 144:ef7eb2e8f9f7 497 HAL_ADC_STATE_READY);
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 else
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 503 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Process unlocked */
<> 144:ef7eb2e8f9f7 509 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Return function status */
<> 144:ef7eb2e8f9f7 512 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /**
<> 144:ef7eb2e8f9f7 516 * @brief Get ADC injected group conversion result.
<> 144:ef7eb2e8f9f7 517 * @note Reading register JDRx automatically clears ADC flag JEOC
<> 144:ef7eb2e8f9f7 518 * (ADC group injected end of unitary conversion).
<> 144:ef7eb2e8f9f7 519 * @note This function does not clear ADC flag JEOS
<> 144:ef7eb2e8f9f7 520 * (ADC group injected end of sequence conversion)
<> 144:ef7eb2e8f9f7 521 * Occurrence of flag JEOS rising:
<> 144:ef7eb2e8f9f7 522 * - If sequencer is composed of 1 rank, flag JEOS is equivalent
<> 144:ef7eb2e8f9f7 523 * to flag JEOC.
<> 144:ef7eb2e8f9f7 524 * - If sequencer is composed of several ranks, during the scan
<> 144:ef7eb2e8f9f7 525 * sequence flag JEOC only is raised, at the end of the scan sequence
<> 144:ef7eb2e8f9f7 526 * both flags JEOC and EOS are raised.
<> 144:ef7eb2e8f9f7 527 * Flag JEOS must not be cleared by this function because
<> 144:ef7eb2e8f9f7 528 * it would not be compliant with low power features
<> 144:ef7eb2e8f9f7 529 * (feature low power auto-wait, not available on all STM32 families).
<> 144:ef7eb2e8f9f7 530 * To clear this flag, either use function:
<> 144:ef7eb2e8f9f7 531 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
<> 144:ef7eb2e8f9f7 532 * model polling: @ref HAL_ADCEx_InjectedPollForConversion()
<> 144:ef7eb2e8f9f7 533 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
<> 144:ef7eb2e8f9f7 534 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 535 * @param InjectedRank: the converted ADC injected rank.
<> 144:ef7eb2e8f9f7 536 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 537 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
<> 144:ef7eb2e8f9f7 538 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
<> 144:ef7eb2e8f9f7 539 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
<> 144:ef7eb2e8f9f7 540 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
<> 144:ef7eb2e8f9f7 541 * @retval ADC group injected conversion data
<> 144:ef7eb2e8f9f7 542 */
<> 144:ef7eb2e8f9f7 543 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
<> 144:ef7eb2e8f9f7 544 {
<> 144:ef7eb2e8f9f7 545 uint32_t tmp_jdr = 0;
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /* Check the parameters */
<> 144:ef7eb2e8f9f7 548 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 549 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Get ADC converted value */
<> 144:ef7eb2e8f9f7 552 switch(InjectedRank)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 case ADC_INJECTED_RANK_4:
<> 144:ef7eb2e8f9f7 555 tmp_jdr = hadc->Instance->JDR4;
<> 144:ef7eb2e8f9f7 556 break;
<> 144:ef7eb2e8f9f7 557 case ADC_INJECTED_RANK_3:
<> 144:ef7eb2e8f9f7 558 tmp_jdr = hadc->Instance->JDR3;
<> 144:ef7eb2e8f9f7 559 break;
<> 144:ef7eb2e8f9f7 560 case ADC_INJECTED_RANK_2:
<> 144:ef7eb2e8f9f7 561 tmp_jdr = hadc->Instance->JDR2;
<> 144:ef7eb2e8f9f7 562 break;
<> 144:ef7eb2e8f9f7 563 case ADC_INJECTED_RANK_1:
<> 144:ef7eb2e8f9f7 564 default:
<> 144:ef7eb2e8f9f7 565 tmp_jdr = hadc->Instance->JDR1;
<> 144:ef7eb2e8f9f7 566 break;
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Return ADC converted value */
<> 144:ef7eb2e8f9f7 570 return tmp_jdr;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @brief Injected conversion complete callback in non blocking mode
<> 144:ef7eb2e8f9f7 575 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 576 * @retval None
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 581 UNUSED(hadc);
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 584 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @}
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 593 * @brief ADC Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 594 *
<> 144:ef7eb2e8f9f7 595 @verbatim
<> 144:ef7eb2e8f9f7 596 ===============================================================================
<> 144:ef7eb2e8f9f7 597 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 598 ===============================================================================
<> 144:ef7eb2e8f9f7 599 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 600 (+) Configure channels on injected group
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 @endverbatim
<> 144:ef7eb2e8f9f7 603 * @{
<> 144:ef7eb2e8f9f7 604 */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Configures the ADC injected group and the selected channel to be
<> 144:ef7eb2e8f9f7 608 * linked to the injected group.
<> 144:ef7eb2e8f9f7 609 * @note Possibility to update parameters on the fly:
<> 144:ef7eb2e8f9f7 610 * This function initializes injected group, following calls to this
<> 144:ef7eb2e8f9f7 611 * function can be used to reconfigure some parameters of structure
<> 144:ef7eb2e8f9f7 612 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
<> 144:ef7eb2e8f9f7 613 * The setting of these parameters is conditioned to ADC state:
<> 144:ef7eb2e8f9f7 614 * this function must be called when ADC is not under conversion.
<> 144:ef7eb2e8f9f7 615 * @param hadc: ADC handle
<> 144:ef7eb2e8f9f7 616 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
<> 144:ef7eb2e8f9f7 617 * injected group.
<> 144:ef7eb2e8f9f7 618 * @retval None
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
<> 144:ef7eb2e8f9f7 623 __IO uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Check the parameters */
<> 144:ef7eb2e8f9f7 626 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
<> 144:ef7eb2e8f9f7 627 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
<> 144:ef7eb2e8f9f7 628 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
<> 144:ef7eb2e8f9f7 629 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
<> 144:ef7eb2e8f9f7 630 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
<> 144:ef7eb2e8f9f7 631 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, sConfigInjected->InjectedOffset));
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 634 {
<> 144:ef7eb2e8f9f7 635 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
<> 144:ef7eb2e8f9f7 636 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
<> 144:ef7eb2e8f9f7 637 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /* Process locked */
<> 144:ef7eb2e8f9f7 646 __HAL_LOCK(hadc);
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /* Configuration of injected group sequencer: */
<> 144:ef7eb2e8f9f7 649 /* - if scan mode is disabled, injected channels sequence length is set to */
<> 144:ef7eb2e8f9f7 650 /* 0x00: 1 channel converted (channel on regular rank 1) */
<> 144:ef7eb2e8f9f7 651 /* Parameter "InjectedNbrOfConversion" is discarded. */
<> 144:ef7eb2e8f9f7 652 /* Note: Scan mode is present by hardware on this device and, if */
<> 144:ef7eb2e8f9f7 653 /* disabled, discards automatically nb of conversions. Anyway, nb of */
<> 144:ef7eb2e8f9f7 654 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
<> 144:ef7eb2e8f9f7 655 /* - if scan mode is enabled, injected channels sequence length is set to */
<> 144:ef7eb2e8f9f7 656 /* parameter ""InjectedNbrOfConversion". */
<> 144:ef7eb2e8f9f7 657 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 /* Clear the old SQx bits for all injected ranks */
<> 144:ef7eb2e8f9f7 662 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 663 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 664 ADC_JSQR_JSQ4 |
<> 144:ef7eb2e8f9f7 665 ADC_JSQR_JSQ3 |
<> 144:ef7eb2e8f9f7 666 ADC_JSQR_JSQ2 |
<> 144:ef7eb2e8f9f7 667 ADC_JSQR_JSQ1 ,
<> 144:ef7eb2e8f9f7 668 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
<> 144:ef7eb2e8f9f7 669 ADC_INJECTED_RANK_1,
<> 144:ef7eb2e8f9f7 670 0x01) );
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672 /* If another injected rank than rank1 was intended to be set, and could */
<> 144:ef7eb2e8f9f7 673 /* not due to ScanConvMode disabled, error is reported. */
<> 144:ef7eb2e8f9f7 674 else
<> 144:ef7eb2e8f9f7 675 {
<> 144:ef7eb2e8f9f7 676 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 677 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682 else
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 /* Since injected channels rank conv. order depends on total number of */
<> 144:ef7eb2e8f9f7 685 /* injected conversions, selected rank must be below or equal to total */
<> 144:ef7eb2e8f9f7 686 /* number of injected conversions to be updated. */
<> 144:ef7eb2e8f9f7 687 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
<> 144:ef7eb2e8f9f7 688 {
<> 144:ef7eb2e8f9f7 689 /* Clear the old SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 690 /* Set the SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 691 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 694 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
<> 144:ef7eb2e8f9f7 695 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 696 sConfigInjected->InjectedNbrOfConversion) ,
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
<> 144:ef7eb2e8f9f7 699 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
<> 144:ef7eb2e8f9f7 700 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 701 sConfigInjected->InjectedNbrOfConversion) );
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 else
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 /* Clear the old SQx bits for the selected rank */
<> 144:ef7eb2e8f9f7 706 MODIFY_REG(hadc->Instance->JSQR ,
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 ADC_JSQR_JL |
<> 144:ef7eb2e8f9f7 709 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
<> 144:ef7eb2e8f9f7 710 sConfigInjected->InjectedRank,
<> 144:ef7eb2e8f9f7 711 sConfigInjected->InjectedNbrOfConversion) ,
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 0x00000000 );
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 }
<> 144:ef7eb2e8f9f7 716
<> 144:ef7eb2e8f9f7 717 /* Enable external trigger if trigger selection is different of software */
<> 144:ef7eb2e8f9f7 718 /* start. */
<> 144:ef7eb2e8f9f7 719 /* Note: This configuration keeps the hardware feature of parameter */
<> 144:ef7eb2e8f9f7 720 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
<> 144:ef7eb2e8f9f7 721 /* software start. */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 MODIFY_REG(hadc->Instance->CR2 ,
<> 144:ef7eb2e8f9f7 726 ADC_CR2_JEXTEN |
<> 144:ef7eb2e8f9f7 727 ADC_CR2_JEXTSEL ,
<> 144:ef7eb2e8f9f7 728 sConfigInjected->ExternalTrigInjecConv |
<> 144:ef7eb2e8f9f7 729 sConfigInjected->ExternalTrigInjecConvEdge );
<> 144:ef7eb2e8f9f7 730 }
<> 144:ef7eb2e8f9f7 731 else
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 MODIFY_REG(hadc->Instance->CR2,
<> 144:ef7eb2e8f9f7 734 ADC_CR2_JEXTEN |
<> 144:ef7eb2e8f9f7 735 ADC_CR2_JEXTSEL ,
<> 144:ef7eb2e8f9f7 736 0x00000000 );
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Configuration of injected group */
<> 144:ef7eb2e8f9f7 740 /* Parameters update conditioned to ADC state: */
<> 144:ef7eb2e8f9f7 741 /* Parameters that can be updated only when ADC is disabled: */
<> 144:ef7eb2e8f9f7 742 /* - Automatic injected conversion */
<> 144:ef7eb2e8f9f7 743 /* - Injected discontinuous mode */
<> 144:ef7eb2e8f9f7 744 if ((ADC_IS_ENABLE(hadc) == RESET))
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO |
<> 144:ef7eb2e8f9f7 747 ADC_CR1_JDISCEN );
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /* Automatic injected conversion can be enabled if injected group */
<> 144:ef7eb2e8f9f7 750 /* external triggers are disabled. */
<> 144:ef7eb2e8f9f7 751 if (sConfigInjected->AutoInjectedConv == ENABLE)
<> 144:ef7eb2e8f9f7 752 {
<> 144:ef7eb2e8f9f7 753 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757 else
<> 144:ef7eb2e8f9f7 758 {
<> 144:ef7eb2e8f9f7 759 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 760 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764 }
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* Injected discontinuous can be enabled only if auto-injected mode is */
<> 144:ef7eb2e8f9f7 767 /* disabled. */
<> 144:ef7eb2e8f9f7 768 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
<> 144:ef7eb2e8f9f7 769 {
<> 144:ef7eb2e8f9f7 770 if (sConfigInjected->AutoInjectedConv == DISABLE)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 else
<> 144:ef7eb2e8f9f7 775 {
<> 144:ef7eb2e8f9f7 776 /* Update ADC state machine to error */
<> 144:ef7eb2e8f9f7 777 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 tmp_hal_status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Channel sampling time configuration */
<> 144:ef7eb2e8f9f7 785 /* For InjectedChannels 0 to 9 */
<> 144:ef7eb2e8f9f7 786 if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 MODIFY_REG(hadc->Instance->SMPR3,
<> 144:ef7eb2e8f9f7 789 ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel),
<> 144:ef7eb2e8f9f7 790 ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792 /* For InjectedChannels 10 to 19 */
<> 144:ef7eb2e8f9f7 793 else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 MODIFY_REG(hadc->Instance->SMPR2,
<> 144:ef7eb2e8f9f7 796 ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
<> 144:ef7eb2e8f9f7 797 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 798 }
<> 144:ef7eb2e8f9f7 799 /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
<> 144:ef7eb2e8f9f7 800 /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */
<> 144:ef7eb2e8f9f7 801 else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX)
<> 144:ef7eb2e8f9f7 802 {
<> 144:ef7eb2e8f9f7 803 MODIFY_REG(hadc->Instance->SMPR1,
<> 144:ef7eb2e8f9f7 804 ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel),
<> 144:ef7eb2e8f9f7 805 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807 /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */
<> 144:ef7eb2e8f9f7 808 else
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
<> 144:ef7eb2e8f9f7 815 switch(sConfigInjected->InjectedRank)
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 case 1:
<> 144:ef7eb2e8f9f7 818 /* Set injected channel 1 offset */
<> 144:ef7eb2e8f9f7 819 MODIFY_REG(hadc->Instance->JOFR1,
<> 144:ef7eb2e8f9f7 820 ADC_JOFR1_JOFFSET1,
<> 144:ef7eb2e8f9f7 821 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 822 break;
<> 144:ef7eb2e8f9f7 823 case 2:
<> 144:ef7eb2e8f9f7 824 /* Set injected channel 2 offset */
<> 144:ef7eb2e8f9f7 825 MODIFY_REG(hadc->Instance->JOFR2,
<> 144:ef7eb2e8f9f7 826 ADC_JOFR2_JOFFSET2,
<> 144:ef7eb2e8f9f7 827 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 828 break;
<> 144:ef7eb2e8f9f7 829 case 3:
<> 144:ef7eb2e8f9f7 830 /* Set injected channel 3 offset */
<> 144:ef7eb2e8f9f7 831 MODIFY_REG(hadc->Instance->JOFR3,
<> 144:ef7eb2e8f9f7 832 ADC_JOFR3_JOFFSET3,
<> 144:ef7eb2e8f9f7 833 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 834 break;
<> 144:ef7eb2e8f9f7 835 case 4:
<> 144:ef7eb2e8f9f7 836 default:
<> 144:ef7eb2e8f9f7 837 MODIFY_REG(hadc->Instance->JOFR4,
<> 144:ef7eb2e8f9f7 838 ADC_JOFR4_JOFFSET4,
<> 144:ef7eb2e8f9f7 839 sConfigInjected->InjectedOffset);
<> 144:ef7eb2e8f9f7 840 break;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
<> 144:ef7eb2e8f9f7 844 /* and VREFINT measurement path. */
<> 144:ef7eb2e8f9f7 845 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
<> 144:ef7eb2e8f9f7 846 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
<> 144:ef7eb2e8f9f7 851 {
<> 144:ef7eb2e8f9f7 852 /* Delay for temperature sensor stabilization time */
<> 144:ef7eb2e8f9f7 853 /* Compute number of CPU cycles to wait for */
<> 144:ef7eb2e8f9f7 854 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 855 while(wait_loop_index != 0)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 wait_loop_index--;
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /* Process unlocked */
<> 144:ef7eb2e8f9f7 863 __HAL_UNLOCK(hadc);
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Return function status */
<> 144:ef7eb2e8f9f7 866 return tmp_hal_status;
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @}
<> 144:ef7eb2e8f9f7 871 */
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /**
<> 144:ef7eb2e8f9f7 874 * @}
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 #endif /* HAL_ADC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @}
<> 144:ef7eb2e8f9f7 880 */
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /**
<> 144:ef7eb2e8f9f7 883 * @}
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/