Toyomasa Watarai / mbed-dev-lpcx1769

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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l1xx_hal_flash_ramfunc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 04-March-2016
<> 144:ef7eb2e8f9f7 7 * @brief FLASH RAMFUNC driver.
<> 144:ef7eb2e8f9f7 8 * This file provides a Flash firmware functions which should be
<> 144:ef7eb2e8f9f7 9 * executed from internal SRAM
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @verbatim
<> 144:ef7eb2e8f9f7 12
<> 144:ef7eb2e8f9f7 13 *** ARM Compiler ***
<> 144:ef7eb2e8f9f7 14 --------------------
<> 144:ef7eb2e8f9f7 15 [..] RAM functions are defined using the toolchain options.
<> 144:ef7eb2e8f9f7 16 Functions that are be executed in RAM should reside in a separate
<> 144:ef7eb2e8f9f7 17 source module. Using the 'Options for File' dialog you can simply change
<> 144:ef7eb2e8f9f7 18 the 'Code / Const' area of a module to a memory space in physical RAM.
<> 144:ef7eb2e8f9f7 19 Available memory areas are declared in the 'Target' tab of the
<> 144:ef7eb2e8f9f7 20 Options for Target' dialog.
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 *** ICCARM Compiler ***
<> 144:ef7eb2e8f9f7 23 -----------------------
<> 144:ef7eb2e8f9f7 24 [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 *** GNU Compiler ***
<> 144:ef7eb2e8f9f7 27 --------------------
<> 144:ef7eb2e8f9f7 28 [..] RAM functions are defined using a specific toolchain attribute
<> 144:ef7eb2e8f9f7 29 "__attribute__((section(".RamFunc")))".
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 @endverbatim
<> 144:ef7eb2e8f9f7 32 ******************************************************************************
<> 144:ef7eb2e8f9f7 33 * @attention
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 38 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 39 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 40 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 41 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 42 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 43 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 44 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 45 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 46 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 47 *
<> 144:ef7eb2e8f9f7 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 51 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 55 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 56 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 58 *
<> 144:ef7eb2e8f9f7 59 ******************************************************************************
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63 #include "stm32l1xx_hal.h"
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 /** @addtogroup STM32L1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 66 * @{
<> 144:ef7eb2e8f9f7 67 */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
<> 144:ef7eb2e8f9f7 72 * @brief FLASH functions executed from RAM
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 82 /** @defgroup FLASH_RAMFUNC_Private_Functions Private Functions
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /**
<> 144:ef7eb2e8f9f7 89 * @}
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @defgroup FLASH_RAMFUNC_Exported_Functions Exported Functions
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 @verbatim
<> 144:ef7eb2e8f9f7 97 ===============================================================================
<> 144:ef7eb2e8f9f7 98 ##### ramfunc functions #####
<> 144:ef7eb2e8f9f7 99 ===============================================================================
<> 144:ef7eb2e8f9f7 100 [..]
<> 144:ef7eb2e8f9f7 101 This subsection provides a set of functions that should be executed from RAM
<> 144:ef7eb2e8f9f7 102 transfers.
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 @endverbatim
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 /**
<> 144:ef7eb2e8f9f7 113 * @brief Enable the power down mode during RUN mode.
<> 144:ef7eb2e8f9f7 114 * @note This function can be used only when the user code is running from Internal SRAM.
<> 144:ef7eb2e8f9f7 115 * @retval None
<> 144:ef7eb2e8f9f7 116 */
<> 144:ef7eb2e8f9f7 117 __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
<> 144:ef7eb2e8f9f7 118 {
<> 144:ef7eb2e8f9f7 119 /* Enable the Power Down in Run mode*/
<> 144:ef7eb2e8f9f7 120 __HAL_FLASH_POWER_DOWN_ENABLE();
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 return HAL_OK;
<> 144:ef7eb2e8f9f7 123 }
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @brief Disable the power down mode during RUN mode.
<> 144:ef7eb2e8f9f7 128 * @note This function can be used only when the user code is running from Internal SRAM.
<> 144:ef7eb2e8f9f7 129 * @retval None
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Disable the Power Down in Run mode*/
<> 144:ef7eb2e8f9f7 134 __HAL_FLASH_POWER_DOWN_DISABLE();
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 return HAL_OK;
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
<> 144:ef7eb2e8f9f7 144 *
<> 144:ef7eb2e8f9f7 145 @verbatim
<> 144:ef7eb2e8f9f7 146 @endverbatim
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #if defined(FLASH_PECR_PARALLBANK)
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @brief Erases a specified 2 page in program memory in parallel.
<> 144:ef7eb2e8f9f7 153 * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
<> 144:ef7eb2e8f9f7 154 * To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 155 * must be called before.
<> 144:ef7eb2e8f9f7 156 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 157 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 144:ef7eb2e8f9f7 158 * @param Page_Address1: The page address in program memory to be erased in
<> 144:ef7eb2e8f9f7 159 * the first Bank (BANK1). This parameter should be between FLASH_BASE
<> 144:ef7eb2e8f9f7 160 * and FLASH_BANK1_END.
<> 144:ef7eb2e8f9f7 161 * @param Page_Address2: The page address in program memory to be erased in
<> 144:ef7eb2e8f9f7 162 * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
<> 144:ef7eb2e8f9f7 163 * and FLASH_BANK2_END.
<> 144:ef7eb2e8f9f7 164 * @note A Page is erased in the Program memory only if the address to load
<> 144:ef7eb2e8f9f7 165 * is the start address of a page (multiple of 256 bytes).
<> 144:ef7eb2e8f9f7 166 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 167 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 174 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 /* If the previous operation is completed, proceed to erase the page */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Set the PARALLBANK bit */
<> 144:ef7eb2e8f9f7 181 FLASH->PECR |= FLASH_PECR_PARALLBANK;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Set the ERASE bit */
<> 144:ef7eb2e8f9f7 184 FLASH->PECR |= FLASH_PECR_ERASE;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Set PROG bit */
<> 144:ef7eb2e8f9f7 187 FLASH->PECR |= FLASH_PECR_PROG;
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /* Write 00000000h to the first word of the first program page to erase */
<> 144:ef7eb2e8f9f7 190 *(__IO uint32_t *)Page_Address1 = 0x00000000;
<> 144:ef7eb2e8f9f7 191 /* Write 00000000h to the first word of the second program page to erase */
<> 144:ef7eb2e8f9f7 192 *(__IO uint32_t *)Page_Address2 = 0x00000000;
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 195 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
<> 144:ef7eb2e8f9f7 198 FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 199 FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
<> 144:ef7eb2e8f9f7 200 FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 201 }
<> 144:ef7eb2e8f9f7 202 /* Return the Erase Status */
<> 144:ef7eb2e8f9f7 203 return status;
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Programs 2 half page in program memory in parallel.
<> 144:ef7eb2e8f9f7 208 * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
<> 144:ef7eb2e8f9f7 209 * @param Address1: specifies the first address to be written in the first bank
<> 144:ef7eb2e8f9f7 210 * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
<> 144:ef7eb2e8f9f7 211 * @param pBuffer1: pointer to the buffer containing the data to be written
<> 144:ef7eb2e8f9f7 212 * to the first half page in the first bank.
<> 144:ef7eb2e8f9f7 213 * @param Address2: specifies the second address to be written in the second bank
<> 144:ef7eb2e8f9f7 214 * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
<> 144:ef7eb2e8f9f7 215 * @param pBuffer2: pointer to the buffer containing the data to be written
<> 144:ef7eb2e8f9f7 216 * to the second half page in the second bank.
<> 144:ef7eb2e8f9f7 217 * @note To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 218 * must be called before.
<> 144:ef7eb2e8f9f7 219 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 220 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 144:ef7eb2e8f9f7 221 * @note Half page write is possible only from SRAM.
<> 144:ef7eb2e8f9f7 222 * @note If there are more than 32 words to write, after 32 words another
<> 144:ef7eb2e8f9f7 223 * Half Page programming operation starts and has to be finished.
<> 144:ef7eb2e8f9f7 224 * @note A half page is written to the program memory only if the first
<> 144:ef7eb2e8f9f7 225 * address to load is the start address of a half page (multiple of 128
<> 144:ef7eb2e8f9f7 226 * bytes) and the 31 remaining words to load are in the same half page.
<> 144:ef7eb2e8f9f7 227 * @note During the Program memory half page write all read operations are
<> 144:ef7eb2e8f9f7 228 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 229 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 230 * @note If a PGAERR is set during a Program memory half page write, the
<> 144:ef7eb2e8f9f7 231 * complete write operation is aborted. Software should then reset the
<> 144:ef7eb2e8f9f7 232 * FPRG and PROG/DATA bits and restart the write operation from the
<> 144:ef7eb2e8f9f7 233 * beginning.
<> 144:ef7eb2e8f9f7 234 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 235 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 uint32_t count = 0;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 144:ef7eb2e8f9f7 244 This bit prevents the interruption of multicycle instructions and therefore
<> 144:ef7eb2e8f9f7 245 will increase the interrupt latency. of Cortex-M3. */
<> 144:ef7eb2e8f9f7 246 SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 249 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 252 {
<> 144:ef7eb2e8f9f7 253 /* If the previous operation is completed, proceed to program the new
<> 144:ef7eb2e8f9f7 254 half page */
<> 144:ef7eb2e8f9f7 255 FLASH->PECR |= FLASH_PECR_PARALLBANK;
<> 144:ef7eb2e8f9f7 256 FLASH->PECR |= FLASH_PECR_FPRG;
<> 144:ef7eb2e8f9f7 257 FLASH->PECR |= FLASH_PECR_PROG;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 260 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 261 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 262 {
<> 144:ef7eb2e8f9f7 263 /* Write the first half page directly with 32 different words */
<> 144:ef7eb2e8f9f7 264 while(count < 32)
<> 144:ef7eb2e8f9f7 265 {
<> 144:ef7eb2e8f9f7 266 *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++);
<> 144:ef7eb2e8f9f7 267 count ++;
<> 144:ef7eb2e8f9f7 268 }
<> 144:ef7eb2e8f9f7 269 count = 0;
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* Write the second half page directly with 32 different words */
<> 144:ef7eb2e8f9f7 272 while(count < 32)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++);
<> 144:ef7eb2e8f9f7 275 count ++;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 278 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 279 }
<> 144:ef7eb2e8f9f7 280 /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
<> 144:ef7eb2e8f9f7 281 FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 282 FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 283 FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /* Return the Write Status */
<> 144:ef7eb2e8f9f7 289 return status;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 #endif /* FLASH_PECR_PARALLBANK */
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Programs a half page in program memory.
<> 144:ef7eb2e8f9f7 295 * @param Address: specifies the address to be written.
<> 144:ef7eb2e8f9f7 296 * @param pBuffer: pointer to the buffer containing the data to be written to
<> 144:ef7eb2e8f9f7 297 * the half page.
<> 144:ef7eb2e8f9f7 298 * @note To correctly run this function, the HAL_FLASH_Unlock() function
<> 144:ef7eb2e8f9f7 299 * must be called before.
<> 144:ef7eb2e8f9f7 300 * Call the HAL_FLASH_Lock() to disable the flash memory access
<> 144:ef7eb2e8f9f7 301 * (recommended to protect the FLASH memory against possible unwanted operation)
<> 144:ef7eb2e8f9f7 302 * @note Half page write is possible only from SRAM.
<> 144:ef7eb2e8f9f7 303 * @note If there are more than 32 words to write, after 32 words another
<> 144:ef7eb2e8f9f7 304 * Half Page programming operation starts and has to be finished.
<> 144:ef7eb2e8f9f7 305 * @note A half page is written to the program memory only if the first
<> 144:ef7eb2e8f9f7 306 * address to load is the start address of a half page (multiple of 128
<> 144:ef7eb2e8f9f7 307 * bytes) and the 31 remaining words to load are in the same half page.
<> 144:ef7eb2e8f9f7 308 * @note During the Program memory half page write all read operations are
<> 144:ef7eb2e8f9f7 309 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 310 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 311 * @note If a PGAERR is set during a Program memory half page write, the
<> 144:ef7eb2e8f9f7 312 * complete write operation is aborted. Software should then reset the
<> 144:ef7eb2e8f9f7 313 * FPRG and PROG/DATA bits and restart the write operation from the
<> 144:ef7eb2e8f9f7 314 * beginning.
<> 144:ef7eb2e8f9f7 315 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 316 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318 __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 uint32_t count = 0;
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 144:ef7eb2e8f9f7 325 This bit prevents the interruption of multicycle instructions and therefore
<> 144:ef7eb2e8f9f7 326 will increase the interrupt latency. of Cortex-M3. */
<> 144:ef7eb2e8f9f7 327 SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 330 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* if the previous operation is completed, proceed to program the new
<> 144:ef7eb2e8f9f7 335 half page */
<> 144:ef7eb2e8f9f7 336 FLASH->PECR |= FLASH_PECR_FPRG;
<> 144:ef7eb2e8f9f7 337 FLASH->PECR |= FLASH_PECR_PROG;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Write one half page directly with 32 different words */
<> 144:ef7eb2e8f9f7 340 while(count < 32)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++);
<> 144:ef7eb2e8f9f7 343 count ++;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 346 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /* if the write operation is completed, disable the PROG and FPRG bits */
<> 144:ef7eb2e8f9f7 349 FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
<> 144:ef7eb2e8f9f7 350 FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /* Return the Write Status */
<> 144:ef7eb2e8f9f7 356 return status;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /**
<> 144:ef7eb2e8f9f7 360 * @}
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 DATA EEPROM functions
<> 144:ef7eb2e8f9f7 364 *
<> 144:ef7eb2e8f9f7 365 * @{
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @brief Erase a double word in data memory.
<> 144:ef7eb2e8f9f7 370 * @param Address: specifies the address to be erased.
<> 144:ef7eb2e8f9f7 371 * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
<> 144:ef7eb2e8f9f7 372 * must be called before.
<> 144:ef7eb2e8f9f7 373 * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
<> 144:ef7eb2e8f9f7 374 * and Flash program erase control register access(recommended to protect
<> 144:ef7eb2e8f9f7 375 * the DATA_EEPROM against possible unwanted operation).
<> 144:ef7eb2e8f9f7 376 * @note Data memory double word erase is possible only from SRAM.
<> 144:ef7eb2e8f9f7 377 * @note A double word is erased to the data memory only if the first address
<> 144:ef7eb2e8f9f7 378 * to load is the start address of a double word (multiple of 8 bytes).
<> 144:ef7eb2e8f9f7 379 * @note During the Data memory double word erase, all read operations are
<> 144:ef7eb2e8f9f7 380 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 381 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 382 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 383 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 144:ef7eb2e8f9f7 391 This bit prevents the interruption of multicycle instructions and therefore
<> 144:ef7eb2e8f9f7 392 will increase the interrupt latency. of Cortex-M3. */
<> 144:ef7eb2e8f9f7 393 SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 396 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 /* If the previous operation is completed, proceed to erase the next double word */
<> 144:ef7eb2e8f9f7 401 /* Set the ERASE bit */
<> 144:ef7eb2e8f9f7 402 FLASH->PECR |= FLASH_PECR_ERASE;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Set DATA bit */
<> 144:ef7eb2e8f9f7 405 FLASH->PECR |= FLASH_PECR_DATA;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Write 00000000h to the 2 words to erase */
<> 144:ef7eb2e8f9f7 408 *(__IO uint32_t *)Address = 0x00000000;
<> 144:ef7eb2e8f9f7 409 Address += 4;
<> 144:ef7eb2e8f9f7 410 *(__IO uint32_t *)Address = 0x00000000;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 413 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* If the erase operation is completed, disable the ERASE and DATA bits */
<> 144:ef7eb2e8f9f7 416 FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
<> 144:ef7eb2e8f9f7 417 FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Return the erase status */
<> 144:ef7eb2e8f9f7 423 return status;
<> 144:ef7eb2e8f9f7 424 }
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**
<> 144:ef7eb2e8f9f7 427 * @brief Write a double word in data memory without erase.
<> 144:ef7eb2e8f9f7 428 * @param Address: specifies the address to be written.
<> 144:ef7eb2e8f9f7 429 * @param Data: specifies the data to be written.
<> 144:ef7eb2e8f9f7 430 * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
<> 144:ef7eb2e8f9f7 431 * must be called before.
<> 144:ef7eb2e8f9f7 432 * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
<> 144:ef7eb2e8f9f7 433 * and Flash program erase control register access(recommended to protect
<> 144:ef7eb2e8f9f7 434 * the DATA_EEPROM against possible unwanted operation).
<> 144:ef7eb2e8f9f7 435 * @note Data memory double word write is possible only from SRAM.
<> 144:ef7eb2e8f9f7 436 * @note A data memory double word is written to the data memory only if the
<> 144:ef7eb2e8f9f7 437 * first address to load is the start address of a double word (multiple
<> 144:ef7eb2e8f9f7 438 * of double word).
<> 144:ef7eb2e8f9f7 439 * @note During the Data memory double word write, all read operations are
<> 144:ef7eb2e8f9f7 440 * forbidden (this includes DMA read operations and debugger read
<> 144:ef7eb2e8f9f7 441 * operations such as breakpoints, periodic updates, etc.).
<> 144:ef7eb2e8f9f7 442 * @retval HAL Status: The returned value can be:
<> 144:ef7eb2e8f9f7 443 * HAL_ERROR, HAL_OK or HAL_TIMEOUT.
<> 144:ef7eb2e8f9f7 444 */
<> 144:ef7eb2e8f9f7 445 __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 144:ef7eb2e8f9f7 450 This bit prevents the interruption of multicycle instructions and therefore
<> 144:ef7eb2e8f9f7 451 will increase the interrupt latency. of Cortex-M3. */
<> 144:ef7eb2e8f9f7 452 SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 455 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 458 {
<> 144:ef7eb2e8f9f7 459 /* If the previous operation is completed, proceed to program the new data*/
<> 144:ef7eb2e8f9f7 460 FLASH->PECR |= FLASH_PECR_FPRG;
<> 144:ef7eb2e8f9f7 461 FLASH->PECR |= FLASH_PECR_DATA;
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 /* Write the 2 words */
<> 144:ef7eb2e8f9f7 464 *(__IO uint32_t *)Address = (uint32_t) Data;
<> 144:ef7eb2e8f9f7 465 Address += 4;
<> 144:ef7eb2e8f9f7 466 *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 469 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* If the write operation is completed, disable the FPRG and DATA bits */
<> 144:ef7eb2e8f9f7 472 FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
<> 144:ef7eb2e8f9f7 473 FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
<> 144:ef7eb2e8f9f7 474 }
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 /* Return the Write Status */
<> 144:ef7eb2e8f9f7 479 return status;
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /**
<> 144:ef7eb2e8f9f7 483 * @}
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /**
<> 144:ef7eb2e8f9f7 487 * @}
<> 144:ef7eb2e8f9f7 488 */
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /** @addtogroup FLASH_RAMFUNC_Private_Functions
<> 144:ef7eb2e8f9f7 491 * @{
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /**
<> 144:ef7eb2e8f9f7 495 * @brief Wait for a FLASH operation to complete.
<> 144:ef7eb2e8f9f7 496 * @param Timeout: maximum flash operationtimeout
<> 144:ef7eb2e8f9f7 497 * @retval HAL status
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
<> 144:ef7eb2e8f9f7 502 Even if the FLASH operation fails, the BUSY flag will be reset and an error
<> 144:ef7eb2e8f9f7 503 flag will be set */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 Timeout--;
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 if(Timeout == 0x00 )
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 513 }
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Check FLASH End of Operation flag */
<> 144:ef7eb2e8f9f7 516 if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
<> 144:ef7eb2e8f9f7 517 {
<> 144:ef7eb2e8f9f7 518 /* Clear FLASH End of Operation pending bit */
<> 144:ef7eb2e8f9f7 519 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
<> 144:ef7eb2e8f9f7 520 }
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||
<> 144:ef7eb2e8f9f7 523 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) ||
<> 144:ef7eb2e8f9f7 524 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) ||
<> 144:ef7eb2e8f9f7 525 #if defined(FLASH_SR_RDERR)
<> 144:ef7eb2e8f9f7 526 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||
<> 144:ef7eb2e8f9f7 527 #endif /* FLASH_SR_RDERR */
<> 144:ef7eb2e8f9f7 528 #if defined(FLASH_SR_OPTVERRUSR)
<> 144:ef7eb2e8f9f7 529 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) ||
<> 144:ef7eb2e8f9f7 530 #endif /* FLASH_SR_OPTVERRUSR */
<> 144:ef7eb2e8f9f7 531 (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) )
<> 144:ef7eb2e8f9f7 532 {
<> 144:ef7eb2e8f9f7 533 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* If there is an error flag set */
<> 144:ef7eb2e8f9f7 537 return HAL_OK;
<> 144:ef7eb2e8f9f7 538 }
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /**
<> 144:ef7eb2e8f9f7 542 * @}
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @}
<> 144:ef7eb2e8f9f7 547 */
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @}
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/