Toyomasa Watarai / mbed-dev-lpcx1769

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Dependents:   LPCXpresso1769_blinky

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targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l1xx_hal_flash.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 04-March-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of Flash HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L1xx_HAL_FLASH_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup FLASHEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup FLASHEx_Private_Defines
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60 #if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 144:ef7eb2e8f9f7 63 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 144:ef7eb2e8f9f7 64 FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 #elif defined(FLASH_SR_RDERR)
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 144:ef7eb2e8f9f7 69 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 144:ef7eb2e8f9f7 70 FLASH_FLAG_RDERR)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 #elif defined(FLASH_SR_OPTVERRUSR)
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 144:ef7eb2e8f9f7 75 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
<> 144:ef7eb2e8f9f7 76 FLASH_FLAG_OPTVERRUSR)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 #else
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
<> 144:ef7eb2e8f9f7 81 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
<> 144:ef7eb2e8f9f7 86 || defined(STM32L151xBA) || defined(STM32L152xBA)
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /******* Devices with FLASH 128K *******/
<> 144:ef7eb2e8f9f7 89 #define FLASH_NBPAGES_MAX 512 /* 512 pages from page 0 to page 511 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 144:ef7eb2e8f9f7 92 || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /******* Devices with FLASH 256K *******/
<> 144:ef7eb2e8f9f7 95 #define FLASH_NBPAGES_MAX 1025 /* 1025 pages from page 0 to page 1024 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 98 || defined(STM32L162xD) || defined(STM32L162xDX)
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /******* Devices with FLASH 384K *******/
<> 144:ef7eb2e8f9f7 101 #define FLASH_NBPAGES_MAX 1536 /* 1536 pages from page 0 to page 1535 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /******* Devices with FLASH 512K *******/
<> 144:ef7eb2e8f9f7 106 #define FLASH_NBPAGES_MAX 2048 /* 2048 pages from page 0 to page 2047 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @defgroup FLASHEx_Option_Bytes_Write_Mask FLASHEx Option Bytes Write Mask
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 #define WRP_MASK_LOW ((uint32_t)0x0000FFFF)
<> 144:ef7eb2e8f9f7 114 #define WRP_MASK_HIGH ((uint32_t)0xFFFF0000)
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @}
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /** @addtogroup FLASHEx_Private_Macros
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 133 ((__VALUE__) == OB_WRPSTATE_ENABLE))
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
<> 144:ef7eb2e8f9f7 136 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
<> 144:ef7eb2e8f9f7 137 ((__LEVEL__) == OB_RDP_LEVEL_2))
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
<> 144:ef7eb2e8f9f7 140 ((__LEVEL__) == OB_BOR_LEVEL1) || \
<> 144:ef7eb2e8f9f7 141 ((__LEVEL__) == OB_BOR_LEVEL2) || \
<> 144:ef7eb2e8f9f7 142 ((__LEVEL__) == OB_BOR_LEVEL3) || \
<> 144:ef7eb2e8f9f7 143 ((__LEVEL__) == OB_BOR_LEVEL4) || \
<> 144:ef7eb2e8f9f7 144 ((__LEVEL__) == OB_BOR_LEVEL5))
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 153 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 160 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 161 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 168 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
<> 144:ef7eb2e8f9f7 171 ((__VALUE__) == OB_PCROP_STATE_ENABLE))
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
<> 144:ef7eb2e8f9f7 176 ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
<> 144:ef7eb2e8f9f7 177 ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
<> 144:ef7eb2e8f9f7 180 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
<> 144:ef7eb2e8f9f7 181 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
<> 144:ef7eb2e8f9f7 182 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
<> 144:ef7eb2e8f9f7 183 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
<> 144:ef7eb2e8f9f7 184 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /** @defgroup FLASHEx_Address FLASHEx Address
<> 144:ef7eb2e8f9f7 188 * @{
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
<> 144:ef7eb2e8f9f7 194 || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
<> 144:ef7eb2e8f9f7 195 || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
<> 144:ef7eb2e8f9f7 196 || defined(STM32L162xCA)
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 #else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
<> 144:ef7eb2e8f9f7 203 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))
<> 144:ef7eb2e8f9f7 204 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX))
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 211 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 212 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @}
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** @defgroup FLASHEx_Exported_Types Exported Types
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief FLASH Erase structure definition
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 typedef struct
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref FLASHEx_Type_Erase */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
<> 144:ef7eb2e8f9f7 239 This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
<> 144:ef7eb2e8f9f7 242 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 } FLASH_EraseInitTypeDef;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /**
<> 144:ef7eb2e8f9f7 247 * @brief FLASH Option Bytes PROGRAM structure definition
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249 typedef struct
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
<> 144:ef7eb2e8f9f7 252 This parameter can be a value of @ref FLASHEx_Option_Type */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
<> 144:ef7eb2e8f9f7 255 This parameter can be a value of @ref FLASHEx_WRP_State */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
<> 144:ef7eb2e8f9f7 258 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 144:ef7eb2e8f9f7 261 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
<> 144:ef7eb2e8f9f7 262 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
<> 144:ef7eb2e8f9f7 263 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 264 uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
<> 144:ef7eb2e8f9f7 265 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
<> 144:ef7eb2e8f9f7 266 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 269 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 270 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 271 uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
<> 144:ef7eb2e8f9f7 272 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */
<> 144:ef7eb2e8f9f7 273 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
<> 144:ef7eb2e8f9f7 276 || defined(STM32L152xDX) || defined(STM32L162xDX)
<> 144:ef7eb2e8f9f7 277 uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
<> 144:ef7eb2e8f9f7 278 Sectors 96 to 111 for STM32L1xxxDX devices.
<> 144:ef7eb2e8f9f7 279 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
<> 144:ef7eb2e8f9f7 280 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
<> 144:ef7eb2e8f9f7 283 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
<> 144:ef7eb2e8f9f7 286 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
<> 144:ef7eb2e8f9f7 289 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
<> 144:ef7eb2e8f9f7 290 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
<> 144:ef7eb2e8f9f7 291 } FLASH_OBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief FLASH Advanced Option Bytes Program structure definition
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 typedef struct
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
<> 144:ef7eb2e8f9f7 299 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 302 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 303 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
<> 144:ef7eb2e8f9f7 304 This parameter can be a value of @ref FLASHEx_PCROP_State */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
<> 144:ef7eb2e8f9f7 307 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 310 uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
<> 144:ef7eb2e8f9f7 311 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
<> 144:ef7eb2e8f9f7 312 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 313 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
<> 144:ef7eb2e8f9f7 316 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
<> 144:ef7eb2e8f9f7 317 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 318 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
<> 144:ef7eb2e8f9f7 319 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
<> 144:ef7eb2e8f9f7 320 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L151xE || STM32L152xE || STM32L162xE*/
<> 144:ef7eb2e8f9f7 321 } FLASH_AdvOBProgramInitTypeDef;
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /** @defgroup FLASHEx_Exported_Constants Exported Constants
<> 144:ef7eb2e8f9f7 331 * @{
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
<> 144:ef7eb2e8f9f7 335 * @{
<> 144:ef7eb2e8f9f7 336 */
<> 144:ef7eb2e8f9f7 337 #define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!<Page erase only*/
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /**
<> 144:ef7eb2e8f9f7 340 * @}
<> 144:ef7eb2e8f9f7 341 */
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
<> 144:ef7eb2e8f9f7 344 * @{
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 #define OPTIONBYTE_WRP ((uint32_t)0x01) /*!<WRP option byte configuration*/
<> 144:ef7eb2e8f9f7 347 #define OPTIONBYTE_RDP ((uint32_t)0x02) /*!<RDP option byte configuration*/
<> 144:ef7eb2e8f9f7 348 #define OPTIONBYTE_USER ((uint32_t)0x04) /*!<USER option byte configuration*/
<> 144:ef7eb2e8f9f7 349 #define OPTIONBYTE_BOR ((uint32_t)0x08) /*!<BOR option byte configuration*/
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @}
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
<> 144:ef7eb2e8f9f7 356 * @{
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358 #define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!<Disable the write protection of the desired bank 1 sectors*/
<> 144:ef7eb2e8f9f7 359 #define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!<Enable the write protection of the desired bank 1 sectors*/
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
<> 144:ef7eb2e8f9f7 370 #define OB_WRP1_PAGES0TO15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
<> 144:ef7eb2e8f9f7 371 #define OB_WRP1_PAGES16TO31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
<> 144:ef7eb2e8f9f7 372 #define OB_WRP1_PAGES32TO47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
<> 144:ef7eb2e8f9f7 373 #define OB_WRP1_PAGES48TO63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
<> 144:ef7eb2e8f9f7 374 #define OB_WRP1_PAGES64TO79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
<> 144:ef7eb2e8f9f7 375 #define OB_WRP1_PAGES80TO95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
<> 144:ef7eb2e8f9f7 376 #define OB_WRP1_PAGES96TO111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
<> 144:ef7eb2e8f9f7 377 #define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
<> 144:ef7eb2e8f9f7 378 #define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
<> 144:ef7eb2e8f9f7 379 #define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
<> 144:ef7eb2e8f9f7 380 #define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
<> 144:ef7eb2e8f9f7 381 #define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
<> 144:ef7eb2e8f9f7 382 #define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
<> 144:ef7eb2e8f9f7 383 #define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
<> 144:ef7eb2e8f9f7 384 #define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
<> 144:ef7eb2e8f9f7 385 #define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
<> 144:ef7eb2e8f9f7 386 #define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
<> 144:ef7eb2e8f9f7 387 #define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
<> 144:ef7eb2e8f9f7 388 #define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
<> 144:ef7eb2e8f9f7 389 #define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
<> 144:ef7eb2e8f9f7 390 #define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
<> 144:ef7eb2e8f9f7 391 #define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
<> 144:ef7eb2e8f9f7 392 #define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
<> 144:ef7eb2e8f9f7 393 #define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
<> 144:ef7eb2e8f9f7 394 #define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
<> 144:ef7eb2e8f9f7 395 #define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
<> 144:ef7eb2e8f9f7 396 #define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
<> 144:ef7eb2e8f9f7 397 #define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
<> 144:ef7eb2e8f9f7 398 #define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
<> 144:ef7eb2e8f9f7 399 #define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
<> 144:ef7eb2e8f9f7 400 #define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
<> 144:ef7eb2e8f9f7 401 #define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 #define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /**
<> 144:ef7eb2e8f9f7 406 * @}
<> 144:ef7eb2e8f9f7 407 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 144:ef7eb2e8f9f7 410 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
<> 144:ef7eb2e8f9f7 411 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
<> 144:ef7eb2e8f9f7 412 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Pages for Cat3, Cat4 & Cat5 devices*/
<> 144:ef7eb2e8f9f7 419 #define OB_WRP2_PAGES512TO527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
<> 144:ef7eb2e8f9f7 420 #define OB_WRP2_PAGES528TO543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
<> 144:ef7eb2e8f9f7 421 #define OB_WRP2_PAGES544TO559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
<> 144:ef7eb2e8f9f7 422 #define OB_WRP2_PAGES560TO575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
<> 144:ef7eb2e8f9f7 423 #define OB_WRP2_PAGES576TO591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
<> 144:ef7eb2e8f9f7 424 #define OB_WRP2_PAGES592TO607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
<> 144:ef7eb2e8f9f7 425 #define OB_WRP2_PAGES608TO623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
<> 144:ef7eb2e8f9f7 426 #define OB_WRP2_PAGES624TO639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
<> 144:ef7eb2e8f9f7 427 #define OB_WRP2_PAGES640TO655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
<> 144:ef7eb2e8f9f7 428 #define OB_WRP2_PAGES656TO671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
<> 144:ef7eb2e8f9f7 429 #define OB_WRP2_PAGES672TO687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
<> 144:ef7eb2e8f9f7 430 #define OB_WRP2_PAGES688TO703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
<> 144:ef7eb2e8f9f7 431 #define OB_WRP2_PAGES704TO719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
<> 144:ef7eb2e8f9f7 432 #define OB_WRP2_PAGES720TO735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
<> 144:ef7eb2e8f9f7 433 #define OB_WRP2_PAGES736TO751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
<> 144:ef7eb2e8f9f7 434 #define OB_WRP2_PAGES752TO767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
<> 144:ef7eb2e8f9f7 437 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
<> 144:ef7eb2e8f9f7 438 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 439 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #define OB_WRP2_PAGES768TO783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
<> 144:ef7eb2e8f9f7 442 #define OB_WRP2_PAGES784TO799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
<> 144:ef7eb2e8f9f7 443 #define OB_WRP2_PAGES800TO815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
<> 144:ef7eb2e8f9f7 444 #define OB_WRP2_PAGES816TO831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
<> 144:ef7eb2e8f9f7 445 #define OB_WRP2_PAGES832TO847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
<> 144:ef7eb2e8f9f7 446 #define OB_WRP2_PAGES848TO863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
<> 144:ef7eb2e8f9f7 447 #define OB_WRP2_PAGES864TO879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
<> 144:ef7eb2e8f9f7 448 #define OB_WRP2_PAGES880TO895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
<> 144:ef7eb2e8f9f7 449 #define OB_WRP2_PAGES896TO911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
<> 144:ef7eb2e8f9f7 450 #define OB_WRP2_PAGES912TO927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
<> 144:ef7eb2e8f9f7 451 #define OB_WRP2_PAGES928TO943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
<> 144:ef7eb2e8f9f7 452 #define OB_WRP2_PAGES944TO959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
<> 144:ef7eb2e8f9f7 453 #define OB_WRP2_PAGES960TO975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
<> 144:ef7eb2e8f9f7 454 #define OB_WRP2_PAGES976TO991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
<> 144:ef7eb2e8f9f7 455 #define OB_WRP2_PAGES992TO1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
<> 144:ef7eb2e8f9f7 456 #define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 #define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /**
<> 144:ef7eb2e8f9f7 463 * @}
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 469 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 470 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
<> 144:ef7eb2e8f9f7 473 * @{
<> 144:ef7eb2e8f9f7 474 */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /* Pages for devices with FLASH >= 256KB*/
<> 144:ef7eb2e8f9f7 477 #define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
<> 144:ef7eb2e8f9f7 478 #define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
<> 144:ef7eb2e8f9f7 479 #define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
<> 144:ef7eb2e8f9f7 480 #define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
<> 144:ef7eb2e8f9f7 481 #define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
<> 144:ef7eb2e8f9f7 482 #define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
<> 144:ef7eb2e8f9f7 483 #define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
<> 144:ef7eb2e8f9f7 484 #define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
<> 144:ef7eb2e8f9f7 485 #define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
<> 144:ef7eb2e8f9f7 486 #define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
<> 144:ef7eb2e8f9f7 487 #define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
<> 144:ef7eb2e8f9f7 488 #define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
<> 144:ef7eb2e8f9f7 489 #define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
<> 144:ef7eb2e8f9f7 490 #define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
<> 144:ef7eb2e8f9f7 491 #define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
<> 144:ef7eb2e8f9f7 492 #define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
<> 144:ef7eb2e8f9f7 493 #define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
<> 144:ef7eb2e8f9f7 494 #define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
<> 144:ef7eb2e8f9f7 495 #define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
<> 144:ef7eb2e8f9f7 496 #define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
<> 144:ef7eb2e8f9f7 497 #define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
<> 144:ef7eb2e8f9f7 498 #define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
<> 144:ef7eb2e8f9f7 499 #define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
<> 144:ef7eb2e8f9f7 500 #define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
<> 144:ef7eb2e8f9f7 501 #define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
<> 144:ef7eb2e8f9f7 502 #define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
<> 144:ef7eb2e8f9f7 503 #define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
<> 144:ef7eb2e8f9f7 504 #define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
<> 144:ef7eb2e8f9f7 505 #define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
<> 144:ef7eb2e8f9f7 506 #define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
<> 144:ef7eb2e8f9f7 507 #define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
<> 144:ef7eb2e8f9f7 508 #define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 #define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @}
<> 144:ef7eb2e8f9f7 514 */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
<> 144:ef7eb2e8f9f7 519 || defined(STM32L152xDX) || defined(STM32L162xDX)
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
<> 144:ef7eb2e8f9f7 522 * @{
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /* Pages for Cat5 devices*/
<> 144:ef7eb2e8f9f7 526 #define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/
<> 144:ef7eb2e8f9f7 527 #define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/
<> 144:ef7eb2e8f9f7 528 #define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/
<> 144:ef7eb2e8f9f7 529 #define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/
<> 144:ef7eb2e8f9f7 530 #define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/
<> 144:ef7eb2e8f9f7 531 #define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/
<> 144:ef7eb2e8f9f7 532 #define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/
<> 144:ef7eb2e8f9f7 533 #define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/
<> 144:ef7eb2e8f9f7 534 #define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/
<> 144:ef7eb2e8f9f7 535 #define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/
<> 144:ef7eb2e8f9f7 536 #define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/
<> 144:ef7eb2e8f9f7 537 #define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/
<> 144:ef7eb2e8f9f7 538 #define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/
<> 144:ef7eb2e8f9f7 539 #define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/
<> 144:ef7eb2e8f9f7 540 #define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/
<> 144:ef7eb2e8f9f7 541 #define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 #define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/
<> 144:ef7eb2e8f9f7 546 #define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/
<> 144:ef7eb2e8f9f7 547 #define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/
<> 144:ef7eb2e8f9f7 548 #define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/
<> 144:ef7eb2e8f9f7 549 #define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/
<> 144:ef7eb2e8f9f7 550 #define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/
<> 144:ef7eb2e8f9f7 551 #define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/
<> 144:ef7eb2e8f9f7 552 #define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/
<> 144:ef7eb2e8f9f7 553 #define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/
<> 144:ef7eb2e8f9f7 554 #define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/
<> 144:ef7eb2e8f9f7 555 #define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/
<> 144:ef7eb2e8f9f7 556 #define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/
<> 144:ef7eb2e8f9f7 557 #define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/
<> 144:ef7eb2e8f9f7 558 #define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/
<> 144:ef7eb2e8f9f7 559 #define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/
<> 144:ef7eb2e8f9f7 560 #define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000) /* Write protection of Sector127*/
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 #define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @}
<> 144:ef7eb2e8f9f7 568 */
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
<> 144:ef7eb2e8f9f7 573 * @{
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575 #define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
<> 144:ef7eb2e8f9f7 576 #define OB_RDP_LEVEL_1 ((uint8_t)0xBB)
<> 144:ef7eb2e8f9f7 577 #define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /* Warning: When enabling read protection level 2
<> 144:ef7eb2e8f9f7 578 it's no more possible to go back to level 1 or 0 */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
<> 144:ef7eb2e8f9f7 585 * @{
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
<> 144:ef7eb2e8f9f7 589 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
<> 144:ef7eb2e8f9f7 590 #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
<> 144:ef7eb2e8f9f7 591 #define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
<> 144:ef7eb2e8f9f7 592 #define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
<> 144:ef7eb2e8f9f7 593 #define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
<> 144:ef7eb2e8f9f7 594 #define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /**
<> 144:ef7eb2e8f9f7 597 * @}
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
<> 144:ef7eb2e8f9f7 601 * @{
<> 144:ef7eb2e8f9f7 602 */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 #define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
<> 144:ef7eb2e8f9f7 605 #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @}
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
<> 144:ef7eb2e8f9f7 612 * @{
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 #define OB_STOP_NORST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 616 #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @}
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
<> 144:ef7eb2e8f9f7 622 * @{
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 #define OB_STDBY_NORST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 626 #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /**
<> 144:ef7eb2e8f9f7 629 * @}
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 633 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
<> 144:ef7eb2e8f9f7 636 * @{
<> 144:ef7eb2e8f9f7 637 */
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 #define OPTIONBYTE_PCROP ((uint32_t)0x01) /*!<PCROP option byte configuration*/
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /**
<> 144:ef7eb2e8f9f7 642 * @}
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 648 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 649 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
<> 144:ef7eb2e8f9f7 652 * @{
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02) /*!<BOOTConfig option byte configuration*/
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @}
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 664 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
<> 144:ef7eb2e8f9f7 667 * @{
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669 #define OB_PCROP_STATE_DISABLE ((uint32_t)0x00) /*!<Disable PCROP for selected sectors */
<> 144:ef7eb2e8f9f7 670 #define OB_PCROP_STATE_ENABLE ((uint32_t)0x01) /*!<Enable PCROP for selected sectors */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /**
<> 144:ef7eb2e8f9f7 673 * @}
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
<> 144:ef7eb2e8f9f7 677 * @{
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 #define OB_PCROP_DESELECTED ((uint16_t)0x0000) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
<> 144:ef7eb2e8f9f7 680 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /**
<> 144:ef7eb2e8f9f7 683 * @}
<> 144:ef7eb2e8f9f7 684 */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
<> 144:ef7eb2e8f9f7 687 * @{
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
<> 144:ef7eb2e8f9f7 691 #define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector0 */
<> 144:ef7eb2e8f9f7 692 #define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector1 */
<> 144:ef7eb2e8f9f7 693 #define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector2 */
<> 144:ef7eb2e8f9f7 694 #define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector3 */
<> 144:ef7eb2e8f9f7 695 #define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector4 */
<> 144:ef7eb2e8f9f7 696 #define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector5 */
<> 144:ef7eb2e8f9f7 697 #define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector6 */
<> 144:ef7eb2e8f9f7 698 #define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector7 */
<> 144:ef7eb2e8f9f7 699 #define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector8 */
<> 144:ef7eb2e8f9f7 700 #define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector9 */
<> 144:ef7eb2e8f9f7 701 #define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector10 */
<> 144:ef7eb2e8f9f7 702 #define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector11 */
<> 144:ef7eb2e8f9f7 703 #define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector12 */
<> 144:ef7eb2e8f9f7 704 #define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector13 */
<> 144:ef7eb2e8f9f7 705 #define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector14 */
<> 144:ef7eb2e8f9f7 706 #define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector15 */
<> 144:ef7eb2e8f9f7 707 #define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000) /* PC Read/Write protection of Sector16 */
<> 144:ef7eb2e8f9f7 708 #define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000) /* PC Read/Write protection of Sector17 */
<> 144:ef7eb2e8f9f7 709 #define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000) /* PC Read/Write protection of Sector18 */
<> 144:ef7eb2e8f9f7 710 #define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000) /* PC Read/Write protection of Sector19 */
<> 144:ef7eb2e8f9f7 711 #define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000) /* PC Read/Write protection of Sector20 */
<> 144:ef7eb2e8f9f7 712 #define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000) /* PC Read/Write protection of Sector21 */
<> 144:ef7eb2e8f9f7 713 #define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000) /* PC Read/Write protection of Sector22 */
<> 144:ef7eb2e8f9f7 714 #define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000) /* PC Read/Write protection of Sector23 */
<> 144:ef7eb2e8f9f7 715 #define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000) /* PC Read/Write protection of Sector24 */
<> 144:ef7eb2e8f9f7 716 #define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000) /* PC Read/Write protection of Sector25 */
<> 144:ef7eb2e8f9f7 717 #define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000) /* PC Read/Write protection of Sector26 */
<> 144:ef7eb2e8f9f7 718 #define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000) /* PC Read/Write protection of Sector27 */
<> 144:ef7eb2e8f9f7 719 #define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000) /* PC Read/Write protection of Sector28 */
<> 144:ef7eb2e8f9f7 720 #define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000) /* PC Read/Write protection of Sector29 */
<> 144:ef7eb2e8f9f7 721 #define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000) /* PC Read/Write protection of Sector30 */
<> 144:ef7eb2e8f9f7 722 #define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000) /* PC Read/Write protection of Sector31 */
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 #define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @}
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
<> 144:ef7eb2e8f9f7 735 * @{
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Pages for Cat3, Cat4 & Cat5 devices*/
<> 144:ef7eb2e8f9f7 739 #define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector32 */
<> 144:ef7eb2e8f9f7 740 #define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector33 */
<> 144:ef7eb2e8f9f7 741 #define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector34 */
<> 144:ef7eb2e8f9f7 742 #define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector35 */
<> 144:ef7eb2e8f9f7 743 #define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector36 */
<> 144:ef7eb2e8f9f7 744 #define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector37 */
<> 144:ef7eb2e8f9f7 745 #define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector38 */
<> 144:ef7eb2e8f9f7 746 #define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector39 */
<> 144:ef7eb2e8f9f7 747 #define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector40 */
<> 144:ef7eb2e8f9f7 748 #define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector41 */
<> 144:ef7eb2e8f9f7 749 #define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector42 */
<> 144:ef7eb2e8f9f7 750 #define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector43 */
<> 144:ef7eb2e8f9f7 751 #define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector44 */
<> 144:ef7eb2e8f9f7 752 #define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector45 */
<> 144:ef7eb2e8f9f7 753 #define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector46 */
<> 144:ef7eb2e8f9f7 754 #define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector47 */
<> 144:ef7eb2e8f9f7 755 #define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000) /* PC Read/Write protection of Sector48 */
<> 144:ef7eb2e8f9f7 756 #define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000) /* PC Read/Write protection of Sector49 */
<> 144:ef7eb2e8f9f7 757 #define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000) /* PC Read/Write protection of Sector50 */
<> 144:ef7eb2e8f9f7 758 #define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000) /* PC Read/Write protection of Sector51 */
<> 144:ef7eb2e8f9f7 759 #define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000) /* PC Read/Write protection of Sector52 */
<> 144:ef7eb2e8f9f7 760 #define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000) /* PC Read/Write protection of Sector53 */
<> 144:ef7eb2e8f9f7 761 #define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000) /* PC Read/Write protection of Sector54 */
<> 144:ef7eb2e8f9f7 762 #define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000) /* PC Read/Write protection of Sector55 */
<> 144:ef7eb2e8f9f7 763 #define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000) /* PC Read/Write protection of Sector56 */
<> 144:ef7eb2e8f9f7 764 #define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000) /* PC Read/Write protection of Sector57 */
<> 144:ef7eb2e8f9f7 765 #define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000) /* PC Read/Write protection of Sector58 */
<> 144:ef7eb2e8f9f7 766 #define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000) /* PC Read/Write protection of Sector59 */
<> 144:ef7eb2e8f9f7 767 #define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000) /* PC Read/Write protection of Sector60 */
<> 144:ef7eb2e8f9f7 768 #define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000) /* PC Read/Write protection of Sector61 */
<> 144:ef7eb2e8f9f7 769 #define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000) /* PC Read/Write protection of Sector62 */
<> 144:ef7eb2e8f9f7 770 #define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* PC Read/Write protection of Sector63 */
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 #define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write protection of all Sectors */
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @}
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
<> 144:ef7eb2e8f9f7 781 * @{
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 #define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00) /*!<Erase byte (8-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 784 #define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01) /*!<Erase a half-word (16-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 785 #define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02) /*!<Erase a word (32-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @}
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
<> 144:ef7eb2e8f9f7 792 * @{
<> 144:ef7eb2e8f9f7 793 */
<> 144:ef7eb2e8f9f7 794 #define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00) /*!<Program byte (8-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 795 #define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01) /*!<Program a half-word (16-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 796 #define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02) /*!<Program a word (32-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 797 #define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04) /*!<Fast Program byte (8-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 798 #define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08) /*!<Fast Program a half-word (16-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 799 #define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10) /*!<Fast Program a word (32-bit) at a specified address.*/
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /**
<> 144:ef7eb2e8f9f7 802 * @}
<> 144:ef7eb2e8f9f7 803 */
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /** @defgroup FLASHEx_Flags FLASHEx Flags
<> 144:ef7eb2e8f9f7 806 * @{
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /* Cat2 & Cat3*/
<> 144:ef7eb2e8f9f7 810 #if defined(FLASH_SR_RDERR)
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read protected error flag */
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 #endif /* FLASH_SR_RDERR */
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /* Cat3, Cat4 & Cat5*/
<> 144:ef7eb2e8f9f7 817 #if defined(FLASH_SR_OPTVERRUSR)
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 #define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #endif /* FLASH_SR_OPTVERRUSR */
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /**
<> 144:ef7eb2e8f9f7 824 * @}
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
<> 144:ef7eb2e8f9f7 828 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
<> 144:ef7eb2e8f9f7 829 || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
<> 144:ef7eb2e8f9f7 832 * @{
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 #define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
<> 144:ef7eb2e8f9f7 836 and this parameter is selected the device will boot from Bank 2
<> 144:ef7eb2e8f9f7 837 or Bank 1, depending on the activation of the bank */
<> 144:ef7eb2e8f9f7 838 #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
<> 144:ef7eb2e8f9f7 839 and this parameter is selected the device will boot from Bank1(Default) */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @}
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /**
<> 144:ef7eb2e8f9f7 847 * @}
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /** @defgroup FLASHEx_Exported_Macros Exported Macros
<> 144:ef7eb2e8f9f7 853 * @{
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /**
<> 144:ef7eb2e8f9f7 857 * @brief Set the FLASH Latency.
<> 144:ef7eb2e8f9f7 858 * @param __LATENCY__ FLASH Latency
<> 144:ef7eb2e8f9f7 859 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 860 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
<> 144:ef7eb2e8f9f7 861 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
<> 144:ef7eb2e8f9f7 862 * @retval none
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
<> 144:ef7eb2e8f9f7 865 if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
<> 144:ef7eb2e8f9f7 866 MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
<> 144:ef7eb2e8f9f7 867 } while(0)
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /**
<> 144:ef7eb2e8f9f7 870 * @brief Get the FLASH Latency.
<> 144:ef7eb2e8f9f7 871 * @retval FLASH Latency
<> 144:ef7eb2e8f9f7 872 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 873 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
<> 144:ef7eb2e8f9f7 874 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
<> 144:ef7eb2e8f9f7 875 */
<> 144:ef7eb2e8f9f7 876 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /**
<> 144:ef7eb2e8f9f7 879 * @brief Enable the FLASH 64-bit access.
<> 144:ef7eb2e8f9f7 880 * @note Read access 64 bit is used.
<> 144:ef7eb2e8f9f7 881 * @note This bit cannot be written at the same time as the LATENCY and
<> 144:ef7eb2e8f9f7 882 * PRFTEN bits.
<> 144:ef7eb2e8f9f7 883 * @retval none
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885 #define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /**
<> 144:ef7eb2e8f9f7 888 * @brief Disable the FLASH 64-bit access.
<> 144:ef7eb2e8f9f7 889 * @note Read access 32 bit is used
<> 144:ef7eb2e8f9f7 890 * @note To reset this bit, the LATENCY should be zero wait state and the
<> 144:ef7eb2e8f9f7 891 * prefetch off.
<> 144:ef7eb2e8f9f7 892 * @retval none
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 #define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /**
<> 144:ef7eb2e8f9f7 897 * @brief Enable the FLASH prefetch buffer.
<> 144:ef7eb2e8f9f7 898 * @retval none
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
<> 144:ef7eb2e8f9f7 901 SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
<> 144:ef7eb2e8f9f7 902 } while(0)
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @brief Disable the FLASH prefetch buffer.
<> 144:ef7eb2e8f9f7 906 * @retval none
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /**
<> 144:ef7eb2e8f9f7 911 * @brief Enable the FLASH power down during Sleep mode
<> 144:ef7eb2e8f9f7 912 * @retval none
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @brief Disable the FLASH power down during Sleep mode
<> 144:ef7eb2e8f9f7 918 * @retval none
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /**
<> 144:ef7eb2e8f9f7 923 * @brief Macro to enable or disable the Flash Run power down mode.
<> 144:ef7eb2e8f9f7 924 * @note Writing this bit to 0 this bit, automatically the keys are
<> 144:ef7eb2e8f9f7 925 * loss and a new unlock sequence is necessary to re-write it to 1.
<> 144:ef7eb2e8f9f7 926 */
<> 144:ef7eb2e8f9f7 927
<> 144:ef7eb2e8f9f7 928 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 144:ef7eb2e8f9f7 929 FLASH->PDKEYR = FLASH_PDKEY2; \
<> 144:ef7eb2e8f9f7 930 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 931 } while (0)
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
<> 144:ef7eb2e8f9f7 934 FLASH->PDKEYR = FLASH_PDKEY2; \
<> 144:ef7eb2e8f9f7 935 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
<> 144:ef7eb2e8f9f7 936 } while (0)
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /**
<> 144:ef7eb2e8f9f7 939 * @}
<> 144:ef7eb2e8f9f7 940 */
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /** @addtogroup FLASHEx_Exported_Functions
<> 144:ef7eb2e8f9f7 945 * @{
<> 144:ef7eb2e8f9f7 946 */
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /** @addtogroup FLASHEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 949 * @{
<> 144:ef7eb2e8f9f7 950 */
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
<> 144:ef7eb2e8f9f7 953 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /**
<> 144:ef7eb2e8f9f7 956 * @}
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /** @addtogroup FLASHEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 960 * @{
<> 144:ef7eb2e8f9f7 961 */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 964 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
<> 144:ef7eb2e8f9f7 965
<> 144:ef7eb2e8f9f7 966 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 967 || defined(STM32L162xC) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) \
<> 144:ef7eb2e8f9f7 968 || defined(STM32L152xDX) || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) \
<> 144:ef7eb2e8f9f7 969 || defined(STM32L152xE) || defined(STM32L162xE)
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
<> 144:ef7eb2e8f9f7 972 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
<> 144:ef7eb2e8f9f7 977 || defined(STM32L162xC)
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
<> 144:ef7eb2e8f9f7 980 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 /**
<> 144:ef7eb2e8f9f7 985 * @}
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /** @addtogroup FLASHEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 989 * @{
<> 144:ef7eb2e8f9f7 990 */
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
<> 144:ef7eb2e8f9f7 993 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
<> 144:ef7eb2e8f9f7 996 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
<> 144:ef7eb2e8f9f7 997 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
<> 144:ef7eb2e8f9f7 998 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /**
<> 144:ef7eb2e8f9f7 1001 * @}
<> 144:ef7eb2e8f9f7 1002 */
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /**
<> 144:ef7eb2e8f9f7 1005 * @}
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /**
<> 144:ef7eb2e8f9f7 1009 * @}
<> 144:ef7eb2e8f9f7 1010 */
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @}
<> 144:ef7eb2e8f9f7 1014 */
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 #endif
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 #endif /* __STM32L1xx_HAL_FLASH_EX_H */
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/