Toyomasa Watarai / easy-connect-type-yd

Easily add all supported connectivity methods to your mbed OS project

Dependencies:   type-yd-driver

stm-spirit1-rf-driver/source/radio_spi.cpp@0:615f90842ce8, 2017-07-12 (annotated)

Committer:
MACRUM
Date:
Wed Jul 12 10:52:58 2017 +0000
Revision:
0:615f90842ce8
Initial commit

Who changed what in which revision?

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MACRUM 0:615f90842ce8 1 /**
MACRUM 0:615f90842ce8 2 ******************************************************************************
MACRUM 0:615f90842ce8 3 * @file radio_spi.c
MACRUM 0:615f90842ce8 4 * @author System Lab - NOIDA
MACRUM 0:615f90842ce8 5 * @version V1.0.0
MACRUM 0:615f90842ce8 6 * @date 15-May-2014
MACRUM 0:615f90842ce8 7 * @brief This file provides code for the configuration of the SPI instances.
MACRUM 0:615f90842ce8 8 ******************************************************************************
MACRUM 0:615f90842ce8 9 * @attention
MACRUM 0:615f90842ce8 10 *
MACRUM 0:615f90842ce8 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
MACRUM 0:615f90842ce8 12 *
MACRUM 0:615f90842ce8 13 * Redistribution and use in source and binary forms, with or without modification,
MACRUM 0:615f90842ce8 14 * are permitted provided that the following conditions are met:
MACRUM 0:615f90842ce8 15 * 1. Redistributions of source code must retain the above copyright notice,
MACRUM 0:615f90842ce8 16 * this list of conditions and the following disclaimer.
MACRUM 0:615f90842ce8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
MACRUM 0:615f90842ce8 18 * this list of conditions and the following disclaimer in the documentation
MACRUM 0:615f90842ce8 19 * and/or other materials provided with the distribution.
MACRUM 0:615f90842ce8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
MACRUM 0:615f90842ce8 21 * may be used to endorse or promote products derived from this software
MACRUM 0:615f90842ce8 22 * without specific prior written permission.
MACRUM 0:615f90842ce8 23 *
MACRUM 0:615f90842ce8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM 0:615f90842ce8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM 0:615f90842ce8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
MACRUM 0:615f90842ce8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
MACRUM 0:615f90842ce8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
MACRUM 0:615f90842ce8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
MACRUM 0:615f90842ce8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
MACRUM 0:615f90842ce8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
MACRUM 0:615f90842ce8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
MACRUM 0:615f90842ce8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MACRUM 0:615f90842ce8 34 *
MACRUM 0:615f90842ce8 35 ******************************************************************************
MACRUM 0:615f90842ce8 36 */
MACRUM 0:615f90842ce8 37
MACRUM 0:615f90842ce8 38
MACRUM 0:615f90842ce8 39 /* Includes ------------------------------------------------------------------*/
MACRUM 0:615f90842ce8 40 #include "radio_spi.h"
MACRUM 0:615f90842ce8 41
MACRUM 0:615f90842ce8 42 #include "SimpleSpirit1.h"
MACRUM 0:615f90842ce8 43
MACRUM 0:615f90842ce8 44
MACRUM 0:615f90842ce8 45 /**
MACRUM 0:615f90842ce8 46 * @addtogroup BSP
MACRUM 0:615f90842ce8 47 * @{
MACRUM 0:615f90842ce8 48 */
MACRUM 0:615f90842ce8 49
MACRUM 0:615f90842ce8 50
MACRUM 0:615f90842ce8 51 /**
MACRUM 0:615f90842ce8 52 * @addtogroup X-NUCLEO-IDS02Ax
MACRUM 0:615f90842ce8 53 * @{
MACRUM 0:615f90842ce8 54 */
MACRUM 0:615f90842ce8 55
MACRUM 0:615f90842ce8 56
MACRUM 0:615f90842ce8 57 /**
MACRUM 0:615f90842ce8 58 * @defgroup RADIO_SPI_Private_TypesDefinitions RADIO_SPI Private Types Definitions
MACRUM 0:615f90842ce8 59 * @{
MACRUM 0:615f90842ce8 60 */
MACRUM 0:615f90842ce8 61
MACRUM 0:615f90842ce8 62 /**
MACRUM 0:615f90842ce8 63 * @}
MACRUM 0:615f90842ce8 64 */
MACRUM 0:615f90842ce8 65
MACRUM 0:615f90842ce8 66
MACRUM 0:615f90842ce8 67 /**
MACRUM 0:615f90842ce8 68 * @defgroup RADIO_SPI_Private_Defines RADIO_SPI Private Defines
MACRUM 0:615f90842ce8 69 * @{
MACRUM 0:615f90842ce8 70 */
MACRUM 0:615f90842ce8 71
MACRUM 0:615f90842ce8 72 /**
MACRUM 0:615f90842ce8 73 * @}
MACRUM 0:615f90842ce8 74 */
MACRUM 0:615f90842ce8 75
MACRUM 0:615f90842ce8 76
MACRUM 0:615f90842ce8 77 /**
MACRUM 0:615f90842ce8 78 * @defgroup RADIO_SPI_Private_Macros RADIO_SPI Private Macros
MACRUM 0:615f90842ce8 79 * @{
MACRUM 0:615f90842ce8 80 */
MACRUM 0:615f90842ce8 81
MACRUM 0:615f90842ce8 82 /**
MACRUM 0:615f90842ce8 83 * @}
MACRUM 0:615f90842ce8 84 */
MACRUM 0:615f90842ce8 85
MACRUM 0:615f90842ce8 86
MACRUM 0:615f90842ce8 87 /**
MACRUM 0:615f90842ce8 88 * @defgroup RADIO_SPI_Private_Variables RADIO_SPI Private Variables
MACRUM 0:615f90842ce8 89 * @{
MACRUM 0:615f90842ce8 90 */
MACRUM 0:615f90842ce8 91
MACRUM 0:615f90842ce8 92 /**
MACRUM 0:615f90842ce8 93 * @}
MACRUM 0:615f90842ce8 94 */
MACRUM 0:615f90842ce8 95
MACRUM 0:615f90842ce8 96
MACRUM 0:615f90842ce8 97 /**
MACRUM 0:615f90842ce8 98 * @defgroup RADIO_SPI_Private_FunctionPrototypes RADIO_SPI Private Function Prototypes
MACRUM 0:615f90842ce8 99 * @{
MACRUM 0:615f90842ce8 100 */
MACRUM 0:615f90842ce8 101
MACRUM 0:615f90842ce8 102 /**
MACRUM 0:615f90842ce8 103 * @}
MACRUM 0:615f90842ce8 104 */
MACRUM 0:615f90842ce8 105
MACRUM 0:615f90842ce8 106 /**
MACRUM 0:615f90842ce8 107 * @defgroup RADIO_SPI_Private_Functions RADIO_SPI Private Functions
MACRUM 0:615f90842ce8 108 * @{
MACRUM 0:615f90842ce8 109 */
MACRUM 0:615f90842ce8 110
MACRUM 0:615f90842ce8 111 /**
MACRUM 0:615f90842ce8 112 * @}
MACRUM 0:615f90842ce8 113 */
MACRUM 0:615f90842ce8 114
MACRUM 0:615f90842ce8 115 /**
MACRUM 0:615f90842ce8 116 * @brief Write single or multiple RF Transceivers register
MACRUM 0:615f90842ce8 117 * @param cRegAddress: base register's address to be write
MACRUM 0:615f90842ce8 118 * @param cNbBytes: number of registers and bytes to be write
MACRUM 0:615f90842ce8 119 * @param pcBuffer: pointer to the buffer of values have to be written into registers
MACRUM 0:615f90842ce8 120 * @retval StatusBytes
MACRUM 0:615f90842ce8 121 */
MACRUM 0:615f90842ce8 122 StatusBytes SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 123 {
MACRUM 0:615f90842ce8 124 return SimpleSpirit1::Instance().SdkEvalSpiWriteRegisters(cRegAddress, cNbBytes, pcBuffer);
MACRUM 0:615f90842ce8 125 }
MACRUM 0:615f90842ce8 126
MACRUM 0:615f90842ce8 127 StatusBytes SimpleSpirit1::SdkEvalSpiWriteRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 128 {
MACRUM 0:615f90842ce8 129 uint8_t aHeader[2] = {0};
MACRUM 0:615f90842ce8 130 uint16_t tmpstatus = 0x0000;
MACRUM 0:615f90842ce8 131 StatusBytes *pStatus=(StatusBytes *)&tmpstatus;
MACRUM 0:615f90842ce8 132
MACRUM 0:615f90842ce8 133 /* Built the aHeader bytes */
MACRUM 0:615f90842ce8 134 aHeader[0] = WRITE_HEADER;
MACRUM 0:615f90842ce8 135 aHeader[1] = cRegAddress;
MACRUM 0:615f90842ce8 136
MACRUM 0:615f90842ce8 137 /* Puts the SPI chip select low to start the transaction */
MACRUM 0:615f90842ce8 138 chip_sync_select();
MACRUM 0:615f90842ce8 139
MACRUM 0:615f90842ce8 140 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 141 tmpstatus = _spi.write(aHeader[0]);
MACRUM 0:615f90842ce8 142 tmpstatus = tmpstatus << 8;
MACRUM 0:615f90842ce8 143
MACRUM 0:615f90842ce8 144 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 145 tmpstatus |= _spi.write(aHeader[1]);
MACRUM 0:615f90842ce8 146
MACRUM 0:615f90842ce8 147 /* Writes the registers according to the number of bytes */
MACRUM 0:615f90842ce8 148 for (int index = 0; index < cNbBytes; index++)
MACRUM 0:615f90842ce8 149 {
MACRUM 0:615f90842ce8 150 _spi.write(pcBuffer[index]);
MACRUM 0:615f90842ce8 151 }
MACRUM 0:615f90842ce8 152
MACRUM 0:615f90842ce8 153 /* Puts the SPI chip select high to end the transaction */
MACRUM 0:615f90842ce8 154 chip_sync_unselect();
MACRUM 0:615f90842ce8 155
MACRUM 0:615f90842ce8 156 return *pStatus;
MACRUM 0:615f90842ce8 157 }
MACRUM 0:615f90842ce8 158
MACRUM 0:615f90842ce8 159
MACRUM 0:615f90842ce8 160 /**
MACRUM 0:615f90842ce8 161 * @brief Read single or multiple SPIRIT1 register
MACRUM 0:615f90842ce8 162 * @param cRegAddress: base register's address to be read
MACRUM 0:615f90842ce8 163 * @param cNbBytes: number of registers and bytes to be read
MACRUM 0:615f90842ce8 164 * @param pcBuffer: pointer to the buffer of registers' values read
MACRUM 0:615f90842ce8 165 * @retval StatusBytes
MACRUM 0:615f90842ce8 166 */
MACRUM 0:615f90842ce8 167 StatusBytes SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 168 {
MACRUM 0:615f90842ce8 169 return SimpleSpirit1::Instance().SdkEvalSpiReadRegisters(cRegAddress, cNbBytes, pcBuffer);
MACRUM 0:615f90842ce8 170 }
MACRUM 0:615f90842ce8 171
MACRUM 0:615f90842ce8 172 StatusBytes SimpleSpirit1::SdkEvalSpiReadRegisters(uint8_t cRegAddress, uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 173 {
MACRUM 0:615f90842ce8 174 uint16_t tmpstatus = 0x00;
MACRUM 0:615f90842ce8 175 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
MACRUM 0:615f90842ce8 176
MACRUM 0:615f90842ce8 177 uint8_t aHeader[2] = {0};
MACRUM 0:615f90842ce8 178
MACRUM 0:615f90842ce8 179 /* Built the aHeader bytes */
MACRUM 0:615f90842ce8 180 aHeader[0] = READ_HEADER;
MACRUM 0:615f90842ce8 181 aHeader[1] = cRegAddress;
MACRUM 0:615f90842ce8 182
MACRUM 0:615f90842ce8 183 /* Put the SPI chip select low to start the transaction */
MACRUM 0:615f90842ce8 184 chip_sync_select();
MACRUM 0:615f90842ce8 185
MACRUM 0:615f90842ce8 186 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 187 tmpstatus = _spi.write(aHeader[0]);
MACRUM 0:615f90842ce8 188 tmpstatus = tmpstatus << 8;
MACRUM 0:615f90842ce8 189
MACRUM 0:615f90842ce8 190 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 191 tmpstatus |= _spi.write(aHeader[1]);
MACRUM 0:615f90842ce8 192
MACRUM 0:615f90842ce8 193 for (int index = 0; index < cNbBytes; index++)
MACRUM 0:615f90842ce8 194 {
MACRUM 0:615f90842ce8 195 pcBuffer[index] = _spi.write(0xFF);
MACRUM 0:615f90842ce8 196 }
MACRUM 0:615f90842ce8 197
MACRUM 0:615f90842ce8 198 /* Put the SPI chip select high to end the transaction */
MACRUM 0:615f90842ce8 199 chip_sync_unselect();
MACRUM 0:615f90842ce8 200
MACRUM 0:615f90842ce8 201 return *pStatus;
MACRUM 0:615f90842ce8 202 }
MACRUM 0:615f90842ce8 203
MACRUM 0:615f90842ce8 204
MACRUM 0:615f90842ce8 205 /**
MACRUM 0:615f90842ce8 206 * @brief Send a command
MACRUM 0:615f90842ce8 207 * @param cCommandCode: command code to be sent
MACRUM 0:615f90842ce8 208 * @retval StatusBytes
MACRUM 0:615f90842ce8 209 */
MACRUM 0:615f90842ce8 210 StatusBytes SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
MACRUM 0:615f90842ce8 211 {
MACRUM 0:615f90842ce8 212 return SimpleSpirit1::Instance().SdkEvalSpiCommandStrobes(cCommandCode);
MACRUM 0:615f90842ce8 213 }
MACRUM 0:615f90842ce8 214
MACRUM 0:615f90842ce8 215 StatusBytes SimpleSpirit1::SdkEvalSpiCommandStrobes(uint8_t cCommandCode)
MACRUM 0:615f90842ce8 216 {
MACRUM 0:615f90842ce8 217 uint8_t aHeader[2] = {0};
MACRUM 0:615f90842ce8 218 uint16_t tmpstatus = 0x0000;
MACRUM 0:615f90842ce8 219
MACRUM 0:615f90842ce8 220 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
MACRUM 0:615f90842ce8 221
MACRUM 0:615f90842ce8 222 /* Built the aHeader bytes */
MACRUM 0:615f90842ce8 223 aHeader[0] = COMMAND_HEADER;
MACRUM 0:615f90842ce8 224 aHeader[1] = cCommandCode;
MACRUM 0:615f90842ce8 225
MACRUM 0:615f90842ce8 226 /* Puts the SPI chip select low to start the transaction */
MACRUM 0:615f90842ce8 227 chip_sync_select();
MACRUM 0:615f90842ce8 228
MACRUM 0:615f90842ce8 229 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 230 tmpstatus = _spi.write(aHeader[0]);
MACRUM 0:615f90842ce8 231 tmpstatus = tmpstatus<<8;
MACRUM 0:615f90842ce8 232
MACRUM 0:615f90842ce8 233 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 234 tmpstatus |= _spi.write(aHeader[1]);
MACRUM 0:615f90842ce8 235
MACRUM 0:615f90842ce8 236 /* Puts the SPI chip select high to end the transaction */
MACRUM 0:615f90842ce8 237 chip_sync_unselect();
MACRUM 0:615f90842ce8 238
MACRUM 0:615f90842ce8 239 return *pStatus;
MACRUM 0:615f90842ce8 240 }
MACRUM 0:615f90842ce8 241
MACRUM 0:615f90842ce8 242
MACRUM 0:615f90842ce8 243 /**
MACRUM 0:615f90842ce8 244 * @brief Write data into TX FIFO
MACRUM 0:615f90842ce8 245 * @param cNbBytes: number of bytes to be written into TX FIFO
MACRUM 0:615f90842ce8 246 * @param pcBuffer: pointer to data to write
MACRUM 0:615f90842ce8 247 * @retval StatusBytes
MACRUM 0:615f90842ce8 248 */
MACRUM 0:615f90842ce8 249 StatusBytes SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 250 {
MACRUM 0:615f90842ce8 251 return SimpleSpirit1::Instance().SdkEvalSpiWriteFifo(cNbBytes, pcBuffer);
MACRUM 0:615f90842ce8 252 }
MACRUM 0:615f90842ce8 253
MACRUM 0:615f90842ce8 254 StatusBytes SimpleSpirit1::SdkEvalSpiWriteFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 255 {
MACRUM 0:615f90842ce8 256 uint16_t tmpstatus = 0x0000;
MACRUM 0:615f90842ce8 257 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
MACRUM 0:615f90842ce8 258
MACRUM 0:615f90842ce8 259 uint8_t aHeader[2] = {0};
MACRUM 0:615f90842ce8 260
MACRUM 0:615f90842ce8 261 /* Built the aHeader bytes */
MACRUM 0:615f90842ce8 262 aHeader[0] = WRITE_HEADER;
MACRUM 0:615f90842ce8 263 aHeader[1] = LINEAR_FIFO_ADDRESS;
MACRUM 0:615f90842ce8 264
MACRUM 0:615f90842ce8 265 /* Put the SPI chip select low to start the transaction */
MACRUM 0:615f90842ce8 266 chip_sync_select();
MACRUM 0:615f90842ce8 267
MACRUM 0:615f90842ce8 268 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 269 tmpstatus = _spi.write(aHeader[0]);
MACRUM 0:615f90842ce8 270 tmpstatus = tmpstatus<<8;
MACRUM 0:615f90842ce8 271
MACRUM 0:615f90842ce8 272 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 273 tmpstatus |= _spi.write(aHeader[1]);
MACRUM 0:615f90842ce8 274
MACRUM 0:615f90842ce8 275 /* Writes the registers according to the number of bytes */
MACRUM 0:615f90842ce8 276 for (int index = 0; index < cNbBytes; index++)
MACRUM 0:615f90842ce8 277 {
MACRUM 0:615f90842ce8 278 _spi.write(pcBuffer[index]);
MACRUM 0:615f90842ce8 279 }
MACRUM 0:615f90842ce8 280
MACRUM 0:615f90842ce8 281 /* Put the SPI chip select high to end the transaction */
MACRUM 0:615f90842ce8 282 chip_sync_unselect();
MACRUM 0:615f90842ce8 283
MACRUM 0:615f90842ce8 284 return *pStatus;
MACRUM 0:615f90842ce8 285 }
MACRUM 0:615f90842ce8 286
MACRUM 0:615f90842ce8 287 /**
MACRUM 0:615f90842ce8 288 * @brief Read data from RX FIFO
MACRUM 0:615f90842ce8 289 * @param cNbBytes: number of bytes to read from RX FIFO
MACRUM 0:615f90842ce8 290 * @param pcBuffer: pointer to data read from RX FIFO
MACRUM 0:615f90842ce8 291 * @retval StatusBytes
MACRUM 0:615f90842ce8 292 */
MACRUM 0:615f90842ce8 293 StatusBytes SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 294 {
MACRUM 0:615f90842ce8 295 return SimpleSpirit1::Instance().SdkEvalSpiReadFifo(cNbBytes, pcBuffer);
MACRUM 0:615f90842ce8 296 }
MACRUM 0:615f90842ce8 297
MACRUM 0:615f90842ce8 298 StatusBytes SimpleSpirit1::SdkEvalSpiReadFifo(uint8_t cNbBytes, uint8_t* pcBuffer)
MACRUM 0:615f90842ce8 299 {
MACRUM 0:615f90842ce8 300 uint16_t tmpstatus = 0x0000;
MACRUM 0:615f90842ce8 301 StatusBytes *pStatus = (StatusBytes *)&tmpstatus;
MACRUM 0:615f90842ce8 302
MACRUM 0:615f90842ce8 303 uint8_t aHeader[2];
MACRUM 0:615f90842ce8 304
MACRUM 0:615f90842ce8 305 /* Built the aHeader bytes */
MACRUM 0:615f90842ce8 306 aHeader[0]=READ_HEADER;
MACRUM 0:615f90842ce8 307 aHeader[1]=LINEAR_FIFO_ADDRESS;
MACRUM 0:615f90842ce8 308
MACRUM 0:615f90842ce8 309 /* Put the SPI chip select low to start the transaction */
MACRUM 0:615f90842ce8 310 chip_sync_select();
MACRUM 0:615f90842ce8 311
MACRUM 0:615f90842ce8 312 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 313 tmpstatus = _spi.write(aHeader[0]);
MACRUM 0:615f90842ce8 314 tmpstatus = tmpstatus<<8;
MACRUM 0:615f90842ce8 315
MACRUM 0:615f90842ce8 316 /* Write the aHeader bytes and read the SPIRIT1 status bytes */
MACRUM 0:615f90842ce8 317 tmpstatus |= _spi.write(aHeader[1]);
MACRUM 0:615f90842ce8 318
MACRUM 0:615f90842ce8 319 for (int index = 0; index < cNbBytes; index++)
MACRUM 0:615f90842ce8 320 {
MACRUM 0:615f90842ce8 321 pcBuffer[index] = _spi.write(0xFF);
MACRUM 0:615f90842ce8 322 }
MACRUM 0:615f90842ce8 323
MACRUM 0:615f90842ce8 324 /* Put the SPI chip select high to end the transaction */
MACRUM 0:615f90842ce8 325 chip_sync_unselect();
MACRUM 0:615f90842ce8 326
MACRUM 0:615f90842ce8 327 return *pStatus;
MACRUM 0:615f90842ce8 328 }
MACRUM 0:615f90842ce8 329
MACRUM 0:615f90842ce8 330
MACRUM 0:615f90842ce8 331 /**
MACRUM 0:615f90842ce8 332 * @}
MACRUM 0:615f90842ce8 333 */
MACRUM 0:615f90842ce8 334
MACRUM 0:615f90842ce8 335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/