easy-connect-type-yd - Easily add all supported connectivity methods to …

Users » MACRUM » Code » easy-connect-type-yd

Easily add all supported connectivity methods to your mbed OS project

stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:615f90842ce8, 2017-07-12 (annotated)

Committer:: MACRUM
Date:: Wed Jul 12 10:52:58 2017 +0000
Revision:: 0:615f90842ce8

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
MACRUM	0:615f90842ce8	1	/**
MACRUM	0:615f90842ce8	2	******************************************************************************
MACRUM	0:615f90842ce8	3	* @file SPIRIT_Regs.h
MACRUM	0:615f90842ce8	4	* @author VMA division - AMS
MACRUM	0:615f90842ce8	5	* @version 3.2.2
MACRUM	0:615f90842ce8	6	* @date 08-July-2015
MACRUM	0:615f90842ce8	7	* @brief This file contains all the SPIRIT registers address and masks.
MACRUM	0:615f90842ce8	8	* @details
MACRUM	0:615f90842ce8	9	*
MACRUM	0:615f90842ce8	10	* @attention
MACRUM	0:615f90842ce8	11	*
MACRUM	0:615f90842ce8	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
MACRUM	0:615f90842ce8	13	*
MACRUM	0:615f90842ce8	14	* Redistribution and use in source and binary forms, with or without modification,
MACRUM	0:615f90842ce8	15	* are permitted provided that the following conditions are met:
MACRUM	0:615f90842ce8	16	* 1. Redistributions of source code must retain the above copyright notice,
MACRUM	0:615f90842ce8	17	* this list of conditions and the following disclaimer.
MACRUM	0:615f90842ce8	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
MACRUM	0:615f90842ce8	19	* this list of conditions and the following disclaimer in the documentation
MACRUM	0:615f90842ce8	20	* and/or other materials provided with the distribution.
MACRUM	0:615f90842ce8	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
MACRUM	0:615f90842ce8	22	* may be used to endorse or promote products derived from this software
MACRUM	0:615f90842ce8	23	* without specific prior written permission.
MACRUM	0:615f90842ce8	24	*
MACRUM	0:615f90842ce8	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
MACRUM	0:615f90842ce8	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
MACRUM	0:615f90842ce8	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
MACRUM	0:615f90842ce8	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
MACRUM	0:615f90842ce8	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
MACRUM	0:615f90842ce8	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
MACRUM	0:615f90842ce8	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
MACRUM	0:615f90842ce8	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
MACRUM	0:615f90842ce8	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
MACRUM	0:615f90842ce8	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
MACRUM	0:615f90842ce8	35	*
MACRUM	0:615f90842ce8	36	******************************************************************************
MACRUM	0:615f90842ce8	37	*/
MACRUM	0:615f90842ce8	38
MACRUM	0:615f90842ce8	39	/* Define to prevent recursive inclusion -------------------------------------*/
MACRUM	0:615f90842ce8	40	#ifndef __SPIRIT1_REGS_H
MACRUM	0:615f90842ce8	41	#define __SPIRIT1_REGS_H
MACRUM	0:615f90842ce8	42
MACRUM	0:615f90842ce8	43	#ifdef __cplusplus
MACRUM	0:615f90842ce8	44	extern "C" {
MACRUM	0:615f90842ce8	45	#endif
MACRUM	0:615f90842ce8	46
MACRUM	0:615f90842ce8	47	/**
MACRUM	0:615f90842ce8	48	* @addtogroup SPIRIT_Registers SPIRIT Registers
MACRUM	0:615f90842ce8	49	* @brief Header file containing all the SPIRIT registers address and masks.
MACRUM	0:615f90842ce8	50	* @details See the file <i>@ref SPIRIT_Regs.h</i> for more details.
MACRUM	0:615f90842ce8	51	* @{
MACRUM	0:615f90842ce8	52	*/
MACRUM	0:615f90842ce8	53
MACRUM	0:615f90842ce8	54	/** @defgroup General_Configuration_Registers
MACRUM	0:615f90842ce8	55	* @{
MACRUM	0:615f90842ce8	56	*/
MACRUM	0:615f90842ce8	57
MACRUM	0:615f90842ce8	58	/** @defgroup ANA_FUNC_CONF_1_Register
MACRUM	0:615f90842ce8	59	* @{
MACRUM	0:615f90842ce8	60	*/
MACRUM	0:615f90842ce8	61
MACRUM	0:615f90842ce8	62	/**
MACRUM	0:615f90842ce8	63	* \brief ANA_FUNC_CONF register 1
MACRUM	0:615f90842ce8	64	* \code
MACRUM	0:615f90842ce8	65	* Read Write
MACRUM	0:615f90842ce8	66	* Default value: 0x0C
MACRUM	0:615f90842ce8	67	* 7:5 NUM_EN_PIPES: Number of enabled pipes (starting from Data Pipe 0).
MACRUM	0:615f90842ce8	68	* 4:2 GM_CONF[2:0]: Sets the driver gm of the XO at start-up:
MACRUM	0:615f90842ce8	69	* GM_CONF2 \| GM_CONF1 \| GM_CONF0 \| GM [mS]
MACRUM	0:615f90842ce8	70	* ------------------------------------------
MACRUM	0:615f90842ce8	71	* 0 \| 0 \| 0 \| 13.2
MACRUM	0:615f90842ce8	72	* 0 \| 0 \| 1 \| 18.2
MACRUM	0:615f90842ce8	73	* 0 \| 1 \| 0 \| 21.5
MACRUM	0:615f90842ce8	74	* 0 \| 1 \| 1 \| 25.6
MACRUM	0:615f90842ce8	75	* 1 \| 0 \| 0 \| 28.8
MACRUM	0:615f90842ce8	76	* 1 \| 0 \| 1 \| 33.9
MACRUM	0:615f90842ce8	77	* 1 \| 1 \| 0 \| 38.5
MACRUM	0:615f90842ce8	78	* 1 \| 1 \| 1 \| 43.0
MACRUM	0:615f90842ce8	79	* 1:0 SET_BLD_LVL[1:0]: Sets the Battery Level Detector threshold:
MACRUM	0:615f90842ce8	80	* SET_BLD_LVL1 \| SET_BLD_LVL0 \| Threshold [V]
MACRUM	0:615f90842ce8	81	* ------------------------------------------
MACRUM	0:615f90842ce8	82	* 0 \| 0 \| 2.7
MACRUM	0:615f90842ce8	83	* 0 \| 1 \| 2.5
MACRUM	0:615f90842ce8	84	* 1 \| 0 \| 2.3
MACRUM	0:615f90842ce8	85	* 1 \| 1 \| 2.1
MACRUM	0:615f90842ce8	86	* \endcode
MACRUM	0:615f90842ce8	87	*/
MACRUM	0:615f90842ce8	88
MACRUM	0:615f90842ce8	89	#define ANA_FUNC_CONF1_BASE ((uint8_t)0x00) /!< ANA_FUNC_CONF1 Address (R/W) /
MACRUM	0:615f90842ce8	90
MACRUM	0:615f90842ce8	91	#define ANA_FUNC_CONF1_NUM_PIPES_MASK ((uint8_t)0xE0) /!< Mask for number of enabled pipes/
MACRUM	0:615f90842ce8	92
MACRUM	0:615f90842ce8	93	#define ANA_FUNC_CONF1_GMCONF_MASK ((uint8_t)0x1C) /!< Mask of the GmConf field of ANA_FUNC_CONF1 register (R/W) /
MACRUM	0:615f90842ce8	94
MACRUM	0:615f90842ce8	95	#define GM_13_2 ((uint8_t)0x00) /!< Transconducatance Gm at start-up 13.2 mS /
MACRUM	0:615f90842ce8	96	#define GM_18_2 ((uint8_t)0x04) /!< Transconducatance Gm at start-up 18.2 mS /
MACRUM	0:615f90842ce8	97	#define GM_21_5 ((uint8_t)0x08) /!< Transconducatance Gm at start-up 21.5 mS /
MACRUM	0:615f90842ce8	98	#define GM_25_6 ((uint8_t)0x0C) /!< Transconducatance Gm at start-up 25.6 mS /
MACRUM	0:615f90842ce8	99	#define GM_28_8 ((uint8_t)0x10) /!< Transconducatance Gm at start-up 28.8 mS /
MACRUM	0:615f90842ce8	100	#define GM_33_9 ((uint8_t)0x14) /!< Transconducatance Gm at start-up 33.9 mS /
MACRUM	0:615f90842ce8	101	#define GM_38_5 ((uint8_t)0x18) /!< Transconducatance Gm at start-up 38.5 mS /
MACRUM	0:615f90842ce8	102	#define GM_43_0 ((uint8_t)0x1C) /!< Transconducatance Gm at start-up 43.0 mS /
MACRUM	0:615f90842ce8	103
MACRUM	0:615f90842ce8	104	#define ANA_FUNC_CONF1_SET_BLD_LVL_MASK ((uint8_t)0x03) /!< Mask of the SET_BLD_LV field of ANA_FUNC_CONF1 register (R/W) /
MACRUM	0:615f90842ce8	105
MACRUM	0:615f90842ce8	106	#define BLD_LVL_2_7 ((uint8_t)0x00) /!< Sets the Battery Level Detector threshold to 2.7V /
MACRUM	0:615f90842ce8	107	#define BLD_LVL_2_5 ((uint8_t)0x01) /!< Sets the Battery Level Detector threshold to 2.5V /
MACRUM	0:615f90842ce8	108	#define BLD_LVL_2_3 ((uint8_t)0x02) /!< Sets the Battery Level Detector threshold to 2.3V /
MACRUM	0:615f90842ce8	109	#define BLD_LVL_2_1 ((uint8_t)0x03) /!< Sets the Battery Level Detector threshold to 2.1V /
MACRUM	0:615f90842ce8	110
MACRUM	0:615f90842ce8	111	/**
MACRUM	0:615f90842ce8	112	* @}
MACRUM	0:615f90842ce8	113	*/
MACRUM	0:615f90842ce8	114
MACRUM	0:615f90842ce8	115
MACRUM	0:615f90842ce8	116	/** @defgroup ANA_FUNC_CONF_0_Register
MACRUM	0:615f90842ce8	117	* @{
MACRUM	0:615f90842ce8	118	*/
MACRUM	0:615f90842ce8	119
MACRUM	0:615f90842ce8	120	/**
MACRUM	0:615f90842ce8	121	* \brief ANA_FUNC_CONF register 0
MACRUM	0:615f90842ce8	122	* \code
MACRUM	0:615f90842ce8	123	* Read Write
MACRUM	0:615f90842ce8	124	* Default value: 0xC0
MACRUM	0:615f90842ce8	125	* 7 Reserved.
MACRUM	0:615f90842ce8	126	* 6 24_26_MHz_SELECT: 1 - 26 MHz configuration
MACRUM	0:615f90842ce8	127	* 0 - 24 MHz configuration
MACRUM	0:615f90842ce8	128	* 5 AES_ON: 1 - AES engine enabled
MACRUM	0:615f90842ce8	129	* 0 - AES engine disabled
MACRUM	0:615f90842ce8	130	* 4 EXT_REF: 1 - Reference signal from XIN pin
MACRUM	0:615f90842ce8	131	* 0 - Reference signal from XO circuit
MACRUM	0:615f90842ce8	132	* 3 HIGH_POWER_MODE: 1 - SET_SMPS_LEVEL word will be set to the value to
MACRUM	0:615f90842ce8	133	* PM_TEST register in RX state, while in TX state it
MACRUM	0:615f90842ce8	134	* will be fixed to 111 (which programs the SMPS output
MACRUM	0:615f90842ce8	135	* at max value 1.8V)
MACRUM	0:615f90842ce8	136	* 0 - SET_SMPS_LEVEL word will hold the value written in the
MACRUM	0:615f90842ce8	137	* PM_TEST register both in RX and TX state
MACRUM	0:615f90842ce8	138	* 2 BROWN_OUT: 1 - Brown_Out Detection enabled
MACRUM	0:615f90842ce8	139	* 0 - Brown_Out Detection disabled
MACRUM	0:615f90842ce8	140	* 1 BATTERY_LEVEL: 1 - Battery level detector enabled
MACRUM	0:615f90842ce8	141	* 0 - Battery level detector disabled
MACRUM	0:615f90842ce8	142	* 0 TS: 1 - Enable the "Temperature Sensor" function
MACRUM	0:615f90842ce8	143	* 0 - Disable the "Temperature Sensor" function
MACRUM	0:615f90842ce8	144	* \endcode
MACRUM	0:615f90842ce8	145	*/
MACRUM	0:615f90842ce8	146
MACRUM	0:615f90842ce8	147
MACRUM	0:615f90842ce8	148	#define ANA_FUNC_CONF0_BASE ((uint8_t)0x01) /!< ANA_FUNC_CONF0 Address (R/W) /
MACRUM	0:615f90842ce8	149
MACRUM	0:615f90842ce8	150	#define SELECT_24_26_MHZ_MASK ((uint8_t)0x40) /!< Configure the RCO if using 26 MHz or 24 MHz master clock/reference signal /
MACRUM	0:615f90842ce8	151	#define AES_MASK ((uint8_t)0x20) /!< AES engine on/off /
MACRUM	0:615f90842ce8	152	#define EXT_REF_MASK ((uint8_t)0x10) /!< Reference signal from XIN pin (oscillator external) or from XO circuit (oscillator internal)/
MACRUM	0:615f90842ce8	153	#define HIGH_POWER_MODE_MASK ((uint8_t)0x08) /*!< SET_SMPS_LEVEL word will be set to the value to PM_TEST register
MACRUM	0:615f90842ce8	154	in RX state, while in TX state it will be fixed to 111
MACRUM	0:615f90842ce8	155	(which programs the SMPS output at max value, 1.8V) */
MACRUM	0:615f90842ce8	156	#define BROWN_OUT_MASK ((uint8_t)0x04) /!< Accurate Brown-Out detection on/off /
MACRUM	0:615f90842ce8	157	#define BATTERY_LEVEL_MASK ((uint8_t)0x02) /!< Battery level detector circuit on/off /
MACRUM	0:615f90842ce8	158	#define TEMPERATURE_SENSOR_MASK ((uint8_t)0x01) /!< The Temperature Sensor (available on GPIO0) on/off /
MACRUM	0:615f90842ce8	159
MACRUM	0:615f90842ce8	160	/**
MACRUM	0:615f90842ce8	161	* @}
MACRUM	0:615f90842ce8	162	*/
MACRUM	0:615f90842ce8	163
MACRUM	0:615f90842ce8	164	/** @defgroup ANT_SELECT_CONF_Register
MACRUM	0:615f90842ce8	165	* @{
MACRUM	0:615f90842ce8	166	*/
MACRUM	0:615f90842ce8	167
MACRUM	0:615f90842ce8	168	/**
MACRUM	0:615f90842ce8	169	* \brief ANT_SELECT_CONF register
MACRUM	0:615f90842ce8	170	* \code
MACRUM	0:615f90842ce8	171	* Read Write
MACRUM	0:615f90842ce8	172	* Default value: 0x05
MACRUM	0:615f90842ce8	173	*
MACRUM	0:615f90842ce8	174	* 7:5 Reserved.
MACRUM	0:615f90842ce8	175	*
MACRUM	0:615f90842ce8	176	* 4 CS_BLANKING: Blank received data if signal is below the CS threshold
MACRUM	0:615f90842ce8	177	*
MACRUM	0:615f90842ce8	178	* 3 AS_ENABLE: Enable antenna switching
MACRUM	0:615f90842ce8	179	* 1 - Enable
MACRUM	0:615f90842ce8	180	* 0 - Disable
MACRUM	0:615f90842ce8	181	*
MACRUM	0:615f90842ce8	182	* 2:0 AS_MEAS_TIME[2:0]: Measurement time according to the formula Tmeas = 242^(EchFlt)2^AS_MEAS_TIME/fxo
MACRUM	0:615f90842ce8	183	* \endcode
MACRUM	0:615f90842ce8	184	*/
MACRUM	0:615f90842ce8	185	#define ANT_SELECT_CONF_BASE ((uint8_t)0x27) /!< Antenna diversity (works only in static carrier sense mode) /
MACRUM	0:615f90842ce8	186	#define ANT_SELECT_CS_BLANKING_MASK ((uint8_t)0x10) /!< CS data blanking on/off /
MACRUM	0:615f90842ce8	187	#define ANT_SELECT_CONF_AS_MASK ((uint8_t)0x08) /!< Antenna diversity on/off /
MACRUM	0:615f90842ce8	188
MACRUM	0:615f90842ce8	189	/**
MACRUM	0:615f90842ce8	190	* @}
MACRUM	0:615f90842ce8	191	*/
MACRUM	0:615f90842ce8	192
MACRUM	0:615f90842ce8	193	/** @defgroup DEVICE_INFO1_Register
MACRUM	0:615f90842ce8	194	* @{
MACRUM	0:615f90842ce8	195	*/
MACRUM	0:615f90842ce8	196
MACRUM	0:615f90842ce8	197	/**
MACRUM	0:615f90842ce8	198	* \brief DEVICE_INFO1[7:0] registers
MACRUM	0:615f90842ce8	199	* \code
MACRUM	0:615f90842ce8	200	* Default value: 0x01
MACRUM	0:615f90842ce8	201	* Read
MACRUM	0:615f90842ce8	202	*
MACRUM	0:615f90842ce8	203	* 7:0 PARTNUM[7:0]: Device part number
MACRUM	0:615f90842ce8	204	* \endcode
MACRUM	0:615f90842ce8	205	*/
MACRUM	0:615f90842ce8	206	#define DEVICE_INFO1_PARTNUM ((uint8_t)(0xF0)) /!< Device part number [7:0] /
MACRUM	0:615f90842ce8	207
MACRUM	0:615f90842ce8	208	/**
MACRUM	0:615f90842ce8	209	* @}
MACRUM	0:615f90842ce8	210	*/
MACRUM	0:615f90842ce8	211
MACRUM	0:615f90842ce8	212	/** @defgroup DEVICE_INFO0_Register
MACRUM	0:615f90842ce8	213	* @{
MACRUM	0:615f90842ce8	214	*/
MACRUM	0:615f90842ce8	215
MACRUM	0:615f90842ce8	216	/**
MACRUM	0:615f90842ce8	217	* \brief DEVICE_INFO0[7:0] registers
MACRUM	0:615f90842ce8	218	* \code
MACRUM	0:615f90842ce8	219	* Read
MACRUM	0:615f90842ce8	220	*
MACRUM	0:615f90842ce8	221	* 7:0 VERSION[7:0]: Device version number
MACRUM	0:615f90842ce8	222	* \endcode
MACRUM	0:615f90842ce8	223	*/
MACRUM	0:615f90842ce8	224	#define DEVICE_INFO0_VERSION ((uint8_t)(0xF1)) /!< Device version [7:0]; (0x55 in CUT1.0) /
MACRUM	0:615f90842ce8	225
MACRUM	0:615f90842ce8	226	/**
MACRUM	0:615f90842ce8	227	* @}
MACRUM	0:615f90842ce8	228	*/
MACRUM	0:615f90842ce8	229
MACRUM	0:615f90842ce8	230
MACRUM	0:615f90842ce8	231	/**
MACRUM	0:615f90842ce8	232	* @}
MACRUM	0:615f90842ce8	233	*/
MACRUM	0:615f90842ce8	234
MACRUM	0:615f90842ce8	235
MACRUM	0:615f90842ce8	236	/** @defgroup GPIO_Registers
MACRUM	0:615f90842ce8	237	* @{
MACRUM	0:615f90842ce8	238	*/
MACRUM	0:615f90842ce8	239
MACRUM	0:615f90842ce8	240	/** @defgroup GPIOx_CONF_Registers
MACRUM	0:615f90842ce8	241	* @{
MACRUM	0:615f90842ce8	242	*/
MACRUM	0:615f90842ce8	243
MACRUM	0:615f90842ce8	244	/**
MACRUM	0:615f90842ce8	245	* \brief GPIOx registers
MACRUM	0:615f90842ce8	246	* \code
MACRUM	0:615f90842ce8	247	* Read Write
MACRUM	0:615f90842ce8	248	* Default value: 0x03
MACRUM	0:615f90842ce8	249	* 7:3 GPIO_SELECT[4:0]: Specify the I/O signal.
MACRUM	0:615f90842ce8	250	* GPIO_SELECT[4:0] \| I/O \| Signal
MACRUM	0:615f90842ce8	251	* ------------------------------------------------
MACRUM	0:615f90842ce8	252	* 0 \| Output \| nIRQ
MACRUM	0:615f90842ce8	253	* 0 \| Input \| TX command
MACRUM	0:615f90842ce8	254	* 1 \| Output \| POR inverted
MACRUM	0:615f90842ce8	255	* 1 \| Input \| RX command
MACRUM	0:615f90842ce8	256	* 2 \| Output \| Wake-Up timer expiration
MACRUM	0:615f90842ce8	257	* 2 \| Input \| TX data for direct modulation
MACRUM	0:615f90842ce8	258	* 3 \| Output \| Low Battery Detection
MACRUM	0:615f90842ce8	259	* 3 \| Input \| Wake-up from external input
MACRUM	0:615f90842ce8	260	* 4 \| Output \| TX clock output
MACRUM	0:615f90842ce8	261	* 5 \| Output \| TX state
MACRUM	0:615f90842ce8	262	* 6 \| Output \| TX FIFO Almost Empty Flag
MACRUM	0:615f90842ce8	263	* 7 \| Output \| TX FIFO ALmost Full Flag
MACRUM	0:615f90842ce8	264	* 8 \| Output \| RX data output
MACRUM	0:615f90842ce8	265	* 9 \| Output \| RX clock output
MACRUM	0:615f90842ce8	266	* 10 \| Output \| RX state
MACRUM	0:615f90842ce8	267	* 11 \| Output \| RX FIFO Almost Full Flag
MACRUM	0:615f90842ce8	268	* 12 \| Output \| RX FIFO Almost Empty Flag
MACRUM	0:615f90842ce8	269	* 13 \| Output \| Antenna switch
MACRUM	0:615f90842ce8	270	* 14 \| Output \| Valid preamble detected
MACRUM	0:615f90842ce8	271	* 15 \| Output \| Sync word detected
MACRUM	0:615f90842ce8	272	* 16 \| Output \| RSSI above threshold
MACRUM	0:615f90842ce8	273	* 17 \| Output \| MCU clock
MACRUM	0:615f90842ce8	274	* 18 \| Output \| TX or RX mode indicator
MACRUM	0:615f90842ce8	275	* 19 \| Output \| VDD
MACRUM	0:615f90842ce8	276	* 20 \| Output \| GND
MACRUM	0:615f90842ce8	277	* 21 \| Output \| External SMPS enable signal
MACRUM	0:615f90842ce8	278	* 22-31 \| Not Used \| Not Used
MACRUM	0:615f90842ce8	279	* 2 Reserved
MACRUM	0:615f90842ce8	280	* 1:0 GpioMode[1:0]: Specify the mode:
MACRUM	0:615f90842ce8	281	* GPIO_MODE1 \| GPIO_MODE0 \| MODE
MACRUM	0:615f90842ce8	282	* ------------------------------------------------------------
MACRUM	0:615f90842ce8	283	* 0 \| 0 \| Analog (valid only for GPIO_0)
MACRUM	0:615f90842ce8	284	* 0 \| 1 \| Digital Input
MACRUM	0:615f90842ce8	285	* 1 \| 0 \| Digital Output Low Power
MACRUM	0:615f90842ce8	286	* 1 \| 1 \| Digital Output High Power
MACRUM	0:615f90842ce8	287	*
MACRUM	0:615f90842ce8	288	* Note: The Analog mode is used only for temperature sensor indication. This is available only
MACRUM	0:615f90842ce8	289	* on GPIO_0 by setting the TS bit in the ANA_FUNC_CONF_0_Register.
MACRUM	0:615f90842ce8	290	* \endcode
MACRUM	0:615f90842ce8	291	*/
MACRUM	0:615f90842ce8	292
MACRUM	0:615f90842ce8	293
MACRUM	0:615f90842ce8	294	#define GPIO3_CONF_BASE ((uint8_t)0x02) /!< GPIO_3 register address /
MACRUM	0:615f90842ce8	295	#define GPIO2_CONF_BASE ((uint8_t)0x03) /!< GPIO_3 register address /
MACRUM	0:615f90842ce8	296	#define GPIO1_CONF_BASE ((uint8_t)0x04) /!< GPIO_3 register address /
MACRUM	0:615f90842ce8	297	#define GPIO0_CONF_BASE ((uint8_t)0x05) /!< GPIO_3 register address /
MACRUM	0:615f90842ce8	298
MACRUM	0:615f90842ce8	299	#define CONF_GPIO_IN_TX_Command ((uint8_t)0x00) /!< TX command direct from PIN (rising edge, width min=50ns) /
MACRUM	0:615f90842ce8	300	#define CONF_GPIO_IN_RX_Command ((uint8_t)0x08) /!< RX command direct from PIN (rising edge, width min=50ns)/
MACRUM	0:615f90842ce8	301	#define CONF_GPIO_IN_TX_Data ((uint8_t)0x10) /!< TX data input for direct modulation /
MACRUM	0:615f90842ce8	302	#define CONF_GPIO_IN_WKUP_Ext ((uint8_t)0x18) /!< Wake up from external input /
MACRUM	0:615f90842ce8	303
MACRUM	0:615f90842ce8	304	#define CONF_GPIO_OUT_nIRQ ((uint8_t)0x00) /!< nIRQ (Interrupt Request, active low) , default configuration after POR /
MACRUM	0:615f90842ce8	305	#define CONF_GPIO_OUT_POR_Inv ((uint8_t)0x08) /!< POR inverted (active low) /
MACRUM	0:615f90842ce8	306	#define CONF_GPIO_OUT_WUT_Exp ((uint8_t)0x10) /!< Wake-Up Timer expiration: 1 when WUT has expired /
MACRUM	0:615f90842ce8	307	#define CONF_GPIO_OUT_LBD ((uint8_t)0x18) /!< Low battery detection: 1 when battery is below threshold setting /
MACRUM	0:615f90842ce8	308	#define CONF_GPIO_OUT_TX_Data ((uint8_t)0x20) /!< TX data internal clock output (TX data are sampled on the rising edge of it) /
MACRUM	0:615f90842ce8	309	#define CONF_GPIO_OUT_TX_State ((uint8_t)0x28) /!< TX state indication: 1 when Spirit1 is transiting in the TX state /
MACRUM	0:615f90842ce8	310	#define CONF_GPIO_OUT_TX_FIFO_Almost_Empty ((uint8_t)0x30) /!< TX FIFO Almost Empty Flag /
MACRUM	0:615f90842ce8	311	#define CONF_GPIO_OUT_TX_FIFO_Amost_Full ((uint8_t)0x38) /!< TX FIFO Almost Full Flag /
MACRUM	0:615f90842ce8	312	#define CONF_GPIO_OUT_RX_Data ((uint8_t)0x40) /!< RX data output /
MACRUM	0:615f90842ce8	313	#define CONF_GPIO_OUT_RX_Clock ((uint8_t)0x48) /!< RX clock output (recovered from received data) /
MACRUM	0:615f90842ce8	314	#define CONF_GPIO_OUT_RX_State ((uint8_t)0x50) /!< RX state indication: 1 when Spirit1 is transiting in the RX state /
MACRUM	0:615f90842ce8	315	#define CONF_GPIO_OUT_RX_FIFO_Almost_Full ((uint8_t)0x58) /!< RX FIFO Almost Full Flag /
MACRUM	0:615f90842ce8	316	#define CONF_GPIO_OUT_RX_FIFO_Almost_Empty ((uint8_t)0x60) /!< RX FIFO Almost Empty Flag /
MACRUM	0:615f90842ce8	317	#define CONF_GPIO_OUT_Antenna_Switch ((uint8_t)0x68) /!< Antenna switch used for antenna diversity /
MACRUM	0:615f90842ce8	318	#define CONF_GPIO_OUT_Valid_Preamble ((uint8_t)0x70) /!< Valid Preamble Detected Flag /
MACRUM	0:615f90842ce8	319	#define CONF_GPIO_OUT_Sync_Detected ((uint8_t)0x78) /!< Sync WordSync Word Detected Flag /
MACRUM	0:615f90842ce8	320	#define CONF_GPIO_OUT_RSSI_Threshold ((uint8_t)0x80) /!< CCA Assessment Flag /
MACRUM	0:615f90842ce8	321	#define CONF_GPIO_OUT_MCU_Clock ((uint8_t)0x88) /!< MCU Clock /
MACRUM	0:615f90842ce8	322	#define CONF_GPIO_OUT_TX_RX_Mode ((uint8_t)0x90) /!< TX or RX mode indicator (to enable an external range extender) /
MACRUM	0:615f90842ce8	323	#define CONF_GPIO_OUT_VDD ((uint8_t)0x98) /!< VDD (to emulate an additional GPIO of the MCU, programmable by SPI) /
MACRUM	0:615f90842ce8	324	#define CONF_GPIO_OUT_GND ((uint8_t)0xA0) /!< GND (to emulate an additional GPIO of the MCU, programmable by SPI) /
MACRUM	0:615f90842ce8	325	#define CONF_GPIO_OUT_SMPS_Ext ((uint8_t)0xA8) /!< External SMPS enable signal (active high) /
MACRUM	0:615f90842ce8	326
MACRUM	0:615f90842ce8	327	#define CONF_GPIO_MODE_ANALOG ((uint8_t)0x00) /!< Analog test BUS on GPIO; used only in test mode (except for temperature sensor) /
MACRUM	0:615f90842ce8	328	#define CONF_GPIO_MODE_DIG_IN ((uint8_t)0x01) /!< Digital Input on GPIO /
MACRUM	0:615f90842ce8	329	#define CONF_GPIO_MODE_DIG_OUTL ((uint8_t)0x02) /!< Digital Output on GPIO (low current) /
MACRUM	0:615f90842ce8	330	#define CONF_GPIO_MODE_DIG_OUTH ((uint8_t)0x03) /!< Digital Output on GPIO (high current) /
MACRUM	0:615f90842ce8	331
MACRUM	0:615f90842ce8	332	/**
MACRUM	0:615f90842ce8	333	* @}
MACRUM	0:615f90842ce8	334	*/
MACRUM	0:615f90842ce8	335
MACRUM	0:615f90842ce8	336
MACRUM	0:615f90842ce8	337	/** @defgroup MCU_CK_CONF_Register
MACRUM	0:615f90842ce8	338	* @{
MACRUM	0:615f90842ce8	339	*/
MACRUM	0:615f90842ce8	340
MACRUM	0:615f90842ce8	341	/**
MACRUM	0:615f90842ce8	342	* \brief MCU_CK_CONF register
MACRUM	0:615f90842ce8	343	* \code
MACRUM	0:615f90842ce8	344	* Read Write
MACRUM	0:615f90842ce8	345	* Default value: 0x00
MACRUM	0:615f90842ce8	346	* 7 Reserved.
MACRUM	0:615f90842ce8	347	* 6:5 CLOCK_TAIL[1:0]: Specifies the number of extra cylces provided before entering in STANDBY state.
MACRUM	0:615f90842ce8	348	* CLOCK_TAIL1 \| CLOCK_TAIL0 \| Number of Extra Cycles
MACRUM	0:615f90842ce8	349	* ------------------------------------------------------------
MACRUM	0:615f90842ce8	350	* 0 \| 0 \| 0
MACRUM	0:615f90842ce8	351	* 0 \| 1 \| 64
MACRUM	0:615f90842ce8	352	* 1 \| 0 \| 256
MACRUM	0:615f90842ce8	353	* 1 \| 1 \| 512
MACRUM	0:615f90842ce8	354	* 4:1 XO_RATIO[3:0]: Specifies the division ratio when XO oscillator is the clock source
MACRUM	0:615f90842ce8	355	* XO_RATIO[3:0] \| Division Ratio
MACRUM	0:615f90842ce8	356	* -----------------------------------
MACRUM	0:615f90842ce8	357	* 0 \| 1
MACRUM	0:615f90842ce8	358	* 1 \| 2/3
MACRUM	0:615f90842ce8	359	* 2 \| 1/2
MACRUM	0:615f90842ce8	360	* 3 \| 1/3
MACRUM	0:615f90842ce8	361	* 4 \| 1/4
MACRUM	0:615f90842ce8	362	* 5 \| 1/6
MACRUM	0:615f90842ce8	363	* 6 \| 1/8
MACRUM	0:615f90842ce8	364	* 7 \| 1/12
MACRUM	0:615f90842ce8	365	* 8 \| 1/16
MACRUM	0:615f90842ce8	366	* 9 \| 1/24
MACRUM	0:615f90842ce8	367	* 10 \| 1/36
MACRUM	0:615f90842ce8	368	* 11 \| 1/48
MACRUM	0:615f90842ce8	369	* 12 \| 1/64
MACRUM	0:615f90842ce8	370	* 13 \| 1/96
MACRUM	0:615f90842ce8	371	* 14 \| 1/128
MACRUM	0:615f90842ce8	372	* 15 \| 1/256
MACRUM	0:615f90842ce8	373	* 0 RCO_RATIO: Specifies the divsion ratio when RC oscillator is the clock source
MACRUM	0:615f90842ce8	374	* 0 - Division Ratio equal to 0
MACRUM	0:615f90842ce8	375	* 1 - Division Ratio equal to 1/128
MACRUM	0:615f90842ce8	376	* \endcode
MACRUM	0:615f90842ce8	377	*/
MACRUM	0:615f90842ce8	378
MACRUM	0:615f90842ce8	379
MACRUM	0:615f90842ce8	380	#define MCU_CK_CONF_BASE ((uint8_t)0x06) /!< MCU Clock Config register address /
MACRUM	0:615f90842ce8	381
MACRUM	0:615f90842ce8	382	#define MCU_CK_ENABLE ((uint8_t)0x80) /!< MCU clock enable bit /
MACRUM	0:615f90842ce8	383
MACRUM	0:615f90842ce8	384	#define MCU_CK_CONF_CLOCK_TAIL_0 ((uint8_t)0x00) /!< 0 extra clock cycles provided to the MCU before switching to STANDBY state /
MACRUM	0:615f90842ce8	385	#define MCU_CK_CONF_CLOCK_TAIL_64 ((uint8_t)0x20) /!< 64 extra clock cycles provided to the MCU before switching to STANDBY state /
MACRUM	0:615f90842ce8	386	#define MCU_CK_CONF_CLOCK_TAIL_256 ((uint8_t)0x40) /!< 256 extra clock cycles provided to the MCU before switching to STANDBY state /
MACRUM	0:615f90842ce8	387	#define MCU_CK_CONF_CLOCK_TAIL_512 ((uint8_t)0x60) /!< 512 extra clock cycles provided to the MCU before switching to STANDBY state /
MACRUM	0:615f90842ce8	388	#define MCU_CK_CONF_XO_RATIO_1 ((uint8_t)0x00) /!< XO Clock signal available on the GPIO divided by 1 /
MACRUM	0:615f90842ce8	389	#define MCU_CK_CONF_XO_RATIO_2_3 ((uint8_t)0x02) /!< XO Clock signal available on the GPIO divided by 2/3 /
MACRUM	0:615f90842ce8	390	#define MCU_CK_CONF_XO_RATIO_1_2 ((uint8_t)0x04) /!< XO Clock signal available on the GPIO divided by 1/2 /
MACRUM	0:615f90842ce8	391	#define MCU_CK_CONF_XO_RATIO_1_3 ((uint8_t)0x06) /!< XO Clock signal available on the GPIO divided by 1/3 /
MACRUM	0:615f90842ce8	392	#define MCU_CK_CONF_XO_RATIO_1_4 ((uint8_t)0x08) /!< XO Clock signal available on the GPIO divided by 1/4 /
MACRUM	0:615f90842ce8	393	#define MCU_CK_CONF_XO_RATIO_1_6 ((uint8_t)0x0A) /!< XO Clock signal available on the GPIO divided by 1/6 /
MACRUM	0:615f90842ce8	394	#define MCU_CK_CONF_XO_RATIO_1_8 ((uint8_t)0x0C) /!< XO Clock signal available on the GPIO divided by 1/8 /
MACRUM	0:615f90842ce8	395	#define MCU_CK_CONF_XO_RATIO_1_12 ((uint8_t)0x0E) /!< XO Clock signal available on the GPIO divided by 1/12 /
MACRUM	0:615f90842ce8	396	#define MCU_CK_CONF_XO_RATIO_1_16 ((uint8_t)0x10) /!< XO Clock signal available on the GPIO divided by 1/16 /
MACRUM	0:615f90842ce8	397	#define MCU_CK_CONF_XO_RATIO_1_24 ((uint8_t)0x12) /!< XO Clock signal available on the GPIO divided by 1/24 /
MACRUM	0:615f90842ce8	398	#define MCU_CK_CONF_XO_RATIO_1_36 ((uint8_t)0x14) /!< XO Clock signal available on the GPIO divided by 1/36 /
MACRUM	0:615f90842ce8	399	#define MCU_CK_CONF_XO_RATIO_1_48 ((uint8_t)0x16) /!< XO Clock signal available on the GPIO divided by 1/48 /
MACRUM	0:615f90842ce8	400	#define MCU_CK_CONF_XO_RATIO_1_64 ((uint8_t)0x18) /!< XO Clock signal available on the GPIO divided by 1/64 /
MACRUM	0:615f90842ce8	401	#define MCU_CK_CONF_XO_RATIO_1_96 ((uint8_t)0x1A) /!< XO Clock signal available on the GPIO divided by 1/96 /
MACRUM	0:615f90842ce8	402	#define MCU_CK_CONF_XO_RATIO_1_128 ((uint8_t)0x1C) /!< XO Clock signal available on the GPIO divided by 1/128 /
MACRUM	0:615f90842ce8	403	#define MCU_CK_CONF_XO_RATIO_1_192 ((uint8_t)0x1E) /!< XO Clock signal available on the GPIO divided by 1/196 /
MACRUM	0:615f90842ce8	404	#define MCU_CK_CONF_RCO_RATIO_1 ((uint8_t)0x00) /!< RCO Clock signal available on the GPIO divided by 1 /
MACRUM	0:615f90842ce8	405	#define MCU_CK_CONF_RCO_RATIO_1_128 ((uint8_t)0x01) /!< RCO Clock signal available on the GPIO divided by 1/128/
MACRUM	0:615f90842ce8	406
MACRUM	0:615f90842ce8	407	/**
MACRUM	0:615f90842ce8	408	* @}
MACRUM	0:615f90842ce8	409	*/
MACRUM	0:615f90842ce8	410
MACRUM	0:615f90842ce8	411	/**
MACRUM	0:615f90842ce8	412	* @}
MACRUM	0:615f90842ce8	413	*/
MACRUM	0:615f90842ce8	414
MACRUM	0:615f90842ce8	415
MACRUM	0:615f90842ce8	416	/** @defgroup Radio_Configuration_Registers
MACRUM	0:615f90842ce8	417	* @{
MACRUM	0:615f90842ce8	418	*/
MACRUM	0:615f90842ce8	419
MACRUM	0:615f90842ce8	420
MACRUM	0:615f90842ce8	421
MACRUM	0:615f90842ce8	422	/** @defgroup SYNT3_Register
MACRUM	0:615f90842ce8	423	* @{
MACRUM	0:615f90842ce8	424	*/
MACRUM	0:615f90842ce8	425
MACRUM	0:615f90842ce8	426	/**
MACRUM	0:615f90842ce8	427	* \brief SYNT3 register
MACRUM	0:615f90842ce8	428	* \code
MACRUM	0:615f90842ce8	429	* Read Write
MACRUM	0:615f90842ce8	430	* Default value: 0x0C
MACRUM	0:615f90842ce8	431	*
MACRUM	0:615f90842ce8	432	* 7:5 WCP[2:0]: Set the charge pump current according to the VCO frequency in RX mode.
MACRUM	0:615f90842ce8	433	*
MACRUM	0:615f90842ce8	434	* VCO Frequency \| WCP2 \| WCP1 \| WCP0 \| Charge Pump Current (uA)
MACRUM	0:615f90842ce8	435	* ------------------------------------------------------------------------------------------------------------
MACRUM	0:615f90842ce8	436	* 4644-4678 \| 0 \| 0 \| 0 \| 378.4
MACRUM	0:615f90842ce8	437	* 4708-4772 \| 0 \| 0 \| 1 \| 368.9
MACRUM	0:615f90842ce8	438	* 4772-4836 \| 0 \| 1 \| 0 \| 359.5
MACRUM	0:615f90842ce8	439	* 4836-4902 \| 0 \| 1 \| 1 \| 350
MACRUM	0:615f90842ce8	440	* 4902-4966 \| 1 \| 0 \| 0 \| 340.5
MACRUM	0:615f90842ce8	441	* 4966-5030 \| 1 \| 0 \| 1 \| 331.1
MACRUM	0:615f90842ce8	442	* 5030-5095 \| 1 \| 1 \| 0 \| 321.6
MACRUM	0:615f90842ce8	443	* 5095-5161 \| 1 \| 1 \| 1 \| 312.2
MACRUM	0:615f90842ce8	444	* 5161-5232 \| 0 \| 0 \| 0 \| 378.4
MACRUM	0:615f90842ce8	445	* 5232-5303 \| 0 \| 0 \| 1 \| 368.9
MACRUM	0:615f90842ce8	446	* 5303-5375 \| 0 \| 1 \| 0 \| 359.5
MACRUM	0:615f90842ce8	447	* 5375-5448 \| 0 \| 1 \| 1 \| 350
MACRUM	0:615f90842ce8	448	* 5448-5519 \| 1 \| 0 \| 0 \| 340.5
MACRUM	0:615f90842ce8	449	* 5519-5592 \| 1 \| 0 \| 1 \| 331.1
MACRUM	0:615f90842ce8	450	* 5592-5663 \| 1 \| 1 \| 0 \| 321.6
MACRUM	0:615f90842ce8	451	* 5663-5736 \| 1 \| 1 \| 1 \| 312.2
MACRUM	0:615f90842ce8	452	*
MACRUM	0:615f90842ce8	453	*
MACRUM	0:615f90842ce8	454	* 4:0 SYNT[25:21]: highest 5 bits of the PLL programmable divider
MACRUM	0:615f90842ce8	455	* The valid range depends on fXO and REFDIV settings; for
MACRUM	0:615f90842ce8	456	* fXO=26MHz
MACRUM	0:615f90842ce8	457	* REFDIV = 0 - SYNT[25:21] = 11...13
MACRUM	0:615f90842ce8	458	* REFDIV = 1 - SYNT[25:21] = 2227
MACRUM	0:615f90842ce8	459	*
MACRUM	0:615f90842ce8	460	*
MACRUM	0:615f90842ce8	461	* \endcode
MACRUM	0:615f90842ce8	462	*/
MACRUM	0:615f90842ce8	463	#define SYNT3_BASE ((uint8_t)0x08) /!< [4:0] -> SYNT[25:21], highest 5 bits of the PLL programmable divider /
MACRUM	0:615f90842ce8	464
MACRUM	0:615f90842ce8	465	#define WCP_CONF_WCP_378UA ((uint8_t)0x00) /!< Charge pump current nominal value = 378uA [VCO 4644-4708]&[VCO 5161-5232] /
MACRUM	0:615f90842ce8	466	#define WCP_CONF_WCP_369UA ((uint8_t)0x01) /!< Charge pump current nominal value = 369uA [VCO 4708-4772]&[VCO 5232-5303] /
MACRUM	0:615f90842ce8	467	#define WCP_CONF_WCP_359UA ((uint8_t)0x02) /!< Charge pump current nominal value = 359uA [VCO 4772-4836]&[VCO 5303-5375] /
MACRUM	0:615f90842ce8	468	#define WCP_CONF_WCP_350UA ((uint8_t)0x03) /!< Charge pump current nominal value = 350uA [VCO 4836-4902]&[VCO 5375-5448] /
MACRUM	0:615f90842ce8	469	#define WCP_CONF_WCP_340UA ((uint8_t)0x04) /!< Charge pump current nominal value = 340uA [VCO 4902-4966]&[VCO 5448-5519] /
MACRUM	0:615f90842ce8	470	#define WCP_CONF_WCP_331UA ((uint8_t)0x05) /!< Charge pump current nominal value = 331uA [VCO 4966-5030]&[VCO 5519-5592] /
MACRUM	0:615f90842ce8	471	#define WCP_CONF_WCP_321UA ((uint8_t)0x06) /!< Charge pump current nominal value = 321uA [VCO 5030-5095]&[VCO 5592-5563] /
MACRUM	0:615f90842ce8	472	#define WCP_CONF_WCP_312UA ((uint8_t)0x07) /!< Charge pump current nominal value = 312uA [VCO 5095-5160]&[VCO 5563-5736] /
MACRUM	0:615f90842ce8	473
MACRUM	0:615f90842ce8	474
MACRUM	0:615f90842ce8	475	/**
MACRUM	0:615f90842ce8	476	* @}
MACRUM	0:615f90842ce8	477	*/
MACRUM	0:615f90842ce8	478
MACRUM	0:615f90842ce8	479
MACRUM	0:615f90842ce8	480	/** @defgroup SYNT2_Register
MACRUM	0:615f90842ce8	481	* @{
MACRUM	0:615f90842ce8	482	*/
MACRUM	0:615f90842ce8	483
MACRUM	0:615f90842ce8	484	/**
MACRUM	0:615f90842ce8	485	* \brief SYNT2 register
MACRUM	0:615f90842ce8	486	* \code
MACRUM	0:615f90842ce8	487	* Read Write
MACRUM	0:615f90842ce8	488	* Default value: 0x84
MACRUM	0:615f90842ce8	489	* 7:0 SYNT[20:13]: intermediate bits of the PLL programmable divider.
MACRUM	0:615f90842ce8	490	*
MACRUM	0:615f90842ce8	491	* \endcode
MACRUM	0:615f90842ce8	492	*/
MACRUM	0:615f90842ce8	493
MACRUM	0:615f90842ce8	494	#define SYNT2_BASE ((uint8_t)0x09) /!< SYNT[20:13], intermediate bits of the PLL programmable divider /
MACRUM	0:615f90842ce8	495
MACRUM	0:615f90842ce8	496	/**
MACRUM	0:615f90842ce8	497	* @}
MACRUM	0:615f90842ce8	498	*/
MACRUM	0:615f90842ce8	499
MACRUM	0:615f90842ce8	500	/** @defgroup SYNT1_Register
MACRUM	0:615f90842ce8	501	* @{
MACRUM	0:615f90842ce8	502	*/
MACRUM	0:615f90842ce8	503
MACRUM	0:615f90842ce8	504	/**
MACRUM	0:615f90842ce8	505	* \brief SYNT1 register
MACRUM	0:615f90842ce8	506	* \code
MACRUM	0:615f90842ce8	507	* Read Write
MACRUM	0:615f90842ce8	508	* Default value: 0xEC
MACRUM	0:615f90842ce8	509	* 7:0 SYNT[12:5]: intermediate bits of the PLL programmable divider.
MACRUM	0:615f90842ce8	510	*
MACRUM	0:615f90842ce8	511	* \endcode
MACRUM	0:615f90842ce8	512	*/
MACRUM	0:615f90842ce8	513
MACRUM	0:615f90842ce8	514	#define SYNT1_BASE ((uint8_t)0x0A) /!< SYNT[12:5], intermediate bits of the PLL programmable divider /
MACRUM	0:615f90842ce8	515
MACRUM	0:615f90842ce8	516	/**
MACRUM	0:615f90842ce8	517	* @}
MACRUM	0:615f90842ce8	518	*/
MACRUM	0:615f90842ce8	519
MACRUM	0:615f90842ce8	520	/** @defgroup SYNT0_Register
MACRUM	0:615f90842ce8	521	* @{
MACRUM	0:615f90842ce8	522	*/
MACRUM	0:615f90842ce8	523
MACRUM	0:615f90842ce8	524	/**
MACRUM	0:615f90842ce8	525	* \brief SYNT0 register
MACRUM	0:615f90842ce8	526	* \code
MACRUM	0:615f90842ce8	527	* Read Write
MACRUM	0:615f90842ce8	528	* Default value: 0x51
MACRUM	0:615f90842ce8	529	* 7:3 SYNT[4:0]: lowest bits of the PLL programmable divider.
MACRUM	0:615f90842ce8	530	* 2:0 BS[2:0]: Synthesizer band select. This parameter selects the out-of-loop divide factor of the synthesizer
MACRUM	0:615f90842ce8	531	* according to the formula fxo/(B/2)/D*SYNT/2^18
MACRUM	0:615f90842ce8	532	*
MACRUM	0:615f90842ce8	533	* BS2 \| BS1 \| BS0 \| value of B
MACRUM	0:615f90842ce8	534	* ---------------------------------------------------------------------------
MACRUM	0:615f90842ce8	535	* 0 \| 0 \| 1 \| 6
MACRUM	0:615f90842ce8	536	* 0 \| 1 \| 0 \| 8
MACRUM	0:615f90842ce8	537	* 0 \| 1 \| 1 \| 12
MACRUM	0:615f90842ce8	538	* 1 \| 0 \| 0 \| 16
MACRUM	0:615f90842ce8	539	* 1 \| 0 \| 1 \| 32
MACRUM	0:615f90842ce8	540	*
MACRUM	0:615f90842ce8	541	* \endcode
MACRUM	0:615f90842ce8	542	*/
MACRUM	0:615f90842ce8	543	#define SYNT0_BASE ((uint8_t)0x0B) /!< [7:3] -> SYNT[4:0], lowest bits of the PLL programmable divider /
MACRUM	0:615f90842ce8	544
MACRUM	0:615f90842ce8	545	#define SYNT0_BS_6 ((uint8_t)0x01) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=6 (779-956MHz) /
MACRUM	0:615f90842ce8	546	#define SYNT0_BS_8 ((uint8_t)0x02) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=8 (387-470MHz)/
MACRUM	0:615f90842ce8	547	#define SYNT0_BS_12 ((uint8_t)0x03) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=12 (387-470MHz)/
MACRUM	0:615f90842ce8	548	#define SYNT0_BS_16 ((uint8_t)0x04) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=16 (300-348MHz)/
MACRUM	0:615f90842ce8	549	#define SYNT0_BS_32 ((uint8_t)0x05) /!< Synthesizer band select (out-of-loop divide factor of the synthesizer)=32 (150-174MHz)/
MACRUM	0:615f90842ce8	550
MACRUM	0:615f90842ce8	551	/**
MACRUM	0:615f90842ce8	552	* @}
MACRUM	0:615f90842ce8	553	*/
MACRUM	0:615f90842ce8	554
MACRUM	0:615f90842ce8	555	/** @defgroup CHSPACE_Register
MACRUM	0:615f90842ce8	556	* @{
MACRUM	0:615f90842ce8	557	*/
MACRUM	0:615f90842ce8	558
MACRUM	0:615f90842ce8	559	/**
MACRUM	0:615f90842ce8	560	* \brief CHSPACE register
MACRUM	0:615f90842ce8	561	* \code
MACRUM	0:615f90842ce8	562	* Read Write
MACRUM	0:615f90842ce8	563	* Default value: 0xFC
MACRUM	0:615f90842ce8	564	* 7:0 CH_SPACING[7:0]: Channel spacing. From ~793Hz to ~200KHz in 793Hz steps
MACRUM	0:615f90842ce8	565	* (in general, frequency step is fXO/215=26MHz/215~793Hz).
MACRUM	0:615f90842ce8	566	*
MACRUM	0:615f90842ce8	567	* \endcode
MACRUM	0:615f90842ce8	568	*/
MACRUM	0:615f90842ce8	569
MACRUM	0:615f90842ce8	570	#define CHSPACE_BASE ((uint8_t)0x0C) /!< Channel spacing. From ~0.8KHz to ~200KHz in (fXO/2^15)Hz (793Hz for 26MHz XO) steps /
MACRUM	0:615f90842ce8	571
MACRUM	0:615f90842ce8	572	/**
MACRUM	0:615f90842ce8	573	* @}
MACRUM	0:615f90842ce8	574	*/
MACRUM	0:615f90842ce8	575
MACRUM	0:615f90842ce8	576
MACRUM	0:615f90842ce8	577
MACRUM	0:615f90842ce8	578	/** @defgroup IF_OFFSET_DIG_Register
MACRUM	0:615f90842ce8	579	* @{
MACRUM	0:615f90842ce8	580	*/
MACRUM	0:615f90842ce8	581
MACRUM	0:615f90842ce8	582	/**
MACRUM	0:615f90842ce8	583	* \brief IF_OFFSET_DIG register
MACRUM	0:615f90842ce8	584	* \code
MACRUM	0:615f90842ce8	585	* Read Write
MACRUM	0:615f90842ce8	586	* Default value: 0xA3
MACRUM	0:615f90842ce8	587	* 7:0 IF_OFFSET_DIG[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
MACRUM	0:615f90842ce8	588	*
MACRUM	0:615f90842ce8	589	* \endcode
MACRUM	0:615f90842ce8	590	*/
MACRUM	0:615f90842ce8	591	#define IF_OFFSET_DIG_BASE ((uint8_t)0x0D) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
MACRUM	0:615f90842ce8	592
MACRUM	0:615f90842ce8	593	/**
MACRUM	0:615f90842ce8	594	* @}
MACRUM	0:615f90842ce8	595	*/
MACRUM	0:615f90842ce8	596
MACRUM	0:615f90842ce8	597	/** @defgroup IF_OFFSET_ANA_Register
MACRUM	0:615f90842ce8	598	* @{
MACRUM	0:615f90842ce8	599	*/
MACRUM	0:615f90842ce8	600
MACRUM	0:615f90842ce8	601	/**
MACRUM	0:615f90842ce8	602	* \brief IF_OFFSET_ANA register
MACRUM	0:615f90842ce8	603	* \code
MACRUM	0:615f90842ce8	604	* Read Write
MACRUM	0:615f90842ce8	605	* Default value: 0xA3
MACRUM	0:615f90842ce8	606	* 7:0 IF_OFFSET_ANA[7:0]: Intermediate frequency setting for the digital shift-to-baseband circuits. According to the formula: fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz.
MACRUM	0:615f90842ce8	607	*
MACRUM	0:615f90842ce8	608	* \endcode
MACRUM	0:615f90842ce8	609	*/
MACRUM	0:615f90842ce8	610	#define IF_OFFSET_ANA_BASE ((uint8_t)0x07) /!< Intermediate frequency fIF=fXO(IF_OFFSET_ANA+64)/(122^10)=fCLK(IF_OFFSET_DIG+64)/(122^10) Hz /
MACRUM	0:615f90842ce8	611
MACRUM	0:615f90842ce8	612
MACRUM	0:615f90842ce8	613	/**
MACRUM	0:615f90842ce8	614	* @}
MACRUM	0:615f90842ce8	615	*/
MACRUM	0:615f90842ce8	616
MACRUM	0:615f90842ce8	617	/** @defgroup FC_OFFSET1_Register
MACRUM	0:615f90842ce8	618	* @{
MACRUM	0:615f90842ce8	619	*/
MACRUM	0:615f90842ce8	620
MACRUM	0:615f90842ce8	621	/**
MACRUM	0:615f90842ce8	622	* \brief FC_OFFSET1 registers
MACRUM	0:615f90842ce8	623	* \code
MACRUM	0:615f90842ce8	624	* Read Write
MACRUM	0:615f90842ce8	625	* Default value: 0xA3
MACRUM	0:615f90842ce8	626	* 7:4 Reserved.
MACRUM	0:615f90842ce8	627	* 3:0 FC_OFFSET[11:8]: Carrier offset. This value is the higher part of a 12-bit 2s complement integer
MACRUM	0:615f90842ce8	628	* representing an offset in 99Hz(2) units added/subtracted to the
MACRUM	0:615f90842ce8	629	* carrier frequency set by registers SYNT3SYNT0.
MACRUM	0:615f90842ce8	630	* This register can be used to set a fixed correction value
MACRUM	0:615f90842ce8	631	* obtained e.g. from crystal measurements.
MACRUM	0:615f90842ce8	632	*
MACRUM	0:615f90842ce8	633	* \endcode
MACRUM	0:615f90842ce8	634	*/
MACRUM	0:615f90842ce8	635	#define FC_OFFSET1_BASE ((uint8_t)0x0E) /!< [3:0] -> [11:8] Carrier offset (upper part) /
MACRUM	0:615f90842ce8	636
MACRUM	0:615f90842ce8	637	/**
MACRUM	0:615f90842ce8	638	* @}
MACRUM	0:615f90842ce8	639	*/
MACRUM	0:615f90842ce8	640
MACRUM	0:615f90842ce8	641
MACRUM	0:615f90842ce8	642	/** @defgroup FC_OFFSET0_Register
MACRUM	0:615f90842ce8	643	* @{
MACRUM	0:615f90842ce8	644	*/
MACRUM	0:615f90842ce8	645
MACRUM	0:615f90842ce8	646	/**
MACRUM	0:615f90842ce8	647	* \brief FC_OFFSET0 registers
MACRUM	0:615f90842ce8	648	* \code
MACRUM	0:615f90842ce8	649	* Default value: 0x00
MACRUM	0:615f90842ce8	650	* Read Write
MACRUM	0:615f90842ce8	651	* 7:0 FC_OFFSET[7:0]: Carrier offset. This value is the lower part of a 12-bit 2s complement integer
MACRUM	0:615f90842ce8	652	* representing an offset in 99Hz(2) units added/subtracted to the
MACRUM	0:615f90842ce8	653	* carrier frequency set by registers SYNT3SYNT0.
MACRUM	0:615f90842ce8	654	* This register can be used to set a fixed correction value
MACRUM	0:615f90842ce8	655	* obtained e.g. from crystal measurements.
MACRUM	0:615f90842ce8	656	*
MACRUM	0:615f90842ce8	657	* \endcode
MACRUM	0:615f90842ce8	658	*/
MACRUM	0:615f90842ce8	659	#define FC_OFFSET0_BASE ((uint8_t)0x0F) /*!< [7:0] -> [7:0] Carrier offset (lower part). This value is a 12-bit 2s complement integer
MACRUM	0:615f90842ce8	660	representing an offset in fXO/2^18 (99Hz for 26 MHz XO) units added/subtracted to the carrier frequency
MACRUM	0:615f90842ce8	661	set by registers SYNT3SYNT0. Range is +/-200kHz with 26 MHz XO */
MACRUM	0:615f90842ce8	662	/**
MACRUM	0:615f90842ce8	663	* @}
MACRUM	0:615f90842ce8	664	*/
MACRUM	0:615f90842ce8	665
MACRUM	0:615f90842ce8	666
MACRUM	0:615f90842ce8	667	/** @defgroup PA_LEVEL_x_Registers
MACRUM	0:615f90842ce8	668	* @{
MACRUM	0:615f90842ce8	669	*/
MACRUM	0:615f90842ce8	670
MACRUM	0:615f90842ce8	671	/**
MACRUM	0:615f90842ce8	672	* \brief PA_POWER_x[8:1] registers
MACRUM	0:615f90842ce8	673	* \code
MACRUM	0:615f90842ce8	674	* Default values from 8 to 1: [0x03, 0x0E, 0x1A, 0x25, 0x35, 0x40, 0x4E, 0x00]
MACRUM	0:615f90842ce8	675	* Read Write
MACRUM	0:615f90842ce8	676	*
MACRUM	0:615f90842ce8	677	* 7 Reserved.
MACRUM	0:615f90842ce8	678	* 6:0 PA_LEVEL_(x-1)[6:0]: Output power level for x-th slot.
MACRUM	0:615f90842ce8	679	* \endcode
MACRUM	0:615f90842ce8	680	*/
MACRUM	0:615f90842ce8	681
MACRUM	0:615f90842ce8	682	#define PA_POWER8_BASE ((uint8_t)0x10) /!< PA Power level for 8th slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	683	#define PA_POWER7_BASE ((uint8_t)0x11) /!< PA Power level for 7th slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	684	#define PA_POWER6_BASE ((uint8_t)0x12) /!< PA Power level for 6th slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	685	#define PA_POWER5_BASE ((uint8_t)0x13) /!< PA Power level for 5th slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	686	#define PA_POWER4_BASE ((uint8_t)0x14) /!< PA Power level for 4th slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	687	#define PA_POWER3_BASE ((uint8_t)0x15) /!< PA Power level for 3rd slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	688	#define PA_POWER2_BASE ((uint8_t)0x16) /!< PA Power level for 2nd slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	689	#define PA_POWER1_BASE ((uint8_t)0x17) /!< PA Power level for 1st slot of PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	690
MACRUM	0:615f90842ce8	691	/**
MACRUM	0:615f90842ce8	692	* @}
MACRUM	0:615f90842ce8	693	*/
MACRUM	0:615f90842ce8	694
MACRUM	0:615f90842ce8	695	/** @defgroup PA_POWER_CONF_Registers
MACRUM	0:615f90842ce8	696	* @{
MACRUM	0:615f90842ce8	697	*/
MACRUM	0:615f90842ce8	698
MACRUM	0:615f90842ce8	699	/**
MACRUM	0:615f90842ce8	700	* \brief PA_POWER_CONF_Registers
MACRUM	0:615f90842ce8	701	* \code
MACRUM	0:615f90842ce8	702	* Default value:0x07
MACRUM	0:615f90842ce8	703	* Read Write
MACRUM	0:615f90842ce8	704	*
MACRUM	0:615f90842ce8	705	* 7:6 CWC[1:0]: Output stage additional load capacitors bank (to be used to
MACRUM	0:615f90842ce8	706	* optimize the PA for different sub-bands).
MACRUM	0:615f90842ce8	707	*
MACRUM	0:615f90842ce8	708	* CWC1 \| CWC0 \| Total capacity in pF
MACRUM	0:615f90842ce8	709	* ---------------------------------------------------------
MACRUM	0:615f90842ce8	710	* 0 \| 0 \| 0
MACRUM	0:615f90842ce8	711	* 0 \| 1 \| 1.2
MACRUM	0:615f90842ce8	712	* 1 \| 0 \| 2.4
MACRUM	0:615f90842ce8	713	* 1 \| 1 \| 3.6
MACRUM	0:615f90842ce8	714	*
MACRUM	0:615f90842ce8	715	* 5 PA_RAMP_ENABLE:
MACRUM	0:615f90842ce8	716	* 1 - Enable the power ramping
MACRUM	0:615f90842ce8	717	* 0 - Disable the power ramping
MACRUM	0:615f90842ce8	718	* 4:3 PA_RAMP_STEP_WIDTH[1:0]: Step width in bit period
MACRUM	0:615f90842ce8	719	*
MACRUM	0:615f90842ce8	720	* PA_RAMP_STEP_WIDTH1 \| PA_RAMP_STEP_WIDTH0 \| PA ramping time step
MACRUM	0:615f90842ce8	721	* -------------------------------------------------------------------------------------------
MACRUM	0:615f90842ce8	722	* 0 \| 0 \| 1/8 Bit period
MACRUM	0:615f90842ce8	723	* 0 \| 1 \| 2/8 Bit period
MACRUM	0:615f90842ce8	724	* 1 \| 0 \| 3/8 Bit period
MACRUM	0:615f90842ce8	725	* 1 \| 1 \| 4/8 Bit period
MACRUM	0:615f90842ce8	726	*
MACRUM	0:615f90842ce8	727	* 2:0 PA_LEVEL_MAX_INDEX[2:0]: Fixes the MAX PA LEVEL in PA ramping or ASK modulation
MACRUM	0:615f90842ce8	728	*
MACRUM	0:615f90842ce8	729	* \endcode
MACRUM	0:615f90842ce8	730	*/
MACRUM	0:615f90842ce8	731	#define PA_POWER0_BASE ((uint8_t)0x18) /*!< PA ramping settings and additional load capacitor banks used
MACRUM	0:615f90842ce8	732	for PA optimization in different sub bands*/
MACRUM	0:615f90842ce8	733	#define PA_POWER0_CWC_MASK ((uint8_t)0x20) /!< Output stage additional load capacitors bank /
MACRUM	0:615f90842ce8	734	#define PA_POWER0_CWC_0 ((uint8_t)0x00) /!< No additional PA load capacitor /
MACRUM	0:615f90842ce8	735	#define PA_POWER0_CWC_1_2P ((uint8_t)0x40) /!< 1.2pF additional PA load capacitor /
MACRUM	0:615f90842ce8	736	#define PA_POWER0_CWC_2_4P ((uint8_t)0x80) /!< 2.4pF additional PA load capacitor /
MACRUM	0:615f90842ce8	737	#define PA_POWER0_CWC_3_6P ((uint8_t)0xC0) /!< 3.6pF additional PA load capacitor /
MACRUM	0:615f90842ce8	738	#define PA_POWER0_PA_RAMP_MASK ((uint8_t)0x20) /!< The PA power ramping /
MACRUM	0:615f90842ce8	739	#define PA_POWER0_PA_RAMP_STEP_WIDTH_MASK ((uint8_t)0x20) /!< The step width /
MACRUM	0:615f90842ce8	740	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_8 ((uint8_t)0x00) /!< PA ramping time step = 1/8 Bit period/
MACRUM	0:615f90842ce8	741	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_4 ((uint8_t)0x08) /!< PA ramping time step = 2/8 Bit period/
MACRUM	0:615f90842ce8	742	#define PA_POWER0_PA_RAMP_STEP_WIDTH_3TB_8 ((uint8_t)0x10) /!< PA ramping time step = 3/8 Bit period/
MACRUM	0:615f90842ce8	743	#define PA_POWER0_PA_RAMP_STEP_WIDTH_TB_2 ((uint8_t)0x18) /!< PA ramping time step = 4/8 Bit period/
MACRUM	0:615f90842ce8	744	#define PA_POWER0_PA_LEVEL_MAX_INDEX ((uint8_t)0x20) /!< Final level for power ramping /
MACRUM	0:615f90842ce8	745	#define PA_POWER0_PA_LEVEL_MAX_INDEX_0 ((uint8_t)0x00) /!< /
MACRUM	0:615f90842ce8	746	#define PA_POWER0_PA_LEVEL_MAX_INDEX_1 ((uint8_t)0x01) /!< Fixes the MAX PA LEVEL in PA ramping or ASK modulation /
MACRUM	0:615f90842ce8	747	#define PA_POWER0_PA_LEVEL_MAX_INDEX_2 ((uint8_t)0x02) /!< /
MACRUM	0:615f90842ce8	748	#define PA_POWER0_PA_LEVEL_MAX_INDEX_3 ((uint8_t)0x03) /!< _________ /
MACRUM	0:615f90842ce8	749	#define PA_POWER0_PA_LEVEL_MAX_INDEX_4 ((uint8_t)0x04) /!< PA_LVL2 _\| <--\| /
MACRUM	0:615f90842ce8	750	#define PA_POWER0_PA_LEVEL_MAX_INDEX_5 ((uint8_t)0x05) /!< _\| \| /
MACRUM	0:615f90842ce8	751	#define PA_POWER0_PA_LEVEL_MAX_INDEX_6 ((uint8_t)0x06) /!< PA_LVL1 _\| \| /
MACRUM	0:615f90842ce8	752	#define PA_POWER0_PA_LEVEL_MAX_INDEX_7 ((uint8_t)0x07) /!< PA_LVL0 _\| MAX_INDEX- /
MACRUM	0:615f90842ce8	753
MACRUM	0:615f90842ce8	754
MACRUM	0:615f90842ce8	755
MACRUM	0:615f90842ce8	756	/**
MACRUM	0:615f90842ce8	757	* @}
MACRUM	0:615f90842ce8	758	*/
MACRUM	0:615f90842ce8	759
MACRUM	0:615f90842ce8	760
MACRUM	0:615f90842ce8	761	/** @defgroup MOD1_Register
MACRUM	0:615f90842ce8	762	* @{
MACRUM	0:615f90842ce8	763	*/
MACRUM	0:615f90842ce8	764
MACRUM	0:615f90842ce8	765	/**
MACRUM	0:615f90842ce8	766	* \brief MOD1 register
MACRUM	0:615f90842ce8	767	* \code
MACRUM	0:615f90842ce8	768	* Read Write
MACRUM	0:615f90842ce8	769	* Default value: 0x83
MACRUM	0:615f90842ce8	770	* 7:0 DATARATE_M[7:0]: The Mantissa of the specified data rate
MACRUM	0:615f90842ce8	771	*
MACRUM	0:615f90842ce8	772	* \endcode
MACRUM	0:615f90842ce8	773	*/
MACRUM	0:615f90842ce8	774	#define MOD1_BASE ((uint8_t)0x1A) /!< The Mantissa of the specified data rate /
MACRUM	0:615f90842ce8	775
MACRUM	0:615f90842ce8	776	/**
MACRUM	0:615f90842ce8	777	* @}
MACRUM	0:615f90842ce8	778	*/
MACRUM	0:615f90842ce8	779
MACRUM	0:615f90842ce8	780	/** @defgroup MOD0_Register
MACRUM	0:615f90842ce8	781	* @{
MACRUM	0:615f90842ce8	782	*/
MACRUM	0:615f90842ce8	783
MACRUM	0:615f90842ce8	784	/**
MACRUM	0:615f90842ce8	785	* \brief MOD0 register
MACRUM	0:615f90842ce8	786	* \code
MACRUM	0:615f90842ce8	787	* Read Write
MACRUM	0:615f90842ce8	788	* Default value: 0x1A
MACRUM	0:615f90842ce8	789	* 7 CW: 1 - CW Mode enabled - enables the generation of a continous wave carrier without any modulation
MACRUM	0:615f90842ce8	790	* 0 - CW Mode disabled
MACRUM	0:615f90842ce8	791	*
MACRUM	0:615f90842ce8	792	* 6 BT_SEL: Select BT value for GFSK
MACRUM	0:615f90842ce8	793	* 1 - BT=0.5
MACRUM	0:615f90842ce8	794	* 0 - BT=1
MACRUM	0:615f90842ce8	795	*
MACRUM	0:615f90842ce8	796	* 5:4 MOD_TYPE[1:0]: Modulation type
MACRUM	0:615f90842ce8	797	*
MACRUM	0:615f90842ce8	798	*
MACRUM	0:615f90842ce8	799	* MOD_TYPE1 \| MOD_TYPE0 \| Modulation
MACRUM	0:615f90842ce8	800	* ---------------------------------------------------------
MACRUM	0:615f90842ce8	801	* 0 \| 0 \| 2-FSK,MSK
MACRUM	0:615f90842ce8	802	* 0 \| 1 \| GFSK,GMSK
MACRUM	0:615f90842ce8	803	* 1 \| 0 \| ASK/OOK
MACRUM	0:615f90842ce8	804	*
MACRUM	0:615f90842ce8	805	* 3:0 DATARATE_E[3:0]: The Exponent of the specified data rate
MACRUM	0:615f90842ce8	806	*
MACRUM	0:615f90842ce8	807	* \endcode
MACRUM	0:615f90842ce8	808	*/
MACRUM	0:615f90842ce8	809	#define MOD0_BASE ((uint8_t)0x1B) /!< Modulation Settings, Exponent of the specified data rate, CW mode/
MACRUM	0:615f90842ce8	810
MACRUM	0:615f90842ce8	811	#define MOD0_MOD_TYPE_2_FSK ((uint8_t)0x00) /!< Modulation type 2-FSK (MSK if the frequency deviation is identical to a quarter of the data rate) /
MACRUM	0:615f90842ce8	812	#define MOD0_MOD_TYPE_GFSK ((uint8_t)0x10) /!< Modulation type GFSK (GMSK if the frequency deviation is identical to a quarter of the data rate) /
MACRUM	0:615f90842ce8	813	#define MOD0_MOD_TYPE_ASK ((uint8_t)0x20) /!< Modulation type ASK (OOK the PA is switched off for symbol "0") /
MACRUM	0:615f90842ce8	814	#define MOD0_MOD_TYPE_MSK ((uint8_t)0x00) /!< Modulation type MSK (the frequency deviation must be identical to a quarter of the data rate) /
MACRUM	0:615f90842ce8	815	#define MOD0_MOD_TYPE_GMSK ((uint8_t)0x10) /!< Modulation type GMSK (the frequency deviation must be identical to a quarter of the data rate) /
MACRUM	0:615f90842ce8	816	#define MOD0_BT_SEL_BT_MASK ((uint8_t)0x00) /!< Select the BT = 1 or BT = 0.5 valid only for GFSK or GMSK modulation/
MACRUM	0:615f90842ce8	817	#define MOD0_CW ((uint8_t)0x80) /!< Set the Continous Wave (no modulation) transmit mode /
MACRUM	0:615f90842ce8	818
MACRUM	0:615f90842ce8	819	/**
MACRUM	0:615f90842ce8	820	* @}
MACRUM	0:615f90842ce8	821	*/
MACRUM	0:615f90842ce8	822
MACRUM	0:615f90842ce8	823
MACRUM	0:615f90842ce8	824	/** @defgroup FDEV0_Register
MACRUM	0:615f90842ce8	825	* @{
MACRUM	0:615f90842ce8	826	*/
MACRUM	0:615f90842ce8	827
MACRUM	0:615f90842ce8	828	/**
MACRUM	0:615f90842ce8	829	* \brief FDEV0 register
MACRUM	0:615f90842ce8	830	* \code
MACRUM	0:615f90842ce8	831	* Read Write
MACRUM	0:615f90842ce8	832	* Default value: 0x45
MACRUM	0:615f90842ce8	833	* 7:4 FDEV_E[3:0]: Exponent of the frequency deviation (allowed values from 0 to 9)
MACRUM	0:615f90842ce8	834	*
MACRUM	0:615f90842ce8	835	* 3 CLOCK_REC_ALGO_SEL: Select PLL or DLL mode for clock recovery
MACRUM	0:615f90842ce8	836	* 1 - DLL mode
MACRUM	0:615f90842ce8	837	* 0 - PLL mode
MACRUM	0:615f90842ce8	838	*
MACRUM	0:615f90842ce8	839	* 2:0 FDEV_M[1:0]: Mantissa of the frequency deviation (allowed values from 0 to 7)
MACRUM	0:615f90842ce8	840	*
MACRUM	0:615f90842ce8	841	*
MACRUM	0:615f90842ce8	842	* \endcode
MACRUM	0:615f90842ce8	843	*/
MACRUM	0:615f90842ce8	844	#define FDEV0_BASE ((uint8_t)0x1C) /*!< Sets the Mantissa and exponent of frequency deviation (frequency separation/2)
MACRUM	0:615f90842ce8	845	and PLL or DLL alogrithm from clock recovery in RX digital demod*/
MACRUM	0:615f90842ce8	846	#define FDEV0_CLOCK_REG_ALGO_SEL_MASK ((uint8_t)0x08) /!< Can be DLL or PLL algorithm for clock recovery in RX digital demod (see CLOCKREC reg) /
MACRUM	0:615f90842ce8	847	#define FDEV0_CLOCK_REG_ALGO_SEL_PLL ((uint8_t)0x00) /!< Sets PLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
MACRUM	0:615f90842ce8	848	#define FDEV0_CLOCK_REG_ALGO_SEL_DLL ((uint8_t)0x08) /!< Sets DLL alogrithm for clock recovery in RX digital demod (see CLOCKREC reg) /
MACRUM	0:615f90842ce8	849
MACRUM	0:615f90842ce8	850	/**
MACRUM	0:615f90842ce8	851	* @}
MACRUM	0:615f90842ce8	852	*/
MACRUM	0:615f90842ce8	853
MACRUM	0:615f90842ce8	854	/** @defgroup CHFLT_Register
MACRUM	0:615f90842ce8	855	* @{
MACRUM	0:615f90842ce8	856	*/
MACRUM	0:615f90842ce8	857
MACRUM	0:615f90842ce8	858	/**
MACRUM	0:615f90842ce8	859	* \brief CHFLT register
MACRUM	0:615f90842ce8	860	* \code
MACRUM	0:615f90842ce8	861	* Read Write
MACRUM	0:615f90842ce8	862	* Default value: 0x23
MACRUM	0:615f90842ce8	863	* 7:4 CHFLT_M[3:0]: Mantissa of the channel filter BW (allowed values from 0 to 8)
MACRUM	0:615f90842ce8	864	*
MACRUM	0:615f90842ce8	865	* 3:0 CHFLT_E[3:0]: Exponent of the channel filter BW (allowed values from 0 to 9)
MACRUM	0:615f90842ce8	866	*
MACRUM	0:615f90842ce8	867	* M\E \| 0 \| 1 \| 2 \| 3 \| 4 \| 5 \| 6 \| 7 \| 8 \| 9 \|
MACRUM	0:615f90842ce8	868	* -----+-------+-------+-------+-------+------+------+------+-----+-----+-----+
MACRUM	0:615f90842ce8	869	* 0 \| 800.1 \| 450.9 \| 224.7 \| 112.3 \| 56.1 \| 28.0 \| 14.0 \| 7.0 \| 3.5 \| 1.8 \|
MACRUM	0:615f90842ce8	870	* 1 \| 795.1 \| 425.9 \| 212.4 \| 106.2 \| 53.0 \| 26.5 \| 13.3 \| 6.6 \| 3.3 \| 1.7 \|
MACRUM	0:615f90842ce8	871	* 2 \| 768.4 \| 403.2 \| 201.1 \| 100.5 \| 50.2 \| 25.1 \| 12.6 \| 6.3 \| 3.1 \| 1.6 \|
MACRUM	0:615f90842ce8	872	* 3 \| 736.8 \| 380.8 \| 190.0 \| 95.0 \| 47.4 \| 23.7 \| 11.9 \| 5.9 \| 3.0 \| 1.5 \|
MACRUM	0:615f90842ce8	873	* 4 \| 705.1 \| 362.1 \| 180.7 \| 90.3 \| 45.1 \| 22.6 \| 11.3 \| 5.6 \| 2.8 \| 1.4 \|
MACRUM	0:615f90842ce8	874	* 5 \| 670.9 \| 341.7 \| 170.6 \| 85.3 \| 42.6 \| 21.3 \| 10.6 \| 5.3 \| 2.7 \| 1.3 \|
MACRUM	0:615f90842ce8	875	* 6 \| 642.3 \| 325.4 \| 162.4 \| 81.2 \| 40.6 \| 20.3 \| 10.1 \| 5.1 \| 2.5 \| 1.3 \|
MACRUM	0:615f90842ce8	876	* 7 \| 586.7 \| 294.5 \| 147.1 \| 73.5 \| 36.7 \| 18.4 \| 9.2 \| 4.6 \| 2.3 \| 1.2 \|
MACRUM	0:615f90842ce8	877	* 8 \| 541.4 \| 270.3 \| 135.0 \| 67.5 \| 33.7 \| 16.9 \| 8.4 \| 4.2 \| 2.1 \| 1.1 \|
MACRUM	0:615f90842ce8	878	*
MACRUM	0:615f90842ce8	879	* \endcode
MACRUM	0:615f90842ce8	880	*/
MACRUM	0:615f90842ce8	881	#define CHFLT_BASE ((uint8_t)0x1D) /!< RX Channel Filter Bandwidth /
MACRUM	0:615f90842ce8	882
MACRUM	0:615f90842ce8	883	#define CHFLT_800_1 ((uint8_t)0x00) /!< RX Channel Filter Bandwidth = 800.1 kHz /
MACRUM	0:615f90842ce8	884	#define CHFLT_795_1 ((uint8_t)0x10) /!< RX Channel Filter Bandwidth = 795.1 kHz /
MACRUM	0:615f90842ce8	885	#define CHFLT_768_4 ((uint8_t)0x20) /!< RX Channel Filter Bandwidth = 768.4 kHz /
MACRUM	0:615f90842ce8	886	#define CHFLT_736_8 ((uint8_t)0x30) /!< RX Channel Filter Bandwidth = 736.8 kHz /
MACRUM	0:615f90842ce8	887	#define CHFLT_705_1 ((uint8_t)0x40) /!< RX Channel Filter Bandwidth = 705.1 kHz /
MACRUM	0:615f90842ce8	888	#define CHFLT_670_9 ((uint8_t)0x50) /!< RX Channel Filter Bandwidth = 670.9 kHz /
MACRUM	0:615f90842ce8	889	#define CHFLT_642_3 ((uint8_t)0x60) /!< RX Channel Filter Bandwidth = 642.3 kHz /
MACRUM	0:615f90842ce8	890	#define CHFLT_586_7 ((uint8_t)0x70) /!< RX Channel Filter Bandwidth = 586.7 kHz /
MACRUM	0:615f90842ce8	891	#define CHFLT_541_4 ((uint8_t)0x80) /!< RX Channel Filter Bandwidth = 541.4 kHz /
MACRUM	0:615f90842ce8	892	#define CHFLT_450_9 ((uint8_t)0x01) /!< RX Channel Filter Bandwidth = 450.9 kHz /
MACRUM	0:615f90842ce8	893	#define CHFLT_425_9 ((uint8_t)0x11) /!< RX Channel Filter Bandwidth = 425.9 kHz /
MACRUM	0:615f90842ce8	894	#define CHFLT_403_2 ((uint8_t)0x21) /!< RX Channel Filter Bandwidth = 403.2 kHz /
MACRUM	0:615f90842ce8	895	#define CHFLT_380_8 ((uint8_t)0x31) /!< RX Channel Filter Bandwidth = 380.8 kHz /
MACRUM	0:615f90842ce8	896	#define CHFLT_362_1 ((uint8_t)0x41) /!< RX Channel Filter Bandwidth = 362.1 kHz /
MACRUM	0:615f90842ce8	897	#define CHFLT_341_7 ((uint8_t)0x51) /!< RX Channel Filter Bandwidth = 341.7 kHz /
MACRUM	0:615f90842ce8	898	#define CHFLT_325_4 ((uint8_t)0x61) /!< RX Channel Filter Bandwidth = 325.4 kHz /
MACRUM	0:615f90842ce8	899	#define CHFLT_294_5 ((uint8_t)0x71) /!< RX Channel Filter Bandwidth = 294.5 kHz /
MACRUM	0:615f90842ce8	900	#define CHFLT_270_3 ((uint8_t)0x81) /!< RX Channel Filter Bandwidth = 270.3 kHz /
MACRUM	0:615f90842ce8	901	#define CHFLT_224_7 ((uint8_t)0x02) /!< RX Channel Filter Bandwidth = 224.7 kHz /
MACRUM	0:615f90842ce8	902	#define CHFLT_212_4 ((uint8_t)0x12) /!< RX Channel Filter Bandwidth = 212.4 kHz /
MACRUM	0:615f90842ce8	903	#define CHFLT_201_1 ((uint8_t)0x22) /!< RX Channel Filter Bandwidth = 201.1 kHz /
MACRUM	0:615f90842ce8	904	#define CHFLT_190 ((uint8_t)0x32) /!< RX Channel Filter Bandwidth = 190.0 kHz /
MACRUM	0:615f90842ce8	905	#define CHFLT_180_7 ((uint8_t)0x42) /!< RX Channel Filter Bandwidth = 180.7 kHz /
MACRUM	0:615f90842ce8	906	#define CHFLT_170_6 ((uint8_t)0x52) /!< RX Channel Filter Bandwidth = 170.6 kHz /
MACRUM	0:615f90842ce8	907	#define CHFLT_162_4 ((uint8_t)0x62) /!< RX Channel Filter Bandwidth = 162.4 kHz /
MACRUM	0:615f90842ce8	908	#define CHFLT_147_1 ((uint8_t)0x72) /!< RX Channel Filter Bandwidth = 147.1 kHz /
MACRUM	0:615f90842ce8	909	#define CHFLT_135 ((uint8_t)0x82) /!< RX Channel Filter Bandwidth = 135.0 kHz /
MACRUM	0:615f90842ce8	910	#define CHFLT_112_3 ((uint8_t)0x03) /!< RX Channel Filter Bandwidth = 112.3 kHz /
MACRUM	0:615f90842ce8	911	#define CHFLT_106_2 ((uint8_t)0x13) /!< RX Channel Filter Bandwidth = 106.2 kHz /
MACRUM	0:615f90842ce8	912	#define CHFLT_100_5 ((uint8_t)0x23) /!< RX Channel Filter Bandwidth = 100.5 kHz /
MACRUM	0:615f90842ce8	913	#define CHFLT_95 ((uint8_t)0x33) /!< RX Channel Filter Bandwidth = 95.0 kHz /
MACRUM	0:615f90842ce8	914	#define CHFLT_90_3 ((uint8_t)0x43) /!< RX Channel Filter Bandwidth = 90.3 kHz /
MACRUM	0:615f90842ce8	915	#define CHFLT_85_3 ((uint8_t)0x53) /!< RX Channel Filter Bandwidth = 85.3 kHz /
MACRUM	0:615f90842ce8	916	#define CHFLT_81_2 ((uint8_t)0x63) /!< RX Channel Filter Bandwidth = 81.2 kHz /
MACRUM	0:615f90842ce8	917	#define CHFLT_73_5 ((uint8_t)0x73) /!< RX Channel Filter Bandwidth = 73.5 kHz /
MACRUM	0:615f90842ce8	918	#define CHFLT_67_5 ((uint8_t)0x83) /!< RX Channel Filter Bandwidth = 67.5 kHz /
MACRUM	0:615f90842ce8	919	#define CHFLT_56_1 ((uint8_t)0x04) /!< RX Channel Filter Bandwidth = 56.1 kHz /
MACRUM	0:615f90842ce8	920	#define CHFLT_53 ((uint8_t)0x14) /!< RX Channel Filter Bandwidth = 53.0 kHz /
MACRUM	0:615f90842ce8	921	#define CHFLT_50_2 ((uint8_t)0x24) /!< RX Channel Filter Bandwidth = 50.2 kHz /
MACRUM	0:615f90842ce8	922	#define CHFLT_47_4 ((uint8_t)0x34) /!< RX Channel Filter Bandwidth = 47.4 kHz /
MACRUM	0:615f90842ce8	923	#define CHFLT_45_1 ((uint8_t)0x44) /!< RX Channel Filter Bandwidth = 45.1 kHz /
MACRUM	0:615f90842ce8	924	#define CHFLT_42_6 ((uint8_t)0x54) /!< RX Channel Filter Bandwidth = 42.6 kHz /
MACRUM	0:615f90842ce8	925	#define CHFLT_40_6 ((uint8_t)0x64) /!< RX Channel Filter Bandwidth = 40.6 kHz /
MACRUM	0:615f90842ce8	926	#define CHFLT_36_7 ((uint8_t)0x74) /!< RX Channel Filter Bandwidth = 36.7 kHz /
MACRUM	0:615f90842ce8	927	#define CHFLT_33_7 ((uint8_t)0x84) /!< RX Channel Filter Bandwidth = 33.7 kHz /
MACRUM	0:615f90842ce8	928	#define CHFLT_28 ((uint8_t)0x05) /!< RX Channel Filter Bandwidth = 28.0 kHz /
MACRUM	0:615f90842ce8	929	#define CHFLT_26_5 ((uint8_t)0x15) /!< RX Channel Filter Bandwidth = 26.5 kHz /
MACRUM	0:615f90842ce8	930	#define CHFLT_25_1 ((uint8_t)0x25) /!< RX Channel Filter Bandwidth = 25.1 kHz /
MACRUM	0:615f90842ce8	931	#define CHFLT_23_7 ((uint8_t)0x35) /!< RX Channel Filter Bandwidth = 23.7 kHz /
MACRUM	0:615f90842ce8	932	#define CHFLT_22_6 ((uint8_t)0x45) /!< RX Channel Filter Bandwidth = 22.6 kHz /
MACRUM	0:615f90842ce8	933	#define CHFLT_21_3 ((uint8_t)0x55) /!< RX Channel Filter Bandwidth = 21.3 kHz /
MACRUM	0:615f90842ce8	934	#define CHFLT_20_3 ((uint8_t)0x65) /!< RX Channel Filter Bandwidth = 20.3 kHz /
MACRUM	0:615f90842ce8	935	#define CHFLT_18_4 ((uint8_t)0x75) /!< RX Channel Filter Bandwidth = 18.4 kHz /
MACRUM	0:615f90842ce8	936	#define CHFLT_16_9 ((uint8_t)0x85) /!< RX Channel Filter Bandwidth = 16.9 kHz /
MACRUM	0:615f90842ce8	937	#define CHFLT_14 ((uint8_t)0x06) /!< RX Channel Filter Bandwidth = 14.0 kHz /
MACRUM	0:615f90842ce8	938	#define CHFLT_13_3 ((uint8_t)0x16) /!< RX Channel Filter Bandwidth = 13.3 kHz /
MACRUM	0:615f90842ce8	939	#define CHFLT_12_6 ((uint8_t)0x26) /!< RX Channel Filter Bandwidth = 12.6 kHz /
MACRUM	0:615f90842ce8	940	#define CHFLT_11_9 ((uint8_t)0x36) /!< RX Channel Filter Bandwidth = 11.9 kHz /
MACRUM	0:615f90842ce8	941	#define CHFLT_11_3 ((uint8_t)0x46) /!< RX Channel Filter Bandwidth = 11.3 kHz /
MACRUM	0:615f90842ce8	942	#define CHFLT_10_6 ((uint8_t)0x56) /!< RX Channel Filter Bandwidth = 10.6 kHz /
MACRUM	0:615f90842ce8	943	#define CHFLT_10_1 ((uint8_t)0x66) /!< RX Channel Filter Bandwidth = 10.1 kHz /
MACRUM	0:615f90842ce8	944	#define CHFLT_9_2 ((uint8_t)0x76) /!< RX Channel Filter Bandwidth = 9.2 kHz /
MACRUM	0:615f90842ce8	945	#define CHFLT_8_4 ((uint8_t)0x86) /!< RX Channel Filter Bandwidth = 8.4 kHz /
MACRUM	0:615f90842ce8	946	#define CHFLT_7 ((uint8_t)0x07) /!< RX Channel Filter Bandwidth = 7.0 kHz /
MACRUM	0:615f90842ce8	947	#define CHFLT_6_6 ((uint8_t)0x17) /!< RX Channel Filter Bandwidth = 6.6 kHz /
MACRUM	0:615f90842ce8	948	#define CHFLT_6_3 ((uint8_t)0x27) /!< RX Channel Filter Bandwidth = 6.3 kHz /
MACRUM	0:615f90842ce8	949	#define CHFLT_5_9 ((uint8_t)0x37) /!< RX Channel Filter Bandwidth = 5.9 kHz /
MACRUM	0:615f90842ce8	950	#define CHFLT_5_6 ((uint8_t)0x47) /!< RX Channel Filter Bandwidth = 5.6 kHz /
MACRUM	0:615f90842ce8	951	#define CHFLT_5_3 ((uint8_t)0x57) /!< RX Channel Filter Bandwidth = 5.3 kHz /
MACRUM	0:615f90842ce8	952	#define CHFLT_5_1 ((uint8_t)0x67) /!< RX Channel Filter Bandwidth = 5.1 kHz /
MACRUM	0:615f90842ce8	953	#define CHFLT_4_6 ((uint8_t)0x77) /!< RX Channel Filter Bandwidth = 4.6 kHz /
MACRUM	0:615f90842ce8	954	#define CHFLT_4_2 ((uint8_t)0x87) /!< RX Channel Filter Bandwidth = 4.2 kHz /
MACRUM	0:615f90842ce8	955	#define CHFLT_3_5 ((uint8_t)0x08) /!< RX Channel Filter Bandwidth = 3.5 kHz /
MACRUM	0:615f90842ce8	956	#define CHFLT_3_3 ((uint8_t)0x18) /!< RX Channel Filter Bandwidth = 3.3 kHz /
MACRUM	0:615f90842ce8	957	#define CHFLT_3_1 ((uint8_t)0x28) /!< RX Channel Filter Bandwidth = 3.1 kHz /
MACRUM	0:615f90842ce8	958	#define CHFLT_3 ((uint8_t)0x38) /!< RX Channel Filter Bandwidth = 3.0 kHz /
MACRUM	0:615f90842ce8	959	#define CHFLT_2_8 ((uint8_t)0x48) /!< RX Channel Filter Bandwidth = 2.8 kHz /
MACRUM	0:615f90842ce8	960	#define CHFLT_2_7 ((uint8_t)0x58) /!< RX Channel Filter Bandwidth = 2.7 kHz /
MACRUM	0:615f90842ce8	961	#define CHFLT_2_5 ((uint8_t)0x68) /!< RX Channel Filter Bandwidth = 2.5 kHz /
MACRUM	0:615f90842ce8	962	#define CHFLT_2_3 ((uint8_t)0x78) /!< RX Channel Filter Bandwidth = 2.3 kHz /
MACRUM	0:615f90842ce8	963	#define CHFLT_2_1 ((uint8_t)0x88) /!< RX Channel Filter Bandwidth = 2.1 kHz /
MACRUM	0:615f90842ce8	964	#define CHFLT_1_8 ((uint8_t)0x09) /!< RX Channel Filter Bandwidth = 1.8 kHz /
MACRUM	0:615f90842ce8	965	#define CHFLT_1_7 ((uint8_t)0x19) /!< RX Channel Filter Bandwidth = 1.7 kHz /
MACRUM	0:615f90842ce8	966	#define CHFLT_1_6 ((uint8_t)0x29) /!< RX Channel Filter Bandwidth = 1.6 kHz /
MACRUM	0:615f90842ce8	967	#define CHFLT_1_5 ((uint8_t)0x39) /!< RX Channel Filter Bandwidth = 1.5 kHz /
MACRUM	0:615f90842ce8	968	#define CHFLT_1_4 ((uint8_t)0x49) /!< RX Channel Filter Bandwidth = 1.4 kHz /
MACRUM	0:615f90842ce8	969	#define CHFLT_1_3a ((uint8_t)0x59) /!< RX Channel Filter Bandwidth = 1.3 kHz /
MACRUM	0:615f90842ce8	970	#define CHFLT_1_3 ((uint8_t)0x69) /!< RX Channel Filter Bandwidth = 1.3 kHz /
MACRUM	0:615f90842ce8	971	#define CHFLT_1_2 ((uint8_t)0x79) /!< RX Channel Filter Bandwidth = 1.2 kHz /
MACRUM	0:615f90842ce8	972	#define CHFLT_1_1 ((uint8_t)0x89) /!< RX Channel Filter Bandwidth = 1.1 kHz /
MACRUM	0:615f90842ce8	973
MACRUM	0:615f90842ce8	974	/**
MACRUM	0:615f90842ce8	975	* @}
MACRUM	0:615f90842ce8	976	*/
MACRUM	0:615f90842ce8	977
MACRUM	0:615f90842ce8	978	/** @defgroup AFC2_Register
MACRUM	0:615f90842ce8	979	* @{
MACRUM	0:615f90842ce8	980	*/
MACRUM	0:615f90842ce8	981
MACRUM	0:615f90842ce8	982	/**
MACRUM	0:615f90842ce8	983	* \brief AFC2 register
MACRUM	0:615f90842ce8	984	* \code
MACRUM	0:615f90842ce8	985	* Read Write
MACRUM	0:615f90842ce8	986	* Default value: 0x48
MACRUM	0:615f90842ce8	987	* 7 AFC Freeze on Sync: Freeze AFC correction upon sync word detection.
MACRUM	0:615f90842ce8	988	* 1 - AFC Freeze enabled
MACRUM	0:615f90842ce8	989	* 0 - AFC Freeze disabled
MACRUM	0:615f90842ce8	990	*
MACRUM	0:615f90842ce8	991	* 6 AFC Enabled: Enable AFC
MACRUM	0:615f90842ce8	992	* 1 - AFC enabled
MACRUM	0:615f90842ce8	993	* 0 - AFC disabled
MACRUM	0:615f90842ce8	994	*
MACRUM	0:615f90842ce8	995	* 5 AFC Mode: Select AFC mode
MACRUM	0:615f90842ce8	996	* 1 - AFC Loop closed on 2nd conversion stage.
MACRUM	0:615f90842ce8	997	* 0 - AFC Loop closed on slicer
MACRUM	0:615f90842ce8	998	*
MACRUM	0:615f90842ce8	999	* 4:0 AFC PD leakage[4:0]: Peak detector leakage. This parameter sets the decay speed of the min/max frequency peak detector (AFC2 register),
MACRUM	0:615f90842ce8	1000	* the range allowed is 0..31 (0 - no leakage, 31 - high leakage). The recommended value for this parameter is 4.
MACRUM	0:615f90842ce8	1001	*
MACRUM	0:615f90842ce8	1002	* \endcode
MACRUM	0:615f90842ce8	1003	*/
MACRUM	0:615f90842ce8	1004	#define AFC2_BASE ((uint8_t)0x1E) /!< Automatic frequency compensation algorithm parameters (FSK/GFSK/MSK)/
MACRUM	0:615f90842ce8	1005
MACRUM	0:615f90842ce8	1006	#define AFC2_AFC_FREEZE_ON_SYNC_MASK ((uint8_t)0x80) /!< The frequency correction value is frozen when SYNC word is detected /
MACRUM	0:615f90842ce8	1007	#define AFC2_AFC_MASK ((uint8_t)0x40) /!< Mask of Automatic Frequency Correction /
MACRUM	0:615f90842ce8	1008	#define AFC2_AFC_MODE_MASK ((uint8_t)0x20) /!< Automatic Frequency Correction can be in Main MODE or Auxiliary MODE/
MACRUM	0:615f90842ce8	1009	#define AFC2_AFC_MODE_SLICER ((uint8_t)0x00) /!< Automatic Frequency Correction Main MODE /
MACRUM	0:615f90842ce8	1010	#define AFC2_AFC_MODE_MIXER ((uint8_t)0x20) /!< Automatic Frequency Correction Auxiliary MODE /
MACRUM	0:615f90842ce8	1011
MACRUM	0:615f90842ce8	1012	/**
MACRUM	0:615f90842ce8	1013	* @}
MACRUM	0:615f90842ce8	1014	*/
MACRUM	0:615f90842ce8	1015
MACRUM	0:615f90842ce8	1016	/** @defgroup AFC1_Register
MACRUM	0:615f90842ce8	1017	* @{
MACRUM	0:615f90842ce8	1018	*/
MACRUM	0:615f90842ce8	1019
MACRUM	0:615f90842ce8	1020	/**
MACRUM	0:615f90842ce8	1021	* \brief AFC1 register
MACRUM	0:615f90842ce8	1022	* \code
MACRUM	0:615f90842ce8	1023	* Read Write
MACRUM	0:615f90842ce8	1024	* Default value: 0x18
MACRUM	0:615f90842ce8	1025	* 7:0 AFC_FAST_PERIOD: Length of the AFC fast period. this parameter sets the length of the fast period in number of samples (AFC1 register), the range allowed
MACRUM	0:615f90842ce8	1026	* is 0..255. The recommended setting for this parameter is such that the fast period equals the preamble length. Since the
MACRUM	0:615f90842ce8	1027	* algorithm operates typically on 2 samples per symbol, the programmed value should be twice the number of preamble
MACRUM	0:615f90842ce8	1028	* symbols.
MACRUM	0:615f90842ce8	1029	*
MACRUM	0:615f90842ce8	1030	* \endcode
MACRUM	0:615f90842ce8	1031	*/
MACRUM	0:615f90842ce8	1032	#define AFC1_BASE ((uint8_t)0x1F) /!< Length of the AFC fast period /
MACRUM	0:615f90842ce8	1033
MACRUM	0:615f90842ce8	1034	/**
MACRUM	0:615f90842ce8	1035	* @}
MACRUM	0:615f90842ce8	1036	*/
MACRUM	0:615f90842ce8	1037
MACRUM	0:615f90842ce8	1038	/** @defgroup AFC0_Register
MACRUM	0:615f90842ce8	1039	* @{
MACRUM	0:615f90842ce8	1040	*/
MACRUM	0:615f90842ce8	1041
MACRUM	0:615f90842ce8	1042	/**
MACRUM	0:615f90842ce8	1043	* \brief AFC0 register
MACRUM	0:615f90842ce8	1044	* \code
MACRUM	0:615f90842ce8	1045	* Read Write
MACRUM	0:615f90842ce8	1046	* Default value: 0x25
MACRUM	0:615f90842ce8	1047	* 7:4 AFC_FAST_GAIN_LOG2[3:0]: AFC loop gain in fast mode (2's log)
MACRUM	0:615f90842ce8	1048	*
MACRUM	0:615f90842ce8	1049	* 3:0 AFC_SLOW_GAIN_LOG2[3:0]: AFC loop gain in slow mode (2's log)
MACRUM	0:615f90842ce8	1050	*
MACRUM	0:615f90842ce8	1051	* \endcode
MACRUM	0:615f90842ce8	1052	*/
MACRUM	0:615f90842ce8	1053	#define AFC0_BASE ((uint8_t)0x20) /!< AFC loop gain in fast and slow modes (2's log) /
MACRUM	0:615f90842ce8	1054
MACRUM	0:615f90842ce8	1055	/**
MACRUM	0:615f90842ce8	1056	* @}
MACRUM	0:615f90842ce8	1057	*/
MACRUM	0:615f90842ce8	1058
MACRUM	0:615f90842ce8	1059	/** @defgroup CLOCKREC_Register
MACRUM	0:615f90842ce8	1060	* @{
MACRUM	0:615f90842ce8	1061	*/
MACRUM	0:615f90842ce8	1062
MACRUM	0:615f90842ce8	1063	/**
MACRUM	0:615f90842ce8	1064	* \brief CLOCKREC register
MACRUM	0:615f90842ce8	1065	* \code
MACRUM	0:615f90842ce8	1066	* Read Write
MACRUM	0:615f90842ce8	1067	* Default value: 0x58
MACRUM	0:615f90842ce8	1068	*
MACRUM	0:615f90842ce8	1069	* 7:5 CLK_REC_P_GAIN [2:0]: Clock recovery loop gain (log2)
MACRUM	0:615f90842ce8	1070	*
MACRUM	0:615f90842ce8	1071	* 4 PSTFLT_LEN: Set Postfilter length
MACRUM	0:615f90842ce8	1072	* 1 - 16 symbols
MACRUM	0:615f90842ce8	1073	* 0 - 8 symbols
MACRUM	0:615f90842ce8	1074	*
MACRUM	0:615f90842ce8	1075	* 3:0 CLK_REC_I_GAIN[3:0]: Integral gain for the clock recovery loop
MACRUM	0:615f90842ce8	1076	* \endcode
MACRUM	0:615f90842ce8	1077	*/
MACRUM	0:615f90842ce8	1078
MACRUM	0:615f90842ce8	1079	#define CLOCKREC_BASE ((uint8_t)0x23) /!< Gain of clock recovery loop - Postfilter length 0-8 symbols, 1-16 symbols /
MACRUM	0:615f90842ce8	1080
MACRUM	0:615f90842ce8	1081	/**
MACRUM	0:615f90842ce8	1082	* @}
MACRUM	0:615f90842ce8	1083	*/
MACRUM	0:615f90842ce8	1084
MACRUM	0:615f90842ce8	1085	/** @defgroup AGCCTRL2_Register
MACRUM	0:615f90842ce8	1086	* @{
MACRUM	0:615f90842ce8	1087	*/
MACRUM	0:615f90842ce8	1088
MACRUM	0:615f90842ce8	1089	/**
MACRUM	0:615f90842ce8	1090	* \brief AGCCTRL2 register
MACRUM	0:615f90842ce8	1091	* \code
MACRUM	0:615f90842ce8	1092	* Read Write
MACRUM	0:615f90842ce8	1093	* Default value: 0x22
MACRUM	0:615f90842ce8	1094	*
MACRUM	0:615f90842ce8	1095	* 7 Reserved
MACRUM	0:615f90842ce8	1096	*
MACRUM	0:615f90842ce8	1097	* 6 FREEZE_ON_STEADY: Enable freezing on steady state
MACRUM	0:615f90842ce8	1098	* 1 - Enable
MACRUM	0:615f90842ce8	1099	* 0 - Disable
MACRUM	0:615f90842ce8	1100	*
MACRUM	0:615f90842ce8	1101	* 5 FREEZE_ON_SYNC: Enable freezing on sync detection
MACRUM	0:615f90842ce8	1102	* 1 - Enable
MACRUM	0:615f90842ce8	1103	* 0 - Disable
MACRUM	0:615f90842ce8	1104	*
MACRUM	0:615f90842ce8	1105	* 4 START_MAX_ATTENUATION: Start with max attenuation
MACRUM	0:615f90842ce8	1106	* 1 - Enable
MACRUM	0:615f90842ce8	1107	* 0 - Disable
MACRUM	0:615f90842ce8	1108	*
MACRUM	0:615f90842ce8	1109	* 3:0 MEAS_TIME[3:0]: Measure time during which the signal peak is detected (according to the formula 12/fxo*2^MEAS_TIME)
MACRUM	0:615f90842ce8	1110	* \endcode
MACRUM	0:615f90842ce8	1111	*/
MACRUM	0:615f90842ce8	1112	#define AGCCTRL2_BASE ((uint8_t)0x24) /!< AGC freeze strategy, AGC attenuation strategy, AGC measure time /
MACRUM	0:615f90842ce8	1113
MACRUM	0:615f90842ce8	1114	#define AGCCTRL2_FREEZE_ON_STEADY_MASK ((uint8_t)0x40) /*!< The attenuation settings will be frozen as soon as signal level
MACRUM	0:615f90842ce8	1115	is betweeen min and max treshold (see AGCCTRL1) */
MACRUM	0:615f90842ce8	1116	#define AGCCTRL2_FREEZE_ON_SYNC_MASK ((uint8_t)0x20) /!< The attenuation settings will be frozen as soon sync word is detected /
MACRUM	0:615f90842ce8	1117	#define AGCCTRL2_START_MAX_ATTENUATION_MASK ((uint8_t)0x10) /!< The AGC algorithm can start with MAX attenuation or MIN attenuation /
MACRUM	0:615f90842ce8	1118
MACRUM	0:615f90842ce8	1119	/**
MACRUM	0:615f90842ce8	1120	* @}
MACRUM	0:615f90842ce8	1121	*/
MACRUM	0:615f90842ce8	1122
MACRUM	0:615f90842ce8	1123	/** @defgroup AGCCTRL1_Register
MACRUM	0:615f90842ce8	1124	* @{
MACRUM	0:615f90842ce8	1125	*/
MACRUM	0:615f90842ce8	1126
MACRUM	0:615f90842ce8	1127	/**
MACRUM	0:615f90842ce8	1128	* \brief AGCCTRL1 register
MACRUM	0:615f90842ce8	1129	* \code
MACRUM	0:615f90842ce8	1130	* Read Write
MACRUM	0:615f90842ce8	1131	* Default value: 0x65
MACRUM	0:615f90842ce8	1132	*
MACRUM	0:615f90842ce8	1133	* 7:4 THRESHOLD_HIGH[3:0]: High threshold for the AGC
MACRUM	0:615f90842ce8	1134	*
MACRUM	0:615f90842ce8	1135	* 3:0 THRESHOLD_LOW[3:0]: Low threshold for the AGC
MACRUM	0:615f90842ce8	1136	* \endcode
MACRUM	0:615f90842ce8	1137	*/
MACRUM	0:615f90842ce8	1138	#define AGCCTRL1_BASE ((uint8_t)0x25) /!< Sets low and high threshold for AGC /
MACRUM	0:615f90842ce8	1139
MACRUM	0:615f90842ce8	1140	/**
MACRUM	0:615f90842ce8	1141	* @}
MACRUM	0:615f90842ce8	1142	*/
MACRUM	0:615f90842ce8	1143
MACRUM	0:615f90842ce8	1144	/** @defgroup AGCCTRL0_Register
MACRUM	0:615f90842ce8	1145	* @{
MACRUM	0:615f90842ce8	1146	*/
MACRUM	0:615f90842ce8	1147
MACRUM	0:615f90842ce8	1148	/**
MACRUM	0:615f90842ce8	1149	* \brief AGCCTRL0 register
MACRUM	0:615f90842ce8	1150	* \code
MACRUM	0:615f90842ce8	1151	* Read Write
MACRUM	0:615f90842ce8	1152	* Default value: 0x8A
MACRUM	0:615f90842ce8	1153	*
MACRUM	0:615f90842ce8	1154	* 7 AGC S_ENABLE: Enable AGC
MACRUM	0:615f90842ce8	1155	* 1 - Enable
MACRUM	0:615f90842ce8	1156	* 0 - Disable
MACRUM	0:615f90842ce8	1157	*
MACRUM	0:615f90842ce8	1158	* 6 AGC_MODE: Set linear-Binary AGC mode
MACRUM	0:615f90842ce8	1159	* 1 - Enable
MACRUM	0:615f90842ce8	1160	* 0 - Disable
MACRUM	0:615f90842ce8	1161	*
MACRUM	0:615f90842ce8	1162	* 5:0 HOLD_TIME[5:0]: Hold time after gain adjustment according to formula 12/fxo*HOLD_TIME
MACRUM	0:615f90842ce8	1163	* \endcode
MACRUM	0:615f90842ce8	1164	*/
MACRUM	0:615f90842ce8	1165	#define AGCCTRL0_BASE ((uint8_t)0x26) /*!< Enables AGC, set AGC algo between linear/binary mode, set hold time
MACRUM	0:615f90842ce8	1166	to account signal propagation through RX chain */
MACRUM	0:615f90842ce8	1167	#define AGCCTRL0_AGC_MASK ((uint8_t)0x80) /!< AGC on/off /
MACRUM	0:615f90842ce8	1168	#define AGCCTRL0_AGC_MODE_MASK ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode or sequential mode /
MACRUM	0:615f90842ce8	1169	#define AGCCTRL0_AGC_MODE_LINEAR ((uint8_t)0x00) /!< AGC search correct attenuation in sequential mode (recommended) /
MACRUM	0:615f90842ce8	1170	#define AGCCTRL0_AGC_MODE_BINARY ((uint8_t)0x40) /!< AGC search correct attenuation in binary mode /
MACRUM	0:615f90842ce8	1171
MACRUM	0:615f90842ce8	1172	/**
MACRUM	0:615f90842ce8	1173	* @}
MACRUM	0:615f90842ce8	1174	*/
MACRUM	0:615f90842ce8	1175
MACRUM	0:615f90842ce8	1176	/** @defgroup CHNUM_Register
MACRUM	0:615f90842ce8	1177	* @{
MACRUM	0:615f90842ce8	1178	*/
MACRUM	0:615f90842ce8	1179
MACRUM	0:615f90842ce8	1180	/**
MACRUM	0:615f90842ce8	1181	* \brief CHNUM registers
MACRUM	0:615f90842ce8	1182	* \code
MACRUM	0:615f90842ce8	1183	* Default value: 0x00
MACRUM	0:615f90842ce8	1184	* Read Write
MACRUM	0:615f90842ce8	1185	* 7:0 CH_NUM[7:0]: Channel number. This value is multiplied by the channel spacing and added to the
MACRUM	0:615f90842ce8	1186	* synthesizer base frequency to generate the actual RF carrier frequency.
MACRUM	0:615f90842ce8	1187	* \endcode
MACRUM	0:615f90842ce8	1188	*/
MACRUM	0:615f90842ce8	1189	#define CHNUM_BASE ((uint8_t)0x6C) /*!< Channel number. This value is multiplied by the channel
MACRUM	0:615f90842ce8	1190	spacing and added to the synthesizer base frequency to generate the actual RF carrier frequency */
MACRUM	0:615f90842ce8	1191	/**
MACRUM	0:615f90842ce8	1192	* @}
MACRUM	0:615f90842ce8	1193	*/
MACRUM	0:615f90842ce8	1194
MACRUM	0:615f90842ce8	1195	/** @defgroup AFC_CORR_Register
MACRUM	0:615f90842ce8	1196	* @{
MACRUM	0:615f90842ce8	1197	*/
MACRUM	0:615f90842ce8	1198
MACRUM	0:615f90842ce8	1199	/**
MACRUM	0:615f90842ce8	1200	* \brief AFC_CORR registers
MACRUM	0:615f90842ce8	1201	* \code
MACRUM	0:615f90842ce8	1202	* Default value: 0x00
MACRUM	0:615f90842ce8	1203	* Read
MACRUM	0:615f90842ce8	1204	*
MACRUM	0:615f90842ce8	1205	* 7:0 AFC_CORR[7:0]: AFC word of the received packet
MACRUM	0:615f90842ce8	1206	* \endcode
MACRUM	0:615f90842ce8	1207	*/
MACRUM	0:615f90842ce8	1208	#define AFC_CORR_BASE ((uint8_t)(0xC4)) /!< AFC word of the received packet /
MACRUM	0:615f90842ce8	1209
MACRUM	0:615f90842ce8	1210	/**
MACRUM	0:615f90842ce8	1211	* @}
MACRUM	0:615f90842ce8	1212	*/
MACRUM	0:615f90842ce8	1213
MACRUM	0:615f90842ce8	1214	/**
MACRUM	0:615f90842ce8	1215	* @}
MACRUM	0:615f90842ce8	1216	*/
MACRUM	0:615f90842ce8	1217
MACRUM	0:615f90842ce8	1218
MACRUM	0:615f90842ce8	1219	/** @defgroup Packet_Configuration_Registers
MACRUM	0:615f90842ce8	1220	* @{
MACRUM	0:615f90842ce8	1221	*/
MACRUM	0:615f90842ce8	1222
MACRUM	0:615f90842ce8	1223	/** @defgroup PCKTCTRL4_Register
MACRUM	0:615f90842ce8	1224	* @{
MACRUM	0:615f90842ce8	1225	*/
MACRUM	0:615f90842ce8	1226
MACRUM	0:615f90842ce8	1227	/**
MACRUM	0:615f90842ce8	1228	* \brief PCKTCTRL4 register
MACRUM	0:615f90842ce8	1229	* \code
MACRUM	0:615f90842ce8	1230	* Read Write
MACRUM	0:615f90842ce8	1231	* Default value: 0x00
MACRUM	0:615f90842ce8	1232	*
MACRUM	0:615f90842ce8	1233	* 7:5 NOT_USED.
MACRUM	0:615f90842ce8	1234	*
MACRUM	0:615f90842ce8	1235	* 4:3 ADDRESS_LEN[1:0]: length of address field in bytes
MACRUM	0:615f90842ce8	1236	*
MACRUM	0:615f90842ce8	1237	* 2:0 control_len[2:0]: length of control field in bytes
MACRUM	0:615f90842ce8	1238	* \endcode
MACRUM	0:615f90842ce8	1239	*/
MACRUM	0:615f90842ce8	1240	#define PCKTCTRL4_BASE ((uint8_t)0x30) /!< lenghts of address and control field /
MACRUM	0:615f90842ce8	1241
MACRUM	0:615f90842ce8	1242	#define PCKTCTRL4_ADDRESS_LEN_MASK ((uint8_t)0x18)
MACRUM	0:615f90842ce8	1243	#define PCKTCTRL4_CONTROL_LEN_MASK ((uint8_t)0x07)
MACRUM	0:615f90842ce8	1244
MACRUM	0:615f90842ce8	1245	/**
MACRUM	0:615f90842ce8	1246	* @}
MACRUM	0:615f90842ce8	1247	*/
MACRUM	0:615f90842ce8	1248
MACRUM	0:615f90842ce8	1249	/** @defgroup PCKTCTRL3_Register
MACRUM	0:615f90842ce8	1250	* @{
MACRUM	0:615f90842ce8	1251	*/
MACRUM	0:615f90842ce8	1252
MACRUM	0:615f90842ce8	1253	/**
MACRUM	0:615f90842ce8	1254	* \brief PCKTCTRL3 register
MACRUM	0:615f90842ce8	1255	* \code
MACRUM	0:615f90842ce8	1256	* Read Write
MACRUM	0:615f90842ce8	1257	* Default value: 0x07
MACRUM	0:615f90842ce8	1258	*
MACRUM	0:615f90842ce8	1259	* 7:6 PCKT_FRMT[1:0]: format of packet
MACRUM	0:615f90842ce8	1260	*
MACRUM	0:615f90842ce8	1261	* PCKT_FRMT1 \| PCKT_FRMT0 \| Format
MACRUM	0:615f90842ce8	1262	* ----------------------------------------------------------------------
MACRUM	0:615f90842ce8	1263	* 0 \| 0 \| BASIC
MACRUM	0:615f90842ce8	1264	* 1 \| 0 \| MBUS
MACRUM	0:615f90842ce8	1265	* 1 \| 1 \| STACK
MACRUM	0:615f90842ce8	1266	*
MACRUM	0:615f90842ce8	1267	* 5:4 RX_MODE[1:0]: length of address 0x30 field in bytes
MACRUM	0:615f90842ce8	1268	*
MACRUM	0:615f90842ce8	1269	* RX_MODE1 \| RX_MODE0 \| Rx Mode
MACRUM	0:615f90842ce8	1270	* --------------------------------------------------------------------
MACRUM	0:615f90842ce8	1271	* 0 \| 0 \| normal
MACRUM	0:615f90842ce8	1272	* 0 \| 1 \| direct through FIFO
MACRUM	0:615f90842ce8	1273	* 1 \| 0 \| direct through GPIO
MACRUM	0:615f90842ce8	1274	*
MACRUM	0:615f90842ce8	1275	* 3:0 LEN_WID[3:0]: length of length field in bits
MACRUM	0:615f90842ce8	1276	* \endcode
MACRUM	0:615f90842ce8	1277	*/
MACRUM	0:615f90842ce8	1278	#define PCKTCTRL3_BASE ((uint8_t)0x31) /!< packet format, RX mode, lenght of length field /
MACRUM	0:615f90842ce8	1279
MACRUM	0:615f90842ce8	1280	#define PCKTCTRL3_PCKT_FRMT_BASIC ((uint8_t)0x00) /!< Basic Packet Format /
MACRUM	0:615f90842ce8	1281	#define PCKTCTRL3_PCKT_FRMT_MBUS ((uint8_t)0x80) /!< Wireless M-BUS Packet Format /
MACRUM	0:615f90842ce8	1282	#define PCKTCTRL3_PCKT_FRMT_STACK ((uint8_t)0xC0) /!< STack Packet Format /
MACRUM	0:615f90842ce8	1283
MACRUM	0:615f90842ce8	1284	#define PCKTCTRL3_RX_MODE_NORMAL ((uint8_t)0x00) /!< Normal RX Mode /
MACRUM	0:615f90842ce8	1285	#define PCKTCTRL3_RX_MODE_DIRECT_FIFO ((uint8_t)0x10) /!< RX Direct Mode; data available through FIFO /
MACRUM	0:615f90842ce8	1286	#define PCKTCTRL3_RX_MODE_DIRECT_GPIO ((uint8_t)0x20) /!< RX Direct Mode; data available through selected GPIO /
MACRUM	0:615f90842ce8	1287
MACRUM	0:615f90842ce8	1288	#define PCKTCTRL3_PKT_FRMT_MASK ((uint8_t)0xC0)
MACRUM	0:615f90842ce8	1289	#define PCKTCTRL3_RX_MODE_MASK ((uint8_t)0x30)
MACRUM	0:615f90842ce8	1290	#define PCKTCTRL3_LEN_WID_MASK ((uint8_t)0x0F)
MACRUM	0:615f90842ce8	1291
MACRUM	0:615f90842ce8	1292	/**
MACRUM	0:615f90842ce8	1293	* @}
MACRUM	0:615f90842ce8	1294	*/
MACRUM	0:615f90842ce8	1295
MACRUM	0:615f90842ce8	1296	/** @defgroup PCKTCTRL2_Register
MACRUM	0:615f90842ce8	1297	* @{
MACRUM	0:615f90842ce8	1298	*/
MACRUM	0:615f90842ce8	1299
MACRUM	0:615f90842ce8	1300	/**
MACRUM	0:615f90842ce8	1301	* \brief PCKTCTRL2 register
MACRUM	0:615f90842ce8	1302	* \code
MACRUM	0:615f90842ce8	1303	* Read Write
MACRUM	0:615f90842ce8	1304	* Default value: 0x1E
MACRUM	0:615f90842ce8	1305	*
MACRUM	0:615f90842ce8	1306	* 7:3 PREAMBLE_LENGTH[4:0]: length of preamble field in bytes (0..31)
MACRUM	0:615f90842ce8	1307	*
MACRUM	0:615f90842ce8	1308	*
MACRUM	0:615f90842ce8	1309	* 2:1 SYNC_LENGTH[1:0]: length of sync field in bytes
MACRUM	0:615f90842ce8	1310	*
MACRUM	0:615f90842ce8	1311	*
MACRUM	0:615f90842ce8	1312	* 0 FIX_VAR_LEN: fixed/variable packet length
MACRUM	0:615f90842ce8	1313	* 1 - Variable
MACRUM	0:615f90842ce8	1314	* 0 - Fixed
MACRUM	0:615f90842ce8	1315	* \endcode
MACRUM	0:615f90842ce8	1316	*/
MACRUM	0:615f90842ce8	1317	#define PCKTCTRL2_BASE ((uint8_t)0x32) /!< length of preamble and sync fields (in bytes), fix or variable packet length /
MACRUM	0:615f90842ce8	1318
MACRUM	0:615f90842ce8	1319	#define PCKTCTRL2_FIX_VAR_LEN_MASK ((uint8_t)0x01) /!< Enable/disable the length mode /
MACRUM	0:615f90842ce8	1320	#define PCKTCTRL2_PREAMBLE_LENGTH_MASK ((uint8_t)0xF8)
MACRUM	0:615f90842ce8	1321	#define PCKTCTRL2_SYNC_LENGTH_MASK ((uint8_t)0x06)
MACRUM	0:615f90842ce8	1322
MACRUM	0:615f90842ce8	1323	/**
MACRUM	0:615f90842ce8	1324	* @}
MACRUM	0:615f90842ce8	1325	*/
MACRUM	0:615f90842ce8	1326
MACRUM	0:615f90842ce8	1327	/** @defgroup PCKTCTRL1_Register
MACRUM	0:615f90842ce8	1328	* @{
MACRUM	0:615f90842ce8	1329	*/
MACRUM	0:615f90842ce8	1330
MACRUM	0:615f90842ce8	1331	/**
MACRUM	0:615f90842ce8	1332	* \brief PCKTCTRL1 register
MACRUM	0:615f90842ce8	1333	* \code
MACRUM	0:615f90842ce8	1334	* Read Write
MACRUM	0:615f90842ce8	1335	* Default value: 0x20
MACRUM	0:615f90842ce8	1336	*
MACRUM	0:615f90842ce8	1337	* 7:5 CRC_MODE[2:0]: CRC type (0, 8, 16, 24 bits)
MACRUM	0:615f90842ce8	1338	*
MACRUM	0:615f90842ce8	1339	* CRC_MODE2 \| CRC_MODE1 \| CRC_MODE0 \| CRC Mode (n. bits - poly)
MACRUM	0:615f90842ce8	1340	* -------------------------------------------------------------------------------------------------
MACRUM	0:615f90842ce8	1341	* 0 \| 0 \| 1 \| 8 - 0x07
MACRUM	0:615f90842ce8	1342	* 0 \| 1 \| 0 \| 16 - 0x8005
MACRUM	0:615f90842ce8	1343	* 0 \| 1 \| 1 \| 16 - 0x1021
MACRUM	0:615f90842ce8	1344	* 1 \| 0 \| 0 \| 24 - 0x864CBF
MACRUM	0:615f90842ce8	1345	*
MACRUM	0:615f90842ce8	1346	* 4 WHIT_EN[0]: Enable Whitening
MACRUM	0:615f90842ce8	1347	* 1 - Enable
MACRUM	0:615f90842ce8	1348	* 0 - Disable
MACRUM	0:615f90842ce8	1349	*
MACRUM	0:615f90842ce8	1350	* 3:2 TX_SOURCE[1:0]: length of sync field in bytes
MACRUM	0:615f90842ce8	1351	*
MACRUM	0:615f90842ce8	1352	* TX_SOURCE1 \| TX_SOURCE0 \| Tx Mode
MACRUM	0:615f90842ce8	1353	* --------------------------------------------------------------------
MACRUM	0:615f90842ce8	1354	* 0 \| 0 \| normal
MACRUM	0:615f90842ce8	1355	* 0 \| 1 \| direct through FIFO
MACRUM	0:615f90842ce8	1356	* 1 \| 0 \| direct through GPIO
MACRUM	0:615f90842ce8	1357	* 1 \| 1 \| pn9
MACRUM	0:615f90842ce8	1358	*
MACRUM	0:615f90842ce8	1359	* 1 NOT_USED
MACRUM	0:615f90842ce8	1360	*
MACRUM	0:615f90842ce8	1361	* 0 FEC_EN: enable FEC
MACRUM	0:615f90842ce8	1362	* 1 - FEC in TX , Viterbi decoding in RX
MACRUM	0:615f90842ce8	1363	* 0 - Disabled
MACRUM	0:615f90842ce8	1364	* \endcode
MACRUM	0:615f90842ce8	1365	*/
MACRUM	0:615f90842ce8	1366	#define PCKTCTRL1_BASE ((uint8_t)0x33) /!< CRC type, whitening enable, TX mode /
MACRUM	0:615f90842ce8	1367
MACRUM	0:615f90842ce8	1368	#define PCKTCTRL1_FEC_MASK ((uint8_t)0x01) /!< Enable/disable the Forward Error Correction /
MACRUM	0:615f90842ce8	1369	#define PCKTCTRL1_TX_SOURCE_MASK ((uint8_t)0x0C) /!< TX source mode /
MACRUM	0:615f90842ce8	1370	#define PCKTCTRL1_CRC_MODE_MASK ((uint8_t)0xE0) /!< CRC type /
MACRUM	0:615f90842ce8	1371	#define PCKTCTRL1_WHIT_MASK ((uint8_t)0x10) /!< Enable/disable the Whitening /
MACRUM	0:615f90842ce8	1372
MACRUM	0:615f90842ce8	1373	/**
MACRUM	0:615f90842ce8	1374	* @}
MACRUM	0:615f90842ce8	1375	*/
MACRUM	0:615f90842ce8	1376
MACRUM	0:615f90842ce8	1377
MACRUM	0:615f90842ce8	1378
MACRUM	0:615f90842ce8	1379	/** @defgroup PCKTLEN1_Register
MACRUM	0:615f90842ce8	1380	* @{
MACRUM	0:615f90842ce8	1381	*/
MACRUM	0:615f90842ce8	1382
MACRUM	0:615f90842ce8	1383	/**
MACRUM	0:615f90842ce8	1384	* \brief PCKTLEN1 register
MACRUM	0:615f90842ce8	1385	* \code
MACRUM	0:615f90842ce8	1386	* Read Write
MACRUM	0:615f90842ce8	1387	* Default value: 0x00
MACRUM	0:615f90842ce8	1388	*
MACRUM	0:615f90842ce8	1389	* 7:0 pktlen1[7:0]: lenght of packet in bytes (upper field) LENGHT/256
MACRUM	0:615f90842ce8	1390	* \endcode
MACRUM	0:615f90842ce8	1391	*/
MACRUM	0:615f90842ce8	1392	#define PCKTLEN1_BASE ((uint8_t)0x34) /!< lenght of packet in bytes (upper field) /
MACRUM	0:615f90842ce8	1393
MACRUM	0:615f90842ce8	1394	/**
MACRUM	0:615f90842ce8	1395	* @}
MACRUM	0:615f90842ce8	1396	*/
MACRUM	0:615f90842ce8	1397
MACRUM	0:615f90842ce8	1398	/** @defgroup PCKTLEN0_Register
MACRUM	0:615f90842ce8	1399	* @{
MACRUM	0:615f90842ce8	1400	*/
MACRUM	0:615f90842ce8	1401
MACRUM	0:615f90842ce8	1402	/**
MACRUM	0:615f90842ce8	1403	* \brief PCKTLEN0 register
MACRUM	0:615f90842ce8	1404	* \code
MACRUM	0:615f90842ce8	1405	* Read Write
MACRUM	0:615f90842ce8	1406	* Default value: 0x14
MACRUM	0:615f90842ce8	1407	*
MACRUM	0:615f90842ce8	1408	* 7:0 pktlen0[7:0]: lenght of packet in bytes (lower field) LENGHT%256
MACRUM	0:615f90842ce8	1409	* \endcode
MACRUM	0:615f90842ce8	1410	*/
MACRUM	0:615f90842ce8	1411	#define PCKTLEN0_BASE ((uint8_t)0x35) /!< lenght of packet in bytes (lower field) [PCKTLEN=PCKTLEN1x256+PCKTLEN0]/
MACRUM	0:615f90842ce8	1412
MACRUM	0:615f90842ce8	1413	/**
MACRUM	0:615f90842ce8	1414	* @}
MACRUM	0:615f90842ce8	1415	*/
MACRUM	0:615f90842ce8	1416
MACRUM	0:615f90842ce8	1417	/** @defgroup SYNCx_Registers
MACRUM	0:615f90842ce8	1418	* @{
MACRUM	0:615f90842ce8	1419	*/
MACRUM	0:615f90842ce8	1420	/**
MACRUM	0:615f90842ce8	1421	* \brief SYNCx[4:1] Registers
MACRUM	0:615f90842ce8	1422	* \code
MACRUM	0:615f90842ce8	1423	* Read Write
MACRUM	0:615f90842ce8	1424	* Default value: 0x88
MACRUM	0:615f90842ce8	1425	*
MACRUM	0:615f90842ce8	1426	* 7:0 SYNCx[7:0]: xth sync word
MACRUM	0:615f90842ce8	1427	* \endcode
MACRUM	0:615f90842ce8	1428	*/
MACRUM	0:615f90842ce8	1429	#define SYNC4_BASE ((uint8_t)0x36) /!< Sync word 4 /
MACRUM	0:615f90842ce8	1430	#define SYNC3_BASE ((uint8_t)0x37) /!< Sync word 3 /
MACRUM	0:615f90842ce8	1431	#define SYNC2_BASE ((uint8_t)0x38) /!< Sync word 2 /
MACRUM	0:615f90842ce8	1432	#define SYNC1_BASE ((uint8_t)0x39) /!< Sync word 1 /
MACRUM	0:615f90842ce8	1433
MACRUM	0:615f90842ce8	1434	/**
MACRUM	0:615f90842ce8	1435	* @}
MACRUM	0:615f90842ce8	1436	*/
MACRUM	0:615f90842ce8	1437
MACRUM	0:615f90842ce8	1438
MACRUM	0:615f90842ce8	1439	/** @defgroup MBUS_PRMBL_Register
MACRUM	0:615f90842ce8	1440	* @{
MACRUM	0:615f90842ce8	1441	*/
MACRUM	0:615f90842ce8	1442
MACRUM	0:615f90842ce8	1443	/**
MACRUM	0:615f90842ce8	1444	* \brief MBUS_PRMBL register
MACRUM	0:615f90842ce8	1445	* \code
MACRUM	0:615f90842ce8	1446	* Read Write
MACRUM	0:615f90842ce8	1447	* Default value: 0x20
MACRUM	0:615f90842ce8	1448	*
MACRUM	0:615f90842ce8	1449	* 7:0 MBUS_PRMBL[7:0]: MBUS preamble control
MACRUM	0:615f90842ce8	1450	* \endcode
MACRUM	0:615f90842ce8	1451	*/
MACRUM	0:615f90842ce8	1452	#define MBUS_PRMBL_BASE ((uint8_t)0x3B) /!< MBUS preamble lenght (in 01 bit pairs) /
MACRUM	0:615f90842ce8	1453
MACRUM	0:615f90842ce8	1454	/**
MACRUM	0:615f90842ce8	1455	* @}
MACRUM	0:615f90842ce8	1456	*/
MACRUM	0:615f90842ce8	1457
MACRUM	0:615f90842ce8	1458
MACRUM	0:615f90842ce8	1459	/** @defgroup MBUS_PSTMBL_Register
MACRUM	0:615f90842ce8	1460	* @{
MACRUM	0:615f90842ce8	1461	*/
MACRUM	0:615f90842ce8	1462
MACRUM	0:615f90842ce8	1463	/**
MACRUM	0:615f90842ce8	1464	* \brief MBUS_PSTMBL register
MACRUM	0:615f90842ce8	1465	* \code
MACRUM	0:615f90842ce8	1466	* Read Write
MACRUM	0:615f90842ce8	1467	* Default value: 0x20
MACRUM	0:615f90842ce8	1468	*
MACRUM	0:615f90842ce8	1469	* 7:0 MBUS_PSTMBL[7:0]: MBUS postamble control
MACRUM	0:615f90842ce8	1470	* \endcode
MACRUM	0:615f90842ce8	1471	*/
MACRUM	0:615f90842ce8	1472	#define MBUS_PSTMBL_BASE ((uint8_t)0x3C) /!< MBUS postamble length (in 01 bit pairs) /
MACRUM	0:615f90842ce8	1473
MACRUM	0:615f90842ce8	1474	/**
MACRUM	0:615f90842ce8	1475	* @}
MACRUM	0:615f90842ce8	1476	*/
MACRUM	0:615f90842ce8	1477
MACRUM	0:615f90842ce8	1478	/** @defgroup MBUS_CTRL_Register
MACRUM	0:615f90842ce8	1479	* @{
MACRUM	0:615f90842ce8	1480	*/
MACRUM	0:615f90842ce8	1481
MACRUM	0:615f90842ce8	1482	/**
MACRUM	0:615f90842ce8	1483	* \brief MBUS_CTRL register
MACRUM	0:615f90842ce8	1484	* \code
MACRUM	0:615f90842ce8	1485	* Read Write
MACRUM	0:615f90842ce8	1486	* Default value: 0x00
MACRUM	0:615f90842ce8	1487	*
MACRUM	0:615f90842ce8	1488	* 7:4 NOT_USED
MACRUM	0:615f90842ce8	1489	*
MACRUM	0:615f90842ce8	1490	* 3:1 MBUS_SUBMODE[2:0]: MBUS submode (allowed values are 0,1,3,5)
MACRUM	0:615f90842ce8	1491	*
MACRUM	0:615f90842ce8	1492	* 0 NOT_USED
MACRUM	0:615f90842ce8	1493	* \endcode
MACRUM	0:615f90842ce8	1494	*/
MACRUM	0:615f90842ce8	1495	#define MBUS_CTRL_BASE ((uint8_t)0x3D) /!< MBUS sub-modes (S1, S2 short/long header, T1, T2, R2) /
MACRUM	0:615f90842ce8	1496
MACRUM	0:615f90842ce8	1497	#define MBUS_CTRL_MBUS_SUBMODE_S1_S2L ((uint8_t)0x00) /!< MBUS sub-modes S1 & S2L, header lenght min 279, sync 0x7696, Manchester /
MACRUM	0:615f90842ce8	1498	#define MBUS_CTRL_MBUS_SUBMODE_S2_S1M_T2_OTHER ((uint8_t)0x02) /!< MBUS sub-modes S2, S1-m, T2 (only other to meter) short header, header lenght min 15, sync 0x7696, Manchester /
MACRUM	0:615f90842ce8	1499	#define MBUS_CTRL_MBUS_SUBMODE_T1_T2_METER ((uint8_t)0x06) /!< MBUS sub-modes T1, T2 (only meter to other), header lenght min 19, sync 0x3D, 3 out of 6 /
MACRUM	0:615f90842ce8	1500	#define MBUS_CTRL_MBUS_SUBMODE_R2 ((uint8_t)0x0A) /!< MBUS sub-mode R2, header lenght min 39, sync 0x7696, Manchester /
MACRUM	0:615f90842ce8	1501
MACRUM	0:615f90842ce8	1502	/**
MACRUM	0:615f90842ce8	1503	* @}
MACRUM	0:615f90842ce8	1504	*/
MACRUM	0:615f90842ce8	1505
MACRUM	0:615f90842ce8	1506
MACRUM	0:615f90842ce8	1507
MACRUM	0:615f90842ce8	1508	/** @defgroup PCKT_FLT_GOALS_CONTROLx_MASK_Registers
MACRUM	0:615f90842ce8	1509	* @{
MACRUM	0:615f90842ce8	1510	*/
MACRUM	0:615f90842ce8	1511
MACRUM	0:615f90842ce8	1512	/**
MACRUM	0:615f90842ce8	1513	* \brief PCKT_FLT_GOALS_CONTROLx_MASK registers
MACRUM	0:615f90842ce8	1514	* \code
MACRUM	0:615f90842ce8	1515	* Default value: 0x00
MACRUM	0:615f90842ce8	1516	* Read Write
MACRUM	0:615f90842ce8	1517	* 7:0 CONTROLx_MASK[7:0]: All 0s - no filtering
MACRUM	0:615f90842ce8	1518	*
MACRUM	0:615f90842ce8	1519	* \endcode
MACRUM	0:615f90842ce8	1520	*/
MACRUM	0:615f90842ce8	1521	#define PCKT_FLT_GOALS_CONTROL0_MASK_BASE ((uint8_t)0x42) /!< Packet control field #3 mask, all 0s -> no filtering /
MACRUM	0:615f90842ce8	1522
MACRUM	0:615f90842ce8	1523	#define PCKT_FLT_GOALS_CONTROL1_MASK_BASE ((uint8_t)0x43) /!< Packet control field #2 mask, all 0s -> no filtering /
MACRUM	0:615f90842ce8	1524
MACRUM	0:615f90842ce8	1525	#define PCKT_FLT_GOALS_CONTROL2_MASK_BASE ((uint8_t)0x44) /!< Packet control field #1 mask, all 0s -> no filtering /
MACRUM	0:615f90842ce8	1526
MACRUM	0:615f90842ce8	1527	#define PCKT_FLT_GOALS_CONTROL3_MASK_BASE ((uint8_t)0x45) /!< Packet control field #0 mask, all 0s -> no filtering /
MACRUM	0:615f90842ce8	1528
MACRUM	0:615f90842ce8	1529	/**
MACRUM	0:615f90842ce8	1530	* @}
MACRUM	0:615f90842ce8	1531	*/
MACRUM	0:615f90842ce8	1532
MACRUM	0:615f90842ce8	1533	/** @defgroup PCKT_FLT_GOALS_CONTROLx_FIELD_Registers
MACRUM	0:615f90842ce8	1534	* @{
MACRUM	0:615f90842ce8	1535	*/
MACRUM	0:615f90842ce8	1536
MACRUM	0:615f90842ce8	1537	/**
MACRUM	0:615f90842ce8	1538	* \brief PCKT_FLT_GOALS_CONTROLx_FIELD registers
MACRUM	0:615f90842ce8	1539	* \code
MACRUM	0:615f90842ce8	1540	* Default value: 0x00
MACRUM	0:615f90842ce8	1541	* Read Write
MACRUM	0:615f90842ce8	1542	* 7:0 CONTROLx_FIELD[7:0]: Control field (byte x) to be used as reference
MACRUM	0:615f90842ce8	1543	*
MACRUM	0:615f90842ce8	1544	* \endcode
MACRUM	0:615f90842ce8	1545	*/
MACRUM	0:615f90842ce8	1546	#define PCKT_FLT_GOALS_CONTROL0_FIELD_BASE ((uint8_t)0x46) /!< Control field (byte #3) /
MACRUM	0:615f90842ce8	1547
MACRUM	0:615f90842ce8	1548	#define PCKT_FLT_GOALS_CONTROL1_FIELD_BASE ((uint8_t)0x47) /!< Control field (byte #2) /
MACRUM	0:615f90842ce8	1549
MACRUM	0:615f90842ce8	1550	#define PCKT_FLT_GOALS_CONTROL2_FIELD_BASE ((uint8_t)0x48) /!< Control field (byte #1) /
MACRUM	0:615f90842ce8	1551
MACRUM	0:615f90842ce8	1552	#define PCKT_FLT_GOALS_CONTROL3_FIELD_BASE ((uint8_t)0x49) /!< Control field (byte #0) /
MACRUM	0:615f90842ce8	1553
MACRUM	0:615f90842ce8	1554	/**
MACRUM	0:615f90842ce8	1555	* @}
MACRUM	0:615f90842ce8	1556	*/
MACRUM	0:615f90842ce8	1557
MACRUM	0:615f90842ce8	1558	/** @defgroup PCKT_FLT_GOALS_SOURCE_MASK_Register
MACRUM	0:615f90842ce8	1559	* @{
MACRUM	0:615f90842ce8	1560	*/
MACRUM	0:615f90842ce8	1561
MACRUM	0:615f90842ce8	1562	/**
MACRUM	0:615f90842ce8	1563	* \brief PCKT_FLT_GOALS_SOURCE_MASK register
MACRUM	0:615f90842ce8	1564	* \code
MACRUM	0:615f90842ce8	1565	* Default value: 0x00
MACRUM	0:615f90842ce8	1566	* Read Write
MACRUM	0:615f90842ce8	1567	* 7:0 RX_SOURCE_MASK[7:0]: For received packet only: all 0s - no filtering
MACRUM	0:615f90842ce8	1568	*
MACRUM	0:615f90842ce8	1569	* \endcode
MACRUM	0:615f90842ce8	1570	*/
MACRUM	0:615f90842ce8	1571	#define PCKT_FLT_GOALS_SOURCE_MASK_BASE ((uint8_t)0x4A) /!< Source address mask, valid in RX mode /
MACRUM	0:615f90842ce8	1572
MACRUM	0:615f90842ce8	1573	/**
MACRUM	0:615f90842ce8	1574	* @}
MACRUM	0:615f90842ce8	1575	*/
MACRUM	0:615f90842ce8	1576
MACRUM	0:615f90842ce8	1577	/** @defgroup PCKT_FLT_GOALS_SOURCE_ADDR_Register
MACRUM	0:615f90842ce8	1578	* @{
MACRUM	0:615f90842ce8	1579	*/
MACRUM	0:615f90842ce8	1580	/**
MACRUM	0:615f90842ce8	1581	* \brief PCKT_FLT_GOALS_SOURCE_ADDR register
MACRUM	0:615f90842ce8	1582	* \code
MACRUM	0:615f90842ce8	1583	* Default value: 0x00
MACRUM	0:615f90842ce8	1584	* Read Write
MACRUM	0:615f90842ce8	1585	* 7:0 RX_SOURCE_ADDR[7:0]: RX packet source / TX packet destination fields
MACRUM	0:615f90842ce8	1586	*
MACRUM	0:615f90842ce8	1587	* \endcode
MACRUM	0:615f90842ce8	1588	*/
MACRUM	0:615f90842ce8	1589	#define PCKT_FLT_GOALS_SOURCE_ADDR_BASE ((uint8_t)0x4B) /!< Source address /
MACRUM	0:615f90842ce8	1590
MACRUM	0:615f90842ce8	1591	/**
MACRUM	0:615f90842ce8	1592	* @}
MACRUM	0:615f90842ce8	1593	*/
MACRUM	0:615f90842ce8	1594
MACRUM	0:615f90842ce8	1595	/** @defgroup PCKT_FLT_GOALS_BROADCAST_Register
MACRUM	0:615f90842ce8	1596	* @{
MACRUM	0:615f90842ce8	1597	*/
MACRUM	0:615f90842ce8	1598
MACRUM	0:615f90842ce8	1599	/**
MACRUM	0:615f90842ce8	1600	* \brief PCKT_FLT_GOALS_BROADCAST register
MACRUM	0:615f90842ce8	1601	* \code
MACRUM	0:615f90842ce8	1602	* Default value: 0x00
MACRUM	0:615f90842ce8	1603	* Read Write
MACRUM	0:615f90842ce8	1604	* 7:0 BROADCAST[7:0]: Address shared for broadcast communication link
MACRUM	0:615f90842ce8	1605	*
MACRUM	0:615f90842ce8	1606	* \endcode
MACRUM	0:615f90842ce8	1607	*/
MACRUM	0:615f90842ce8	1608	#define PCKT_FLT_GOALS_BROADCAST_BASE ((uint8_t)0x4C) /!< Address shared for broadcast communication links /
MACRUM	0:615f90842ce8	1609
MACRUM	0:615f90842ce8	1610	/**
MACRUM	0:615f90842ce8	1611	* @}
MACRUM	0:615f90842ce8	1612	*/
MACRUM	0:615f90842ce8	1613
MACRUM	0:615f90842ce8	1614	/** @defgroup PCKT_FLT_GOALS_MULTICAST_Register
MACRUM	0:615f90842ce8	1615	* @{
MACRUM	0:615f90842ce8	1616	*/
MACRUM	0:615f90842ce8	1617
MACRUM	0:615f90842ce8	1618	/**
MACRUM	0:615f90842ce8	1619	* \brief PCKT_FLT_GOALS_MULTICAST register
MACRUM	0:615f90842ce8	1620	* \code
MACRUM	0:615f90842ce8	1621	* Default value: 0x00
MACRUM	0:615f90842ce8	1622	* Read Write
MACRUM	0:615f90842ce8	1623	* 7:0 MULTICAST[7:0]: Address shared for multicast communication links
MACRUM	0:615f90842ce8	1624	*
MACRUM	0:615f90842ce8	1625	* \endcode
MACRUM	0:615f90842ce8	1626	*/
MACRUM	0:615f90842ce8	1627	#define PCKT_FLT_GOALS_MULTICAST_BASE ((uint8_t)0x4D) /!< Address shared for multicast communication links /
MACRUM	0:615f90842ce8	1628
MACRUM	0:615f90842ce8	1629	/**
MACRUM	0:615f90842ce8	1630	* @}
MACRUM	0:615f90842ce8	1631	*/
MACRUM	0:615f90842ce8	1632
MACRUM	0:615f90842ce8	1633	/** @defgroup PCKT_FLT_GOALS_TX_SOURCE_ADDR_Register
MACRUM	0:615f90842ce8	1634	* @{
MACRUM	0:615f90842ce8	1635	*/
MACRUM	0:615f90842ce8	1636
MACRUM	0:615f90842ce8	1637	/**
MACRUM	0:615f90842ce8	1638	* \brief PCKT_FLT_GOALS_TX_SOURCE_ADDR register
MACRUM	0:615f90842ce8	1639	* \code
MACRUM	0:615f90842ce8	1640	* Default value: 0x00
MACRUM	0:615f90842ce8	1641	* Read Write
MACRUM	0:615f90842ce8	1642	* 7:0 TX_SOURCE_ADDR[7:0]: TX packet source / RX packet destination fields
MACRUM	0:615f90842ce8	1643	*
MACRUM	0:615f90842ce8	1644	* \endcode
MACRUM	0:615f90842ce8	1645	*/
MACRUM	0:615f90842ce8	1646	#define PCKT_FLT_GOALS_TX_ADDR_BASE ((uint8_t)0x4E) /!< Address of the destination (also device own address) /
MACRUM	0:615f90842ce8	1647
MACRUM	0:615f90842ce8	1648	/**
MACRUM	0:615f90842ce8	1649	* @}
MACRUM	0:615f90842ce8	1650	*/
MACRUM	0:615f90842ce8	1651
MACRUM	0:615f90842ce8	1652	/** @defgroup PCKT_FLT_OPTIONS_Register
MACRUM	0:615f90842ce8	1653	* @{
MACRUM	0:615f90842ce8	1654	*/
MACRUM	0:615f90842ce8	1655
MACRUM	0:615f90842ce8	1656	/**
MACRUM	0:615f90842ce8	1657	* \brief PCKT_FLT_OPTIONS register
MACRUM	0:615f90842ce8	1658	* \code
MACRUM	0:615f90842ce8	1659	* Default value: 0x70
MACRUM	0:615f90842ce8	1660	* Read Write
MACRUM	0:615f90842ce8	1661	* 7 Reserved.
MACRUM	0:615f90842ce8	1662	*
MACRUM	0:615f90842ce8	1663	* 6 RX_TIMEOUT_AND_OR_SELECT[0]: 1 - OR logical function applied to CS/SQI/PQI
MACRUM	0:615f90842ce8	1664	* values (masked by 7:5 bits in PROTOCOL register)
MACRUM	0:615f90842ce8	1665	* 5 CONTROL_FILTERING[0]: 1 - RX packet accepted if its control fields matches
MACRUM	0:615f90842ce8	1666	* with masked CONTROLx_FIELD registers.
MACRUM	0:615f90842ce8	1667	* 4 SOURCE_FILTERING[0]: 1 - RX packet accepted if its source field
MACRUM	0:615f90842ce8	1668	* matches w/ masked RX_SOURCE_ADDR register.
MACRUM	0:615f90842ce8	1669	* 3 DEST_VS_ SOURCE _ADDR[0]: 1 - RX packet accepted if its destination
MACRUM	0:615f90842ce8	1670	* address matches with TX_SOURCE_ADDR reg.
MACRUM	0:615f90842ce8	1671	* 2 DEST_VS_MULTICAST_ADDR[0]: 1 - RX packet accepted if its destination
MACRUM	0:615f90842ce8	1672	* address matches with MULTICAST register
MACRUM	0:615f90842ce8	1673	* 1 DEST_VS_BROADCAST_ADDR[0]: 1 - RX packet accepted if its destination
MACRUM	0:615f90842ce8	1674	* address matches with BROADCAST register.
MACRUM	0:615f90842ce8	1675	* 0 CRC_CHECK[0]: 1 - packet discarded if CRC not valid.
MACRUM	0:615f90842ce8	1676	*
MACRUM	0:615f90842ce8	1677	* \endcode
MACRUM	0:615f90842ce8	1678	*/
MACRUM	0:615f90842ce8	1679	#define PCKT_FLT_OPTIONS_BASE ((uint8_t)0x4F) /!< Options relative to packet filtering /
MACRUM	0:615f90842ce8	1680
MACRUM	0:615f90842ce8	1681	#define PCKT_FLT_OPTIONS_CRC_CHECK_MASK ((uint8_t)0x01) /!< Enable/disable of CRC check: packet is discarded if CRC is not valid [RX] /
MACRUM	0:615f90842ce8	1682	#define PCKT_FLT_OPTIONS_DEST_VS_BROADCAST_ADDR_MASK ((uint8_t)0x02) /!< Packet discarded if destination address differs from BROADCAST register [RX] /
MACRUM	0:615f90842ce8	1683	#define PCKT_FLT_OPTIONS_DEST_VS_MULTICAST_ADDR_MASK ((uint8_t)0x04) /!< Packet discarded if destination address differs from MULTICAST register [RX] /
MACRUM	0:615f90842ce8	1684	#define PCKT_FLT_OPTIONS_DEST_VS_TX_ADDR_MASK ((uint8_t)0x08) /!< Packet discarded if destination address differs from TX_ADDR register [RX] /
MACRUM	0:615f90842ce8	1685	#define PCKT_FLT_OPTIONS_SOURCE_FILTERING_MASK ((uint8_t)0x10) /*!< Packet discarded if source address (masked by the SOURCE_MASK register)
MACRUM	0:615f90842ce8	1686	differs from SOURCE_ADDR register [RX] */
MACRUM	0:615f90842ce8	1687	#define PCKT_FLT_OPTIONS_CONTROL_FILTERING_MASK ((uint8_t)0x20) /*!< Packet discarded if the x-byte (x=1¸4) control field (masked by the CONTROLx_MASK register)
MACRUM	0:615f90842ce8	1688	differs from CONTROLx_FIELD register [RX] */
MACRUM	0:615f90842ce8	1689	#define PCKT_FLT_OPTIONS_RX_TIMEOUT_AND_OR_SELECT ((uint8_t)0x40) /*!< Logical function applied to CS/SQI/PQI values (masked by [7:5] bits in PROTOCOL[2]
MACRUM	0:615f90842ce8	1690	register) */
MACRUM	0:615f90842ce8	1691
MACRUM	0:615f90842ce8	1692	/**
MACRUM	0:615f90842ce8	1693	* @}
MACRUM	0:615f90842ce8	1694	*/
MACRUM	0:615f90842ce8	1695
MACRUM	0:615f90842ce8	1696	/** @defgroup TX_CTRL_FIELD_Registers
MACRUM	0:615f90842ce8	1697	* @{
MACRUM	0:615f90842ce8	1698	*/
MACRUM	0:615f90842ce8	1699
MACRUM	0:615f90842ce8	1700	/**
MACRUM	0:615f90842ce8	1701	* \brief TX_CTRL_FIELDx registers
MACRUM	0:615f90842ce8	1702	* \code
MACRUM	0:615f90842ce8	1703	* Default value: 0x00
MACRUM	0:615f90842ce8	1704	* Read Write
MACRUM	0:615f90842ce8	1705	* 7:0 TX_CTRLx[7:0]: Control field value to be used in TX packet as byte n.x
MACRUM	0:615f90842ce8	1706	* \endcode
MACRUM	0:615f90842ce8	1707	*/
MACRUM	0:615f90842ce8	1708	#define TX_CTRL_FIELD3_BASE ((uint8_t)0x68) /!< Control field value to be used in TX packet as byte n.3 /
MACRUM	0:615f90842ce8	1709
MACRUM	0:615f90842ce8	1710	#define TX_CTRL_FIELD2_BASE ((uint8_t)0x69) /!< Control field value to be used in TX packet as byte n.2 /
MACRUM	0:615f90842ce8	1711
MACRUM	0:615f90842ce8	1712	#define TX_CTRL_FIELD1_BASE ((uint8_t)0x6A) /!< Control field value to be used in TX packet as byte n.1 /
MACRUM	0:615f90842ce8	1713
MACRUM	0:615f90842ce8	1714	#define TX_CTRL_FIELD0_BASE ((uint8_t)0x6B) /!< Control field value to be used in TX packet as byte n.0 /
MACRUM	0:615f90842ce8	1715
MACRUM	0:615f90842ce8	1716	/**
MACRUM	0:615f90842ce8	1717	* @}
MACRUM	0:615f90842ce8	1718	*/
MACRUM	0:615f90842ce8	1719
MACRUM	0:615f90842ce8	1720
MACRUM	0:615f90842ce8	1721	/** @defgroup TX_PCKT_INFO_Register
MACRUM	0:615f90842ce8	1722	* @{
MACRUM	0:615f90842ce8	1723	*/
MACRUM	0:615f90842ce8	1724
MACRUM	0:615f90842ce8	1725	/**
MACRUM	0:615f90842ce8	1726	* \brief TX_PCKT_INFO registers
MACRUM	0:615f90842ce8	1727	* \code
MACRUM	0:615f90842ce8	1728	* Default value: 0x00
MACRUM	0:615f90842ce8	1729	* Read
MACRUM	0:615f90842ce8	1730	*
MACRUM	0:615f90842ce8	1731	* 7:6 Not used.
MACRUM	0:615f90842ce8	1732	*
MACRUM	0:615f90842ce8	1733	* 5:4 TX_SEQ_NUM: Current TX packet sequence number
MACRUM	0:615f90842ce8	1734	*
MACRUM	0:615f90842ce8	1735	* 0 N_RETX[3:0]: Number of retransmissions done on the
MACRUM	0:615f90842ce8	1736	* last TX packet
MACRUM	0:615f90842ce8	1737	* \endcode
MACRUM	0:615f90842ce8	1738	*/
MACRUM	0:615f90842ce8	1739	#define TX_PCKT_INFO_BASE ((uint8_t)(0xC2)) /*!< Current TX packet sequence number [5:4];
MACRUM	0:615f90842ce8	1740	Number of retransmissions done on the last TX packet [3:0]*/
MACRUM	0:615f90842ce8	1741	/**
MACRUM	0:615f90842ce8	1742	* @}
MACRUM	0:615f90842ce8	1743	*/
MACRUM	0:615f90842ce8	1744
MACRUM	0:615f90842ce8	1745	/** @defgroup RX_PCKT_INFO_Register
MACRUM	0:615f90842ce8	1746	* @{
MACRUM	0:615f90842ce8	1747	*/
MACRUM	0:615f90842ce8	1748
MACRUM	0:615f90842ce8	1749	/**
MACRUM	0:615f90842ce8	1750	* \brief RX_PCKT_INFO registers
MACRUM	0:615f90842ce8	1751	* \code
MACRUM	0:615f90842ce8	1752	* Default value: 0x00
MACRUM	0:615f90842ce8	1753	* Read
MACRUM	0:615f90842ce8	1754	*
MACRUM	0:615f90842ce8	1755	* 7:3 Not used.
MACRUM	0:615f90842ce8	1756	*
MACRUM	0:615f90842ce8	1757	* 2 NACK_RX: NACK field of the received packet
MACRUM	0:615f90842ce8	1758	*
MACRUM	0:615f90842ce8	1759	* 1:0 RX_SEQ_NUM[1:0]: Sequence number of the received packet
MACRUM	0:615f90842ce8	1760	* \endcode
MACRUM	0:615f90842ce8	1761	*/
MACRUM	0:615f90842ce8	1762	#define RX_PCKT_INFO_BASE ((uint8_t)(0xC3)) /*!< NO_ACK field of the received packet [2];
MACRUM	0:615f90842ce8	1763	sequence number of the received packet [1:0]*/
MACRUM	0:615f90842ce8	1764
MACRUM	0:615f90842ce8	1765	#define TX_PCKT_INFO_NACK_RX ((uint8_t)(0x04)) /!< NACK field of the received packet /
MACRUM	0:615f90842ce8	1766
MACRUM	0:615f90842ce8	1767	/**
MACRUM	0:615f90842ce8	1768	* @}
MACRUM	0:615f90842ce8	1769	*/
MACRUM	0:615f90842ce8	1770
MACRUM	0:615f90842ce8	1771	/** @defgroup RX_PCKT_LEN1
MACRUM	0:615f90842ce8	1772	* @{
MACRUM	0:615f90842ce8	1773	*/
MACRUM	0:615f90842ce8	1774
MACRUM	0:615f90842ce8	1775	/**
MACRUM	0:615f90842ce8	1776	* \brief RX_PCKT_LEN1 registers
MACRUM	0:615f90842ce8	1777	* \code
MACRUM	0:615f90842ce8	1778	* Default value: 0x00
MACRUM	0:615f90842ce8	1779	* Read
MACRUM	0:615f90842ce8	1780	*
MACRUM	0:615f90842ce8	1781	* 7:0 RX_PCKT_LEN1[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
MACRUM	0:615f90842ce8	1782	* This value is packet_length/256
MACRUM	0:615f90842ce8	1783	* \endcode
MACRUM	0:615f90842ce8	1784	*/
MACRUM	0:615f90842ce8	1785	#define RX_PCKT_LEN1_BASE ((uint8_t)(0xC9)) /!< Length (number of bytes) of the received packet: /
MACRUM	0:615f90842ce8	1786
MACRUM	0:615f90842ce8	1787	/**
MACRUM	0:615f90842ce8	1788	* @}
MACRUM	0:615f90842ce8	1789	*/
MACRUM	0:615f90842ce8	1790
MACRUM	0:615f90842ce8	1791	/** @defgroup RX_PCKT_LEN0
MACRUM	0:615f90842ce8	1792	* @{
MACRUM	0:615f90842ce8	1793	*/
MACRUM	0:615f90842ce8	1794
MACRUM	0:615f90842ce8	1795	/**
MACRUM	0:615f90842ce8	1796	* \brief RX_PCKT_LEN0 registers
MACRUM	0:615f90842ce8	1797	* \code
MACRUM	0:615f90842ce8	1798	* Default value: 0x00
MACRUM	0:615f90842ce8	1799	* Read
MACRUM	0:615f90842ce8	1800	*
MACRUM	0:615f90842ce8	1801	* 7:0 RX_PCKT_LEN0[7:0]: Length (number of bytes) of the received packet: RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0
MACRUM	0:615f90842ce8	1802	* This value is packet_length%256
MACRUM	0:615f90842ce8	1803	* \endcode
MACRUM	0:615f90842ce8	1804	*/
MACRUM	0:615f90842ce8	1805	#define RX_PCKT_LEN0_BASE ((uint8_t)(0xCA)) /!< RX_PCKT_LEN=RX_PCKT_LEN1 × 256 + RX_PCKT_LEN0 /
MACRUM	0:615f90842ce8	1806
MACRUM	0:615f90842ce8	1807	/**
MACRUM	0:615f90842ce8	1808	* @}
MACRUM	0:615f90842ce8	1809	*/
MACRUM	0:615f90842ce8	1810
MACRUM	0:615f90842ce8	1811
MACRUM	0:615f90842ce8	1812	/** @defgroup CRC_FIELD_Register
MACRUM	0:615f90842ce8	1813	* @{
MACRUM	0:615f90842ce8	1814	*/
MACRUM	0:615f90842ce8	1815
MACRUM	0:615f90842ce8	1816	/**
MACRUM	0:615f90842ce8	1817	* \brief CRC_FIELD[2:0] registers
MACRUM	0:615f90842ce8	1818	* \code
MACRUM	0:615f90842ce8	1819	* Default value: 0x00
MACRUM	0:615f90842ce8	1820	* Read
MACRUM	0:615f90842ce8	1821	*
MACRUM	0:615f90842ce8	1822	* 7:0 CRC_FIELDx[7:0]: upper(x=2), middle(x=1) and lower(x=0) part of the crc field of the received packet
MACRUM	0:615f90842ce8	1823	* \endcode
MACRUM	0:615f90842ce8	1824	*/
MACRUM	0:615f90842ce8	1825	#define CRC_FIELD2_BASE ((uint8_t)(0xCB)) /!< CRC2 field of the received packet /
MACRUM	0:615f90842ce8	1826
MACRUM	0:615f90842ce8	1827	#define CRC_FIELD1_BASE ((uint8_t)(0xCC)) /!< CRC1 field of the received packet /
MACRUM	0:615f90842ce8	1828
MACRUM	0:615f90842ce8	1829	#define CRC_FIELD0_BASE ((uint8_t)(0xCD)) /!< CRC0 field of the received packet /
MACRUM	0:615f90842ce8	1830
MACRUM	0:615f90842ce8	1831	/**
MACRUM	0:615f90842ce8	1832	* @}
MACRUM	0:615f90842ce8	1833	*/
MACRUM	0:615f90842ce8	1834
MACRUM	0:615f90842ce8	1835	/** @defgroup RX_CTRL_FIELD_Register
MACRUM	0:615f90842ce8	1836	* @{
MACRUM	0:615f90842ce8	1837	*/
MACRUM	0:615f90842ce8	1838
MACRUM	0:615f90842ce8	1839	/**
MACRUM	0:615f90842ce8	1840	* \brief RX_CTRL_FIELD[3:0] registers
MACRUM	0:615f90842ce8	1841	* \code
MACRUM	0:615f90842ce8	1842	* Default value: 0x00
MACRUM	0:615f90842ce8	1843	* Read
MACRUM	0:615f90842ce8	1844	*
MACRUM	0:615f90842ce8	1845	* 7:0 RX_CTRL_FIELDx[7:0]: upper(x=3), middle(x=2), middle(x=1) and lower(x=0) part of the control field of the received packet
MACRUM	0:615f90842ce8	1846	* \endcode
MACRUM	0:615f90842ce8	1847	*/
MACRUM	0:615f90842ce8	1848	#define RX_CTRL_FIELD0_BASE ((uint8_t)(0xCE)) /!< CRTL3 Control field of the received packet /
MACRUM	0:615f90842ce8	1849
MACRUM	0:615f90842ce8	1850	#define RX_CTRL_FIELD1_BASE ((uint8_t)(0xCF)) /!< CRTL2 Control field of the received packet /
MACRUM	0:615f90842ce8	1851
MACRUM	0:615f90842ce8	1852	#define RX_CTRL_FIELD2_BASE ((uint8_t)(0xD0)) /!< CRTL1 Control field of the received packet /
MACRUM	0:615f90842ce8	1853
MACRUM	0:615f90842ce8	1854	#define RX_CTRL_FIELD3_BASE ((uint8_t)(0xD1)) /!< CRTL0 Control field of the received packet /
MACRUM	0:615f90842ce8	1855
MACRUM	0:615f90842ce8	1856	/**
MACRUM	0:615f90842ce8	1857	* @}
MACRUM	0:615f90842ce8	1858	*/
MACRUM	0:615f90842ce8	1859
MACRUM	0:615f90842ce8	1860	/** @defgroup RX_ADDR_FIELD_Register
MACRUM	0:615f90842ce8	1861	* @{
MACRUM	0:615f90842ce8	1862	*/
MACRUM	0:615f90842ce8	1863
MACRUM	0:615f90842ce8	1864	/**
MACRUM	0:615f90842ce8	1865	* \brief RX_ADDR_FIELD[1:0] registers
MACRUM	0:615f90842ce8	1866	* \code
MACRUM	0:615f90842ce8	1867	* Default value: 0x00
MACRUM	0:615f90842ce8	1868	* Read
MACRUM	0:615f90842ce8	1869	*
MACRUM	0:615f90842ce8	1870	* 7:0 RX_ADDR_FIELDx[7:0]: source(x=1) and destination(x=0) address field of the received packet
MACRUM	0:615f90842ce8	1871	* \endcode
MACRUM	0:615f90842ce8	1872	*/
MACRUM	0:615f90842ce8	1873	#define RX_ADDR_FIELD1_BASE ((uint8_t)(0xD2)) /!< ADDR1 Address field of the received packet /
MACRUM	0:615f90842ce8	1874
MACRUM	0:615f90842ce8	1875	#define RX_ADDR_FIELD0_BASE ((uint8_t)(0xD3)) /!< ADDR0 Address field of the received packet /
MACRUM	0:615f90842ce8	1876
MACRUM	0:615f90842ce8	1877	/**
MACRUM	0:615f90842ce8	1878	* @}
MACRUM	0:615f90842ce8	1879	*/
MACRUM	0:615f90842ce8	1880
MACRUM	0:615f90842ce8	1881	/**
MACRUM	0:615f90842ce8	1882	* @}
MACRUM	0:615f90842ce8	1883	*/
MACRUM	0:615f90842ce8	1884
MACRUM	0:615f90842ce8	1885
MACRUM	0:615f90842ce8	1886	/** @defgroup Protocol_Registers
MACRUM	0:615f90842ce8	1887	* @{
MACRUM	0:615f90842ce8	1888	*/
MACRUM	0:615f90842ce8	1889
MACRUM	0:615f90842ce8	1890	/** @defgroup PROTOCOL2_Register
MACRUM	0:615f90842ce8	1891	* @{
MACRUM	0:615f90842ce8	1892	*/
MACRUM	0:615f90842ce8	1893
MACRUM	0:615f90842ce8	1894	/**
MACRUM	0:615f90842ce8	1895	* \brief PROTOCOL2 register
MACRUM	0:615f90842ce8	1896	* \code
MACRUM	0:615f90842ce8	1897	* Default value: 0x06
MACRUM	0:615f90842ce8	1898	* Read Write
MACRUM	0:615f90842ce8	1899	* 7 CS_TIMEOUT_MASK: 1 - CS value contributes to timeout disabling
MACRUM	0:615f90842ce8	1900	*
MACRUM	0:615f90842ce8	1901	* 6 SQI_TIMEOUT_MASK: 1 - SQI value contributes to timeout disabling
MACRUM	0:615f90842ce8	1902	*
MACRUM	0:615f90842ce8	1903	* 5 PQI_TIMEOUT_MASK: 1 - PQI value contributes to timeout disabling
MACRUM	0:615f90842ce8	1904	*
MACRUM	0:615f90842ce8	1905	* 4:3 TX_SEQ_NUM_RELOAD[1:0]: TX sequence number to be used when counting reset is required using the related command.
MACRUM	0:615f90842ce8	1906	*
MACRUM	0:615f90842ce8	1907	* 2 RCO_CALIBRATION[0]: 1 - Enables the automatic RCO calibration
MACRUM	0:615f90842ce8	1908	*
MACRUM	0:615f90842ce8	1909	* 1 VCO_CALIBRATION[0]: 1 - Enables the automatic VCO calibration
MACRUM	0:615f90842ce8	1910	*
MACRUM	0:615f90842ce8	1911	* 0 LDCR_MODE[0]: 1 - LDCR mode enabled
MACRUM	0:615f90842ce8	1912	*
MACRUM	0:615f90842ce8	1913	* \endcode
MACRUM	0:615f90842ce8	1914	*/
MACRUM	0:615f90842ce8	1915	#define PROTOCOL2_BASE ((uint8_t)0x50) /!< Protocol2 regisetr address /
MACRUM	0:615f90842ce8	1916
MACRUM	0:615f90842ce8	1917	#define PROTOCOL2_LDC_MODE_MASK ((uint8_t)0x01) /!< Enable/disable Low duty Cycle mode /
MACRUM	0:615f90842ce8	1918	#define PROTOCOL2_VCO_CALIBRATION_MASK ((uint8_t)0x02) /!< Enable/disable VCO automatic calibration /
MACRUM	0:615f90842ce8	1919	#define PROTOCOL2_RCO_CALIBRATION_MASK ((uint8_t)0x04) /!< Enable/disable RCO automatic calibration /
MACRUM	0:615f90842ce8	1920	#define PROTOCOL2_PQI_TIMEOUT_MASK ((uint8_t)0x20) /!< PQI value contributes to timeout disabling /
MACRUM	0:615f90842ce8	1921	#define PROTOCOL2_SQI_TIMEOUT_MASK ((uint8_t)0x40) /!< SQI value contributes to timeout disabling /
MACRUM	0:615f90842ce8	1922	#define PROTOCOL2_CS_TIMEOUT_MASK ((uint8_t)0x80) /!< CS value contributes to timeout disabling /
MACRUM	0:615f90842ce8	1923
MACRUM	0:615f90842ce8	1924	/**
MACRUM	0:615f90842ce8	1925	* @}
MACRUM	0:615f90842ce8	1926	*/
MACRUM	0:615f90842ce8	1927
MACRUM	0:615f90842ce8	1928	/** @defgroup PROTOCOL1_Register
MACRUM	0:615f90842ce8	1929	* @{
MACRUM	0:615f90842ce8	1930	*/
MACRUM	0:615f90842ce8	1931
MACRUM	0:615f90842ce8	1932	/**
MACRUM	0:615f90842ce8	1933	* \brief PROTOCOL1 register
MACRUM	0:615f90842ce8	1934	* \code
MACRUM	0:615f90842ce8	1935	* Default value: 0x00
MACRUM	0:615f90842ce8	1936	* Read Write
MACRUM	0:615f90842ce8	1937	* 7 LDCR_RELOAD_ON_SYNC: 1 - LDCR timer will be reloaded with the value stored in the LDCR_RELOAD registers
MACRUM	0:615f90842ce8	1938	*
MACRUM	0:615f90842ce8	1939	* 6 PIGGYBACKING: 1 - PIGGYBACKING enabled
MACRUM	0:615f90842ce8	1940	*
MACRUM	0:615f90842ce8	1941	* 5:4 Reserved.
MACRUM	0:615f90842ce8	1942	*
MACRUM	0:615f90842ce8	1943	* 3 SEED_RELOAD[0]: 1 - Reload the back-off random generator
MACRUM	0:615f90842ce8	1944	* seed using the value written in the
MACRUM	0:615f90842ce8	1945	* BU_COUNTER_SEED_MSByte / LSByte registers
MACRUM	0:615f90842ce8	1946	*
MACRUM	0:615f90842ce8	1947	* 2 CSMA_ON [0]: 1 - CSMA channel access mode enabled
MACRUM	0:615f90842ce8	1948	*
MACRUM	0:615f90842ce8	1949	* 1 CSMA_PERS_ON[0]: 1 - CSMA persistent (no back-off) enabled
MACRUM	0:615f90842ce8	1950	*
MACRUM	0:615f90842ce8	1951	* 0 AUTO_PCKT_FLT[0]: 1 - automatic packet filtering mode enabled
MACRUM	0:615f90842ce8	1952	*
MACRUM	0:615f90842ce8	1953	* \endcode
MACRUM	0:615f90842ce8	1954	*/
MACRUM	0:615f90842ce8	1955	#define PROTOCOL1_BASE ((uint8_t)0x51) /!< Protocol1 regisetr address /
MACRUM	0:615f90842ce8	1956
MACRUM	0:615f90842ce8	1957	#define PROTOCOL1_AUTO_PCKT_FLT_MASK ((uint8_t)0x01) /!< Enable/disable automatic packet filtering mode /
MACRUM	0:615f90842ce8	1958	#define PROTOCOL1_CSMA_PERS_ON_MASK ((uint8_t)0x02) /!< Enable/disable CSMA persistent (no back-off) /
MACRUM	0:615f90842ce8	1959	#define PROTOCOL1_CSMA_ON_MASK ((uint8_t)0x04) /!< Enable/disable CSMA channel access mode /
MACRUM	0:615f90842ce8	1960	#define PROTOCOL1_SEED_RELOAD_MASK ((uint8_t)0x08) /!< Reloads the seed of the PN generator for CSMA procedure /
MACRUM	0:615f90842ce8	1961	#define PROTOCOL1_PIGGYBACKING_MASK ((uint8_t)0x40) /!< Enable/disable Piggybacking /
MACRUM	0:615f90842ce8	1962	#define PROTOCOL1_LDC_RELOAD_ON_SYNC_MASK ((uint8_t)0x80) /!< LDC timer will be reloaded with the value stored in the LDC_RELOAD registers /
MACRUM	0:615f90842ce8	1963
MACRUM	0:615f90842ce8	1964	/**
MACRUM	0:615f90842ce8	1965	* @}
MACRUM	0:615f90842ce8	1966	*/
MACRUM	0:615f90842ce8	1967
MACRUM	0:615f90842ce8	1968	/** @defgroup PROTOCOL0_Register
MACRUM	0:615f90842ce8	1969	* @{
MACRUM	0:615f90842ce8	1970	*/
MACRUM	0:615f90842ce8	1971
MACRUM	0:615f90842ce8	1972	/**
MACRUM	0:615f90842ce8	1973	* \brief PROTOCOL0 register
MACRUM	0:615f90842ce8	1974	* \code
MACRUM	0:615f90842ce8	1975	* Default value: 0x08
MACRUM	0:615f90842ce8	1976	* Read Write
MACRUM	0:615f90842ce8	1977	* 7:4 NMAX_RETX[3:0]: Max number of re-TX. 0 - re-transmission is not performed
MACRUM	0:615f90842ce8	1978	*
MACRUM	0:615f90842ce8	1979	* 3 NACK_TX[0]: 1 - field NO_ACK=1 on transmitted packet
MACRUM	0:615f90842ce8	1980	*
MACRUM	0:615f90842ce8	1981	* 2 AUTO_ACK[0]: 1 - automatic ack after RX
MACRUM	0:615f90842ce8	1982	*
MACRUM	0:615f90842ce8	1983	* 1 PERS_RX[0]: 1 - persistent reception enabled
MACRUM	0:615f90842ce8	1984	*
MACRUM	0:615f90842ce8	1985	* 0 PERS_TX[0]: 1 - persistent transmission enabled
MACRUM	0:615f90842ce8	1986	*
MACRUM	0:615f90842ce8	1987	* \endcode
MACRUM	0:615f90842ce8	1988	*/
MACRUM	0:615f90842ce8	1989	#define PROTOCOL0_BASE ((uint8_t)0x52) /!< Persistent RX/TX, autoack, Max number of retransmissions /
MACRUM	0:615f90842ce8	1990
MACRUM	0:615f90842ce8	1991	#define PROTOCOL0_PERS_TX_MASK ((uint8_t)0x01) /!< Enables persistent transmission /
MACRUM	0:615f90842ce8	1992	#define PROTOCOL0_PERS_RX_MASK ((uint8_t)0x02) /!< Enables persistent reception /
MACRUM	0:615f90842ce8	1993	#define PROTOCOL0_AUTO_ACK_MASK ((uint8_t)0x04) /!< Enables auto acknowlegment /
MACRUM	0:615f90842ce8	1994	#define PROTOCOL0_NACK_TX_MASK ((uint8_t)0x08) /!< Writes field NO_ACK=1 on transmitted packet /
MACRUM	0:615f90842ce8	1995	#define PROTOCOL0_NMAX_RETX_MASK ((uint8_t)0xF0) /!< Retransmission mask /
MACRUM	0:615f90842ce8	1996
MACRUM	0:615f90842ce8	1997	/**
MACRUM	0:615f90842ce8	1998	* @}
MACRUM	0:615f90842ce8	1999	*/
MACRUM	0:615f90842ce8	2000
MACRUM	0:615f90842ce8	2001	/** @defgroup TIMERS5_Register
MACRUM	0:615f90842ce8	2002	* @{
MACRUM	0:615f90842ce8	2003	*/
MACRUM	0:615f90842ce8	2004
MACRUM	0:615f90842ce8	2005	/**
MACRUM	0:615f90842ce8	2006	* \brief TIMERS5 register
MACRUM	0:615f90842ce8	2007	* \code
MACRUM	0:615f90842ce8	2008	* Default value: 0x00
MACRUM	0:615f90842ce8	2009	* Read Write
MACRUM	0:615f90842ce8	2010	* 7:0 RX_TIMEOUT_PRESCALER[7:0] : RX operation timeout: prescaler value
MACRUM	0:615f90842ce8	2011	* \endcode
MACRUM	0:615f90842ce8	2012	*/
MACRUM	0:615f90842ce8	2013	#define TIMERS5_RX_TIMEOUT_PRESCALER_BASE ((uint8_t)0x53) /!< RX operation timeout: prescaler value /
MACRUM	0:615f90842ce8	2014
MACRUM	0:615f90842ce8	2015	/**
MACRUM	0:615f90842ce8	2016	* @}
MACRUM	0:615f90842ce8	2017	*/
MACRUM	0:615f90842ce8	2018
MACRUM	0:615f90842ce8	2019	/** @defgroup TIMERS4_Register
MACRUM	0:615f90842ce8	2020	* @{
MACRUM	0:615f90842ce8	2021	*/
MACRUM	0:615f90842ce8	2022
MACRUM	0:615f90842ce8	2023	/**
MACRUM	0:615f90842ce8	2024	* \brief TIMERS4 register
MACRUM	0:615f90842ce8	2025	* \code
MACRUM	0:615f90842ce8	2026	* Default value: 0x00
MACRUM	0:615f90842ce8	2027	* Read Write
MACRUM	0:615f90842ce8	2028	* 7:0 RX_TIMEOUT_COUNTER[7:0] : RX operation timeout: counter value
MACRUM	0:615f90842ce8	2029	* \endcode
MACRUM	0:615f90842ce8	2030	*/
MACRUM	0:615f90842ce8	2031	#define TIMERS4_RX_TIMEOUT_COUNTER_BASE ((uint8_t)0x54) /!< RX operation timeout: counter value /
MACRUM	0:615f90842ce8	2032
MACRUM	0:615f90842ce8	2033	/**
MACRUM	0:615f90842ce8	2034	* @}
MACRUM	0:615f90842ce8	2035	*/
MACRUM	0:615f90842ce8	2036
MACRUM	0:615f90842ce8	2037	/** @defgroup TIMERS3_Register
MACRUM	0:615f90842ce8	2038	* @{
MACRUM	0:615f90842ce8	2039	*/
MACRUM	0:615f90842ce8	2040
MACRUM	0:615f90842ce8	2041	/**
MACRUM	0:615f90842ce8	2042	* \brief TIMERS3 register
MACRUM	0:615f90842ce8	2043	* \code
MACRUM	0:615f90842ce8	2044	* Default value: 0x00
MACRUM	0:615f90842ce8	2045	* Read Write
MACRUM	0:615f90842ce8	2046	* 7:0 LDCR_PRESCALER[7:0] : LDC Mode: Prescaler part of the wake-up value
MACRUM	0:615f90842ce8	2047	* \endcode
MACRUM	0:615f90842ce8	2048	*/
MACRUM	0:615f90842ce8	2049	#define TIMERS3_LDC_PRESCALER_BASE ((uint8_t)0x55) /!< LDC Mode: Prescaler of the wake-up timer /
MACRUM	0:615f90842ce8	2050
MACRUM	0:615f90842ce8	2051	/**
MACRUM	0:615f90842ce8	2052	* @}
MACRUM	0:615f90842ce8	2053	*/
MACRUM	0:615f90842ce8	2054
MACRUM	0:615f90842ce8	2055	/** @defgroup TIMERS2_Register
MACRUM	0:615f90842ce8	2056	* @{
MACRUM	0:615f90842ce8	2057	*/
MACRUM	0:615f90842ce8	2058
MACRUM	0:615f90842ce8	2059	/**
MACRUM	0:615f90842ce8	2060	* \brief TIMERS2 register
MACRUM	0:615f90842ce8	2061	* \code
MACRUM	0:615f90842ce8	2062	* Default value: 0x00
MACRUM	0:615f90842ce8	2063	* Read Write
MACRUM	0:615f90842ce8	2064	* 7:0 LDCR_COUNTER[7:0] : LDC Mode: counter part of the wake-up value
MACRUM	0:615f90842ce8	2065	* \endcode
MACRUM	0:615f90842ce8	2066	*/
MACRUM	0:615f90842ce8	2067	#define TIMERS2_LDC_COUNTER_BASE ((uint8_t)0x56) /!< LDC Mode: counter of the wake-up timer /
MACRUM	0:615f90842ce8	2068
MACRUM	0:615f90842ce8	2069	/**
MACRUM	0:615f90842ce8	2070	* @}
MACRUM	0:615f90842ce8	2071	*/
MACRUM	0:615f90842ce8	2072
MACRUM	0:615f90842ce8	2073	/** @defgroup TIMERS1_Register
MACRUM	0:615f90842ce8	2074	* @{
MACRUM	0:615f90842ce8	2075	*/
MACRUM	0:615f90842ce8	2076
MACRUM	0:615f90842ce8	2077	/**
MACRUM	0:615f90842ce8	2078	* \brief TIMERS1 register
MACRUM	0:615f90842ce8	2079	* \code
MACRUM	0:615f90842ce8	2080	* Default value: 0x00
MACRUM	0:615f90842ce8	2081	* Read Write
MACRUM	0:615f90842ce8	2082	* 7:0 LDCR_RELOAD_PRESCALER[7:0] : LDC Mode: Prescaler part of the reload value
MACRUM	0:615f90842ce8	2083	* \endcode
MACRUM	0:615f90842ce8	2084	*/
MACRUM	0:615f90842ce8	2085	#define TIMERS1_LDC_RELOAD_PRESCALER_BASE ((uint8_t)0x57) /!< LDC Mode: Prescaler part of the reload value /
MACRUM	0:615f90842ce8	2086
MACRUM	0:615f90842ce8	2087	/**
MACRUM	0:615f90842ce8	2088	* @}
MACRUM	0:615f90842ce8	2089	*/
MACRUM	0:615f90842ce8	2090
MACRUM	0:615f90842ce8	2091	/** @defgroup TIMERS0_Register
MACRUM	0:615f90842ce8	2092	* @{
MACRUM	0:615f90842ce8	2093	*/
MACRUM	0:615f90842ce8	2094
MACRUM	0:615f90842ce8	2095	/**
MACRUM	0:615f90842ce8	2096	* \brief TIMERS0 register
MACRUM	0:615f90842ce8	2097	* \code
MACRUM	0:615f90842ce8	2098	* Default value: 0x00
MACRUM	0:615f90842ce8	2099	* Read Write
MACRUM	0:615f90842ce8	2100	* 7:0 LDCR_RELOAD_COUNTER[7:0] : LDC Mode: Counter part of the reload value
MACRUM	0:615f90842ce8	2101	* \endcode
MACRUM	0:615f90842ce8	2102	*/
MACRUM	0:615f90842ce8	2103	#define TIMERS0_LDC_RELOAD_COUNTER_BASE ((uint8_t)0x58) /!< LDC Mode: Counter part of the reload value /
MACRUM	0:615f90842ce8	2104
MACRUM	0:615f90842ce8	2105	/**
MACRUM	0:615f90842ce8	2106	* @}
MACRUM	0:615f90842ce8	2107	*/
MACRUM	0:615f90842ce8	2108
MACRUM	0:615f90842ce8	2109
MACRUM	0:615f90842ce8	2110	/** @defgroup CSMA_CONFIG3_Register
MACRUM	0:615f90842ce8	2111	* @{
MACRUM	0:615f90842ce8	2112	*/
MACRUM	0:615f90842ce8	2113
MACRUM	0:615f90842ce8	2114	/**
MACRUM	0:615f90842ce8	2115	* \brief CSMA_CONFIG3 registers
MACRUM	0:615f90842ce8	2116	* \code
MACRUM	0:615f90842ce8	2117	* Default value: 0xFF
MACRUM	0:615f90842ce8	2118	* Read Write
MACRUM	0:615f90842ce8	2119	* 7:0 BU_COUNTER_SEED_MSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB)
MACRUM	0:615f90842ce8	2120	* \endcode
MACRUM	0:615f90842ce8	2121	*/
MACRUM	0:615f90842ce8	2122	#define CSMA_CONFIG3_BASE ((uint8_t)0x64) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (MSB) /
MACRUM	0:615f90842ce8	2123
MACRUM	0:615f90842ce8	2124	/**
MACRUM	0:615f90842ce8	2125	* @}
MACRUM	0:615f90842ce8	2126	*/
MACRUM	0:615f90842ce8	2127
MACRUM	0:615f90842ce8	2128	/** @defgroup CSMA_CONFIG2_Register
MACRUM	0:615f90842ce8	2129	* @{
MACRUM	0:615f90842ce8	2130	*/
MACRUM	0:615f90842ce8	2131
MACRUM	0:615f90842ce8	2132	/**
MACRUM	0:615f90842ce8	2133	* \brief CSMA_CONFIG2 registers
MACRUM	0:615f90842ce8	2134	* \code
MACRUM	0:615f90842ce8	2135	* Default value: 0x00
MACRUM	0:615f90842ce8	2136	* Read Write
MACRUM	0:615f90842ce8	2137	* 7:0 BU_COUNTER_SEED_LSByte: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB)
MACRUM	0:615f90842ce8	2138	* \endcode
MACRUM	0:615f90842ce8	2139	*/
MACRUM	0:615f90842ce8	2140	#define CSMA_CONFIG2_BASE ((uint8_t)0x65) /!< CSMA/CA: Seed of the random number generator used to apply the BEB (Binary Exponential Backoff) algorithm (LSB) /
MACRUM	0:615f90842ce8	2141
MACRUM	0:615f90842ce8	2142	/**
MACRUM	0:615f90842ce8	2143	* @}
MACRUM	0:615f90842ce8	2144	*/
MACRUM	0:615f90842ce8	2145
MACRUM	0:615f90842ce8	2146	/** @defgroup CSMA_CONFIG1_Register
MACRUM	0:615f90842ce8	2147	* @{
MACRUM	0:615f90842ce8	2148	*/
MACRUM	0:615f90842ce8	2149
MACRUM	0:615f90842ce8	2150	/**
MACRUM	0:615f90842ce8	2151	* \brief CSMA_CONFIG1 registers
MACRUM	0:615f90842ce8	2152	* \code
MACRUM	0:615f90842ce8	2153	* Default value: 0x04
MACRUM	0:615f90842ce8	2154	* Read Write
MACRUM	0:615f90842ce8	2155	* 7:2 BU_PRESCALER[5:0]: Used to program the back-off unit BU
MACRUM	0:615f90842ce8	2156	*
MACRUM	0:615f90842ce8	2157	* 1:0 CCA_PERIOD[1:0]: Used to program the Tcca time (64 / 128 /256 / 512 × Tbit.
MACRUM	0:615f90842ce8	2158	* \endcode
MACRUM	0:615f90842ce8	2159	*/
MACRUM	0:615f90842ce8	2160	#define CSMA_CONFIG1_BASE ((uint8_t)0x66) /!< CSMA/CA: Prescaler of the back-off time unit (BU); CCA period /
MACRUM	0:615f90842ce8	2161
MACRUM	0:615f90842ce8	2162	#define CSMA_CCA_PERIOD_64TBIT ((uint8_t)0x00) /!< CSMA/CA: Sets CCA period to 64TBIT */
MACRUM	0:615f90842ce8	2163	#define CSMA_CCA_PERIOD_128TBIT ((uint8_t)0x01) /!< CSMA/CA: Sets CCA period to 128TBIT */
MACRUM	0:615f90842ce8	2164	#define CSMA_CCA_PERIOD_256TBIT ((uint8_t)0x02) /!< CSMA/CA: Sets CCA period to 256TBIT */
MACRUM	0:615f90842ce8	2165	#define CSMA_CCA_PERIOD_512TBIT ((uint8_t)0x03) /!< CSMA/CA: Sets CCA period to 512TBIT */
MACRUM	0:615f90842ce8	2166
MACRUM	0:615f90842ce8	2167	/**
MACRUM	0:615f90842ce8	2168	* @}
MACRUM	0:615f90842ce8	2169	*/
MACRUM	0:615f90842ce8	2170
MACRUM	0:615f90842ce8	2171	/** @defgroup CSMA_CONFIG0_Register
MACRUM	0:615f90842ce8	2172	* @{
MACRUM	0:615f90842ce8	2173	*/
MACRUM	0:615f90842ce8	2174
MACRUM	0:615f90842ce8	2175	/**
MACRUM	0:615f90842ce8	2176	* \brief CSMA_CONFIG0 registers
MACRUM	0:615f90842ce8	2177	* \code
MACRUM	0:615f90842ce8	2178	* Default value: 0x00
MACRUM	0:615f90842ce8	2179	* Read Write
MACRUM	0:615f90842ce8	2180	* 7:4 CCA_LENGTH[3:0]: Used to program the Tlisten time
MACRUM	0:615f90842ce8	2181	*
MACRUM	0:615f90842ce8	2182	* 3 Reserved.
MACRUM	0:615f90842ce8	2183	*
MACRUM	0:615f90842ce8	2184	* 2:0 NBACKOFF_MAX[2:0]: Max number of back-off cycles.
MACRUM	0:615f90842ce8	2185	* \endcode
MACRUM	0:615f90842ce8	2186	*/
MACRUM	0:615f90842ce8	2187	#define CSMA_CONFIG0_BASE ((uint8_t)0x67) /!< CSMA/CA: CCA lenght; Max number of backoff cycles /
MACRUM	0:615f90842ce8	2188
MACRUM	0:615f90842ce8	2189	/**
MACRUM	0:615f90842ce8	2190	* @}
MACRUM	0:615f90842ce8	2191	*/
MACRUM	0:615f90842ce8	2192
MACRUM	0:615f90842ce8	2193	/**
MACRUM	0:615f90842ce8	2194	* @}
MACRUM	0:615f90842ce8	2195	*/
MACRUM	0:615f90842ce8	2196
MACRUM	0:615f90842ce8	2197
MACRUM	0:615f90842ce8	2198	/** @defgroup Link_Quality_Registers
MACRUM	0:615f90842ce8	2199	* @{
MACRUM	0:615f90842ce8	2200	*/
MACRUM	0:615f90842ce8	2201
MACRUM	0:615f90842ce8	2202	/** @defgroup QI_Register
MACRUM	0:615f90842ce8	2203	* @{
MACRUM	0:615f90842ce8	2204	*/
MACRUM	0:615f90842ce8	2205
MACRUM	0:615f90842ce8	2206	/**
MACRUM	0:615f90842ce8	2207	* \brief QI register
MACRUM	0:615f90842ce8	2208	* \code
MACRUM	0:615f90842ce8	2209	* Read Write
MACRUM	0:615f90842ce8	2210	* Default value: 0x02
MACRUM	0:615f90842ce8	2211	*
MACRUM	0:615f90842ce8	2212	* 7:6 SQI_TH[1:0]: SQI threshold according to the formula: 8SYNC_LEN - 2SQI_TH
MACRUM	0:615f90842ce8	2213	*
MACRUM	0:615f90842ce8	2214	* 5:2 PQI_TH[3:0]: PQI threshold according to the formula: 4*PQI_THR
MACRUM	0:615f90842ce8	2215	*
MACRUM	0:615f90842ce8	2216	*
MACRUM	0:615f90842ce8	2217	* 1 SQI_EN[0]: SQI enable
MACRUM	0:615f90842ce8	2218	* 1 - Enable
MACRUM	0:615f90842ce8	2219	* 0 - Disable
MACRUM	0:615f90842ce8	2220	*
MACRUM	0:615f90842ce8	2221	* 0 PQI_EN[0]: PQI enable
MACRUM	0:615f90842ce8	2222	* 1 - Enable
MACRUM	0:615f90842ce8	2223	* 0 - Disable
MACRUM	0:615f90842ce8	2224	* \endcode
MACRUM	0:615f90842ce8	2225	*/
MACRUM	0:615f90842ce8	2226	#define QI_BASE ((uint8_t)0x3A) /!< QI register /
MACRUM	0:615f90842ce8	2227
MACRUM	0:615f90842ce8	2228	#define QI_PQI_MASK ((uint8_t)0x01) /!< PQI enable/disable /
MACRUM	0:615f90842ce8	2229	#define QI_SQI_MASK ((uint8_t)0x02) /!< SQI enable/disable /
MACRUM	0:615f90842ce8	2230
MACRUM	0:615f90842ce8	2231	/**
MACRUM	0:615f90842ce8	2232	* @}
MACRUM	0:615f90842ce8	2233	*/
MACRUM	0:615f90842ce8	2234
MACRUM	0:615f90842ce8	2235	/** @defgroup LINK_QUALIF2
MACRUM	0:615f90842ce8	2236	* @{
MACRUM	0:615f90842ce8	2237	*/
MACRUM	0:615f90842ce8	2238
MACRUM	0:615f90842ce8	2239	/**
MACRUM	0:615f90842ce8	2240	* \brief LINK_QUALIF2 registers
MACRUM	0:615f90842ce8	2241	* \code
MACRUM	0:615f90842ce8	2242	* Default value: 0x00
MACRUM	0:615f90842ce8	2243	* Read
MACRUM	0:615f90842ce8	2244	*
MACRUM	0:615f90842ce8	2245	* 7:0 PQI[7:0]: PQI value of the received packet
MACRUM	0:615f90842ce8	2246	* \endcode
MACRUM	0:615f90842ce8	2247	*/
MACRUM	0:615f90842ce8	2248	#define LINK_QUALIF2_BASE ((uint8_t)(0xC5)) /!< PQI value of the received packet /
MACRUM	0:615f90842ce8	2249
MACRUM	0:615f90842ce8	2250	/**
MACRUM	0:615f90842ce8	2251	* @}
MACRUM	0:615f90842ce8	2252	*/
MACRUM	0:615f90842ce8	2253
MACRUM	0:615f90842ce8	2254	/** @defgroup LINK_QUALIF1
MACRUM	0:615f90842ce8	2255	* @{
MACRUM	0:615f90842ce8	2256	*/
MACRUM	0:615f90842ce8	2257
MACRUM	0:615f90842ce8	2258	/**
MACRUM	0:615f90842ce8	2259	* \brief LINK_QUALIF1 registers
MACRUM	0:615f90842ce8	2260	* \code
MACRUM	0:615f90842ce8	2261	* Default value: 0x00
MACRUM	0:615f90842ce8	2262	* Read
MACRUM	0:615f90842ce8	2263	*
MACRUM	0:615f90842ce8	2264	* 7 CS: Carrier Sense indication
MACRUM	0:615f90842ce8	2265	*
MACRUM	0:615f90842ce8	2266	* 6:0 SQI[6:0]: SQI value of the received packet
MACRUM	0:615f90842ce8	2267	* \endcode
MACRUM	0:615f90842ce8	2268	*/
MACRUM	0:615f90842ce8	2269	#define LINK_QUALIF1_BASE ((uint8_t)(0xC6)) /!< Carrier sense indication [7]; SQI value of the received packet /
MACRUM	0:615f90842ce8	2270
MACRUM	0:615f90842ce8	2271	#define LINK_QUALIF1_CS ((uint8_t)(0x80)) /!< Carrier sense indication [7] /
MACRUM	0:615f90842ce8	2272
MACRUM	0:615f90842ce8	2273	/**
MACRUM	0:615f90842ce8	2274	* @}
MACRUM	0:615f90842ce8	2275	*/
MACRUM	0:615f90842ce8	2276
MACRUM	0:615f90842ce8	2277	/** @defgroup LINK_QUALIF0
MACRUM	0:615f90842ce8	2278	* @{
MACRUM	0:615f90842ce8	2279	*/
MACRUM	0:615f90842ce8	2280
MACRUM	0:615f90842ce8	2281	/**
MACRUM	0:615f90842ce8	2282	* \brief LINK_QUALIF0 registers
MACRUM	0:615f90842ce8	2283	* \code
MACRUM	0:615f90842ce8	2284	* Default value: 0x00
MACRUM	0:615f90842ce8	2285	* Read
MACRUM	0:615f90842ce8	2286	*
MACRUM	0:615f90842ce8	2287	* 7:4 LQI [3:0]: LQI value of the received packet
MACRUM	0:615f90842ce8	2288	*
MACRUM	0:615f90842ce8	2289	* 3:0 AGC_WORD[3:0]: AGC word of the received packet
MACRUM	0:615f90842ce8	2290	* \endcode
MACRUM	0:615f90842ce8	2291	*/
MACRUM	0:615f90842ce8	2292	#define LINK_QUALIF0_BASE ((uint8_t)(0xC7)) /!< LQI value of the received packet [7:4]; AGC word of the received packet [3:0] /
MACRUM	0:615f90842ce8	2293
MACRUM	0:615f90842ce8	2294	/**
MACRUM	0:615f90842ce8	2295	* @}
MACRUM	0:615f90842ce8	2296	*/
MACRUM	0:615f90842ce8	2297
MACRUM	0:615f90842ce8	2298	/** @defgroup RSSI_LEVEL
MACRUM	0:615f90842ce8	2299	* @{
MACRUM	0:615f90842ce8	2300	*/
MACRUM	0:615f90842ce8	2301
MACRUM	0:615f90842ce8	2302	/**
MACRUM	0:615f90842ce8	2303	* \brief RSSI_LEVEL registers
MACRUM	0:615f90842ce8	2304	* \code
MACRUM	0:615f90842ce8	2305	* Default value: 0x00
MACRUM	0:615f90842ce8	2306	* Read
MACRUM	0:615f90842ce8	2307	*
MACRUM	0:615f90842ce8	2308	* 7:0 RSSI_LEVEL[7:0]: RSSI level of the received packet
MACRUM	0:615f90842ce8	2309	* \endcode
MACRUM	0:615f90842ce8	2310	*/
MACRUM	0:615f90842ce8	2311	#define RSSI_LEVEL_BASE ((uint8_t)(0xC8)) /!< RSSI level of the received packet /
MACRUM	0:615f90842ce8	2312
MACRUM	0:615f90842ce8	2313	/**
MACRUM	0:615f90842ce8	2314	* @}
MACRUM	0:615f90842ce8	2315	*/
MACRUM	0:615f90842ce8	2316
MACRUM	0:615f90842ce8	2317	/** @defgroup RSSI_FLT_Register
MACRUM	0:615f90842ce8	2318	* @{
MACRUM	0:615f90842ce8	2319	*/
MACRUM	0:615f90842ce8	2320
MACRUM	0:615f90842ce8	2321	/**
MACRUM	0:615f90842ce8	2322	* \brief RSSI register
MACRUM	0:615f90842ce8	2323	* \code
MACRUM	0:615f90842ce8	2324	* Read Write
MACRUM	0:615f90842ce8	2325	* Default value: 0xF3
MACRUM	0:615f90842ce8	2326	* 7:4 RSSI_FLT[3:0]: Gain of the RSSI filter
MACRUM	0:615f90842ce8	2327	*
MACRUM	0:615f90842ce8	2328	* 3:2 CS_MODE[1:0]: AFC loop gain in slow mode (2's log)
MACRUM	0:615f90842ce8	2329	*
MACRUM	0:615f90842ce8	2330	* CS_MODE1 \| CS_MODE0 \| CS Mode
MACRUM	0:615f90842ce8	2331	* -----------------------------------------------------------------------------------------
MACRUM	0:615f90842ce8	2332	* 0 \| 0 \| Static CS
MACRUM	0:615f90842ce8	2333	* 0 \| 1 \| Dynamic CS with 6dB dynamic threshold
MACRUM	0:615f90842ce8	2334	* 1 \| 0 \| Dynamic CS with 12dB dynamic threshold
MACRUM	0:615f90842ce8	2335	* 1 \| 1 \| Dynamic CS with 18dB dynamic threshold
MACRUM	0:615f90842ce8	2336	*
MACRUM	0:615f90842ce8	2337	* 1:0 OOK_PEAK_DECAY[1:0]: Peak decay control for OOK: 3 slow decay; 0 fast decay
MACRUM	0:615f90842ce8	2338	*
MACRUM	0:615f90842ce8	2339	* \endcode
MACRUM	0:615f90842ce8	2340	*/
MACRUM	0:615f90842ce8	2341	#define RSSI_FLT_BASE ((uint8_t)0x21) /*!< Gain of the RSSI filter; lower value is fast but inaccurate,
MACRUM	0:615f90842ce8	2342	higher value is slow and more accurate */
MACRUM	0:615f90842ce8	2343	#define RSSI_FLT_CS_MODE_MASK ((uint8_t)0x0C) /!< Carrier sense mode mask /
MACRUM	0:615f90842ce8	2344	#define RSSI_FLT_CS_MODE_STATIC ((uint8_t)0x00) /!< Carrier sense mode; static carrier sensing /
MACRUM	0:615f90842ce8	2345	#define RSSI_FLT_CS_MODE_DYNAMIC_6 ((uint8_t)0x04) /!< Carrier sense mode; dynamic carrier sensing with 6dB threshold /
MACRUM	0:615f90842ce8	2346	#define RSSI_FLT_CS_MODE_DYNAMIC_12 ((uint8_t)0x08) /!< Carrier sense mode; dynamic carrier sensing with 12dB threshold /
MACRUM	0:615f90842ce8	2347	#define RSSI_FLT_CS_MODE_DYNAMIC_18 ((uint8_t)0x0C) /!< Carrier sense mode; dynamic carrier sensing with 18dB threshold /
MACRUM	0:615f90842ce8	2348	#define RSSI_FLT_OOK_PEAK_DECAY_MASK ((uint8_t)0x03) /!< Peak decay control for OOK mask /
MACRUM	0:615f90842ce8	2349	#define RSSI_FLT_OOK_PEAK_DECAY_FAST ((uint8_t)0x00) /!< Peak decay control for OOK: fast decay /
MACRUM	0:615f90842ce8	2350	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_FAST ((uint8_t)0x01) /!< Peak decay control for OOK: medium_fast decay /
MACRUM	0:615f90842ce8	2351	#define RSSI_FLT_OOK_PEAK_DECAY_MEDIUM_SLOW ((uint8_t)0x02) /!< Peak decay control for OOK: medium_fast decay /
MACRUM	0:615f90842ce8	2352	#define RSSI_FLT_OOK_PEAK_DECAY_SLOW ((uint8_t)0x03) /!< Peak decay control for OOK: slow decay /
MACRUM	0:615f90842ce8	2353
MACRUM	0:615f90842ce8	2354	/**
MACRUM	0:615f90842ce8	2355	* @}
MACRUM	0:615f90842ce8	2356	*/
MACRUM	0:615f90842ce8	2357
MACRUM	0:615f90842ce8	2358	/** @defgroup RSSI_TH_Register
MACRUM	0:615f90842ce8	2359	* @{
MACRUM	0:615f90842ce8	2360	*/
MACRUM	0:615f90842ce8	2361
MACRUM	0:615f90842ce8	2362	/**
MACRUM	0:615f90842ce8	2363	* \brief RSSI_TH register
MACRUM	0:615f90842ce8	2364	* \code
MACRUM	0:615f90842ce8	2365	* Read Write
MACRUM	0:615f90842ce8	2366	* Default value: 0x24
MACRUM	0:615f90842ce8	2367	*
MACRUM	0:615f90842ce8	2368	* 7:0 RSSI_THRESHOLD [7:0]: Signal detect threshold in 0.5dB. -120dBm corresponds to 20
MACRUM	0:615f90842ce8	2369	* \endcode
MACRUM	0:615f90842ce8	2370	*/
MACRUM	0:615f90842ce8	2371	#define RSSI_TH_BASE ((uint8_t)0x22) /!< Signal detect threshold in 0.5dB stp. 20 correspond to -120 dBm /
MACRUM	0:615f90842ce8	2372
MACRUM	0:615f90842ce8	2373	/**
MACRUM	0:615f90842ce8	2374	* @}
MACRUM	0:615f90842ce8	2375	*/
MACRUM	0:615f90842ce8	2376
MACRUM	0:615f90842ce8	2377	/**
MACRUM	0:615f90842ce8	2378	* @}
MACRUM	0:615f90842ce8	2379	*/
MACRUM	0:615f90842ce8	2380
MACRUM	0:615f90842ce8	2381
MACRUM	0:615f90842ce8	2382	/** @defgroup FIFO_Registers
MACRUM	0:615f90842ce8	2383	* @{
MACRUM	0:615f90842ce8	2384	*/
MACRUM	0:615f90842ce8	2385
MACRUM	0:615f90842ce8	2386	/** @defgroup FIFO_CONFIG3_Register
MACRUM	0:615f90842ce8	2387	* @{
MACRUM	0:615f90842ce8	2388	*/
MACRUM	0:615f90842ce8	2389
MACRUM	0:615f90842ce8	2390	/**
MACRUM	0:615f90842ce8	2391	* \brief FIFO_CONFIG3 registers
MACRUM	0:615f90842ce8	2392	* \code
MACRUM	0:615f90842ce8	2393	* Default value: 0x30
MACRUM	0:615f90842ce8	2394	* Read Write
MACRUM	0:615f90842ce8	2395	* 7 Reserved.
MACRUM	0:615f90842ce8	2396	*
MACRUM	0:615f90842ce8	2397	* 6:0 rxafthr [6:0]: FIFO Almost Full threshold for rx fifo.
MACRUM	0:615f90842ce8	2398	*
MACRUM	0:615f90842ce8	2399	* \endcode
MACRUM	0:615f90842ce8	2400	*/
MACRUM	0:615f90842ce8	2401	#define FIFO_CONFIG3_RXAFTHR_BASE ((uint8_t)0x3E) /!< FIFO Almost Full threshold for rx fifo [6:0] /
MACRUM	0:615f90842ce8	2402
MACRUM	0:615f90842ce8	2403	/**
MACRUM	0:615f90842ce8	2404	* @}
MACRUM	0:615f90842ce8	2405	*/
MACRUM	0:615f90842ce8	2406
MACRUM	0:615f90842ce8	2407	/** @defgroup FIFO_CONFIG2_Register
MACRUM	0:615f90842ce8	2408	* @{
MACRUM	0:615f90842ce8	2409	*/
MACRUM	0:615f90842ce8	2410
MACRUM	0:615f90842ce8	2411	/**
MACRUM	0:615f90842ce8	2412	* \brief FIFO_CONFIG2 registers
MACRUM	0:615f90842ce8	2413	* \code
MACRUM	0:615f90842ce8	2414	* Default value: 0x30
MACRUM	0:615f90842ce8	2415	* Read Write
MACRUM	0:615f90842ce8	2416	* 7 Reserved.
MACRUM	0:615f90842ce8	2417	*
MACRUM	0:615f90842ce8	2418	* 6:0 rxaethr [6:0]: FIFO Almost Empty threshold for rx fifo.
MACRUM	0:615f90842ce8	2419	*
MACRUM	0:615f90842ce8	2420	* \endcode
MACRUM	0:615f90842ce8	2421	*/
MACRUM	0:615f90842ce8	2422	#define FIFO_CONFIG2_RXAETHR_BASE ((uint8_t)0x3F) /!< FIFO Almost Empty threshold for rx fifo [6:0] /
MACRUM	0:615f90842ce8	2423
MACRUM	0:615f90842ce8	2424	/**
MACRUM	0:615f90842ce8	2425	* @}
MACRUM	0:615f90842ce8	2426	*/
MACRUM	0:615f90842ce8	2427
MACRUM	0:615f90842ce8	2428	/** @defgroup FIFO_CONFIG1_Register
MACRUM	0:615f90842ce8	2429	* @{
MACRUM	0:615f90842ce8	2430	*/
MACRUM	0:615f90842ce8	2431
MACRUM	0:615f90842ce8	2432	/**
MACRUM	0:615f90842ce8	2433	* \brief FIFO_CONFIG1 registers
MACRUM	0:615f90842ce8	2434	* \code
MACRUM	0:615f90842ce8	2435	* Default value: 0x30
MACRUM	0:615f90842ce8	2436	* Read Write
MACRUM	0:615f90842ce8	2437	* 7 Reserved.
MACRUM	0:615f90842ce8	2438	*
MACRUM	0:615f90842ce8	2439	* 6:0 txafthr [6:0]: FIFO Almost Full threshold for tx fifo.
MACRUM	0:615f90842ce8	2440	*
MACRUM	0:615f90842ce8	2441	* \endcode
MACRUM	0:615f90842ce8	2442	*/
MACRUM	0:615f90842ce8	2443	#define FIFO_CONFIG1_TXAFTHR_BASE ((uint8_t)0x40) /!< FIFO Almost Full threshold for tx fifo [6:0] /
MACRUM	0:615f90842ce8	2444
MACRUM	0:615f90842ce8	2445	/**
MACRUM	0:615f90842ce8	2446	* @}
MACRUM	0:615f90842ce8	2447	*/
MACRUM	0:615f90842ce8	2448
MACRUM	0:615f90842ce8	2449	/** @defgroup FIFO_CONFIG0_Register
MACRUM	0:615f90842ce8	2450	* @{
MACRUM	0:615f90842ce8	2451	*/
MACRUM	0:615f90842ce8	2452
MACRUM	0:615f90842ce8	2453	/**
MACRUM	0:615f90842ce8	2454	* \brief FIFO_CONFIG0 registers
MACRUM	0:615f90842ce8	2455	* \code
MACRUM	0:615f90842ce8	2456	* Default value: 0x30
MACRUM	0:615f90842ce8	2457	* Read Write
MACRUM	0:615f90842ce8	2458	* 7 Reserved.
MACRUM	0:615f90842ce8	2459	*
MACRUM	0:615f90842ce8	2460	* 6:0 txaethr [6:0]: FIFO Almost Empty threshold for tx fifo.
MACRUM	0:615f90842ce8	2461	*
MACRUM	0:615f90842ce8	2462	* \endcode
MACRUM	0:615f90842ce8	2463	*/
MACRUM	0:615f90842ce8	2464	#define FIFO_CONFIG0_TXAETHR_BASE ((uint8_t)0x41) /!< FIFO Almost Empty threshold for tx fifo [6:0] /
MACRUM	0:615f90842ce8	2465
MACRUM	0:615f90842ce8	2466	/**
MACRUM	0:615f90842ce8	2467	* @}
MACRUM	0:615f90842ce8	2468	*/
MACRUM	0:615f90842ce8	2469
MACRUM	0:615f90842ce8	2470	/** @defgroup LINEAR_FIFO_STATUS1_Register
MACRUM	0:615f90842ce8	2471	* @{
MACRUM	0:615f90842ce8	2472	*/
MACRUM	0:615f90842ce8	2473
MACRUM	0:615f90842ce8	2474	/**
MACRUM	0:615f90842ce8	2475	* \brief LINEAR_FIFO_STATUS1 registers
MACRUM	0:615f90842ce8	2476	* \code
MACRUM	0:615f90842ce8	2477	* Default value: 0x00
MACRUM	0:615f90842ce8	2478	* Read
MACRUM	0:615f90842ce8	2479	*
MACRUM	0:615f90842ce8	2480	* 7 Reserved.
MACRUM	0:615f90842ce8	2481	*
MACRUM	0:615f90842ce8	2482	* 6:0 elem_txfifo[6:0]: Number of elements in the linear TXFIFO (<=96)
MACRUM	0:615f90842ce8	2483	* \endcode
MACRUM	0:615f90842ce8	2484	*/
MACRUM	0:615f90842ce8	2485	#define LINEAR_FIFO_STATUS1_BASE ((uint8_t)(0xE6)) /!< Number of elements in the linear TX FIFO [6:0] (<=96) /
MACRUM	0:615f90842ce8	2486
MACRUM	0:615f90842ce8	2487	/**
MACRUM	0:615f90842ce8	2488	* @}
MACRUM	0:615f90842ce8	2489	*/
MACRUM	0:615f90842ce8	2490
MACRUM	0:615f90842ce8	2491	/** @defgroup LINEAR_FIFO_STATUS0_Register
MACRUM	0:615f90842ce8	2492	* @{
MACRUM	0:615f90842ce8	2493	*/
MACRUM	0:615f90842ce8	2494
MACRUM	0:615f90842ce8	2495	/**
MACRUM	0:615f90842ce8	2496	* \brief LINEAR_FIFO_STATUS0 registers
MACRUM	0:615f90842ce8	2497	* \code
MACRUM	0:615f90842ce8	2498	* Default value: 0x00
MACRUM	0:615f90842ce8	2499	* Read
MACRUM	0:615f90842ce8	2500	*
MACRUM	0:615f90842ce8	2501	* 7 Reserved.
MACRUM	0:615f90842ce8	2502	*
MACRUM	0:615f90842ce8	2503	* 6:0 elem_rxfifo[6:0]: Number of elements in the linear RXFIFO (<=96)
MACRUM	0:615f90842ce8	2504	* \endcode
MACRUM	0:615f90842ce8	2505	*/
MACRUM	0:615f90842ce8	2506	#define LINEAR_FIFO_STATUS0_BASE ((uint8_t)(0xE7)) /!< Number of elements in the linear RX FIFO [6:0] (<=96) /
MACRUM	0:615f90842ce8	2507
MACRUM	0:615f90842ce8	2508	/**
MACRUM	0:615f90842ce8	2509	* @}
MACRUM	0:615f90842ce8	2510	*/
MACRUM	0:615f90842ce8	2511
MACRUM	0:615f90842ce8	2512
MACRUM	0:615f90842ce8	2513	/**
MACRUM	0:615f90842ce8	2514	* @}
MACRUM	0:615f90842ce8	2515	*/
MACRUM	0:615f90842ce8	2516
MACRUM	0:615f90842ce8	2517
MACRUM	0:615f90842ce8	2518	/** @defgroup Calibration_Registers
MACRUM	0:615f90842ce8	2519	* @{
MACRUM	0:615f90842ce8	2520	*/
MACRUM	0:615f90842ce8	2521
MACRUM	0:615f90842ce8	2522	/** @defgroup RCO_VCO_CALIBR_IN2_Register
MACRUM	0:615f90842ce8	2523	* @{
MACRUM	0:615f90842ce8	2524	*/
MACRUM	0:615f90842ce8	2525
MACRUM	0:615f90842ce8	2526	/**
MACRUM	0:615f90842ce8	2527	* \brief RCO_VCO_CALIBR_IN2 registers
MACRUM	0:615f90842ce8	2528	* \code
MACRUM	0:615f90842ce8	2529	* Default value: 0x70
MACRUM	0:615f90842ce8	2530	* Read Write
MACRUM	0:615f90842ce8	2531	* 7:4 RWT_IN[3:0]: RaWThermometric word value for the RCO [7:4]
MACRUM	0:615f90842ce8	2532	*
MACRUM	0:615f90842ce8	2533	* 3:0 RFB_IN[4:1]: ResistorFineBit word value for the RCO (first 4 bits)
MACRUM	0:615f90842ce8	2534	* \endcode
MACRUM	0:615f90842ce8	2535	*/
MACRUM	0:615f90842ce8	2536	#define RCO_VCO_CALIBR_IN2_BASE ((uint8_t)0x6D) /!< RaWThermometric word value for the RCO [7:4]; ResistorFineBit word value for the RCO [3:0] /
MACRUM	0:615f90842ce8	2537
MACRUM	0:615f90842ce8	2538	/**
MACRUM	0:615f90842ce8	2539	* @}
MACRUM	0:615f90842ce8	2540	*/
MACRUM	0:615f90842ce8	2541
MACRUM	0:615f90842ce8	2542	/** @defgroup RCO_VCO_CALIBR_IN1_Register
MACRUM	0:615f90842ce8	2543	* @{
MACRUM	0:615f90842ce8	2544	*/
MACRUM	0:615f90842ce8	2545
MACRUM	0:615f90842ce8	2546	/**
MACRUM	0:615f90842ce8	2547	* \brief RCO_VCO_CALIBR_IN1 registers
MACRUM	0:615f90842ce8	2548	* \code
MACRUM	0:615f90842ce8	2549	* Default value: 0x48
MACRUM	0:615f90842ce8	2550	* Read Write
MACRUM	0:615f90842ce8	2551	*
MACRUM	0:615f90842ce8	2552	* 7 RFB_IN[0]: ResistorFineBit word value for the RCO (LSb)
MACRUM	0:615f90842ce8	2553	*
MACRUM	0:615f90842ce8	2554	* 6:0 VCO_CALIBR_TX[6:0]: Word value for the VCO to be used in TX mode
MACRUM	0:615f90842ce8	2555	* \endcode
MACRUM	0:615f90842ce8	2556	*/
MACRUM	0:615f90842ce8	2557	#define RCO_VCO_CALIBR_IN1_BASE ((uint8_t)0x6E) /!< ResistorFineBit word value for the RCO [7]; Word value for the VCO to be used in TX mode [6:0]/
MACRUM	0:615f90842ce8	2558
MACRUM	0:615f90842ce8	2559	/**
MACRUM	0:615f90842ce8	2560	* @}
MACRUM	0:615f90842ce8	2561	*/
MACRUM	0:615f90842ce8	2562
MACRUM	0:615f90842ce8	2563	/** @defgroup RCO_VCO_CALIBR_IN0_Register
MACRUM	0:615f90842ce8	2564	* @{
MACRUM	0:615f90842ce8	2565	*/
MACRUM	0:615f90842ce8	2566
MACRUM	0:615f90842ce8	2567	/**
MACRUM	0:615f90842ce8	2568	* \brief RCO_VCO_CALIBR_IN0 registers
MACRUM	0:615f90842ce8	2569	* \code
MACRUM	0:615f90842ce8	2570	* Default value: 0x48
MACRUM	0:615f90842ce8	2571	* Read Write
MACRUM	0:615f90842ce8	2572	*
MACRUM	0:615f90842ce8	2573	* 7 Reserved.
MACRUM	0:615f90842ce8	2574	*
MACRUM	0:615f90842ce8	2575	* 6:0 VCO_CALIBR_RX[6:0]: Word value for the VCO to be used in RX mode
MACRUM	0:615f90842ce8	2576	* \endcode
MACRUM	0:615f90842ce8	2577	*/
MACRUM	0:615f90842ce8	2578	#define RCO_VCO_CALIBR_IN0_BASE ((uint8_t)0x6F) /!< Word value for the VCO to be used in RX mode [6:0] /
MACRUM	0:615f90842ce8	2579
MACRUM	0:615f90842ce8	2580	/**
MACRUM	0:615f90842ce8	2581	* @}
MACRUM	0:615f90842ce8	2582	*/
MACRUM	0:615f90842ce8	2583
MACRUM	0:615f90842ce8	2584	/** @defgroup RCO_VCO_CALIBR_OUT1_Register
MACRUM	0:615f90842ce8	2585	* @{
MACRUM	0:615f90842ce8	2586	*/
MACRUM	0:615f90842ce8	2587
MACRUM	0:615f90842ce8	2588	/**
MACRUM	0:615f90842ce8	2589	* \brief RCO_VCO_CALIBR_OUT1 registers
MACRUM	0:615f90842ce8	2590	* \code
MACRUM	0:615f90842ce8	2591	* Default value: 0x00
MACRUM	0:615f90842ce8	2592	* Read
MACRUM	0:615f90842ce8	2593	*
MACRUM	0:615f90842ce8	2594	* 7:4 RWT_OUT[3:0]: RWT word from internal RCO calibrator
MACRUM	0:615f90842ce8	2595	*
MACRUM	0:615f90842ce8	2596	* 3:0 RFB_OUT[4:1]: RFB word from internal RCO calibrator (upper part)
MACRUM	0:615f90842ce8	2597	* \endcode
MACRUM	0:615f90842ce8	2598	*/
MACRUM	0:615f90842ce8	2599	#define RCO_VCO_CALIBR_OUT1_BASE ((uint8_t)(0xE4)) /*!< RaWThermometric RWT word from internal RCO calibrator [7];
MACRUM	0:615f90842ce8	2600	ResistorFineBit RFB word from internal RCO oscillator [6:0] */
MACRUM	0:615f90842ce8	2601	/**
MACRUM	0:615f90842ce8	2602	* @}
MACRUM	0:615f90842ce8	2603	*/
MACRUM	0:615f90842ce8	2604
MACRUM	0:615f90842ce8	2605	/** @defgroup RCO_VCO_CALIBR_OUT0_Register
MACRUM	0:615f90842ce8	2606	* @{
MACRUM	0:615f90842ce8	2607	*/
MACRUM	0:615f90842ce8	2608
MACRUM	0:615f90842ce8	2609	/**
MACRUM	0:615f90842ce8	2610	* \brief RCO_VCO_CALIBR_OUT0 registers
MACRUM	0:615f90842ce8	2611	* \code
MACRUM	0:615f90842ce8	2612	* Default value: 0x00
MACRUM	0:615f90842ce8	2613	* Read
MACRUM	0:615f90842ce8	2614	*
MACRUM	0:615f90842ce8	2615	* 7 RFB_OUT[0]: RFB word from internal RCO calibrator (last bit LSB)
MACRUM	0:615f90842ce8	2616	*
MACRUM	0:615f90842ce8	2617	* 6:0 VCO_CALIBR_DATA[6:0]: Output word from internal VCO calibrator
MACRUM	0:615f90842ce8	2618	* \endcode
MACRUM	0:615f90842ce8	2619	*/
MACRUM	0:615f90842ce8	2620	#define RCO_VCO_CALIBR_OUT0_BASE ((uint8_t)(0xE5)) /*!< ResistorFineBit RFB word from internal RCO oscillator [0];
MACRUM	0:615f90842ce8	2621	Output word from internal calibrator [6:0]; */
MACRUM	0:615f90842ce8	2622	/**
MACRUM	0:615f90842ce8	2623	* @}
MACRUM	0:615f90842ce8	2624	*/
MACRUM	0:615f90842ce8	2625
MACRUM	0:615f90842ce8	2626	/**
MACRUM	0:615f90842ce8	2627	* @}
MACRUM	0:615f90842ce8	2628	*/
MACRUM	0:615f90842ce8	2629
MACRUM	0:615f90842ce8	2630
MACRUM	0:615f90842ce8	2631	/** @defgroup AES_Registers
MACRUM	0:615f90842ce8	2632	* @{
MACRUM	0:615f90842ce8	2633	*/
MACRUM	0:615f90842ce8	2634
MACRUM	0:615f90842ce8	2635	/** @defgroup AES_KEY_IN_Register
MACRUM	0:615f90842ce8	2636	* @{
MACRUM	0:615f90842ce8	2637	*/
MACRUM	0:615f90842ce8	2638
MACRUM	0:615f90842ce8	2639	/**
MACRUM	0:615f90842ce8	2640	* \brief AES_KEY_INx registers
MACRUM	0:615f90842ce8	2641	* \code
MACRUM	0:615f90842ce8	2642	* Default value: 0x00
MACRUM	0:615f90842ce8	2643	* Read Write
MACRUM	0:615f90842ce8	2644	*
MACRUM	0:615f90842ce8	2645	* 7:0 AES_KEY_INx[7:0]: AES engine key input (total - 128 bits)
MACRUM	0:615f90842ce8	2646	* \endcode
MACRUM	0:615f90842ce8	2647	*/
MACRUM	0:615f90842ce8	2648	#define AES_KEY_IN_15_BASE ((uint8_t)0x70) /!< AES engine key input 15 /
MACRUM	0:615f90842ce8	2649
MACRUM	0:615f90842ce8	2650	#define AES_KEY_IN_14_BASE ((uint8_t)0x71) /!< AES engine key input 14 /
MACRUM	0:615f90842ce8	2651
MACRUM	0:615f90842ce8	2652	#define AES_KEY_IN_13_BASE ((uint8_t)0x72) /!< AES engine key input 13 /
MACRUM	0:615f90842ce8	2653
MACRUM	0:615f90842ce8	2654	#define AES_KEY_IN_12_BASE ((uint8_t)0x73) /!< AES engine key input 12 /
MACRUM	0:615f90842ce8	2655
MACRUM	0:615f90842ce8	2656	#define AES_KEY_IN_11_BASE ((uint8_t)0x74) /!< AES engine key input 11 /
MACRUM	0:615f90842ce8	2657
MACRUM	0:615f90842ce8	2658	#define AES_KEY_IN_10_BASE ((uint8_t)0x75) /!< AES engine key input 10 /
MACRUM	0:615f90842ce8	2659
MACRUM	0:615f90842ce8	2660	#define AES_KEY_IN_9_BASE ((uint8_t)0x76) /!< AES engine key input 9 /
MACRUM	0:615f90842ce8	2661
MACRUM	0:615f90842ce8	2662	#define AES_KEY_IN_8_BASE ((uint8_t)0x77) /!< AES engine key input 8 /
MACRUM	0:615f90842ce8	2663
MACRUM	0:615f90842ce8	2664	#define AES_KEY_IN_7_BASE ((uint8_t)0x78) /!< AES engine key input 7 /
MACRUM	0:615f90842ce8	2665
MACRUM	0:615f90842ce8	2666	#define AES_KEY_IN_6_BASE ((uint8_t)0x79) /!< AES engine key input 6 /
MACRUM	0:615f90842ce8	2667
MACRUM	0:615f90842ce8	2668	#define AES_KEY_IN_5_BASE ((uint8_t)0x7A) /!< AES engine key input 5 /
MACRUM	0:615f90842ce8	2669
MACRUM	0:615f90842ce8	2670	#define AES_KEY_IN_4_BASE ((uint8_t)0x7B) /!< AES engine key input 4 /
MACRUM	0:615f90842ce8	2671
MACRUM	0:615f90842ce8	2672	#define AES_KEY_IN_3_BASE ((uint8_t)0x7C) /!< AES engine key input 3 /
MACRUM	0:615f90842ce8	2673
MACRUM	0:615f90842ce8	2674	#define AES_KEY_IN_2_BASE ((uint8_t)0x7D) /!< AES engine key input 2 /
MACRUM	0:615f90842ce8	2675
MACRUM	0:615f90842ce8	2676	#define AES_KEY_IN_1_BASE ((uint8_t)0x7E) /!< AES engine key input 1 /
MACRUM	0:615f90842ce8	2677
MACRUM	0:615f90842ce8	2678	#define AES_KEY_IN_0_BASE ((uint8_t)0x7F) /!< AES engine key input 0 /
MACRUM	0:615f90842ce8	2679
MACRUM	0:615f90842ce8	2680	/**
MACRUM	0:615f90842ce8	2681	* @}
MACRUM	0:615f90842ce8	2682	*/
MACRUM	0:615f90842ce8	2683
MACRUM	0:615f90842ce8	2684	/** @defgroup AES_DATA_IN_Register
MACRUM	0:615f90842ce8	2685	* @{
MACRUM	0:615f90842ce8	2686	*/
MACRUM	0:615f90842ce8	2687
MACRUM	0:615f90842ce8	2688	/**
MACRUM	0:615f90842ce8	2689	* \brief AES_DATA_INx registers
MACRUM	0:615f90842ce8	2690	* \code
MACRUM	0:615f90842ce8	2691	* Default value: 0x00
MACRUM	0:615f90842ce8	2692	* Read Write
MACRUM	0:615f90842ce8	2693	*
MACRUM	0:615f90842ce8	2694	* 7:0 AES_DATA_INx[7:0]: AES engine data input (total - 128 bits)
MACRUM	0:615f90842ce8	2695	* \endcode
MACRUM	0:615f90842ce8	2696	*/
MACRUM	0:615f90842ce8	2697	#define AES_DATA_IN_15_BASE ((uint8_t)0x80) /*!< AES engine data input 15
MACRUM	0:615f90842ce8	2698	Take care: Address is in reverse order respect data numbering; eg.: 0x81 -> AES_data14[7:0] */
MACRUM	0:615f90842ce8	2699	#define AES_DATA_IN_14_BASE ((uint8_t)0x81) /!< AES engine data input 14 /
MACRUM	0:615f90842ce8	2700
MACRUM	0:615f90842ce8	2701	#define AES_DATA_IN_13_BASE ((uint8_t)0x82) /!< AES engine data input 13 /
MACRUM	0:615f90842ce8	2702
MACRUM	0:615f90842ce8	2703	#define AES_DATA_IN_12_BASE ((uint8_t)0x83) /!< AES engine data input 12 /
MACRUM	0:615f90842ce8	2704
MACRUM	0:615f90842ce8	2705	#define AES_DATA_IN_11_BASE ((uint8_t)0x84) /!< AES engine data input 11 /
MACRUM	0:615f90842ce8	2706
MACRUM	0:615f90842ce8	2707	#define AES_DATA_IN_10_BASE ((uint8_t)0x85) /!< AES engine data input 10 /
MACRUM	0:615f90842ce8	2708
MACRUM	0:615f90842ce8	2709	#define AES_DATA_IN_9_BASE ((uint8_t)0x86) /!< AES engine data input 9 /
MACRUM	0:615f90842ce8	2710
MACRUM	0:615f90842ce8	2711	#define AES_DATA_IN_8_BASE ((uint8_t)0x87) /!< AES engine data input 8 /
MACRUM	0:615f90842ce8	2712
MACRUM	0:615f90842ce8	2713	#define AES_DATA_IN_7_BASE ((uint8_t)0x88) /!< AES engine data input 7 /
MACRUM	0:615f90842ce8	2714
MACRUM	0:615f90842ce8	2715	#define AES_DATA_IN_6_BASE ((uint8_t)0x89) /!< AES engine data input 6 /
MACRUM	0:615f90842ce8	2716
MACRUM	0:615f90842ce8	2717	#define AES_DATA_IN_5_BASE ((uint8_t)0x8A) /!< AES engine data input 5 /
MACRUM	0:615f90842ce8	2718
MACRUM	0:615f90842ce8	2719	#define AES_DATA_IN_4_BASE ((uint8_t)0x8B) /!< AES engine data input 4 /
MACRUM	0:615f90842ce8	2720
MACRUM	0:615f90842ce8	2721	#define AES_DATA_IN_3_BASE ((uint8_t)0x8C) /!< AES engine data input 3 /
MACRUM	0:615f90842ce8	2722
MACRUM	0:615f90842ce8	2723	#define AES_DATA_IN_2_BASE ((uint8_t)0x8D) /!< AES engine data input 2 /
MACRUM	0:615f90842ce8	2724
MACRUM	0:615f90842ce8	2725	#define AES_DATA_IN_1_BASE ((uint8_t)0x8E) /!< AES engine data input 1 /
MACRUM	0:615f90842ce8	2726
MACRUM	0:615f90842ce8	2727	#define AES_DATA_IN_0_BASE ((uint8_t)0x8F) /!< AES engine data input 0 /
MACRUM	0:615f90842ce8	2728
MACRUM	0:615f90842ce8	2729	/**
MACRUM	0:615f90842ce8	2730	* @}
MACRUM	0:615f90842ce8	2731	*/
MACRUM	0:615f90842ce8	2732
MACRUM	0:615f90842ce8	2733	/** @defgroup AES_DATA_OUT_Register
MACRUM	0:615f90842ce8	2734	* @{
MACRUM	0:615f90842ce8	2735	*/
MACRUM	0:615f90842ce8	2736
MACRUM	0:615f90842ce8	2737	/**
MACRUM	0:615f90842ce8	2738	* \brief AES_DATA_OUT[15:0] registers
MACRUM	0:615f90842ce8	2739	* \code
MACRUM	0:615f90842ce8	2740	* Default value: 0x00
MACRUM	0:615f90842ce8	2741	* Read
MACRUM	0:615f90842ce8	2742	*
MACRUM	0:615f90842ce8	2743	* 7:0 AES_DATA_OUTx[7:0]: AES engine data output (128 bits)
MACRUM	0:615f90842ce8	2744	* \endcode
MACRUM	0:615f90842ce8	2745	*/
MACRUM	0:615f90842ce8	2746	#define AES_DATA_OUT_15_BASE ((uint8_t)(0xD4)) /!< AES engine data output 15 /
MACRUM	0:615f90842ce8	2747
MACRUM	0:615f90842ce8	2748	#define AES_DATA_OUT_14_BASE ((uint8_t)(0xD5)) /!< AES engine data output 14 /
MACRUM	0:615f90842ce8	2749
MACRUM	0:615f90842ce8	2750	#define AES_DATA_OUT_13_BASE ((uint8_t)(0xD6)) /!< AES engine data output 13 /
MACRUM	0:615f90842ce8	2751
MACRUM	0:615f90842ce8	2752	#define AES_DATA_OUT_12_BASE ((uint8_t)(0xD7)) /!< AES engine data output 12 /
MACRUM	0:615f90842ce8	2753
MACRUM	0:615f90842ce8	2754	#define AES_DATA_OUT_11_BASE ((uint8_t)(0xD8)) /!< AES engine data output 11 /
MACRUM	0:615f90842ce8	2755
MACRUM	0:615f90842ce8	2756	#define AES_DATA_OUT_10_BASE ((uint8_t)(0xD9)) /!< AES engine data output 10 /
MACRUM	0:615f90842ce8	2757
MACRUM	0:615f90842ce8	2758	#define AES_DATA_OUT_9_BASE ((uint8_t)(0xDA)) /!< AES engine data output 9 /
MACRUM	0:615f90842ce8	2759
MACRUM	0:615f90842ce8	2760	#define AES_DATA_OUT_8_BASE ((uint8_t)(0xDB)) /!< AES engine data output 8 /
MACRUM	0:615f90842ce8	2761
MACRUM	0:615f90842ce8	2762	#define AES_DATA_OUT_7_BASE ((uint8_t)(0xDC)) /!< AES engine data output 7 /
MACRUM	0:615f90842ce8	2763
MACRUM	0:615f90842ce8	2764	#define AES_DATA_OUT_6_BASE ((uint8_t)(0xDD)) /!< AES engine data output 6 /
MACRUM	0:615f90842ce8	2765
MACRUM	0:615f90842ce8	2766	#define AES_DATA_OUT_5_BASE ((uint8_t)(0xDE)) /!< AES engine data output 5 /
MACRUM	0:615f90842ce8	2767
MACRUM	0:615f90842ce8	2768	#define AES_DATA_OUT_4_BASE ((uint8_t)(0xDF)) /!< AES engine data output 4 /
MACRUM	0:615f90842ce8	2769
MACRUM	0:615f90842ce8	2770	#define AES_DATA_OUT_3_BASE ((uint8_t)(0xE0)) /!< AES engine data output 3 /
MACRUM	0:615f90842ce8	2771
MACRUM	0:615f90842ce8	2772	#define AES_DATA_OUT_2_BASE ((uint8_t)(0xE1)) /!< AES engine data output 2 /
MACRUM	0:615f90842ce8	2773
MACRUM	0:615f90842ce8	2774	#define AES_DATA_OUT_1_BASE ((uint8_t)(0xE2)) /!< AES engine data output 1 /
MACRUM	0:615f90842ce8	2775
MACRUM	0:615f90842ce8	2776	#define AES_DATA_OUT_0_BASE ((uint8_t)(0xE3)) /!< AES engine data output 0 /
MACRUM	0:615f90842ce8	2777
MACRUM	0:615f90842ce8	2778	/**
MACRUM	0:615f90842ce8	2779	* @}
MACRUM	0:615f90842ce8	2780	*/
MACRUM	0:615f90842ce8	2781
MACRUM	0:615f90842ce8	2782	/**
MACRUM	0:615f90842ce8	2783	* @}
MACRUM	0:615f90842ce8	2784	*/
MACRUM	0:615f90842ce8	2785
MACRUM	0:615f90842ce8	2786	/** @defgroup IRQ_Registers
MACRUM	0:615f90842ce8	2787	* @{
MACRUM	0:615f90842ce8	2788	*/
MACRUM	0:615f90842ce8	2789
MACRUM	0:615f90842ce8	2790	/** @defgroup IRQ_MASK0_Register
MACRUM	0:615f90842ce8	2791	* @{
MACRUM	0:615f90842ce8	2792	*/
MACRUM	0:615f90842ce8	2793
MACRUM	0:615f90842ce8	2794	/**
MACRUM	0:615f90842ce8	2795	* \brief IRQ_MASK0 registers
MACRUM	0:615f90842ce8	2796	* \code
MACRUM	0:615f90842ce8	2797	* Default value: 0x00
MACRUM	0:615f90842ce8	2798	* Read Write
MACRUM	0:615f90842ce8	2799	*
MACRUM	0:615f90842ce8	2800	* 7:0 INT_MASK0: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
MACRUM	0:615f90842ce8	2801	*
MACRUM	0:615f90842ce8	2802	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	2803	* -------------------------------------------------------
MACRUM	0:615f90842ce8	2804	* 0 \| RX data ready
MACRUM	0:615f90842ce8	2805	* 1 \| RX data discarded (upon filtering)
MACRUM	0:615f90842ce8	2806	* 2 \| TX data sent
MACRUM	0:615f90842ce8	2807	* 3 \| Max re-TX reached
MACRUM	0:615f90842ce8	2808	* 4 \| CRC error
MACRUM	0:615f90842ce8	2809	* 5 \| TX FIFO underflow/overflow error
MACRUM	0:615f90842ce8	2810	* 6 \| RX FIFO underflow/overflow error
MACRUM	0:615f90842ce8	2811	* 7 \| TX FIFO almost full
MACRUM	0:615f90842ce8	2812	* \endcode
MACRUM	0:615f90842ce8	2813	*/
MACRUM	0:615f90842ce8	2814
MACRUM	0:615f90842ce8	2815
MACRUM	0:615f90842ce8	2816	#define IRQ_MASK0_BASE ((uint8_t)0x93) /!< IRQ_MASK is split into 4 registers/
MACRUM	0:615f90842ce8	2817
MACRUM	0:615f90842ce8	2818	#define IRQ_MASK0_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
MACRUM	0:615f90842ce8	2819	#define IRQ_MASK0_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
MACRUM	0:615f90842ce8	2820	#define IRQ_MASK0_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
MACRUM	0:615f90842ce8	2821	#define IRQ_MASK0_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
MACRUM	0:615f90842ce8	2822	#define IRQ_MASK0_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
MACRUM	0:615f90842ce8	2823	#define IRQ_MASK0_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
MACRUM	0:615f90842ce8	2824	#define IRQ_MASK0_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
MACRUM	0:615f90842ce8	2825	#define IRQ_MASK0_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
MACRUM	0:615f90842ce8	2826
MACRUM	0:615f90842ce8	2827	/**
MACRUM	0:615f90842ce8	2828	* @}
MACRUM	0:615f90842ce8	2829	*/
MACRUM	0:615f90842ce8	2830
MACRUM	0:615f90842ce8	2831	/** @defgroup IRQ_MASK1_Register
MACRUM	0:615f90842ce8	2832	* @{
MACRUM	0:615f90842ce8	2833	*/
MACRUM	0:615f90842ce8	2834
MACRUM	0:615f90842ce8	2835	/**
MACRUM	0:615f90842ce8	2836	* \brief IRQ_MASK1 registers
MACRUM	0:615f90842ce8	2837	* \code
MACRUM	0:615f90842ce8	2838	* Default value: 0x00
MACRUM	0:615f90842ce8	2839	* Read Write
MACRUM	0:615f90842ce8	2840	*
MACRUM	0:615f90842ce8	2841	* 7:0 INT_MASK1: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
MACRUM	0:615f90842ce8	2842	*
MACRUM	0:615f90842ce8	2843	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	2844	* -------------------------------------------------------
MACRUM	0:615f90842ce8	2845	* 8 \| TX FIFO almost empty
MACRUM	0:615f90842ce8	2846	* 9 \| RX FIFO almost full
MACRUM	0:615f90842ce8	2847	* 10 \| RX FIFO almost empty
MACRUM	0:615f90842ce8	2848	* 11 \| Max number of back-off during CCA
MACRUM	0:615f90842ce8	2849	* 12 \| Valid preamble detected
MACRUM	0:615f90842ce8	2850	* 13 \| Sync word detected
MACRUM	0:615f90842ce8	2851	* 14 \| RSSI above threshold (Carrier Sense)
MACRUM	0:615f90842ce8	2852	* 15 \| Wake-up timeout in LDCR mode13
MACRUM	0:615f90842ce8	2853	* \endcode
MACRUM	0:615f90842ce8	2854	*/
MACRUM	0:615f90842ce8	2855
MACRUM	0:615f90842ce8	2856	#define IRQ_MASK1_BASE ((uint8_t)0x92) /!< IRQ_MASK is split into 4 registers/
MACRUM	0:615f90842ce8	2857
MACRUM	0:615f90842ce8	2858	#define IRQ_MASK1_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
MACRUM	0:615f90842ce8	2859	#define IRQ_MASK1_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
MACRUM	0:615f90842ce8	2860	#define IRQ_MASK1_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
MACRUM	0:615f90842ce8	2861	#define IRQ_MASK1_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
MACRUM	0:615f90842ce8	2862	#define IRQ_MASK1_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
MACRUM	0:615f90842ce8	2863	#define IRQ_MASK1_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
MACRUM	0:615f90842ce8	2864	#define IRQ_MASK1_RSSI_ABOVE_TH ((uint8_t)0x40) /!< IRQ: RSSI above threshold /
MACRUM	0:615f90842ce8	2865	#define IRQ_MASK1_WKUP_TOUT_LDC ((uint8_t)0x80) /!< IRQ: Wake-up timeout in LDC mode /
MACRUM	0:615f90842ce8	2866
MACRUM	0:615f90842ce8	2867	/**
MACRUM	0:615f90842ce8	2868	* @}
MACRUM	0:615f90842ce8	2869	*/
MACRUM	0:615f90842ce8	2870
MACRUM	0:615f90842ce8	2871	/** @defgroup IRQ_MASK2_Register
MACRUM	0:615f90842ce8	2872	* @{
MACRUM	0:615f90842ce8	2873	*/
MACRUM	0:615f90842ce8	2874
MACRUM	0:615f90842ce8	2875	/**
MACRUM	0:615f90842ce8	2876	* \brief IRQ_MASK2 registers
MACRUM	0:615f90842ce8	2877	* \code
MACRUM	0:615f90842ce8	2878	* Default value: 0x00
MACRUM	0:615f90842ce8	2879	* Read Write
MACRUM	0:615f90842ce8	2880	*
MACRUM	0:615f90842ce8	2881	* 7:0 INT_MASK2: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
MACRUM	0:615f90842ce8	2882	*
MACRUM	0:615f90842ce8	2883	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	2884	* -------------------------------------------------------
MACRUM	0:615f90842ce8	2885	* 16 \| READY state in steady condition14
MACRUM	0:615f90842ce8	2886	* 17 \| STANDBY state switching in progress
MACRUM	0:615f90842ce8	2887	* 18 \| Low battery level
MACRUM	0:615f90842ce8	2888	* 19 \| Power-On reset
MACRUM	0:615f90842ce8	2889	* 20 \| Brown-Out event
MACRUM	0:615f90842ce8	2890	* 21 \| LOCK state in steady condition
MACRUM	0:615f90842ce8	2891	* 22 \| PM start-up timer expiration
MACRUM	0:615f90842ce8	2892	* 23 \| XO settling timeout
MACRUM	0:615f90842ce8	2893	* \endcode
MACRUM	0:615f90842ce8	2894	*/
MACRUM	0:615f90842ce8	2895	#define IRQ_MASK2_BASE ((uint8_t)0x91) /!< IRQ_MASK is split into 4 registers/
MACRUM	0:615f90842ce8	2896
MACRUM	0:615f90842ce8	2897	#define IRQ_MASK2_READY ((uint8_t)0x01) /!< IRQ: READY state /
MACRUM	0:615f90842ce8	2898	#define IRQ_MASK2_STANDBY_DELAYED ((uint8_t)0x02) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
MACRUM	0:615f90842ce8	2899	#define IRQ_MASK2_LOW_BATT_LVL ((uint8_t)0x04) /!< IRQ: Battery level below threshold/
MACRUM	0:615f90842ce8	2900	#define IRQ_MASK2_POR ((uint8_t)0x08) /!< IRQ: Power On Reset /
MACRUM	0:615f90842ce8	2901	#define IRQ_MASK2_BOR ((uint8_t)0x10) /!< IRQ: Brown out event (both accurate and inaccurate)/
MACRUM	0:615f90842ce8	2902	#define IRQ_MASK2_LOCK ((uint8_t)0x20) /!< IRQ: LOCK state /
MACRUM	0:615f90842ce8	2903	#define IRQ_MASK2_PM_COUNT_EXPIRED ((uint8_t)0x40) /!< IRQ: only for debug; Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
MACRUM	0:615f90842ce8	2904	#define IRQ_MASK2_XO_COUNT_EXPIRED ((uint8_t)0x80) /!< IRQ: only for debug; Crystal oscillator settling time counter expired /
MACRUM	0:615f90842ce8	2905
MACRUM	0:615f90842ce8	2906	/**
MACRUM	0:615f90842ce8	2907	* @}
MACRUM	0:615f90842ce8	2908	*/
MACRUM	0:615f90842ce8	2909
MACRUM	0:615f90842ce8	2910	/** @defgroup IRQ_MASK3_Register
MACRUM	0:615f90842ce8	2911	* @{
MACRUM	0:615f90842ce8	2912	*/
MACRUM	0:615f90842ce8	2913
MACRUM	0:615f90842ce8	2914	/**
MACRUM	0:615f90842ce8	2915	* \brief IRQ_MASK3 registers
MACRUM	0:615f90842ce8	2916	* \code
MACRUM	0:615f90842ce8	2917	* Default value: 0x00
MACRUM	0:615f90842ce8	2918	* Read Write
MACRUM	0:615f90842ce8	2919	*
MACRUM	0:615f90842ce8	2920	* 7:0 INT_MASK3: IRQ mask, if the correspondent bit is set and IRQ can be generated (according to the next table)
MACRUM	0:615f90842ce8	2921	*
MACRUM	0:615f90842ce8	2922	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	2923	* -------------------------------------------------------
MACRUM	0:615f90842ce8	2924	* 24 \| SYNTH locking timeout
MACRUM	0:615f90842ce8	2925	* 25 \| SYNTH calibration start-up time
MACRUM	0:615f90842ce8	2926	* 26 \| SYNTH calibration timeout
MACRUM	0:615f90842ce8	2927	* 27 \| TX circuitry start-up time
MACRUM	0:615f90842ce8	2928	* 28 \| RX circuitry start-up time
MACRUM	0:615f90842ce8	2929	* 29 \| RX operation timeout
MACRUM	0:615f90842ce8	2930	* 30 \| Others AES Endof Operation
MACRUM	0:615f90842ce8	2931	* 31 \| Reserved
MACRUM	0:615f90842ce8	2932	* \endcode
MACRUM	0:615f90842ce8	2933	*/
MACRUM	0:615f90842ce8	2934	#define IRQ_MASK3_BASE ((uint8_t)0x90) /!< IRQ_MASK is split into 4 registers/
MACRUM	0:615f90842ce8	2935
MACRUM	0:615f90842ce8	2936	#define IRQ_MASK3_SYNTH_LOCK_TIMEOUT ((uint8_t)0x01) /!< IRQ: only for debug; LOCK state timeout /
MACRUM	0:615f90842ce8	2937	#define IRQ_MASK3_SYNTH_LOCK_STARTUP ((uint8_t)0x02) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
MACRUM	0:615f90842ce8	2938	#define IRQ_MASK3_SYNTH_CAL_TIMEOUT ((uint8_t)0x04) /!< IRQ: only for debug; SYNTH calibration timeout /
MACRUM	0:615f90842ce8	2939	#define IRQ_MASK3_TX_START_TIME ((uint8_t)0x08) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
MACRUM	0:615f90842ce8	2940	#define IRQ_MASK3_RX_START_TIME ((uint8_t)0x10) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
MACRUM	0:615f90842ce8	2941	#define IRQ_MASK3_RX_TIMEOUT ((uint8_t)0x20) /!< IRQ: RX operation timeout /
MACRUM	0:615f90842ce8	2942	#define IRQ_MASK3_AES_END ((uint8_t)0x40) /!< IRQ: AES End of operation /
MACRUM	0:615f90842ce8	2943
MACRUM	0:615f90842ce8	2944	/**
MACRUM	0:615f90842ce8	2945	* @}
MACRUM	0:615f90842ce8	2946	*/
MACRUM	0:615f90842ce8	2947
MACRUM	0:615f90842ce8	2948
MACRUM	0:615f90842ce8	2949	/** @defgroup IRQ_STATUS0_Register
MACRUM	0:615f90842ce8	2950	* @{
MACRUM	0:615f90842ce8	2951	*/
MACRUM	0:615f90842ce8	2952
MACRUM	0:615f90842ce8	2953	/**
MACRUM	0:615f90842ce8	2954	* \brief IRQ_STATUS0 registers
MACRUM	0:615f90842ce8	2955	* \code
MACRUM	0:615f90842ce8	2956	* Default value: 0x00
MACRUM	0:615f90842ce8	2957	* Read Write
MACRUM	0:615f90842ce8	2958	*
MACRUM	0:615f90842ce8	2959	* 7:0 INT_STATUS0: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
MACRUM	0:615f90842ce8	2960	*
MACRUM	0:615f90842ce8	2961	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	2962	* -------------------------------------------------------
MACRUM	0:615f90842ce8	2963	* 0 \| RX data ready
MACRUM	0:615f90842ce8	2964	* 1 \| RX data discarded (upon filtering)
MACRUM	0:615f90842ce8	2965	* 2 \| TX data sent
MACRUM	0:615f90842ce8	2966	* 3 \| Max re-TX reached
MACRUM	0:615f90842ce8	2967	* 4 \| CRC error
MACRUM	0:615f90842ce8	2968	* 5 \| TX FIFO underflow/overflow error
MACRUM	0:615f90842ce8	2969	* 6 \| RX FIFO underflow/overflow error
MACRUM	0:615f90842ce8	2970	* 7 \| TX FIFO almost full
MACRUM	0:615f90842ce8	2971	* \endcode
MACRUM	0:615f90842ce8	2972	*/
MACRUM	0:615f90842ce8	2973
MACRUM	0:615f90842ce8	2974	#define IRQ_STATUS0_BASE ((uint8_t)(0xFD)) /!< IRQ Events(RR, split into 4 registers) /
MACRUM	0:615f90842ce8	2975
MACRUM	0:615f90842ce8	2976	#define IRQ_STATUS0_SYNTH_LOCK_TIMEOUT ((uint8_t)(0x01)) /!< IRQ: LOCK state timeout /
MACRUM	0:615f90842ce8	2977	#define IRQ_STATUS0_SYNTH_LOCK_STARTUP ((uint8_t)(0x02)) /!< IRQ: only for debug; see CALIBR_START_COUNTER /
MACRUM	0:615f90842ce8	2978	#define IRQ_STATUS0_SYNTH_CAL_TIMEOUT ((uint8_t)(0x04)) /!< IRQ: SYNTH locking timeout /
MACRUM	0:615f90842ce8	2979	#define IRQ_STATUS0_TX_START_TIME ((uint8_t)(0x08)) /!< IRQ: only for debug; TX circuitry startup time; see TX_START_COUNTER /
MACRUM	0:615f90842ce8	2980	#define IRQ_STATUS0_RX_START_TIME ((uint8_t)(0x10)) /!< IRQ: only for debug; RX circuitry startup time; see TX_START_COUNTER /
MACRUM	0:615f90842ce8	2981	#define IRQ_STATUS0_RX_TIMEOUT ((uint8_t)(0x20)) /!< IRQ: RX operation timeout expiration /
MACRUM	0:615f90842ce8	2982	#define IRQ_STATUS0_AES_END ((uint8_t)(0x40)) /!< IRQ: AES End of operation /
MACRUM	0:615f90842ce8	2983
MACRUM	0:615f90842ce8	2984	/**
MACRUM	0:615f90842ce8	2985	* @}
MACRUM	0:615f90842ce8	2986	*/
MACRUM	0:615f90842ce8	2987
MACRUM	0:615f90842ce8	2988	/** @defgroup IRQ_STATUS1_Register
MACRUM	0:615f90842ce8	2989	* @{
MACRUM	0:615f90842ce8	2990	*/
MACRUM	0:615f90842ce8	2991
MACRUM	0:615f90842ce8	2992	/**
MACRUM	0:615f90842ce8	2993	* \brief IRQ_STATUS1 registers
MACRUM	0:615f90842ce8	2994	* \code
MACRUM	0:615f90842ce8	2995	* Default value: 0x00
MACRUM	0:615f90842ce8	2996	* Read Write
MACRUM	0:615f90842ce8	2997	*
MACRUM	0:615f90842ce8	2998	* 7:0 INT_STATUS1: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
MACRUM	0:615f90842ce8	2999	*
MACRUM	0:615f90842ce8	3000	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	3001	* -------------------------------------------------------
MACRUM	0:615f90842ce8	3002	* 8 \| TX FIFO almost empty
MACRUM	0:615f90842ce8	3003	* 9 \| RX FIFO almost full
MACRUM	0:615f90842ce8	3004	* 10 \| RX FIFO almost empty
MACRUM	0:615f90842ce8	3005	* 11 \| Max number of back-off during CCA
MACRUM	0:615f90842ce8	3006	* 12 \| Valid preamble detected
MACRUM	0:615f90842ce8	3007	* 13 \| Sync word detected
MACRUM	0:615f90842ce8	3008	* 14 \| RSSI above threshold (Carrier Sense)
MACRUM	0:615f90842ce8	3009	* 15 \| Wake-up timeout in LDCR mode13
MACRUM	0:615f90842ce8	3010	* \endcode
MACRUM	0:615f90842ce8	3011	*/
MACRUM	0:615f90842ce8	3012
MACRUM	0:615f90842ce8	3013	#define IRQ_STATUS1_BASE ((uint8_t)(0xFC)) /!< IRQ Events(RR, split into 4 registers) /
MACRUM	0:615f90842ce8	3014
MACRUM	0:615f90842ce8	3015	#define IRQ_STATUS1_READY ((uint8_t)(0x01)) /!< IRQ: READY state in steady condition/
MACRUM	0:615f90842ce8	3016	#define IRQ_STATUS1_STANDBY_DELAYED ((uint8_t)(0x02)) /!< IRQ: STANDBY state after MCU_CK_CONF_CLOCK_TAIL_X clock cycles /
MACRUM	0:615f90842ce8	3017	#define IRQ_STATUS1_LOW_BATT_LVL ((uint8_t)(0x04)) /!< IRQ: Battery level below threshold/
MACRUM	0:615f90842ce8	3018	#define IRQ_STATUS1_POR ((uint8_t)(0x08)) /!< IRQ: Power On Reset /
MACRUM	0:615f90842ce8	3019	#define IRQ_STATUS1_BOR ((uint8_t)(0x10)) /!< IRQ: Brown out event (both accurate and inaccurate)/
MACRUM	0:615f90842ce8	3020	#define IRQ_STATUS1_LOCK ((uint8_t)(0x20)) /!< IRQ: LOCK state in steady condition /
MACRUM	0:615f90842ce8	3021	#define IRQ_STATUS1_PM_COUNT_EXPIRED ((uint8_t)(0x40)) /!< IRQ: Power Management startup timer expiration (see reg PM_START_COUNTER, 0xB5) /
MACRUM	0:615f90842ce8	3022	#define IRQ_STATUS1_XO_COUNT_EXPIRED ((uint8_t)(0x80)) /!< IRQ: Crystal oscillator settling time counter expired /
MACRUM	0:615f90842ce8	3023
MACRUM	0:615f90842ce8	3024	/**
MACRUM	0:615f90842ce8	3025	* @}
MACRUM	0:615f90842ce8	3026	*/
MACRUM	0:615f90842ce8	3027
MACRUM	0:615f90842ce8	3028	/** @defgroup IRQ_STATUS2_Register
MACRUM	0:615f90842ce8	3029	* @{
MACRUM	0:615f90842ce8	3030	*/
MACRUM	0:615f90842ce8	3031
MACRUM	0:615f90842ce8	3032	/**
MACRUM	0:615f90842ce8	3033	* \brief IRQ_STATUS2 registers
MACRUM	0:615f90842ce8	3034	* \code
MACRUM	0:615f90842ce8	3035	* Default value: 0x00
MACRUM	0:615f90842ce8	3036	* Read Write
MACRUM	0:615f90842ce8	3037	*
MACRUM	0:615f90842ce8	3038	* 7:0 INT_STATUS2: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
MACRUM	0:615f90842ce8	3039	*
MACRUM	0:615f90842ce8	3040	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	3041	* -------------------------------------------------------
MACRUM	0:615f90842ce8	3042	* 16 \| READY state in steady condition14
MACRUM	0:615f90842ce8	3043	* 17 \| STANDBY state switching in progress
MACRUM	0:615f90842ce8	3044	* 18 \| Low battery level
MACRUM	0:615f90842ce8	3045	* 19 \| Power-On reset
MACRUM	0:615f90842ce8	3046	* 20 \| Brown-Out event
MACRUM	0:615f90842ce8	3047	* 21 \| LOCK state in steady condition
MACRUM	0:615f90842ce8	3048	* 22 \| PM start-up timer expiration
MACRUM	0:615f90842ce8	3049	* 23 \| XO settling timeout
MACRUM	0:615f90842ce8	3050	* \endcode
MACRUM	0:615f90842ce8	3051	*/
MACRUM	0:615f90842ce8	3052
MACRUM	0:615f90842ce8	3053	#define IRQ_STATUS2_BASE ((uint8_t)0xFB) /!< IRQ Events(RR, split into 4 registers) /
MACRUM	0:615f90842ce8	3054
MACRUM	0:615f90842ce8	3055	#define IRQ_STATUS2_TX_FIFO_ALMOST_EMPTY ((uint8_t)0x01) /!< IRQ: TX FIFO almost empty /
MACRUM	0:615f90842ce8	3056	#define IRQ_STATUS2_RX_FIFO_ALMOST_FULL ((uint8_t)0x02) /!< IRQ: RX FIFO almost full /
MACRUM	0:615f90842ce8	3057	#define IRQ_STATUS2_RX_FIFO_ALMOST_EMPTY ((uint8_t)0x04) /!< IRQ: RX FIFO almost empty /
MACRUM	0:615f90842ce8	3058	#define IRQ_STATUS2_MAX_BO_CCA_REACH ((uint8_t)0x08) /!< IRQ: Max number of back-off during CCA /
MACRUM	0:615f90842ce8	3059	#define IRQ_STATUS2_VALID_PREAMBLE ((uint8_t)0x10) /!< IRQ: Valid preamble detected /
MACRUM	0:615f90842ce8	3060	#define IRQ_STATUS2_VALID_SYNC ((uint8_t)0x20) /!< IRQ: Sync word detected /
MACRUM	0:615f90842ce8	3061	#define IRQ_STATUS2_RSSI_ABOVE_TH ((uint8_t)(0x40)) /!< IRQ: RSSI above threshold /
MACRUM	0:615f90842ce8	3062	#define IRQ_STATUS2_WKUP_TOUT_LDC ((uint8_t)(0x80)) /!< IRQ: Wake-up timeout in LDC mode /
MACRUM	0:615f90842ce8	3063
MACRUM	0:615f90842ce8	3064	/**
MACRUM	0:615f90842ce8	3065	* @}
MACRUM	0:615f90842ce8	3066	*/
MACRUM	0:615f90842ce8	3067
MACRUM	0:615f90842ce8	3068	/** @defgroup IRQ_STATUS3_Register
MACRUM	0:615f90842ce8	3069	* @{
MACRUM	0:615f90842ce8	3070	*/
MACRUM	0:615f90842ce8	3071
MACRUM	0:615f90842ce8	3072	/**
MACRUM	0:615f90842ce8	3073	* \brief IRQ_STATUS3 registers
MACRUM	0:615f90842ce8	3074	* \code
MACRUM	0:615f90842ce8	3075	* Default value: 0x00
MACRUM	0:615f90842ce8	3076	* Read Write
MACRUM	0:615f90842ce8	3077	*
MACRUM	0:615f90842ce8	3078	* 7:0 INT_STATUS3: IRQ status, if the correspondent bit is set and IRQ has been generated (according to the next table)
MACRUM	0:615f90842ce8	3079	*
MACRUM	0:615f90842ce8	3080	* Bit \| Events Group Interrupt Event
MACRUM	0:615f90842ce8	3081	* -------------------------------------------------------
MACRUM	0:615f90842ce8	3082	* 24 \| SYNTH locking timeout
MACRUM	0:615f90842ce8	3083	* 25 \| SYNTH calibration start-up time
MACRUM	0:615f90842ce8	3084	* 26 \| SYNTH calibration timeout
MACRUM	0:615f90842ce8	3085	* 27 \| TX circuitry start-up time
MACRUM	0:615f90842ce8	3086	* 28 \| RX circuitry start-up time
MACRUM	0:615f90842ce8	3087	* 29 \| RX operation timeout
MACRUM	0:615f90842ce8	3088	* 30 \| Others AES Endof Operation
MACRUM	0:615f90842ce8	3089	* 31 \| Reserved
MACRUM	0:615f90842ce8	3090	* \endcode
MACRUM	0:615f90842ce8	3091	*/
MACRUM	0:615f90842ce8	3092	#define IRQ_STATUS3_BASE ((uint8_t)0xFA) /!< IRQ Events(RR, split into 4 registers) /
MACRUM	0:615f90842ce8	3093
MACRUM	0:615f90842ce8	3094	#define IRQ_STATUS3_RX_DATA_READY ((uint8_t)0x01) /!< IRQ: RX data ready /
MACRUM	0:615f90842ce8	3095	#define IRQ_STATUS3_RX_DATA_DISC ((uint8_t)0x02) /!< IRQ: RX data discarded (upon filtering) /
MACRUM	0:615f90842ce8	3096	#define IRQ_STATUS3_TX_DATA_SENT ((uint8_t)0x04) /!< IRQ: TX data sent /
MACRUM	0:615f90842ce8	3097	#define IRQ_STATUS3_MAX_RE_TX_REACH ((uint8_t)0x08) /!< IRQ: Max re-TX reached /
MACRUM	0:615f90842ce8	3098	#define IRQ_STATUS3_CRC_ERROR ((uint8_t)0x10) /!< IRQ: CRC error /
MACRUM	0:615f90842ce8	3099	#define IRQ_STATUS3_TX_FIFO_ERROR ((uint8_t)0x20) /!< IRQ: TX FIFO underflow/overflow error /
MACRUM	0:615f90842ce8	3100	#define IRQ_STATUS3_RX_FIFO_ERROR ((uint8_t)0x40) /!< IRQ: RX FIFO underflow/overflow error /
MACRUM	0:615f90842ce8	3101	#define IRQ_STATUS3_TX_FIFO_ALMOST_FULL ((uint8_t)0x80) /!< IRQ: TX FIFO almost full /
MACRUM	0:615f90842ce8	3102
MACRUM	0:615f90842ce8	3103	/**
MACRUM	0:615f90842ce8	3104	* @}
MACRUM	0:615f90842ce8	3105	*/
MACRUM	0:615f90842ce8	3106
MACRUM	0:615f90842ce8	3107	/**
MACRUM	0:615f90842ce8	3108	* @}
MACRUM	0:615f90842ce8	3109	*/
MACRUM	0:615f90842ce8	3110
MACRUM	0:615f90842ce8	3111
MACRUM	0:615f90842ce8	3112	/** @defgroup MC_STATE_Registers
MACRUM	0:615f90842ce8	3113	* @{
MACRUM	0:615f90842ce8	3114	*/
MACRUM	0:615f90842ce8	3115
MACRUM	0:615f90842ce8	3116	/** @defgroup MC_STATE1_Register
MACRUM	0:615f90842ce8	3117	* @{
MACRUM	0:615f90842ce8	3118	*/
MACRUM	0:615f90842ce8	3119
MACRUM	0:615f90842ce8	3120	/**
MACRUM	0:615f90842ce8	3121	* \brief MC_STATE1 registers
MACRUM	0:615f90842ce8	3122	* \code
MACRUM	0:615f90842ce8	3123	* Default value: 0x50
MACRUM	0:615f90842ce8	3124	* Read
MACRUM	0:615f90842ce8	3125	*
MACRUM	0:615f90842ce8	3126	* 7:4 Reserved.
MACRUM	0:615f90842ce8	3127	*
MACRUM	0:615f90842ce8	3128	* 3 ANT_SELECT: Currently selected antenna
MACRUM	0:615f90842ce8	3129	*
MACRUM	0:615f90842ce8	3130	* 2 TX_FIFO_Full: 1 - TX FIFO is full
MACRUM	0:615f90842ce8	3131	*
MACRUM	0:615f90842ce8	3132	* 1 RX_FIFO_Empty: 1 - RX FIFO is empty
MACRUM	0:615f90842ce8	3133	*
MACRUM	0:615f90842ce8	3134	* 0 ERROR_LOCK: 1 - RCO calibrator error
MACRUM	0:615f90842ce8	3135	* \endcode
MACRUM	0:615f90842ce8	3136	*/
MACRUM	0:615f90842ce8	3137	#define MC_STATE1_BASE ((uint8_t)(0xC0)) /!< MC_STATE1 register address (see the SpiritStatus struct /
MACRUM	0:615f90842ce8	3138
MACRUM	0:615f90842ce8	3139
MACRUM	0:615f90842ce8	3140	/**
MACRUM	0:615f90842ce8	3141	* @}
MACRUM	0:615f90842ce8	3142	*/
MACRUM	0:615f90842ce8	3143
MACRUM	0:615f90842ce8	3144
MACRUM	0:615f90842ce8	3145	/** @defgroup MC_STATE0_Register
MACRUM	0:615f90842ce8	3146	* @{
MACRUM	0:615f90842ce8	3147	*/
MACRUM	0:615f90842ce8	3148
MACRUM	0:615f90842ce8	3149	/**
MACRUM	0:615f90842ce8	3150	* \brief MC_STATE0 registers
MACRUM	0:615f90842ce8	3151	* \code
MACRUM	0:615f90842ce8	3152	* Default value: 0x00
MACRUM	0:615f90842ce8	3153	* Read
MACRUM	0:615f90842ce8	3154	*
MACRUM	0:615f90842ce8	3155	* 7:1 STATE[6:0]: Current MC state.
MACRUM	0:615f90842ce8	3156	*
MACRUM	0:615f90842ce8	3157	* REGISTER VALUE \| STATE
MACRUM	0:615f90842ce8	3158	* --------------------------------------------
MACRUM	0:615f90842ce8	3159	* 0x40 \| STANDBY
MACRUM	0:615f90842ce8	3160	* 0x36 \| SLEEP
MACRUM	0:615f90842ce8	3161	* 0x03 \| READY
MACRUM	0:615f90842ce8	3162	* 0x3B \| PM setup
MACRUM	0:615f90842ce8	3163	* 0x23 \| XO settling
MACRUM	0:615f90842ce8	3164	* 0x53 \| SYNTH setup
MACRUM	0:615f90842ce8	3165	* 0x1F \| PROTOCOL
MACRUM	0:615f90842ce8	3166	* 0x4F \| SYNTH calibration
MACRUM	0:615f90842ce8	3167	* 0x0F \| LOCK
MACRUM	0:615f90842ce8	3168	* 0x33 \| RX
MACRUM	0:615f90842ce8	3169	* 0x5F \| TX
MACRUM	0:615f90842ce8	3170	*
MACRUM	0:615f90842ce8	3171	* 0 XO_ON: 1 - XO is operating
MACRUM	0:615f90842ce8	3172	* \endcode
MACRUM	0:615f90842ce8	3173	*/
MACRUM	0:615f90842ce8	3174	#define MC_STATE0_BASE ((uint8_t)(0xC1)) /*!< MC_STATE0 register address. In this version ALL existing states have been inserted
MACRUM	0:615f90842ce8	3175	and are still to be verified */
MACRUM	0:615f90842ce8	3176	/**
MACRUM	0:615f90842ce8	3177	* @}
MACRUM	0:615f90842ce8	3178	*/
MACRUM	0:615f90842ce8	3179
MACRUM	0:615f90842ce8	3180	/**
MACRUM	0:615f90842ce8	3181	* @}
MACRUM	0:615f90842ce8	3182	*/
MACRUM	0:615f90842ce8	3183
MACRUM	0:615f90842ce8	3184	/** @defgroup Engineering-Test_Registers
MACRUM	0:615f90842ce8	3185	* @{
MACRUM	0:615f90842ce8	3186	*/
MACRUM	0:615f90842ce8	3187
MACRUM	0:615f90842ce8	3188	#define SYNTH_CONFIG1_BASE ((uint8_t)(0x9E)) /*!< Synthesizier registers: M, A, K data sync on positive/negative clock edges [4],
MACRUM	0:615f90842ce8	3189	Enable Linearization of the charge pump [3], split time 1.75/3.45ns [2], VCO calibration window 16,32,64,128 clock cycles [1:0]*/
MACRUM	0:615f90842ce8	3190	#define SYNTH_CONFIG0_BASE ((uint8_t)(0x9F)) /!< Enable DSM randomizer [7], Window width 1.2-7.5ns (Down-up) of lock detector/
MACRUM	0:615f90842ce8	3191	#define VCOTH_BASE ((uint8_t)(0xA0)) /*!< Controls the threshold frequency between VCO low and VCO high [7:0]
MACRUM	0:615f90842ce8	3192	VCOth frequency=2fXO(96+VCO_TH/16), fmin=4992 MHz, fmax=5820 MHz*/
MACRUM	0:615f90842ce8	3193	#define PM_CONFIG2_BASE ((uint8_t)(0xA4)) /!< Enables high current buffer on Temperature sensor, sets SMPS options /
MACRUM	0:615f90842ce8	3194	#define PM_CONFIG1_BASE ((uint8_t)(0xA5)) /!< Set SMPS options /
MACRUM	0:615f90842ce8	3195	#define PM_CONFIG0_BASE ((uint8_t)(0xA6)) /!< Set SMPS options /
MACRUM	0:615f90842ce8	3196	#define VCO_CONFIG_BASE ((uint8_t)(0xA1)) /!< Set VCO current [5:2]part and [1:0] part /
MACRUM	0:615f90842ce8	3197	#define XO_CONFIG_BASE ((uint8_t)(0xA7)) /!< Clock management options from XO to digital part /
MACRUM	0:615f90842ce8	3198
MACRUM	0:615f90842ce8	3199	#define XO_RCO_TEST_BASE ((uint8_t)(0xB4)) /!< Test of XO and RCO /
MACRUM	0:615f90842ce8	3200
MACRUM	0:615f90842ce8	3201	/**
MACRUM	0:615f90842ce8	3202	* @}
MACRUM	0:615f90842ce8	3203	*/
MACRUM	0:615f90842ce8	3204
MACRUM	0:615f90842ce8	3205
MACRUM	0:615f90842ce8	3206	/** @addtogroup Commands
MACRUM	0:615f90842ce8	3207	* @{
MACRUM	0:615f90842ce8	3208	*/
MACRUM	0:615f90842ce8	3209
MACRUM	0:615f90842ce8	3210	#define COMMAND_TX ((uint8_t)(0x60)) /!< Start to transmit; valid only from READY /
MACRUM	0:615f90842ce8	3211	#define COMMAND_RX ((uint8_t)(0x61)) /!< Start to receive; valid only from READY /
MACRUM	0:615f90842ce8	3212	#define COMMAND_READY ((uint8_t)(0x62)) /!< Go to READY; valid only from STANDBY or SLEEP or LOCK /
MACRUM	0:615f90842ce8	3213	#define COMMAND_STANDBY ((uint8_t)(0x63)) /!< Go to STANDBY; valid only from READY /
MACRUM	0:615f90842ce8	3214	#define COMMAND_SLEEP ((uint8_t)(0x64)) /!< Go to SLEEP; valid only from READY /
MACRUM	0:615f90842ce8	3215	#define COMMAND_LOCKRX ((uint8_t)(0x65)) /!< Go to LOCK state by using the RX configuration of the synth; valid only from READY /
MACRUM	0:615f90842ce8	3216	#define COMMAND_LOCKTX ((uint8_t)(0x66)) /!< Go to LOCK state by using the TX configuration of the synth; valid only from READY /
MACRUM	0:615f90842ce8	3217	#define COMMAND_SABORT ((uint8_t)(0x67)) /!< Force exit form TX or RX states and go to READY state; valid only from TX or RX /
MACRUM	0:615f90842ce8	3218	#define COMMAND_LDC_RELOAD ((uint8_t)(0x68)) /*!< LDC Mode: Reload the LDC timer with the value stored in the LDC_PRESCALER / COUNTER
MACRUM	0:615f90842ce8	3219	registers; valid from all states */
MACRUM	0:615f90842ce8	3220	#define COMMAND_SEQUENCE_UPDATE ((uint8_t)(0x69)) /*!< Autoretransmission: Reload the Packet sequence counter with the value stored in the PROTOCOL[2] register
MACRUM	0:615f90842ce8	3221	valid from all states */
MACRUM	0:615f90842ce8	3222	#define COMMAND_AES_ENC ((uint8_t)(0x6A)) /!< AES: Start the encryption routine; valid from all states; valid from all states /
MACRUM	0:615f90842ce8	3223	#define COMMAND_AES_KEY ((uint8_t)(0x6B)) /!< AES: Start the procedure to compute the key for the decryption; valid from all states /
MACRUM	0:615f90842ce8	3224	#define COMMAND_AES_DEC ((uint8_t)(0x6C)) /!< AES: Start the decryption routine using the current key; valid from all states /
MACRUM	0:615f90842ce8	3225	#define COMMAND_AES_KEY_DEC ((uint8_t)(0x6D)) /!< AES: Compute the key and start the decryption; valid from all states /
MACRUM	0:615f90842ce8	3226	#define COMMAND_SRES ((uint8_t)(0x70)) /!< Reset of all digital part, except SPI registers /
MACRUM	0:615f90842ce8	3227	#define COMMAND_FLUSHRXFIFO ((uint8_t)(0x71)) /!< Clean the RX FIFO; valid from all states /
MACRUM	0:615f90842ce8	3228	#define COMMAND_FLUSHTXFIFO ((uint8_t)(0x72)) /!< Clean the TX FIFO; valid from all states /
MACRUM	0:615f90842ce8	3229
MACRUM	0:615f90842ce8	3230	/**
MACRUM	0:615f90842ce8	3231	* @}
MACRUM	0:615f90842ce8	3232	*/
MACRUM	0:615f90842ce8	3233
MACRUM	0:615f90842ce8	3234	/**
MACRUM	0:615f90842ce8	3235	* @}
MACRUM	0:615f90842ce8	3236	*/
MACRUM	0:615f90842ce8	3237
MACRUM	0:615f90842ce8	3238	#ifdef __cplusplus
MACRUM	0:615f90842ce8	3239	}
MACRUM	0:615f90842ce8	3240	#endif
MACRUM	0:615f90842ce8	3241
MACRUM	0:615f90842ce8	3242	#endif
MACRUM	0:615f90842ce8	3243
MACRUM	0:615f90842ce8	3244	/***************** (C) COPYRIGHT 2015 STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	12 Jul 2017
Imports:	26
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

The code in this repository is Apache licensed.

stm-spirit1-rf-driver/source/libs/spirit1/SPIRIT1_Library/Inc/SPIRIT_Regs.h@0:615f90842ce8, 2017-07-12 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning