Toyomasa Watarai / PowerControl

*power consumption control(phy , semihost) library written by Michael Wei (some compile errors with mbed lib (20131011) were fixed) *for Mbed LPC1768 *for clock control , see "ClockControl"

Dependents:   HTTPClient_WiFi_HelloWorld HTTPClient_WiFi_HelloWorld_src IBMIoTClientWifiExample

Fork of PowerControl by JST 2011

EthernetPowerControl.cpp@2:9bcf87e81217, 2015-03-25 (annotated)

Committer:
MACRUM
Date:
Wed Mar 25 10:34:40 2015 +0000
Revision:
2:9bcf87e81217
Parent:
0:8599d485662f 
Avoid compile error when target is not LPC1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
MACRUM 2:9bcf87e81217 1 #if defined(TARGET_LPC1768)
MACRUM 2:9bcf87e81217 2
JST2011 0:8599d485662f 3 #include "EthernetPowerControl.h"
JST2011 0:8599d485662f 4
JST2011 0:8599d485662f 5 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
JST2011 0:8599d485662f 6 /* Write a data 'Value' to PHY register 'PhyReg'. */
JST2011 0:8599d485662f 7 unsigned int tout;
JST2011 0:8599d485662f 8 /* Hardware MII Management for LPC176x devices. */
JST2011 0:8599d485662f 9 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
JST2011 0:8599d485662f 10 LPC_EMAC->MWTD = Value;
JST2011 0:8599d485662f 11
JST2011 0:8599d485662f 12 /* Wait utill operation completed */
JST2011 0:8599d485662f 13 for (tout = 0; tout < MII_WR_TOUT; tout++) {
JST2011 0:8599d485662f 14 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
JST2011 0:8599d485662f 15 break;
JST2011 0:8599d485662f 16 }
JST2011 0:8599d485662f 17 }
JST2011 0:8599d485662f 18 }
JST2011 0:8599d485662f 19
JST2011 0:8599d485662f 20 static unsigned short read_PHY (unsigned int PhyReg) {
JST2011 0:8599d485662f 21 /* Read a PHY register 'PhyReg'. */
JST2011 0:8599d485662f 22 unsigned int tout, val;
JST2011 0:8599d485662f 23
JST2011 0:8599d485662f 24 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
JST2011 0:8599d485662f 25 LPC_EMAC->MCMD = MCMD_READ;
JST2011 0:8599d485662f 26
JST2011 0:8599d485662f 27 /* Wait until operation completed */
JST2011 0:8599d485662f 28 for (tout = 0; tout < MII_RD_TOUT; tout++) {
JST2011 0:8599d485662f 29 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
JST2011 0:8599d485662f 30 break;
JST2011 0:8599d485662f 31 }
JST2011 0:8599d485662f 32 }
JST2011 0:8599d485662f 33 LPC_EMAC->MCMD = 0;
JST2011 0:8599d485662f 34 val = LPC_EMAC->MRDD;
JST2011 0:8599d485662f 35
JST2011 0:8599d485662f 36 return (val);
JST2011 0:8599d485662f 37 }
JST2011 0:8599d485662f 38
JST2011 0:8599d485662f 39 void EMAC_Init()
JST2011 0:8599d485662f 40 {
JST2011 0:8599d485662f 41 unsigned int tout,regv;
JST2011 0:8599d485662f 42 /* Power Up the EMAC controller. */
JST2011 0:8599d485662f 43 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
JST2011 0:8599d485662f 44
JST2011 0:8599d485662f 45 LPC_PINCON->PINSEL2 = 0x50150105;
JST2011 0:8599d485662f 46 LPC_PINCON->PINSEL3 &= ~0x0000000F;
JST2011 0:8599d485662f 47 LPC_PINCON->PINSEL3 |= 0x00000005;
JST2011 0:8599d485662f 48
JST2011 0:8599d485662f 49 /* Reset all EMAC internal modules. */
JST2011 0:8599d485662f 50 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
JST2011 0:8599d485662f 51 MAC1_SIM_RES | MAC1_SOFT_RES;
JST2011 0:8599d485662f 52 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
JST2011 0:8599d485662f 53
JST2011 0:8599d485662f 54 /* A short delay after reset. */
JST2011 0:8599d485662f 55 for (tout = 100; tout; tout--);
JST2011 0:8599d485662f 56
JST2011 0:8599d485662f 57 /* Initialize MAC control registers. */
JST2011 0:8599d485662f 58 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
JST2011 0:8599d485662f 59 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
JST2011 0:8599d485662f 60 LPC_EMAC->MAXF = ETH_MAX_FLEN;
JST2011 0:8599d485662f 61 LPC_EMAC->CLRT = CLRT_DEF;
JST2011 0:8599d485662f 62 LPC_EMAC->IPGR = IPGR_DEF;
JST2011 0:8599d485662f 63
JST2011 0:8599d485662f 64 /* Enable Reduced MII interface. */
JST2011 0:8599d485662f 65 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
JST2011 0:8599d485662f 66
JST2011 0:8599d485662f 67 /* Reset Reduced MII Logic. */
JST2011 0:8599d485662f 68 LPC_EMAC->SUPP = SUPP_RES_RMII;
JST2011 0:8599d485662f 69 for (tout = 100; tout; tout--);
JST2011 0:8599d485662f 70 LPC_EMAC->SUPP = 0;
JST2011 0:8599d485662f 71
JST2011 0:8599d485662f 72 /* Put the DP83848C in reset mode */
JST2011 0:8599d485662f 73 write_PHY (PHY_REG_BMCR, 0x8000);
JST2011 0:8599d485662f 74
JST2011 0:8599d485662f 75 /* Wait for hardware reset to end. */
JST2011 0:8599d485662f 76 for (tout = 0; tout < 0x100000; tout++) {
JST2011 0:8599d485662f 77 regv = read_PHY (PHY_REG_BMCR);
JST2011 0:8599d485662f 78 if (!(regv & 0x8000)) {
JST2011 0:8599d485662f 79 /* Reset complete */
JST2011 0:8599d485662f 80 break;
JST2011 0:8599d485662f 81 }
JST2011 0:8599d485662f 82 }
JST2011 0:8599d485662f 83 }
JST2011 0:8599d485662f 84
JST2011 0:8599d485662f 85
JST2011 0:8599d485662f 86 void PHY_PowerDown()
JST2011 0:8599d485662f 87 {
JST2011 0:8599d485662f 88 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 89 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 90
JST2011 0:8599d485662f 91 unsigned int regv;
JST2011 0:8599d485662f 92 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 93 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
JST2011 0:8599d485662f 94 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 95
JST2011 0:8599d485662f 96 //shouldn't need the EMAC now.
JST2011 0:8599d485662f 97 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
JST2011 0:8599d485662f 98
JST2011 0:8599d485662f 99 //and turn off the PHY OSC
JST2011 0:8599d485662f 100 LPC_GPIO1->FIODIR |= 0x8000000;
JST2011 0:8599d485662f 101 LPC_GPIO1->FIOCLR = 0x8000000;
JST2011 0:8599d485662f 102 }
JST2011 0:8599d485662f 103
JST2011 0:8599d485662f 104 void PHY_PowerUp()
JST2011 0:8599d485662f 105 {
JST2011 0:8599d485662f 106 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 107 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 108
JST2011 0:8599d485662f 109 LPC_GPIO1->FIODIR |= 0x8000000;
JST2011 0:8599d485662f 110 LPC_GPIO1->FIOSET = 0x8000000;
JST2011 0:8599d485662f 111
JST2011 0:8599d485662f 112 //wait for osc to be stable
JST2011 0:8599d485662f 113 wait_ms(200);
JST2011 0:8599d485662f 114
JST2011 0:8599d485662f 115 unsigned int regv;
JST2011 0:8599d485662f 116 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 117 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
JST2011 0:8599d485662f 118 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 119 }
JST2011 0:8599d485662f 120
JST2011 0:8599d485662f 121 void PHY_EnergyDetect_Enable()
JST2011 0:8599d485662f 122 {
JST2011 0:8599d485662f 123 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 124 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 125
JST2011 0:8599d485662f 126 unsigned int regv;
JST2011 0:8599d485662f 127 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 128 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
JST2011 0:8599d485662f 129 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 130 }
JST2011 0:8599d485662f 131
JST2011 0:8599d485662f 132 void PHY_EnergyDetect_Disable()
JST2011 0:8599d485662f 133 {
JST2011 0:8599d485662f 134 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 135 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 136 unsigned int regv;
JST2011 0:8599d485662f 137 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 138 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
JST2011 0:8599d485662f 139 regv = read_PHY(PHY_REG_EDCR);
MACRUM 2:9bcf87e81217 140 }
MACRUM 2:9bcf87e81217 141 #endif