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system_LPC17xx.c
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00001 /**************************************************************************//** 00002 * @file system_LPC17xx.c 00003 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File 00004 * for the NXP LPC17xx Device Series 00005 * @version V1.03 00006 * @date 07. October 2009 00007 * 00008 * @note 00009 * Copyright (C) 2009 ARM Limited. All rights reserved. 00010 * 00011 * @par 00012 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00013 * processor based microcontrollers. This file can be freely distributed 00014 * within development tools that are supporting such ARM based processors. 00015 * 00016 * @par 00017 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00018 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00019 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00020 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00021 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00022 * 00023 ******************************************************************************/ 00024 00025 00026 #include <stdint.h> 00027 #include "LPC17xx.h" 00028 00029 /* 00030 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 00031 */ 00032 00033 /*--------------------- Clock Configuration ---------------------------------- 00034 // 00035 // <e> Clock Configuration 00036 // <h> System Controls and Status Register (SCS) 00037 // <o1.4> OSCRANGE: Main Oscillator Range Select 00038 // <0=> 1 MHz to 20 MHz 00039 // <1=> 15 MHz to 24 MHz 00040 // <e1.5> OSCEN: Main Oscillator Enable 00041 // </e> 00042 // </h> 00043 // 00044 // <h> Clock Source Select Register (CLKSRCSEL) 00045 // <o2.0..1> CLKSRC: PLL Clock Source Selection 00046 // <0=> Internal RC oscillator 00047 // <1=> Main oscillator 00048 // <2=> RTC oscillator 00049 // </h> 00050 // 00051 // <e3> PLL0 Configuration (Main PLL) 00052 // <h> PLL0 Configuration Register (PLL0CFG) 00053 // <i> F_cco0 = (2 * M * F_in) / N 00054 // <i> F_in must be in the range of 32 kHz to 50 MHz 00055 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz 00056 // <o4.0..14> MSEL: PLL Multiplier Selection 00057 // <6-32768><#-1> 00058 // <i> M Value 00059 // <o4.16..23> NSEL: PLL Divider Selection 00060 // <1-256><#-1> 00061 // <i> N Value 00062 // </h> 00063 // </e> 00064 // 00065 // <e5> PLL1 Configuration (USB PLL) 00066 // <h> PLL1 Configuration Register (PLL1CFG) 00067 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) 00068 // <i> F_cco1 = F_osc * M * 2 * P 00069 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz 00070 // <o6.0..4> MSEL: PLL Multiplier Selection 00071 // <1-32><#-1> 00072 // <i> M Value (for USB maximum value is 4) 00073 // <o6.5..6> PSEL: PLL Divider Selection 00074 // <0=> 1 00075 // <1=> 2 00076 // <2=> 4 00077 // <3=> 8 00078 // <i> P Value 00079 // </h> 00080 // </e> 00081 // 00082 // <h> CPU Clock Configuration Register (CCLKCFG) 00083 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 00084 // <3-256><#-1> 00085 // </h> 00086 // 00087 // <h> USB Clock Configuration Register (USBCLKCFG) 00088 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 00089 // <0-15> 00090 // <i> Divide is USBSEL + 1 00091 // </h> 00092 // 00093 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) 00094 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT 00095 // <0=> Pclk = Cclk / 4 00096 // <1=> Pclk = Cclk 00097 // <2=> Pclk = Cclk / 2 00098 // <3=> Pclk = Hclk / 8 00099 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 00100 // <0=> Pclk = Cclk / 4 00101 // <1=> Pclk = Cclk 00102 // <2=> Pclk = Cclk / 2 00103 // <3=> Pclk = Hclk / 8 00104 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 00105 // <0=> Pclk = Cclk / 4 00106 // <1=> Pclk = Cclk 00107 // <2=> Pclk = Cclk / 2 00108 // <3=> Pclk = Hclk / 8 00109 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 00110 // <0=> Pclk = Cclk / 4 00111 // <1=> Pclk = Cclk 00112 // <2=> Pclk = Cclk / 2 00113 // <3=> Pclk = Hclk / 8 00114 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 00115 // <0=> Pclk = Cclk / 4 00116 // <1=> Pclk = Cclk 00117 // <2=> Pclk = Cclk / 2 00118 // <3=> Pclk = Hclk / 8 00119 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 00120 // <0=> Pclk = Cclk / 4 00121 // <1=> Pclk = Cclk 00122 // <2=> Pclk = Cclk / 2 00123 // <3=> Pclk = Hclk / 8 00124 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 00125 // <0=> Pclk = Cclk / 4 00126 // <1=> Pclk = Cclk 00127 // <2=> Pclk = Cclk / 2 00128 // <3=> Pclk = Hclk / 8 00129 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI 00130 // <0=> Pclk = Cclk / 4 00131 // <1=> Pclk = Cclk 00132 // <2=> Pclk = Cclk / 2 00133 // <3=> Pclk = Hclk / 8 00134 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 00135 // <0=> Pclk = Cclk / 4 00136 // <1=> Pclk = Cclk 00137 // <2=> Pclk = Cclk / 2 00138 // <3=> Pclk = Hclk / 8 00139 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC 00140 // <0=> Pclk = Cclk / 4 00141 // <1=> Pclk = Cclk 00142 // <2=> Pclk = Cclk / 2 00143 // <3=> Pclk = Hclk / 8 00144 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC 00145 // <0=> Pclk = Cclk / 4 00146 // <1=> Pclk = Cclk 00147 // <2=> Pclk = Cclk / 2 00148 // <3=> Pclk = Hclk / 8 00149 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 00150 // <0=> Pclk = Cclk / 4 00151 // <1=> Pclk = Cclk 00152 // <2=> Pclk = Cclk / 2 00153 // <3=> Pclk = Hclk / 6 00154 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 00155 // <0=> Pclk = Cclk / 4 00156 // <1=> Pclk = Cclk 00157 // <2=> Pclk = Cclk / 2 00158 // <3=> Pclk = Hclk / 6 00159 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF 00160 // <0=> Pclk = Cclk / 4 00161 // <1=> Pclk = Cclk 00162 // <2=> Pclk = Cclk / 2 00163 // <3=> Pclk = Hclk / 6 00164 // </h> 00165 // 00166 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) 00167 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface 00168 // <0=> Pclk = Cclk / 4 00169 // <1=> Pclk = Cclk 00170 // <2=> Pclk = Cclk / 2 00171 // <3=> Pclk = Hclk / 8 00172 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs 00173 // <0=> Pclk = Cclk / 4 00174 // <1=> Pclk = Cclk 00175 // <2=> Pclk = Cclk / 2 00176 // <3=> Pclk = Hclk / 8 00177 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block 00178 // <0=> Pclk = Cclk / 4 00179 // <1=> Pclk = Cclk 00180 // <2=> Pclk = Cclk / 2 00181 // <3=> Pclk = Hclk / 8 00182 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 00183 // <0=> Pclk = Cclk / 4 00184 // <1=> Pclk = Cclk 00185 // <2=> Pclk = Cclk / 2 00186 // <3=> Pclk = Hclk / 8 00187 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 00188 // <0=> Pclk = Cclk / 4 00189 // <1=> Pclk = Cclk 00190 // <2=> Pclk = Cclk / 2 00191 // <3=> Pclk = Hclk / 8 00192 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 00193 // <0=> Pclk = Cclk / 4 00194 // <1=> Pclk = Cclk 00195 // <2=> Pclk = Cclk / 2 00196 // <3=> Pclk = Hclk / 8 00197 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 00198 // <0=> Pclk = Cclk / 4 00199 // <1=> Pclk = Cclk 00200 // <2=> Pclk = Cclk / 2 00201 // <3=> Pclk = Hclk / 8 00202 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 00203 // <0=> Pclk = Cclk / 4 00204 // <1=> Pclk = Cclk 00205 // <2=> Pclk = Cclk / 2 00206 // <3=> Pclk = Hclk / 8 00207 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 00208 // <0=> Pclk = Cclk / 4 00209 // <1=> Pclk = Cclk 00210 // <2=> Pclk = Cclk / 2 00211 // <3=> Pclk = Hclk / 8 00212 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 00213 // <0=> Pclk = Cclk / 4 00214 // <1=> Pclk = Cclk 00215 // <2=> Pclk = Cclk / 2 00216 // <3=> Pclk = Hclk / 8 00217 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S 00218 // <0=> Pclk = Cclk / 4 00219 // <1=> Pclk = Cclk 00220 // <2=> Pclk = Cclk / 2 00221 // <3=> Pclk = Hclk / 8 00222 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer 00223 // <0=> Pclk = Cclk / 4 00224 // <1=> Pclk = Cclk 00225 // <2=> Pclk = Cclk / 2 00226 // <3=> Pclk = Hclk / 8 00227 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block 00228 // <0=> Pclk = Cclk / 4 00229 // <1=> Pclk = Cclk 00230 // <2=> Pclk = Cclk / 2 00231 // <3=> Pclk = Hclk / 8 00232 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM 00233 // <0=> Pclk = Cclk / 4 00234 // <1=> Pclk = Cclk 00235 // <2=> Pclk = Cclk / 2 00236 // <3=> Pclk = Hclk / 8 00237 // </h> 00238 // 00239 // <h> Power Control for Peripherals Register (PCONP) 00240 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable 00241 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable 00242 // <o11.3> PCUART0: UART 0 power/clock enable 00243 // <o11.4> PCUART1: UART 1 power/clock enable 00244 // <o11.6> PCPWM1: PWM 1 power/clock enable 00245 // <o11.7> PCI2C0: I2C interface 0 power/clock enable 00246 // <o11.8> PCSPI: SPI interface power/clock enable 00247 // <o11.9> PCRTC: RTC power/clock enable 00248 // <o11.10> PCSSP1: SSP interface 1 power/clock enable 00249 // <o11.12> PCAD: A/D converter power/clock enable 00250 // <o11.13> PCCAN1: CAN controller 1 power/clock enable 00251 // <o11.14> PCCAN2: CAN controller 2 power/clock enable 00252 // <o11.15> PCGPIO: GPIOs power/clock enable 00253 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable 00254 // <o11.17> PCMC: Motor control PWM power/clock enable 00255 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable 00256 // <o11.19> PCI2C1: I2C interface 1 power/clock enable 00257 // <o11.21> PCSSP0: SSP interface 0 power/clock enable 00258 // <o11.22> PCTIM2: Timer 2 power/clock enable 00259 // <o11.23> PCTIM3: Timer 3 power/clock enable 00260 // <o11.24> PCUART2: UART 2 power/clock enable 00261 // <o11.25> PCUART3: UART 3 power/clock enable 00262 // <o11.26> PCI2C2: I2C interface 2 power/clock enable 00263 // <o11.27> PCI2S: I2S interface power/clock enable 00264 // <o11.29> PCGPDMA: GP DMA function power/clock enable 00265 // <o11.30> PCENET: Ethernet block power/clock enable 00266 // <o11.31> PCUSB: USB interface power/clock enable 00267 // </h> 00268 // 00269 // <h> Clock Output Configuration Register (CLKOUTCFG) 00270 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT 00271 // <0=> CPU clock 00272 // <1=> Main oscillator 00273 // <2=> Internal RC oscillator 00274 // <3=> USB clock 00275 // <4=> RTC oscillator 00276 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT 00277 // <1-16><#-1> 00278 // <o12.8> CLKOUT_EN: CLKOUT enable control 00279 // </h> 00280 // 00281 // </e> 00282 */ 00283 00284 // сейчас получается частота 100 Mhz 00285 //12 * 2 * (99+1) / (5+1) = 400 (должна быть в пределах 275...550) 00286 //потом еше делится на 4 = 100 00287 //нам нужно 921600* 16 = 14 745 000, теперб выбираем делитель уартовский 7 = 103 219 200, дибо 8 = 117 964 800 00288 00289 //1 выбираем второе 117 964 800 округляем до 100 000 (для второго таймера) 118 000. таку. частоту нужно на входе УАРТА. 00290 //118 * 3 = 354, 118 * 4 = 472. 00291 00292 // 354 / "3" = 118 00293 //попробуем с 474 >> умножитель на 59 и делитель на 3 => 12 * 2 * ("58" + 1) / ("2" + 1) = 472. 00294 // 472 / "4" = 118 00295 00296 // с другой стороны не рекомендуют частоты выше 100 (120 только для 1769 или чото там еще ) 00297 // 103,200 => *3 = 309.6; * 4 = 412,8. 00298 // 412,8 умножитель на 86 и делитель на 5 => 12 * 2 * ("85" + 1) / ("4" + 1) = 412,8. !!!!!наверно можно остоновиься и попробовать!!!!!!!! 00299 // 412,8 / "4" = 103,2 00300 00301 #define CLOCK_SETUP 1 00302 00303 //System control - system control and status register: 00304 // bit 4 - main oscillator range: 00305 // 0 - 1...20MHz 00306 // 1 - 15...25MHz 00307 // bit 5 - main oscillator enable 00308 // 0 - disabled 00309 // 1 - enabled 00310 // bit 6 - main oscillator status 00311 // 0 - not ready 00312 // 1 - ready 00313 #define SCS_Val 0x00000020 //Enable main oscillator,1...20MHz 00314 //Clock Source Select register 00315 // bits 0-1: 00316 // 00 - Selects the Internal RC oscillator as the PLL0 clock source (default) 00317 // 01 - Selects the main oscillator as the PLL0 clock source 00318 // 10 - Selects the RTC oscillator as the PLL0 clock source 00319 // 11 - Reserved, do not use this setting 00320 #define CLKSRCSEL_Val 0x00000001//Select the main oscillator as the PLL0 clock source 00321 #define PLL0_SETUP 1 00322 //PLL0 Configuration register 00323 // bits 0...14 - PLL0 multiplier value minus 1. Supported multiplier M range 6...512 00324 // bits 16...23 - PLL0 Pre-Divider value minus 1. Supported divider N range 1...32 00325 // Fcc0 = (2 * M * Fin) / N 00326 #define PLL0CFG_Val 0x00040055//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz 00327 // #define PLL0CFG_Val 0x0003003d//M - 86, N - 5, output = 2 * 86 * 12MHz / 5 = 400MHz 00328 #define PLL1_SETUP 1 00329 #define PLL1CFG_Val 0x00000023//M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz? 00330 //CPU Clock Configure Register 00331 #define CCLKCFG_Val 0x00000003 //Divide by 4 00332 00333 //USB Clock Configuration register 00334 // bits 0...3 00335 // 5 - PLL0 output is divided by 6. PLL0 output must be 288 MHz 00336 // 7 - PLL0 output is divided by 8. PLL0 output must be 384 MHz 00337 // 9 - PLL0 output is divided by 10. PLL0 output must be 480 MHz 00338 #define USBCLKCFG_Val 0x00000000//default 00339 //Peripheral Clock Selection register 0 00340 // 1:0 PCLK_WDT Peripheral clock selection for WDT. 00 00341 // 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00 00342 // 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00 00343 // 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00 00344 // 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00 00345 // 11:10 - Reserved. NA 00346 // 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00 00347 // 15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00 00348 // 17:16 PCLK_SPI Peripheral clock selection for SPI. 00 00349 // 19:18 - Reserved. NA 00350 // 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00 00351 // 23:22 PCLK_DAC Peripheral clock selection for DAC. 00 00352 // 25:24 PCLK_ADC Peripheral clock selection for ADC. 00 00353 // 27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00 00354 // 29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00 00355 // 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering 00356 // bits values: 00357 // 00 PCLK_peripheral = CCLK/4 00358 // 01 PCLK_peripheral = CCLK 00359 // 10 PCLK_peripheral = CCLK/2 00360 // 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6. 00361 //#define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4 00362 #define PCLKSEL0_Val 0x40000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4 00363 //#define PCLKSEL0_Val 0x000003d0//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4 00364 //Peripheral Clock Selection register 1 00365 // 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00 00366 // 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00 00367 // 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00 00368 // 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00 00369 // 9:8 - Reserved. NA 00370 // 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00 00371 // 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00 00372 // 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00 00373 // 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00 00374 // 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00 00375 // 21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00 00376 // 23:22 PCLK_I2S Peripheral clock selection for I2S. 00 00377 // 25:24 - Reserved. NA 00378 // 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00 00379 // 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00 00380 // 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM 00381 #define PCLKSEL1_Val 0x00000000//CCLK/4 00382 //Power Control for Peripherals register 00383 //0 - Reserved. NA 00384 //1 PCTIM0 Timer/Counter 0 power/clock control bit. 1 00385 //2 PCTIM1 Timer/Counter 1 power/clock control bit. 1 00386 //3 PCUART0 UART0 power/clock control bit. 1 00387 //4 PCUART1 UART1 power/clock control bit. 1 00388 //5 - Reserved. NA 00389 //6 PCPWM1 PWM1 power/clock control bit. 1 00390 //7 PCI2C0 The I2C0 interface power/clock control bit. 1 00391 //8 PCSPI The SPI interface power/clock control bit. 1 00392 //9 PCRTC The RTC power/clock control bit. 1 00393 //10 PCSSP1 The SSP 1 interface power/clock control bit. 1 00394 //11 - Reserved. NA 00395 //12 PCADC A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN. 0 00396 //13 PCCAN1 CAN Controller 1 power/clock control bit. 0 00397 //14 PCCAN2 CAN Controller 2 power/clock control bit. 0 00398 //15 PCGPIO Power/clock control bit for IOCON, GPIO, and GPIO interrupts. 1 00399 //16 PCRIT Repetitive Interrupt Timer power/clock control bit. 0 00400 //17 PCMCPWM Motor Control PWM 0 00401 //18 PCQEI Quadrature Encoder Interface power/clock control bit. 0 00402 //19 PCI2C1 The I2C1 interface power/clock control bit. 1 00403 //20 - Reserved. NA 00404 //21 PCSSP0 The SSP0 interface power/clock control bit. 1 00405 //22 PCTIM2 Timer 2 power/clock control bit. 0 00406 //23 PCTIM3 Timer 3 power/clock control bit. 0 00407 //24 PCUART2 UART 2 power/clock control bit. 0 00408 //25 PCUART3 UART 3 power/clock control bit. 0 00409 //26 PCI2C2 I2C interface 2 power/clock control bit. 1 00410 #define PCONP_Val 0x046887DE//ADC,CAN1/2,RIT,Timer3,UART2,UART3 disabled 00411 //Clock Output Configuration register 00412 // 3:0 CLKOUTSEL Selects the clock source for the CLKOUT function. 0 00413 // 0000 Selects the CPU clock as the CLKOUT source. 00414 // 0001 Selects the main oscillator as the CLKOUT source. 00415 // 0010 Selects the Internal RC oscillator as the CLKOUT source. 00416 // 0011 Selects the USB clock as the CLKOUT source. 00417 // 0100 Selects the RTC oscillator as the CLKOUT source. 00418 // Others Reserved, do not use these settings. 00419 // 7:4 CLKOUTDIV Integer value to divide the output clock by, minus one. 0 00420 // 0000 Clock is divided by 1. 00421 // 0001 Clock is divided by 2. 00422 // 0010 Clock is divided by 3. 00423 // ... ... 00424 // 1111 Clock is divided by 16. 00425 // 8 CLKOUT_EN CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT. 0 00426 // 9 CLKOUT_ACT CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped. 00427 #define CLKOUTCFG_Val 0x00000000//Host4: CLKOUT pin not used 00428 00429 00430 /*--------------------- Flash Accelerator Configuration ---------------------- 00431 // 00432 // <e> Flash Accelerator Configuration 00433 // <o1.0..1> FETCHCFG: Fetch Configuration 00434 // <0=> Instruction fetches from flash are not buffered 00435 // <1=> One buffer is used for all instruction fetch buffering 00436 // <2=> All buffers may be used for instruction fetch buffering 00437 // <3=> Reserved (do not use this setting) 00438 // <o1.2..3> DATACFG: Data Configuration 00439 // <0=> Data accesses from flash are not buffered 00440 // <1=> One buffer is used for all data access buffering 00441 // <2=> All buffers may be used for data access buffering 00442 // <3=> Reserved (do not use this setting) 00443 // <o1.4> ACCEL: Acceleration Enable 00444 // <o1.5> PREFEN: Prefetch Enable 00445 // <o1.6> PREFOVR: Prefetch Override 00446 // <o1.12..15> FLASHTIM: Flash Access Time 00447 // <0=> 1 CPU clock (for CPU clock up to 20 MHz) 00448 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) 00449 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) 00450 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) 00451 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) 00452 // <5=> 6 CPU clocks (for any CPU clock) 00453 // </e> 00454 */ 00455 #define FLASH_SETUP 1 00456 //Flash Accelerator Configuration Register 00457 // 11:0 - - Reserved, user software should not change these bits from the reset value. 0x03A 00458 // 15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. 0x3 00459 // 0000 Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock. 00460 // 0001 Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock. 00461 // 0010 Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock. 00462 // 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock. 00463 // 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only. 00464 // 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices. 00465 00466 // 31:16 - Reserved. The value read from a reserved bit is not defined. NA 00467 #define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access 00468 00469 /* 00470 //-------- <<< end of configuration section >>> ------------------------------ 00471 */ 00472 00473 /*---------------------------------------------------------------------------- 00474 Check the register settings 00475 *----------------------------------------------------------------------------*/ 00476 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) 00477 #define CHECK_RSVD(val, mask) (val & mask) 00478 00479 /* Clock Configuration -------------------------------------------------------*/ 00480 #if (CHECK_RSVD((SCS_Val), ~0x00000030)) 00481 #error "SCS: Invalid values of reserved bits!" 00482 #endif 00483 00484 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) 00485 #error "CLKSRCSEL: Value out of range!" 00486 #endif 00487 00488 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) 00489 #error "PLL0CFG: Invalid values of reserved bits!" 00490 #endif 00491 00492 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) 00493 #error "PLL1CFG: Invalid values of reserved bits!" 00494 #endif 00495 00496 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) 00497 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" 00498 #endif 00499 00500 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) 00501 #error "USBCLKCFG: Invalid values of reserved bits!" 00502 #endif 00503 00504 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) 00505 #error "PCLKSEL0: Invalid values of reserved bits!" 00506 #endif 00507 00508 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) 00509 #error "PCLKSEL1: Invalid values of reserved bits!" 00510 #endif 00511 00512 #if (CHECK_RSVD((PCONP_Val), 0x10100821)) 00513 #error "PCONP: Invalid values of reserved bits!" 00514 #endif 00515 00516 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) 00517 #error "CLKOUTCFG: Invalid values of reserved bits!" 00518 #endif 00519 00520 /* Flash Accelerator Configuration -------------------------------------------*/ 00521 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) 00522 #error "FLASHCFG: Invalid values of reserved bits!" 00523 #endif 00524 00525 00526 /*---------------------------------------------------------------------------- 00527 DEFINES 00528 *----------------------------------------------------------------------------*/ 00529 00530 /*---------------------------------------------------------------------------- 00531 Define clocks 00532 *----------------------------------------------------------------------------*/ 00533 #define XTAL (12000000UL) /* Oscillator frequency */ 00534 #define OSC_CLK ( XTAL) /* Main oscillator frequency */ 00535 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */ 00536 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ 00537 00538 00539 /* F_cco0 = (2 * M * F_in) / N */ 00540 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) 00541 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) 00542 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) 00543 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) 00544 00545 /* Determine core clock frequency according to settings */ 00546 #if (PLL0_SETUP) 00547 #if ((CLKSRCSEL_Val & 0x03) == 1) 00548 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) 00549 #elif ((CLKSRCSEL_Val & 0x03) == 2) 00550 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) 00551 #else 00552 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) 00553 #endif 00554 #else 00555 #if ((CLKSRCSEL_Val & 0x03) == 1) 00556 #define __CORE_CLK (OSC_CLK / __CCLK_DIV) 00557 #elif ((CLKSRCSEL_Val & 0x03) == 2) 00558 #define __CORE_CLK (RTC_CLK / __CCLK_DIV) 00559 #else 00560 #define __CORE_CLK (IRC_OSC / __CCLK_DIV) 00561 #endif 00562 #endif 00563 00564 00565 /*---------------------------------------------------------------------------- 00566 Clock Variable definitions 00567 *----------------------------------------------------------------------------*/ 00568 uint32_t SystemFrequency = IRC_OSC; 00569 uint32_t SystemCoreClock1 = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ 00570 00571 00572 /*---------------------------------------------------------------------------- 00573 Clock functions 00574 *----------------------------------------------------------------------------*/ 00575 void SystemCoreClockUpdate1 (void) /* Get Core Clock Frequency */ 00576 { 00577 /* Determine clock frequency according to clock register values */ 00578 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ 00579 switch (LPC_SC->CLKSRCSEL & 0x03) { 00580 case 0: /* Int. RC oscillator => PLL0 */ 00581 case 3: /* Reserved, default to Int. RC */ 00582 SystemCoreClock1 = (IRC_OSC * 00583 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00584 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 00585 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00586 break; 00587 case 1: /* Main oscillator => PLL0 */ 00588 SystemCoreClock1 = (OSC_CLK * //it is our case osc_clk = 12 MHz 00589 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value 00590 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider 00591 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock) 00592 break; 00593 case 2: /* RTC oscillator => PLL0 */ 00594 SystemCoreClock1 = (RTC_CLK * 00595 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00596 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 00597 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00598 break; 00599 } 00600 } else { 00601 switch (LPC_SC->CLKSRCSEL & 0x03) { 00602 case 0: /* Int. RC oscillator => PLL0 */ 00603 case 3: /* Reserved, default to Int. RC */ 00604 SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00605 break; 00606 case 1: /* Main oscillator => PLL0 */ 00607 SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00608 break; 00609 case 2: /* RTC oscillator => PLL0 */ 00610 SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00611 break; 00612 } 00613 } 00614 00615 } 00616 00617 /** 00618 * Initialize the system 00619 * 00620 * @param none 00621 * @return none 00622 * 00623 * @brief Setup the microcontroller system. 00624 * Initialize the System. 00625 */ 00626 void SystemInit1 (void) 00627 { 00628 #if (CLOCK_SETUP) /* Clock Setup */ 00629 //Init system control and status register 00630 LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz) 00631 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ 00632 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ 00633 } 00634 00635 //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output 00636 LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz) 00637 00638 #if (PLL0_SETUP) 00639 //Init Clock Source Select register 00640 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source 00641 //Init PLL0 Configuration register 00642 LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz 00643 //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG 00644 //registers into the shadow registers that actually affect PLL0 operation. 00645 //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect 00646 LPC_SC->PLL0FEED = 0xAA; 00647 LPC_SC->PLL0FEED = 0x55; 00648 //Init PLL0 Control register 00649 // bit 0 - PLL0 Enable 00650 // bit 1 - PLL0 connect 00651 LPC_SC->PLL0CON = 0x01;//PLL0 Enable 00652 //Update shadow registers to settings take effect 00653 LPC_SC->PLL0FEED = 0xAA; 00654 LPC_SC->PLL0FEED = 0x55; 00655 //PLL0 Status register 00656 // bits 0...14 - Read-back for the PLL0 Multiplier value 00657 // bits 16...23 - Read-back for the PLL0 Pre-Divider value 00658 // bit 24 - Read-back for the PLL0 Enable bit 00659 // bit 25 - Read-back for the PLL0 Connect bit 00660 // bit 26 - Reflects the PLL0 Lock status: 1 - locked 00661 while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0) 00662 00663 LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect 00664 LPC_SC->PLL0FEED = 0xAA; 00665 LPC_SC->PLL0FEED = 0x55; 00666 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT) 00667 #endif 00668 00669 #if (PLL1_SETUP) 00670 LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz? 00671 LPC_SC->PLL1FEED = 0xAA; 00672 LPC_SC->PLL1FEED = 0x55; 00673 00674 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ 00675 LPC_SC->PLL1FEED = 0xAA; 00676 LPC_SC->PLL1FEED = 0x55; 00677 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ 00678 00679 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ 00680 LPC_SC->PLL1FEED = 0xAA; 00681 LPC_SC->PLL1FEED = 0x55; 00682 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */ 00683 #else 00684 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ 00685 #endif 00686 00687 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ 00688 LPC_SC->PCLKSEL1 = PCLKSEL1_Val; 00689 00690 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ 00691 00692 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ 00693 #endif 00694 00695 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ 00696 LPC_SC->FLASHCFG = FLASHCFG_Val; 00697 #endif 00698 } 00699 00700 00701 00702 00703 00704 00705 00706 void SystemInitDef (void) 00707 { 00708 00709 00710 #if (CLOCK_SETUP) /* Clock Setup */ 00711 LPC_SC->SCS = SCS_Val; 00712 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */ 00713 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ 00714 } 00715 00716 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ 00717 00718 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ 00719 LPC_SC->PCLKSEL1 = PCLKSEL1_Val; 00720 00721 #if (PLL0_SETUP) 00722 LPC_SC->CLKSRCSEL = 0;// CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ 00723 LPC_SC->PLL0CFG = PLL0CFG_Val; 00724 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ 00725 LPC_SC->PLL0FEED = 0xAA; 00726 LPC_SC->PLL0FEED = 0x55; 00727 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ 00728 00729 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ 00730 LPC_SC->PLL0FEED = 0xAA; 00731 LPC_SC->PLL0FEED = 0x55; 00732 #endif 00733 00734 #if (PLL1_SETUP) 00735 LPC_SC->PLL1CFG = PLL1CFG_Val; 00736 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ 00737 LPC_SC->PLL1FEED = 0xAA; 00738 LPC_SC->PLL1FEED = 0x55; 00739 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ 00740 00741 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ 00742 LPC_SC->PLL1FEED = 0xAA; 00743 LPC_SC->PLL1FEED = 0x55; 00744 #else 00745 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ 00746 #endif 00747 00748 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ 00749 00750 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ 00751 #endif 00752 00753 /* Determine clock frequency according to clock register values */ 00754 if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */ 00755 switch (LPC_SC->CLKSRCSEL & 0x03) { 00756 case 0: /* Internal RC oscillator => PLL0 */ 00757 case 3: /* Reserved, default to Internal RC */ 00758 SystemFrequency = (IRC_OSC * 00759 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00760 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / 00761 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00762 break; 00763 case 1: /* Main oscillator => PLL0 */ 00764 SystemFrequency = (OSC_CLK * 00765 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00766 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / 00767 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00768 break; 00769 case 2: /* RTC oscillator => PLL0 */ 00770 SystemFrequency = (RTC_CLK * 00771 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 00772 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) / 00773 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 00774 break; 00775 } 00776 } else { 00777 switch (LPC_SC->CLKSRCSEL & 0x03) { 00778 case 0: /* Internal RC oscillator => PLL0 */ 00779 case 3: /* Reserved, default to Internal RC */ 00780 SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00781 break; 00782 case 1: /* Main oscillator => PLL0 */ 00783 SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00784 break; 00785 case 2: /* RTC oscillator => PLL0 */ 00786 SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 00787 break; 00788 } 00789 } 00790 00791 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ 00792 LPC_SC->FLASHCFG = FLASHCFG_Val; 00793 #endif 00794 00795 00796 } 00797
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