Dmitry Kovalev
/
LGstaandart
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
LG2
by 
Dmitry Kovalev
Embed:
(wiki syntax)
Show/hide line numbers
LPC17xx.h
00001 /****************************************************************************** 00002 * @file: LPC17xx.h 00003 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 00004 * NXP LPC17xx Device Series 00005 * @version: V1.10 00006 * @date: 24. September 2010 00007 *---------------------------------------------------------------------------- 00008 * 00009 * @note 00010 * Copyright (C) 2010 ARM Limited. All rights reserved. 00011 * 00012 * @par 00013 * ARM Limited (ARM) is supplying this software for use with Cortex-M3 00014 * processor based microcontrollers. This file can be freely distributed 00015 * within development tools that are supporting such ARM based processors. 00016 * 00017 * @par 00018 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00019 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00020 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00021 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00022 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00023 * 00024 ******************************************************************************/ 00025 00026 00027 #ifndef __LPC17xx_H__ 00028 #define __LPC17xx_H__ 00029 00030 /* 00031 * ========================================================================== 00032 * ---------- Interrupt Number Definition ----------------------------------- 00033 * ========================================================================== 00034 */ 00035 00036 /** @addtogroup LPC17xx_System 00037 * @{ 00038 */ 00039 #define rISER0 (*(volatile unsigned *)0xE000E100) 00040 #define rICER0 (*(volatile unsigned *)0xE000E180) 00041 #define rISPR0 (*(volatile unsigned *)0xE000E200) 00042 #define rICPR0 (*(volatile unsigned *)0xE000E280) 00043 #define rIABR0 (*(volatile unsigned *)0xE000E300) 00044 00045 00046 /** @brief IRQ interrupt source definition */ 00047 typedef enum IRQn 00048 { 00049 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00050 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00051 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00052 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00053 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00054 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00055 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00056 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00057 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00058 00059 /****** LPC17xx Specific Interrupt Numbers *******************************************************/ 00060 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ 00061 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ 00062 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ 00063 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ 00064 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ 00065 UART0_IRQn = 5, /*!< UART0 Interrupt */ 00066 UART1_IRQn = 6, /*!< UART1 Interrupt */ 00067 UART2_IRQn = 7, /*!< UART2 Interrupt */ 00068 UART3_IRQn = 8, /*!< UART3 Interrupt */ 00069 PWM1_IRQn = 9, /*!< PWM1 Interrupt */ 00070 I2C0_IRQn = 10, /*!< I2C0 Interrupt */ 00071 I2C1_IRQn = 11, /*!< I2C1 Interrupt */ 00072 I2C2_IRQn = 12, /*!< I2C2 Interrupt */ 00073 SPI_IRQn = 13, /*!< SPI Interrupt */ 00074 SSP0_IRQn = 14, /*!< SSP0 Interrupt */ 00075 SSP1_IRQn = 15, /*!< SSP1 Interrupt */ 00076 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ 00077 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ 00078 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ 00079 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ 00080 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ 00081 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ 00082 ADC_IRQn = 22, /*!< A/D Converter Interrupt */ 00083 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ 00084 USB_IRQn = 24, /*!< USB Interrupt */ 00085 CAN_IRQn = 25, /*!< CAN Interrupt */ 00086 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ 00087 I2S_IRQn = 27, /*!< I2S Interrupt */ 00088 ENET_IRQn = 28, /*!< Ethernet Interrupt */ 00089 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ 00090 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ 00091 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ 00092 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ 00093 USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */ 00094 CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */ 00095 } IRQn_Type; 00096 00097 00098 /* 00099 * ========================================================================== 00100 * ----------- Processor and Core Peripheral Section ------------------------ 00101 * ========================================================================== 00102 */ 00103 00104 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00105 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00106 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00107 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00108 00109 00110 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ 00111 #include "system_LPC17xx.h" /* System Header */ 00112 00113 00114 /******************************************************************************/ 00115 /* Device Specific Peripheral registers structures */ 00116 /******************************************************************************/ 00117 00118 #if defined ( __CC_ARM ) 00119 #pragma anon_unions 00120 #endif 00121 00122 /*------------- System Control (SC) ------------------------------------------*/ 00123 /** @brief System Control (SC) register structure definition */ 00124 typedef struct 00125 { 00126 __IO uint32_t FLASHCFG ; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ 00127 uint32_t RESERVED0[31]; 00128 __IO uint32_t PLL0CON ; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ 00129 __IO uint32_t PLL0CFG ; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ 00130 __I uint32_t PLL0STAT ; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ 00131 __O uint32_t PLL0FEED ; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ 00132 uint32_t RESERVED1[4]; 00133 __IO uint32_t PLL1CON ; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ 00134 __IO uint32_t PLL1CFG ; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ 00135 __I uint32_t PLL1STAT ; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ 00136 __O uint32_t PLL1FEED ; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ 00137 uint32_t RESERVED2[4]; 00138 __IO uint32_t PCON ; /*!< Offset: 0x0C0 (R/W) Power Control Register */ 00139 __IO uint32_t PCONP ; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ 00140 uint32_t RESERVED3[15]; 00141 __IO uint32_t CCLKCFG ; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */ 00142 __IO uint32_t USBCLKCFG ; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */ 00143 __IO uint32_t CLKSRCSEL ; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ 00144 __IO uint32_t CANSLEEPCLR ; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ 00145 __IO uint32_t CANWAKEFLAGS ; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ 00146 uint32_t RESERVED4[10]; 00147 __IO uint32_t EXTINT ; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ 00148 uint32_t RESERVED5[1]; 00149 __IO uint32_t EXTMODE ; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ 00150 __IO uint32_t EXTPOLAR ; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ 00151 uint32_t RESERVED6[12]; 00152 __IO uint32_t RSID ; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ 00153 uint32_t RESERVED7[7]; 00154 __IO uint32_t SCS ; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ 00155 __IO uint32_t IRCTRIM; /* Clock Dividers */ 00156 __IO uint32_t PCLKSEL0 ; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */ 00157 __IO uint32_t PCLKSEL1 ; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */ 00158 uint32_t RESERVED8[4]; 00159 __IO uint32_t USBIntSt ; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ 00160 __IO uint32_t DMAREQSEL ; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ 00161 __IO uint32_t CLKOUTCFG ; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ 00162 00163 } LPC_SC_TypeDef; 00164 00165 00166 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00167 /** @brief Pin Connect Block (PINCON) register structure definition */ 00168 typedef struct 00169 { 00170 __IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */ 00171 __IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */ 00172 __IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */ 00173 __IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */ 00174 __IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */ 00175 __IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */ 00176 __IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */ 00177 __IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */ 00178 __IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */ 00179 __IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */ 00180 __IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */ 00181 uint32_t RESERVED0[5]; 00182 __IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */ 00183 __IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */ 00184 __IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */ 00185 __IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */ 00186 __IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */ 00187 __IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */ 00188 __IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */ 00189 __IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */ 00190 __IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */ 00191 __IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */ 00192 __IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */ 00193 __IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */ 00194 __IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */ 00195 __IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */ 00196 __IO uint32_t PINMODE_OD4; /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */ 00197 __IO uint32_t I2CPADCFG; /* !< Offset: 0x07C I2C Pad Configure (R/W) */ 00198 } LPC_PINCON_TypeDef; 00199 00200 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00201 /** @brief General Purpose Input/Output (GPIO) register structure definition */ 00202 typedef struct 00203 { 00204 union { 00205 __IO uint32_t FIODIR; /* !< Offset: 0x00 Port direction (R/W) */ 00206 struct { 00207 __IO uint16_t FIODIRL; 00208 __IO uint16_t FIODIRH; 00209 }; 00210 struct { 00211 __IO uint8_t FIODIR0; 00212 __IO uint8_t FIODIR1; 00213 __IO uint8_t FIODIR2; 00214 __IO uint8_t FIODIR3; 00215 }; 00216 }; 00217 uint32_t RESERVED0[3]; 00218 union { 00219 __IO uint32_t FIOMASK; /* !< Offset: 0x10 Port mask (R/W) */ 00220 struct { 00221 __IO uint16_t FIOMASKL; 00222 __IO uint16_t FIOMASKH; 00223 }; 00224 struct { 00225 __IO uint8_t FIOMASK0; 00226 __IO uint8_t FIOMASK1; 00227 __IO uint8_t FIOMASK2; 00228 __IO uint8_t FIOMASK3; 00229 }; 00230 }; 00231 union { 00232 __IO uint32_t FIOPIN; /* !< Offset: 0x14 Port value (R/W) */ 00233 struct { 00234 __IO uint16_t FIOPINL; 00235 __IO uint16_t FIOPINH; 00236 }; 00237 struct { 00238 __IO uint8_t FIOPIN0; 00239 __IO uint8_t FIOPIN1; 00240 __IO uint8_t FIOPIN2; 00241 __IO uint8_t FIOPIN3; 00242 }; 00243 }; 00244 union { 00245 __IO uint32_t FIOSET; /* !< Offset: 0x18 Port output set (R/W) */ 00246 struct { 00247 __IO uint16_t FIOSETL; 00248 __IO uint16_t FIOSETH; 00249 }; 00250 struct { 00251 __IO uint8_t FIOSET0; 00252 __IO uint8_t FIOSET1; 00253 __IO uint8_t FIOSET2; 00254 __IO uint8_t FIOSET3; 00255 }; 00256 }; 00257 union { 00258 __O uint32_t FIOCLR; /* !< Offset: 0x1C Port output clear (R/W) */ 00259 struct { 00260 __O uint16_t FIOCLRL; 00261 __O uint16_t FIOCLRH; 00262 }; 00263 struct { 00264 __O uint8_t FIOCLR0; 00265 __O uint8_t FIOCLR1; 00266 __O uint8_t FIOCLR2; 00267 __O uint8_t FIOCLR3; 00268 }; 00269 }; 00270 } LPC_GPIO_TypeDef; 00271 00272 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */ 00273 typedef struct 00274 { 00275 __I uint32_t IntStatus ; /*!< Offset: 0x000 (R/ ) GPIO overall Interrupt Status Register */ 00276 __I uint32_t IO0IntStatR ; /*!< Offset: 0x004 (R/ ) GPIO Interrupt Status Register 0 for Rising edge */ 00277 __I uint32_t IO0IntStatF ; /*!< Offset: 0x008 (R/ ) GPIO Interrupt Status Register 0 for Falling edge */ 00278 __O uint32_t IO0IntClr ; /*!< Offset: 0x00C (R/W) GPIO Interrupt Clear Register 0 */ 00279 __IO uint32_t IO0IntEnR ; /*!< Offset: 0x010 ( /W) GPIO Interrupt Enable Register 0 for Rising edge */ 00280 __IO uint32_t IO0IntEnF ; /*!< Offset: 0x014 (R/W) GPIO Interrupt Enable Register 0 for Falling edge */ 00281 uint32_t RESERVED0[3]; 00282 __I uint32_t IO2IntStatR ; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Rising edge */ 00283 __I uint32_t IO2IntStatF ; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Falling edge */ 00284 __O uint32_t IO2IntClr ; /*!< Offset: 0x000 ( /W) GPIO Interrupt Clear Register 2 */ 00285 __IO uint32_t IO2IntEnR ; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Rising edge */ 00286 __IO uint32_t IO2IntEnF ; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Falling edge */ 00287 } LPC_GPIOINT_TypeDef; 00288 00289 /*------------- Timer (TIM) --------------------------------------------------*/ 00290 /** @brief Timer (TIM) register structure definition */ 00291 typedef struct 00292 { 00293 __IO uint32_t IR ; /*!< Offset: 0x000 (R/W) Interrupt Register */ 00294 __IO uint32_t TCR ; /*!< Offset: 0x004 (R/W) Timer Control Register */ 00295 __IO uint32_t TC ; /*!< Offset: 0x008 (R/W) Timer Counter Register */ 00296 __IO uint32_t PR ; /*!< Offset: 0x00C (R/W) Prescale Register */ 00297 __IO uint32_t PC ; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ 00298 __IO uint32_t MCR ; /*!< Offset: 0x014 (R/W) Match Control Register */ 00299 __IO uint32_t MR0 ; /*!< Offset: 0x018 (R/W) Match Register 0 */ 00300 __IO uint32_t MR1 ; /*!< Offset: 0x01C (R/W) Match Register 1 */ 00301 __IO uint32_t MR2 ; /*!< Offset: 0x020 (R/W) Match Register 2 */ 00302 __IO uint32_t MR3 ; /*!< Offset: 0x024 (R/W) Match Register 3 */ 00303 __IO uint32_t CCR ; /*!< Offset: 0x028 (R/W) Capture Control Register */ 00304 __I uint32_t CR0 ; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ 00305 __I uint32_t CR1 ; /*!< Offset: 0x030 (R/ ) Capture Register */ 00306 uint32_t RESERVED0[2]; 00307 __IO uint32_t EMR ; /*!< Offset: 0x03C (R/W) External Match Register */ 00308 uint32_t RESERVED1[12]; 00309 __IO uint32_t CTCR ; /*!< Offset: 0x070 (R/W) Count Control Register */ 00310 } LPC_TIM_TypeDef; 00311 00312 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00313 /** @brief Pulse-Width Modulation (PWM) register structure definition */ 00314 typedef struct 00315 { 00316 __IO uint32_t IR ; /*!< Offset: 0x000 (R/W) Interrupt Register */ 00317 __IO uint32_t TCR ; /*!< Offset: 0x004 (R/W) Timer Control Register. Register */ 00318 __IO uint32_t TC ; /*!< Offset: 0x008 (R/W) Timer Counter Register */ 00319 __IO uint32_t PR ; /*!< Offset: 0x00C (R/W) Prescale Register */ 00320 __IO uint32_t PC ; /*!< Offset: 0x010 (R/W) Prescale Counter Register */ 00321 __IO uint32_t MCR ; /*!< Offset: 0x014 (R/W) Match Control Register */ 00322 __IO uint32_t MR0 ; /*!< Offset: 0x018 (R/W) Match Register 0 */ 00323 __IO uint32_t MR1 ; /*!< Offset: 0x01C (R/W) Match Register 1 */ 00324 __IO uint32_t MR2 ; /*!< Offset: 0x020 (R/W) Match Register 2 */ 00325 __IO uint32_t MR3 ; /*!< Offset: 0x024 (R/W) Match Register 3 */ 00326 __IO uint32_t CCR ; /*!< Offset: 0x028 (R/W) Capture Control Register */ 00327 __I uint32_t CR0 ; /*!< Offset: 0x02C (R/ ) Capture Register 0 */ 00328 __I uint32_t CR1 ; /*!< Offset: 0x030 (R/ ) Capture Register 1 */ 00329 __I uint32_t CR2 ; /*!< Offset: 0x034 (R/ ) Capture Register 2 */ 00330 __I uint32_t CR3 ; /*!< Offset: 0x038 (R/ ) Capture Register 3 */ 00331 uint32_t RESERVED0; 00332 __IO uint32_t MR4 ; /*!< Offset: 0x040 (R/W) Match Register 4 */ 00333 __IO uint32_t MR5 ; /*!< Offset: 0x044 (R/W) Match Register 5 */ 00334 __IO uint32_t MR6 ; /*!< Offset: 0x048 (R/W) Match Register 6 */ 00335 __IO uint32_t PCR ; /*!< Offset: 0x04C (R/W) PWM Control Register */ 00336 __IO uint32_t LER ; /*!< Offset: 0x050 (R/W) Load Enable Register */ 00337 uint32_t RESERVED1[7]; 00338 __IO uint32_t CTCR ; /*!< Offset: 0x070 (R/W) Count Control Register */ 00339 } LPC_PWM_TypeDef; 00340 00341 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ 00342 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */ 00343 typedef struct 00344 { 00345 union { 00346 __I uint32_t RBR ; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ 00347 __O uint32_t THR ; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ 00348 __IO uint32_t DLL ; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ 00349 }; 00350 union { 00351 __IO uint32_t DLM ; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ 00352 __IO uint32_t IER ; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */ 00353 }; 00354 union { 00355 __I uint32_t IIR ; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ 00356 __O uint32_t FCR ; /*!< Offset: 0x008 FIFO Control Register ( /W) */ 00357 }; 00358 __IO uint32_t LCR ; /*!< Offset: 0x00C Line Control Register (R/W) */ 00359 uint32_t RESERVED0; 00360 __I uint32_t LSR ; /*!< Offset: 0x014 Line Status Register (R/ ) */ 00361 uint32_t RESERVED1; 00362 __IO uint32_t SCR ; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ 00363 __IO uint32_t ACR ; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ 00364 __IO uint32_t ICR ; /*!< Offset: 0x024 IrDA Control Register (R/W) */ 00365 __IO uint32_t FDR ; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ 00366 uint32_t RESERVED2; 00367 __IO uint32_t TER ; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ 00368 } LPC_UART_TypeDef; 00369 00370 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */ 00371 typedef struct 00372 { 00373 union { 00374 __I uint32_t RBR ; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ 00375 __O uint32_t THR ; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ 00376 __IO uint32_t DLL ; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ 00377 }; 00378 union { 00379 __IO uint32_t DLM ; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ 00380 __IO uint32_t IER ; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ 00381 }; 00382 union { 00383 __I uint32_t IIR ; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ 00384 __O uint32_t FCR ; /*!< Offset: 0x008 FIFO Control Register ( /W) */ 00385 }; 00386 __IO uint32_t LCR ; /*!< Offset: 0x00C Line Control Register (R/W) */ 00387 __IO uint32_t MCR ; /*!< Offset: 0x010 Modem control Register (R/W) */ 00388 __I uint32_t LSR ; /*!< Offset: 0x014 Line Status Register (R/ ) */ 00389 __I uint32_t MSR ; /*!< Offset: 0x018 Modem status Register (R/ ) */ 00390 __IO uint32_t SCR ; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ 00391 __IO uint32_t ACR ; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ 00392 uint32_t RESERVED0; 00393 __IO uint32_t FDR ; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ 00394 uint32_t RESERVED1; 00395 __IO uint32_t TER ; /*!< Offset: 0x030 Transmit Enable Register (R/W) */ 00396 uint32_t RESERVED2[6]; 00397 __IO uint32_t RS485CTRL ; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ 00398 __IO uint32_t ADRMATCH ; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ 00399 __IO uint32_t RS485DLY ; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ 00400 } LPC_UART1_TypeDef; 00401 00402 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ 00403 /** @brief Serial Peripheral Interface (SPI) register structure definition */ 00404 typedef struct 00405 { 00406 __IO uint32_t SPCR ; /*!< Offset: 0x000 SPI Control Register (R/W) */ 00407 __I uint32_t SPSR ; /*!< Offset: 0x004 SPI Status Register (R/) */ 00408 __IO uint32_t SPDR ; /*!< Offset: 0x008 SPI Data Register (R/W) */ 00409 __IO uint32_t SPCCR ; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */ 00410 uint32_t RESERVED0[3]; 00411 __IO uint32_t SPINT ; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */ 00412 } LPC_SPI_TypeDef; 00413 00414 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00415 /** @brief Synchronous Serial Communication (SSP) register structure definition */ 00416 typedef struct 00417 { 00418 __IO uint32_t CR0 ; /*!< Offset: 0x000 (R/W) Control Register 0 */ 00419 __IO uint32_t CR1 ; /*!< Offset: 0x004 (R/W) Control Register 1 */ 00420 __IO uint32_t DR ; /*!< Offset: 0x008 (R/W) Data Register */ 00421 __I uint32_t SR ; /*!< Offset: 0x00C (R/ ) Status Register */ 00422 __IO uint32_t CPSR ; /*!< Offset: 0x010 (R/W) Clock Prescale Register */ 00423 __IO uint32_t IMSC ; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */ 00424 __IO uint32_t RIS ; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */ 00425 __IO uint32_t MIS ; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */ 00426 __IO uint32_t ICR ; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */ 00427 __IO uint32_t DMACR ; /*!< Offset: 0x024 (R/W) DMA Control Register */ 00428 } LPC_SSP_TypeDef; 00429 00430 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00431 /** @brief Inter-Integrated Circuit (I2C) register structure definition */ 00432 typedef struct 00433 { 00434 __IO uint32_t CONSET ; /*!< Offset: 0x000 (R/W) I2C Control Set Register */ 00435 __I uint32_t STAT ; /*!< Offset: 0x004 (R/ ) I2C Status Register */ 00436 __IO uint32_t DAT ; /*!< Offset: 0x008 (R/W) I2C Data Register */ 00437 __IO uint32_t ADR0 ; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */ 00438 __IO uint32_t SCLH ; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */ 00439 __IO uint32_t SCLL ; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */ 00440 __O uint32_t CONCLR ; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */ 00441 __IO uint32_t MMCTRL ; /*!< Offset: 0x01C (R/W) Monitor mode control register */ 00442 __IO uint32_t ADR1 ; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */ 00443 __IO uint32_t ADR2 ; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */ 00444 __IO uint32_t ADR3 ; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */ 00445 __I uint32_t DATA_BUFFER ; /*!< Offset: 0x02C (R/ ) Data buffer Register */ 00446 __IO uint32_t MASK0 ; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */ 00447 __IO uint32_t MASK1 ; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */ 00448 __IO uint32_t MASK2 ; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */ 00449 __IO uint32_t MASK3 ; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */ 00450 } LPC_I2C_TypeDef; 00451 00452 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00453 /** @brief Inter IC Sound (I2S) register structure definition */ 00454 typedef struct 00455 { 00456 __IO uint32_t DAO ; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */ 00457 __IO uint32_t DAI ; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */ 00458 __O uint32_t TXFIFO ; /*!< Offset: 0x008 ( /W) Transmit FIFO */ 00459 __I uint32_t RXFIFO ; /*!< Offset: 0x00C (R/ ) Receive FIFO */ 00460 __I uint32_t STATE ; /*!< Offset: 0x010 (R/W) Status Feedback Register */ 00461 __IO uint32_t DMA1 ; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */ 00462 __IO uint32_t DMA2 ; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */ 00463 __IO uint32_t IRQ ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */ 00464 __IO uint32_t TXRATE ; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */ 00465 __IO uint32_t RXRATE ; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */ 00466 __IO uint32_t TXBITRATE ; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */ 00467 __IO uint32_t RXBITRATE ; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */ 00468 __IO uint32_t TXMODE ; /*!< Offset: 0x030 (R/W) Transmit mode control Register */ 00469 __IO uint32_t RXMODE ; /*!< Offset: 0x034 (R/W) Receive mode control Register */ 00470 } LPC_I2S_TypeDef; 00471 00472 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ 00473 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */ 00474 typedef struct 00475 { 00476 __IO uint32_t RICOMPVAL; 00477 __IO uint32_t RIMASK; 00478 __IO uint32_t RICTRL; 00479 __IO uint32_t RICOUNTER; 00480 } LPC_RIT_TypeDef; 00481 00482 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00483 /** @brief Real-Time Clock (RTC) register structure definition */ 00484 typedef struct 00485 { 00486 __IO uint32_t ILR ; /*!< Offset: 0x000 (R/W) Interrupt Location Register */ 00487 uint32_t RESERVED0; 00488 __IO uint32_t CCR ; /*!< Offset: 0x008 (R/W) Clock Control Register */ 00489 __IO uint32_t CIIR ; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */ 00490 __IO uint32_t AMR ; /*!< Offset: 0x010 (R/W) Alarm Mask Register */ 00491 __I uint32_t CTIME0 ; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */ 00492 __I uint32_t CTIME1 ; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */ 00493 __I uint32_t CTIME2 ; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */ 00494 __IO uint32_t SEC ; /*!< Offset: 0x020 (R/W) Seconds Counter Register */ 00495 __IO uint32_t MIN ; /*!< Offset: 0x024 (R/W) Minutes Register */ 00496 __IO uint32_t HOUR ; /*!< Offset: 0x028 (R/W) Hours Register */ 00497 __IO uint32_t DOM ; /*!< Offset: 0x02C (R/W) Day of Month Register */ 00498 __IO uint32_t DOW ; /*!< Offset: 0x030 (R/W) Day of Week Register */ 00499 __IO uint32_t DOY ; /*!< Offset: 0x034 (R/W) Day of Year Register */ 00500 __IO uint32_t MONTH ; /*!< Offset: 0x038 (R/W) Months Register */ 00501 __IO uint32_t YEAR ; /*!< Offset: 0x03C (R/W) Years Register */ 00502 __IO uint32_t CALIBRATION ; /*!< Offset: 0x040 (R/W) Calibration Value Register */ 00503 __IO uint32_t GPREG0 ; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */ 00504 __IO uint32_t GPREG1 ; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */ 00505 __IO uint32_t GPREG2 ; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */ 00506 __IO uint32_t GPREG3 ; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */ 00507 __IO uint32_t GPREG4 ; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */ 00508 __IO uint32_t RTC_AUXEN ; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */ 00509 __IO uint32_t RTC_AUX ; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */ 00510 __IO uint32_t ALSEC ; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */ 00511 __IO uint32_t ALMIN ; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */ 00512 __IO uint32_t ALHOUR ; /*!< Offset: 0x068 (R/W) Alarm value for Hours */ 00513 __IO uint32_t ALDOM ; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */ 00514 __IO uint32_t ALDOW ; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */ 00515 __IO uint32_t ALDOY ; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */ 00516 __IO uint32_t ALMON ; /*!< Offset: 0x078 (R/W) Alarm value for Months */ 00517 __IO uint32_t ALYEAR ; /*!< Offset: 0x07C (R/W) Alarm value for Year */ 00518 } LPC_RTC_TypeDef; 00519 00520 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00521 /** @brief Watchdog Timer (WDT) register structure definition */ 00522 typedef struct 00523 { 00524 __IO uint32_t MOD ; /*!< Offset: 0x000 (R/W) Watchdog mode Register */ 00525 __IO uint32_t TC ; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */ 00526 __O uint32_t FEED ; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */ 00527 __I uint32_t TV ; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */ 00528 __IO uint32_t WDCLKSEL; 00529 } LPC_WDT_TypeDef; 00530 00531 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00532 /** @brief Analog-to-Digital Converter (ADC) register structure definition */ 00533 typedef struct 00534 { 00535 __IO uint32_t CR ; /*!< Offset: 0x000 (R/W) A/D Control Register */ 00536 __IO uint32_t GDR ; /*!< Offset: 0x004 (R/W) A/D Global Data Register */ 00537 uint32_t RESERVED0; 00538 __IO uint32_t INTEN ; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */ 00539 __I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */ 00540 __I uint32_t STAT ; /*!< Offset: 0x030 (R/ ) A/D Status Register */ 00541 __IO uint32_t ADTRM ; /*!< Offset: 0x034 (R/W) ADC trim Register */ 00542 } LPC_ADC_TypeDef; 00543 00544 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00545 /** @brief Digital-to-Analog Converter (DAC) register structure definition */ 00546 typedef struct 00547 { 00548 __IO uint32_t DACR ; /*!< Offset: 0x000 (R/W) D/A Converter Register */ 00549 __IO uint32_t CTRL ; /*!< Offset: 0x004 (R/W) DAC Control register */ 00550 __IO uint32_t CNTVAL ; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */ 00551 } LPC_DAC_TypeDef; 00552 00553 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00554 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */ 00555 typedef struct 00556 { 00557 __I uint32_t CON ; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */ 00558 __O uint32_t CON_SET ; /*!< Offset: 0x004 ( /W) PWM Control set address Register */ 00559 __O uint32_t CON_CLR ; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */ 00560 __I uint32_t CAPCON ; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */ 00561 __O uint32_t CAPCON_SET ; /*!< Offset: 0x010 ( /W) Capture Control set address Register */ 00562 __O uint32_t CAPCON_CLR ; /*!< Offset: 0x014 ( /W) Event Control clear address Register */ 00563 __IO uint32_t TC0 ; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */ 00564 __IO uint32_t TC1 ; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */ 00565 __IO uint32_t TC2 ; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */ 00566 __IO uint32_t LIM0 ; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */ 00567 __IO uint32_t LIM1 ; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */ 00568 __IO uint32_t LIM2 ; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */ 00569 __IO uint32_t MAT0 ; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */ 00570 __IO uint32_t MAT1 ; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */ 00571 __IO uint32_t MAT2 ; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */ 00572 __IO uint32_t DT ; /*!< Offset: 0x03C (R/W) Dead time Register */ 00573 __IO uint32_t CP ; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */ 00574 __IO uint32_t CAP0 ; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */ 00575 __IO uint32_t CAP1 ; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */ 00576 __IO uint32_t CAP2 ; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */ 00577 __I uint32_t INTEN ; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */ 00578 __O uint32_t INTEN_SET ; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */ 00579 __O uint32_t INTEN_CLR ; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */ 00580 __I uint32_t CNTCON ; /*!< Offset: 0x05C (R/ ) Count Control read address Register */ 00581 __O uint32_t CNTCON_SET ; /*!< Offset: 0x060 ( /W) Count Control set address Register */ 00582 __O uint32_t CNTCON_CLR ; /*!< Offset: 0x064 ( /W) Count Control clear address Register */ 00583 __I uint32_t INTF ; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */ 00584 __O uint32_t INTF_SET ; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */ 00585 __O uint32_t INTF_CLR ; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */ 00586 __O uint32_t CAP_CLR ; /*!< Offset: 0x074 ( /W) Capture clear address Register */ 00587 } LPC_MCPWM_TypeDef; 00588 00589 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00590 /** @brief Quadrature Encoder Interface (QEI) register structure definition */ 00591 typedef struct 00592 { 00593 __O uint32_t CON ; /*!< Offset: 0x000 ( /W) Control Register */ 00594 __I uint32_t STAT ; /*!< Offset: 0x004 (R/ ) Encoder Status Register */ 00595 __IO uint32_t CONF ; /*!< Offset: 0x008 (R/W) Configuration Register */ 00596 __I uint32_t POS ; /*!< Offset: 0x00C (R/ ) Position Register */ 00597 __IO uint32_t MAXPOS ; /*!< Offset: 0x010 (R/W) Maximum position Register */ 00598 __IO uint32_t CMPOS0 ; /*!< Offset: 0x014 (R/W) Position compare Register 0 */ 00599 __IO uint32_t CMPOS1 ; /*!< Offset: 0x018 (R/W) Position compare Register 1 */ 00600 __IO uint32_t CMPOS2 ; /*!< Offset: 0x01C (R/W) Position compare Register 2 */ 00601 __I uint32_t INXCNT ; /*!< Offset: 0x020 (R/ ) Index count Register */ 00602 __IO uint32_t INXCMP0 ; /*!< Offset: 0x024 (R/W) Index compare Register 0 */ 00603 __IO uint32_t LOAD ; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */ 00604 __I uint32_t TIME ; /*!< Offset: 0x02C (R/ ) Velocity timer Register */ 00605 __I uint32_t VEL ; /*!< Offset: 0x030 (R/ ) Velocity counter Register */ 00606 __I uint32_t CAP ; /*!< Offset: 0x034 (R/ ) Velocity capture Register */ 00607 __IO uint32_t VELCOMP ; /*!< Offset: 0x038 (R/W) Velocity compare Register */ 00608 __IO uint32_t FILTER; 00609 uint32_t RESERVED0[998]; 00610 __O uint32_t IEC ; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */ 00611 __O uint32_t IES ; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */ 00612 __I uint32_t INTSTAT ; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */ 00613 __I uint32_t IE ; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */ 00614 __O uint32_t CLR ; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */ 00615 __O uint32_t SET ; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */ 00616 } LPC_QEI_TypeDef; 00617 00618 /*------------- Controller Area Network (CAN) --------------------------------*/ 00619 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */ 00620 typedef struct 00621 { 00622 __IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */ 00623 } LPC_CANAF_RAM_TypeDef; 00624 00625 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */ 00626 typedef struct /* Acceptance Filter Registers */ 00627 { 00628 __IO uint32_t AFMR ; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */ 00629 __IO uint32_t SFF_sa ; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */ 00630 __IO uint32_t SFF_GRP_sa ; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */ 00631 __IO uint32_t EFF_sa ; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */ 00632 __IO uint32_t EFF_GRP_sa ; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */ 00633 __IO uint32_t ENDofTable ; /*!< Offset: 0x014 (R/W) End of AF Tables Register */ 00634 __I uint32_t LUTerrAd ; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */ 00635 __I uint32_t LUTerr ; /*!< Offset: 0x01C (R/ ) LUT Error Register */ 00636 __IO uint32_t FCANIE ; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */ 00637 __IO uint32_t FCANIC0 ; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */ 00638 __IO uint32_t FCANIC1 ; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */ 00639 } LPC_CANAF_TypeDef; 00640 00641 /** @brief Controller Area Network Central (CANCR) register structure definition */ 00642 typedef struct /* Central Registers */ 00643 { 00644 __I uint32_t TxSR ; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */ 00645 __I uint32_t RxSR ; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */ 00646 __I uint32_t MSR ; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */ 00647 } LPC_CANCR_TypeDef; 00648 00649 /** @brief Controller Area Network Controller (CAN) register structure definition */ 00650 typedef struct /* Controller Registers */ 00651 { 00652 __IO uint32_t MOD ; /*!< Offset: 0x000 (R/W) CAN Mode Register */ 00653 __O uint32_t CMR ; /*!< Offset: 0x004 ( /W) CAN Command Register */ 00654 __IO uint32_t GSR ; /*!< Offset: 0x008 (R/W) CAN Global Status Register */ 00655 __I uint32_t ICR ; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */ 00656 __IO uint32_t IER ; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */ 00657 __IO uint32_t BTR ; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */ 00658 __IO uint32_t EWL ; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */ 00659 __I uint32_t SR ; /*!< Offset: 0x01C (R/ ) CAN Status Register */ 00660 __IO uint32_t RFS ; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */ 00661 __IO uint32_t RID ; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */ 00662 __IO uint32_t RDA ; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */ 00663 __IO uint32_t RDB ; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */ 00664 __IO uint32_t TFI1 ; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */ 00665 __IO uint32_t TID1 ; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */ 00666 __IO uint32_t TDA1 ; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */ 00667 __IO uint32_t TDB1 ; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */ 00668 __IO uint32_t TFI2 ; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */ 00669 __IO uint32_t TID2 ; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */ 00670 __IO uint32_t TDA2 ; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */ 00671 __IO uint32_t TDB2 ; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */ 00672 __IO uint32_t TFI3 ; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */ 00673 __IO uint32_t TID3 ; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */ 00674 __IO uint32_t TDA3 ; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */ 00675 __IO uint32_t TDB3 ; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */ 00676 } LPC_CAN_TypeDef; 00677 00678 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00679 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */ 00680 typedef struct /* Common Registers */ 00681 { 00682 __I uint32_t IntStat ; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */ 00683 __I uint32_t IntTCStat ; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */ 00684 __O uint32_t IntTCClear ; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */ 00685 __I uint32_t IntErrStat ; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */ 00686 __O uint32_t IntErrClr ; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */ 00687 __I uint32_t RawIntTCStat ; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */ 00688 __I uint32_t RawIntErrStat ; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */ 00689 __I uint32_t EnbldChns ; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */ 00690 __IO uint32_t SoftBReq ; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */ 00691 __IO uint32_t SoftSReq ; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */ 00692 __IO uint32_t SoftLBReq ; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */ 00693 __IO uint32_t SoftLSReq ; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */ 00694 __IO uint32_t Config ; /*!< Offset: 0x030 (R/W) DMA Configuration Register */ 00695 __IO uint32_t Sync ; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */ 00696 } LPC_GPDMA_TypeDef; 00697 00698 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */ 00699 typedef struct /* Channel Registers */ 00700 { 00701 __IO uint32_t CSrcAddr ; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */ 00702 __IO uint32_t CDestAddr ; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */ 00703 __IO uint32_t CLLI ; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */ 00704 __IO uint32_t CControl ; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */ 00705 __IO uint32_t CConfig ; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */ 00706 } LPC_GPDMACH_TypeDef; 00707 00708 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00709 /** @brief Universal Serial Bus (USB) register structure definition */ 00710 typedef struct 00711 { 00712 __I uint32_t Revision ; /*!< Offset: 0x000 (R/ ) Revision Register */ 00713 __IO uint32_t Control ; /*!< Offset: 0x004 (R/W) Control Register */ 00714 __IO uint32_t CommandStatus ; /*!< Offset: 0x008 (R/W) Command / Status Register */ 00715 __IO uint32_t InterruptStatus ; /*!< Offset: 0x00C (R/W) Interrupt Status Register */ 00716 __IO uint32_t InterruptEnable ; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */ 00717 __IO uint32_t InterruptDisable ; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */ 00718 __IO uint32_t HCCA ; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */ 00719 __I uint32_t PeriodCurrentED ; /*!< Offset: 0x01C (R/ ) Register */ 00720 __IO uint32_t ControlHeadED ; /*!< Offset: 0x020 (R/W) Register */ 00721 __IO uint32_t ControlCurrentED ; /*!< Offset: 0x024 (R/W) Register */ 00722 __IO uint32_t BulkHeadED ; /*!< Offset: 0x028 (R/W) Register */ 00723 __IO uint32_t BulkCurrentED ; /*!< Offset: 0x02C (R/W) Register */ 00724 __I uint32_t DoneHead ; /*!< Offset: 0x030 (R/ ) Register */ 00725 __IO uint32_t FmInterval ; /*!< Offset: 0x034 (R/W) Register */ 00726 __I uint32_t FmRemaining ; /*!< Offset: 0x038 (R/ ) Register */ 00727 __I uint32_t FmNumber ; /*!< Offset: 0x03C (R/ ) Register */ 00728 __IO uint32_t PeriodicStart ; /*!< Offset: 0x040 (R/W) Register */ 00729 __IO uint32_t LSTreshold ; /*!< Offset: 0x044 (R/W) Register */ 00730 __IO uint32_t RhDescriptorA ; /*!< Offset: 0x048 (R/W) Register */ 00731 __IO uint32_t RhDescriptorB ; /*!< Offset: 0x04C (R/W) Register */ 00732 __IO uint32_t RhStatus ; /*!< Offset: 0x050 (R/W) Register */ 00733 __IO uint32_t RhPortStatus1 ; /*!< Offset: 0x054 (R/W) Register */ 00734 __IO uint32_t RhPortStatus2 ; /*!< Offset: 0x05C (R/W) Register */ 00735 uint32_t RESERVED0[40]; 00736 __I uint32_t Module_ID ; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */ 00737 /* USB On-The-Go Registers */ 00738 __I uint32_t IntSt ; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */ 00739 __IO uint32_t IntEn ; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */ 00740 __O uint32_t IntSet ; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */ 00741 __O uint32_t IntClr ; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */ 00742 __IO uint32_t StCtrl ; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */ 00743 __IO uint32_t Tmr ; /*!< Offset: 0x114 (R/W) OTG Timer Register */ 00744 uint32_t RESERVED1[58]; 00745 /* USB Device Interrupt Registers */ 00746 __I uint32_t DevIntSt ; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */ 00747 __IO uint32_t DevIntEn ; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */ 00748 __O uint32_t DevIntClr ; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */ 00749 __O uint32_t DevIntSet ; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */ 00750 /* USB Device SIE Command Registers */ 00751 __O uint32_t CmdCode ; /*!< Offset: 0x210 (R/W) USB Command Code Register */ 00752 __I uint32_t CmdData ; /*!< Offset: 0x214 (R/W) USB Command Data Register */ 00753 /* USB Device Transfer Registers */ 00754 __I uint32_t RxData ; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */ 00755 __O uint32_t TxData ; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */ 00756 __I uint32_t RxPLen ; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */ 00757 __O uint32_t TxPLen ; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */ 00758 __IO uint32_t Ctrl ; /*!< Offset: 0x228 (R/W) USB Control Register */ 00759 __O uint32_t DevIntPri ; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */ 00760 /* USB Device Endpoint Interrupt Regs */ 00761 __I uint32_t EpIntSt ; /*!< Offset: 0x230 (R/ ) USB Endpoint Interrupt Status Register */ 00762 __IO uint32_t EpIntEn ; /*!< Offset: 0x234 (R/W) USB Endpoint Interrupt Enable Register */ 00763 __O uint32_t EpIntClr ; /*!< Offset: 0x238 ( /W) USB Endpoint Interrupt Clear Register */ 00764 __O uint32_t EpIntSet ; /*!< Offset: 0x23C ( /W) USB Endpoint Interrupt Set Register */ 00765 __O uint32_t EpIntPri ; /*!< Offset: 0x240 ( /W) USB Endpoint Interrupt Priority Register */ 00766 /* USB Device Endpoint Realization Reg*/ 00767 __IO uint32_t ReEp ; /*!< Offset: 0x244 (R/W) USB Realize Endpoint Register */ 00768 __O uint32_t EpInd ; /*!< Offset: 0x248 ( /W) USB Endpoint Index Register */ 00769 __IO uint32_t MaxPSize ; /*!< Offset: 0x24C (R/W) USB MaxPacketSize Register */ 00770 /* USB Device DMA Registers */ 00771 __I uint32_t DMARSt ; /*!< Offset: 0x250 (R/ ) USB DMA Request Status Register */ 00772 __O uint32_t DMARClr ; /*!< Offset: 0x254 ( /W) USB DMA Request Clear Register */ 00773 __O uint32_t DMARSet ; /*!< Offset: 0x258 ( /W) USB DMA Request Set Register */ 00774 uint32_t RESERVED2[9]; 00775 __IO uint32_t UDCAH ; /*!< Offset: 0x280 (R/W) USB UDCA Head Register */ 00776 __I uint32_t EpDMASt ; /*!< Offset: 0x284 (R/ ) USB EP DMA Status Register */ 00777 __O uint32_t EpDMAEn ; /*!< Offset: 0x288 ( /W) USB EP DMA Enable Register */ 00778 __O uint32_t EpDMADis ; /*!< Offset: 0x28C ( /W) USB EP DMA Disable Register */ 00779 __I uint32_t DMAIntSt ; /*!< Offset: 0x290 (R/ ) USB DMA Interrupt Status Register */ 00780 __IO uint32_t DMAIntEn ; /*!< Offset: 0x294 (R/W) USB DMA Interrupt Enable Register */ 00781 uint32_t RESERVED3[2]; 00782 __I uint32_t EoTIntSt ; /*!< Offset: 0x2A0 (R/ ) USB End of Transfer Interrupt Status Register */ 00783 __O uint32_t EoTIntClr ; /*!< Offset: 0x2A4 ( /W) USB End of Transfer Interrupt Clear Register */ 00784 __O uint32_t EoTIntSet ; /*!< Offset: 0x2A8 ( /W) USB End of Transfer Interrupt Set Register */ 00785 __I uint32_t NDDRIntSt ; /*!< Offset: 0x2AC (R/ ) USB New DD Request Interrupt Status Register */ 00786 __O uint32_t NDDRIntClr ; /*!< Offset: 0x2B0 ( /W) USB New DD Request Interrupt Clear Register */ 00787 __O uint32_t NDDRIntSet ; /*!< Offset: 0x2B4 ( /W) USB New DD Request Interrupt Set Register */ 00788 __I uint32_t SysErrIntSt ; /*!< Offset: 0x2B8 (R/ ) USB System Error Interrupt Status Register */ 00789 __O uint32_t SysErrIntClr ; /*!< Offset: 0x2BC ( /W) USB System Error Interrupt Clear Register */ 00790 __O uint32_t SysErrIntSet ; /*!< Offset: 0x2C0 ( /W) USB System Error Interrupt Set Register */ 00791 uint32_t RESERVED4[15]; 00792 /* USB OTG I2C Registers */ 00793 union { 00794 __I uint32_t I2C_RX ; /*!< Offset: 0x300 (R/ ) OTG I2C Receive Register */ 00795 __O uint32_t I2C_TX ; /*!< Offset: 0x300 ( /W) OTG I2C Transmit Register */ 00796 }; 00797 __I uint32_t I2C_STS ; /*!< Offset: 0x304 (R/ ) OTG I2C Status Register */ 00798 __IO uint32_t I2C_CTL ; /*!< Offset: 0x308 (R/W) OTG I2C Control Register */ 00799 __IO uint32_t I2C_CLKHI ; /*!< Offset: 0x30C (R/W) OTG I2C Clock High Register */ 00800 __O uint32_t I2C_CLKLO ; /*!< Offset: 0x310 ( /W) OTG I2C Clock Low Register */ 00801 uint32_t RESERVED5[824]; 00802 /* USB Clock Control Registers */ 00803 union { 00804 __IO uint32_t USBClkCtrl ; /*!< Offset: 0xFF4 (R/W) OTG clock controller Register */ 00805 __IO uint32_t OTGClkCtrl ; /*!< Offset: 0xFF4 (R/W) USB clock controller Register */ 00806 }; 00807 union { 00808 __I uint32_t USBClkSt ; /*!< Offset: 0xFF8 (R/ ) OTG clock status Register */ 00809 __I uint32_t OTGClkSt ; /*!< Offset: 0xFF8 (R/ ) USB clock status Register */ 00810 }; 00811 } LPC_USB_TypeDef; 00812 00813 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00814 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */ 00815 typedef struct 00816 { 00817 __IO uint32_t MAC1 ; /*!< Offset: 0x000 (R/W) MAC Configuration Register 1 */ 00818 __IO uint32_t MAC2 ; /*!< Offset: 0x004 (R/W) MAC Configuration Register 2 */ 00819 __IO uint32_t IPGT ; /*!< Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register */ 00820 __IO uint32_t IPGR ; /*!< Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register */ 00821 __IO uint32_t CLRT ; /*!< Offset: 0x010 (R/W) Collision Window / Retry Register */ 00822 __IO uint32_t MAXF ; /*!< Offset: 0x014 (R/W) Maximum Frame Register */ 00823 __IO uint32_t SUPP ; /*!< Offset: 0x018 (R/W) PHY Support Register */ 00824 __IO uint32_t TEST ; /*!< Offset: 0x01C (R/W) Test Register */ 00825 __IO uint32_t MCFG ; /*!< Offset: 0x020 (R/W) MII Mgmt Configuration Register */ 00826 __IO uint32_t MCMD ; /*!< Offset: 0x024 (R/W) MII Mgmt Command Register */ 00827 __IO uint32_t MADR ; /*!< Offset: 0x028 (R/W) MII Mgmt Address Register */ 00828 __O uint32_t MWTD ; /*!< Offset: 0x02C ( /W) MII Mgmt Write Data Register */ 00829 __I uint32_t MRDD ; /*!< Offset: 0x030 (R/ ) MII Mgmt Read Data Register */ 00830 __I uint32_t MIND ; /*!< Offset: 0x034 (R/ ) MII Mgmt Indicators Register */ 00831 uint32_t RESERVED0[2]; 00832 __IO uint32_t SA0 ; /*!< Offset: 0x040 (R/W) Station Address 0 Register */ 00833 __IO uint32_t SA1 ; /*!< Offset: 0x044 (R/W) Station Address 1 Register */ 00834 __IO uint32_t SA2 ; /*!< Offset: 0x048 (R/W) Station Address 2 Register */ 00835 uint32_t RESERVED1[45]; 00836 __IO uint32_t Command ; /*!< Offset: 0x100 (R/W) Command Register */ 00837 __I uint32_t Status ; /*!< Offset: 0x104 (R/ ) Status Register */ 00838 __IO uint32_t RxDescriptor ; /*!< Offset: 0x108 (R/W) Receive Descriptor Base Address Register */ 00839 __IO uint32_t RxStatus ; /*!< Offset: 0x10C (R/W) Receive Status Base Address Register */ 00840 __IO uint32_t RxDescriptorNumber ; /*!< Offset: 0x110 (R/W) Receive Number of Descriptors Register */ 00841 __I uint32_t RxProduceIndex ; /*!< Offset: 0x114 (R/ ) Receive Produce Index Register */ 00842 __IO uint32_t RxConsumeIndex ; /*!< Offset: 0x118 (R/W) Receive Consume Index Register */ 00843 __IO uint32_t TxDescriptor ; /*!< Offset: 0x11C (R/W) Transmit Descriptor Base Address Register */ 00844 __IO uint32_t TxStatus ; /*!< Offset: 0x120 (R/W) Transmit Status Base Address Register */ 00845 __IO uint32_t TxDescriptorNumber ; /*!< Offset: 0x124 (R/W) Transmit Number of Descriptors Register */ 00846 __IO uint32_t TxProduceIndex ; /*!< Offset: 0x128 (R/W) Transmit Produce Index Register */ 00847 __I uint32_t TxConsumeIndex ; /*!< Offset: 0x12C (R/ ) Transmit Consume Index Register */ 00848 uint32_t RESERVED2[10]; 00849 __I uint32_t TSV0 ; /*!< Offset: 0x158 (R/ ) Transmit Status Vector 0 Register */ 00850 __I uint32_t TSV1 ; /*!< Offset: 0x15C (R/ ) Transmit Status Vector 1 Register */ 00851 __I uint32_t RSV ; /*!< Offset: 0x160 (R/ ) Receive Status Vector Register */ 00852 uint32_t RESERVED3[3]; 00853 __IO uint32_t FlowControlCounter ; /*!< Offset: 0x170 (R/W) Flow Control Counter Register */ 00854 __I uint32_t FlowControlStatus ; /*!< Offset: 0x174 (R/ ) Flow Control Status egister */ 00855 uint32_t RESERVED4[34]; 00856 __IO uint32_t RxFilterCtrl ; /*!< Offset: 0x200 (R/W) Receive Filter Control Register */ 00857 __I uint32_t RxFilterWoLStatus ; /*!< Offset: 0x204 (R/ ) Receive Filter WoL Status Register */ 00858 __O uint32_t RxFilterWoLClear ; /*!< Offset: 0x208 ( /W) Receive Filter WoL Clear Register */ 00859 uint32_t RESERVED5; 00860 __IO uint32_t HashFilterL ; /*!< Offset: 0x210 (R/W) Hash Filter Table LSBs Register */ 00861 __IO uint32_t HashFilterH ; /*!< Offset: 0x214 (R/W) Hash Filter Table MSBs Register */ 00862 uint32_t RESERVED6[882]; 00863 __I uint32_t IntStatus ; /*!< Offset: 0xFE0 (R/ ) Interrupt Status Register */ 00864 __IO uint32_t IntEnable ; /*!< Offset: 0xFE4 (R/W) Interrupt Enable Register */ 00865 __O uint32_t IntClear ; /*!< Offset: 0xFE8 ( /W) Interrupt Clear Register */ 00866 __O uint32_t IntSet ; /*!< Offset: 0xFEC ( /W) Interrupt Set Register */ 00867 uint32_t RESERVED7; 00868 __IO uint32_t PowerDown ; /*!< Offset: 0xFF4 (R/W) Power-Down Register */ 00869 } LPC_EMAC_TypeDef; 00870 00871 #if defined ( __CC_ARM ) 00872 #pragma no_anon_unions 00873 #endif 00874 00875 00876 /******************************************************************************/ 00877 /* Peripheral memory map */ 00878 /******************************************************************************/ 00879 /* Base addresses */ 00880 #define LPC_FLASH_BASE (0x00000000UL) 00881 #define LPC_RAM_BASE (0x10000000UL) 00882 #ifdef __LPC17XX_REV00 00883 #define LPC_AHBRAM0_BASE (0x20000000UL) 00884 #define LPC_AHBRAM1_BASE (0x20004000UL) 00885 #else 00886 #define LPC_AHBRAM0_BASE (0x2007C000UL) 00887 #define LPC_AHBRAM1_BASE (0x20080000UL) 00888 #endif 00889 #define LPC_GPIO_BASE (0x2009C000UL) 00890 #define LPC_APB0_BASE (0x40000000UL) 00891 #define LPC_APB1_BASE (0x40080000UL) 00892 #define LPC_AHB_BASE (0x50000000UL) 00893 #define LPC_CM3_BASE (0xE0000000UL) 00894 00895 /* APB0 peripherals */ 00896 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 00897 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 00898 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 00899 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 00900 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 00901 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 00902 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 00903 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) 00904 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 00905 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 00906 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) 00907 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 00908 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 00909 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 00910 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 00911 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 00912 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 00913 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 00914 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 00915 00916 /* APB1 peripherals */ 00917 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 00918 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 00919 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 00920 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 00921 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 00922 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 00923 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 00924 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 00925 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) 00926 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 00927 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 00928 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 00929 00930 /* AHB peripherals */ 00931 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) 00932 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) 00933 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) 00934 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) 00935 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) 00936 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) 00937 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) 00938 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) 00939 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) 00940 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) 00941 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 00942 00943 /* GPIOs */ 00944 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) 00945 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) 00946 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) 00947 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) 00948 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) 00949 00950 00951 /******************************************************************************/ 00952 /* Peripheral declaration */ 00953 /******************************************************************************/ 00954 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 00955 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 00956 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 00957 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 00958 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 00959 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 00960 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 00961 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 00962 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 00963 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 00964 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 00965 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) 00966 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) 00967 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 00968 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 00969 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 00970 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 00971 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 00972 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 00973 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 00974 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 00975 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) 00976 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 00977 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 00978 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) 00979 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 00980 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 00981 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 00982 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 00983 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 00984 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 00985 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 00986 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 00987 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 00988 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 00989 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 00990 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 00991 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 00992 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 00993 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 00994 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 00995 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 00996 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 00997 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 00998 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 00999 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01000 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01001 01002 01003 /** 01004 * @} 01005 */ 01006 01007 #endif // __LPC17xx_H__ 01008
Generated on Thu Jul 14 2022 02:34:42 by
1.7.2