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Dependencies:   mbed

Fork of LG2 by Dmitry Kovalev

host/Source/App/LPC17xx.h@23:12e6183f04d4, 2016-02-03 (annotated)

Committer:
Kovalev_D
Date:
Wed Feb 03 10:44:42 2016 +0300
Revision:
23:12e6183f04d4
[thyz

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kovalev_D 23:12e6183f04d4 1 /******************************************************************************
Kovalev_D 23:12e6183f04d4 2 * @file: LPC17xx.h
Kovalev_D 23:12e6183f04d4 3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
Kovalev_D 23:12e6183f04d4 4 * NXP LPC17xx Device Series
Kovalev_D 23:12e6183f04d4 5 * @version: V1.10
Kovalev_D 23:12e6183f04d4 6 * @date: 24. September 2010
Kovalev_D 23:12e6183f04d4 7 *----------------------------------------------------------------------------
Kovalev_D 23:12e6183f04d4 8 *
Kovalev_D 23:12e6183f04d4 9 * @note
Kovalev_D 23:12e6183f04d4 10 * Copyright (C) 2010 ARM Limited. All rights reserved.
Kovalev_D 23:12e6183f04d4 11 *
Kovalev_D 23:12e6183f04d4 12 * @par
Kovalev_D 23:12e6183f04d4 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M3
Kovalev_D 23:12e6183f04d4 14 * processor based microcontrollers. This file can be freely distributed
Kovalev_D 23:12e6183f04d4 15 * within development tools that are supporting such ARM based processors.
Kovalev_D 23:12e6183f04d4 16 *
Kovalev_D 23:12e6183f04d4 17 * @par
Kovalev_D 23:12e6183f04d4 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Kovalev_D 23:12e6183f04d4 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Kovalev_D 23:12e6183f04d4 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Kovalev_D 23:12e6183f04d4 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Kovalev_D 23:12e6183f04d4 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Kovalev_D 23:12e6183f04d4 23 *
Kovalev_D 23:12e6183f04d4 24 ******************************************************************************/
Kovalev_D 23:12e6183f04d4 25
Kovalev_D 23:12e6183f04d4 26
Kovalev_D 23:12e6183f04d4 27 #ifndef __LPC17xx_H__
Kovalev_D 23:12e6183f04d4 28 #define __LPC17xx_H__
Kovalev_D 23:12e6183f04d4 29
Kovalev_D 23:12e6183f04d4 30 /*
Kovalev_D 23:12e6183f04d4 31 * ==========================================================================
Kovalev_D 23:12e6183f04d4 32 * ---------- Interrupt Number Definition -----------------------------------
Kovalev_D 23:12e6183f04d4 33 * ==========================================================================
Kovalev_D 23:12e6183f04d4 34 */
Kovalev_D 23:12e6183f04d4 35
Kovalev_D 23:12e6183f04d4 36 /** @addtogroup LPC17xx_System
Kovalev_D 23:12e6183f04d4 37 * @{
Kovalev_D 23:12e6183f04d4 38 */
Kovalev_D 23:12e6183f04d4 39 #define rISER0 (*(volatile unsigned *)0xE000E100)
Kovalev_D 23:12e6183f04d4 40 #define rICER0 (*(volatile unsigned *)0xE000E180)
Kovalev_D 23:12e6183f04d4 41 #define rISPR0 (*(volatile unsigned *)0xE000E200)
Kovalev_D 23:12e6183f04d4 42 #define rICPR0 (*(volatile unsigned *)0xE000E280)
Kovalev_D 23:12e6183f04d4 43 #define rIABR0 (*(volatile unsigned *)0xE000E300)
Kovalev_D 23:12e6183f04d4 44
Kovalev_D 23:12e6183f04d4 45
Kovalev_D 23:12e6183f04d4 46 /** @brief IRQ interrupt source definition */
Kovalev_D 23:12e6183f04d4 47 typedef enum IRQn
Kovalev_D 23:12e6183f04d4 48 {
Kovalev_D 23:12e6183f04d4 49 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
Kovalev_D 23:12e6183f04d4 50 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kovalev_D 23:12e6183f04d4 51 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Kovalev_D 23:12e6183f04d4 52 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Kovalev_D 23:12e6183f04d4 53 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Kovalev_D 23:12e6183f04d4 54 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Kovalev_D 23:12e6183f04d4 55 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Kovalev_D 23:12e6183f04d4 56 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Kovalev_D 23:12e6183f04d4 57 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Kovalev_D 23:12e6183f04d4 58
Kovalev_D 23:12e6183f04d4 59 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
Kovalev_D 23:12e6183f04d4 60 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
Kovalev_D 23:12e6183f04d4 61 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
Kovalev_D 23:12e6183f04d4 62 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
Kovalev_D 23:12e6183f04d4 63 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
Kovalev_D 23:12e6183f04d4 64 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
Kovalev_D 23:12e6183f04d4 65 UART0_IRQn = 5, /*!< UART0 Interrupt */
Kovalev_D 23:12e6183f04d4 66 UART1_IRQn = 6, /*!< UART1 Interrupt */
Kovalev_D 23:12e6183f04d4 67 UART2_IRQn = 7, /*!< UART2 Interrupt */
Kovalev_D 23:12e6183f04d4 68 UART3_IRQn = 8, /*!< UART3 Interrupt */
Kovalev_D 23:12e6183f04d4 69 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
Kovalev_D 23:12e6183f04d4 70 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
Kovalev_D 23:12e6183f04d4 71 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
Kovalev_D 23:12e6183f04d4 72 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
Kovalev_D 23:12e6183f04d4 73 SPI_IRQn = 13, /*!< SPI Interrupt */
Kovalev_D 23:12e6183f04d4 74 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
Kovalev_D 23:12e6183f04d4 75 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
Kovalev_D 23:12e6183f04d4 76 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
Kovalev_D 23:12e6183f04d4 77 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
Kovalev_D 23:12e6183f04d4 78 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
Kovalev_D 23:12e6183f04d4 79 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
Kovalev_D 23:12e6183f04d4 80 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
Kovalev_D 23:12e6183f04d4 81 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
Kovalev_D 23:12e6183f04d4 82 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
Kovalev_D 23:12e6183f04d4 83 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
Kovalev_D 23:12e6183f04d4 84 USB_IRQn = 24, /*!< USB Interrupt */
Kovalev_D 23:12e6183f04d4 85 CAN_IRQn = 25, /*!< CAN Interrupt */
Kovalev_D 23:12e6183f04d4 86 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
Kovalev_D 23:12e6183f04d4 87 I2S_IRQn = 27, /*!< I2S Interrupt */
Kovalev_D 23:12e6183f04d4 88 ENET_IRQn = 28, /*!< Ethernet Interrupt */
Kovalev_D 23:12e6183f04d4 89 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
Kovalev_D 23:12e6183f04d4 90 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
Kovalev_D 23:12e6183f04d4 91 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
Kovalev_D 23:12e6183f04d4 92 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
Kovalev_D 23:12e6183f04d4 93 USBActivity_IRQn = 33, /*!< USB Activity Interrupt(For wakeup only) */
Kovalev_D 23:12e6183f04d4 94 CANActivity_IRQn = 34 /*!< CAN Activity Interrupt(For wakeup only) */
Kovalev_D 23:12e6183f04d4 95 } IRQn_Type;
Kovalev_D 23:12e6183f04d4 96
Kovalev_D 23:12e6183f04d4 97
Kovalev_D 23:12e6183f04d4 98 /*
Kovalev_D 23:12e6183f04d4 99 * ==========================================================================
Kovalev_D 23:12e6183f04d4 100 * ----------- Processor and Core Peripheral Section ------------------------
Kovalev_D 23:12e6183f04d4 101 * ==========================================================================
Kovalev_D 23:12e6183f04d4 102 */
Kovalev_D 23:12e6183f04d4 103
Kovalev_D 23:12e6183f04d4 104 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
Kovalev_D 23:12e6183f04d4 105 #define __MPU_PRESENT 1 /*!< MPU present or not */
Kovalev_D 23:12e6183f04d4 106 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
Kovalev_D 23:12e6183f04d4 107 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kovalev_D 23:12e6183f04d4 108
Kovalev_D 23:12e6183f04d4 109
Kovalev_D 23:12e6183f04d4 110 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
Kovalev_D 23:12e6183f04d4 111 #include "system_LPC17xx.h" /* System Header */
Kovalev_D 23:12e6183f04d4 112
Kovalev_D 23:12e6183f04d4 113
Kovalev_D 23:12e6183f04d4 114 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 115 /* Device Specific Peripheral registers structures */
Kovalev_D 23:12e6183f04d4 116 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 117
Kovalev_D 23:12e6183f04d4 118 #if defined ( __CC_ARM )
Kovalev_D 23:12e6183f04d4 119 #pragma anon_unions
Kovalev_D 23:12e6183f04d4 120 #endif
Kovalev_D 23:12e6183f04d4 121
Kovalev_D 23:12e6183f04d4 122 /*------------- System Control (SC) ------------------------------------------*/
Kovalev_D 23:12e6183f04d4 123 /** @brief System Control (SC) register structure definition */
Kovalev_D 23:12e6183f04d4 124 typedef struct
Kovalev_D 23:12e6183f04d4 125 {
Kovalev_D 23:12e6183f04d4 126 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
Kovalev_D 23:12e6183f04d4 127 uint32_t RESERVED0[31];
Kovalev_D 23:12e6183f04d4 128 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
Kovalev_D 23:12e6183f04d4 129 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
Kovalev_D 23:12e6183f04d4 130 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
Kovalev_D 23:12e6183f04d4 131 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
Kovalev_D 23:12e6183f04d4 132 uint32_t RESERVED1[4];
Kovalev_D 23:12e6183f04d4 133 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
Kovalev_D 23:12e6183f04d4 134 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
Kovalev_D 23:12e6183f04d4 135 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
Kovalev_D 23:12e6183f04d4 136 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
Kovalev_D 23:12e6183f04d4 137 uint32_t RESERVED2[4];
Kovalev_D 23:12e6183f04d4 138 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
Kovalev_D 23:12e6183f04d4 139 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
Kovalev_D 23:12e6183f04d4 140 uint32_t RESERVED3[15];
Kovalev_D 23:12e6183f04d4 141 __IO uint32_t CCLKCFG; /*!< Offset: 0x104 (R/W) CPU Clock Configure Register */
Kovalev_D 23:12e6183f04d4 142 __IO uint32_t USBCLKCFG; /*!< Offset: 0x108 (R/W) USB Clock Configure Register */
Kovalev_D 23:12e6183f04d4 143 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
Kovalev_D 23:12e6183f04d4 144 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
Kovalev_D 23:12e6183f04d4 145 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
Kovalev_D 23:12e6183f04d4 146 uint32_t RESERVED4[10];
Kovalev_D 23:12e6183f04d4 147 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
Kovalev_D 23:12e6183f04d4 148 uint32_t RESERVED5[1];
Kovalev_D 23:12e6183f04d4 149 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
Kovalev_D 23:12e6183f04d4 150 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
Kovalev_D 23:12e6183f04d4 151 uint32_t RESERVED6[12];
Kovalev_D 23:12e6183f04d4 152 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
Kovalev_D 23:12e6183f04d4 153 uint32_t RESERVED7[7];
Kovalev_D 23:12e6183f04d4 154 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
Kovalev_D 23:12e6183f04d4 155 __IO uint32_t IRCTRIM; /* Clock Dividers */
Kovalev_D 23:12e6183f04d4 156 __IO uint32_t PCLKSEL0; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register */
Kovalev_D 23:12e6183f04d4 157 __IO uint32_t PCLKSEL1; /*!< Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register */
Kovalev_D 23:12e6183f04d4 158 uint32_t RESERVED8[4];
Kovalev_D 23:12e6183f04d4 159 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 160 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
Kovalev_D 23:12e6183f04d4 161 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
Kovalev_D 23:12e6183f04d4 162
Kovalev_D 23:12e6183f04d4 163 } LPC_SC_TypeDef;
Kovalev_D 23:12e6183f04d4 164
Kovalev_D 23:12e6183f04d4 165
Kovalev_D 23:12e6183f04d4 166 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
Kovalev_D 23:12e6183f04d4 167 /** @brief Pin Connect Block (PINCON) register structure definition */
Kovalev_D 23:12e6183f04d4 168 typedef struct
Kovalev_D 23:12e6183f04d4 169 {
Kovalev_D 23:12e6183f04d4 170 __IO uint32_t PINSEL0; /* !< Offset: 0x000 PIN Select0 (R/W) */
Kovalev_D 23:12e6183f04d4 171 __IO uint32_t PINSEL1; /* !< Offset: 0x004 PIN Select1 (R/W) */
Kovalev_D 23:12e6183f04d4 172 __IO uint32_t PINSEL2; /* !< Offset: 0x008 PIN Select2 (R/W) */
Kovalev_D 23:12e6183f04d4 173 __IO uint32_t PINSEL3; /* !< Offset: 0x00C PIN Select3 (R/W) */
Kovalev_D 23:12e6183f04d4 174 __IO uint32_t PINSEL4; /* !< Offset: 0x010 PIN Select4 (R/W) */
Kovalev_D 23:12e6183f04d4 175 __IO uint32_t PINSEL5; /* !< Offset: 0x014 PIN Select5 (R/W) */
Kovalev_D 23:12e6183f04d4 176 __IO uint32_t PINSEL6; /* !< Offset: 0x018 PIN Select6 (R/W) */
Kovalev_D 23:12e6183f04d4 177 __IO uint32_t PINSEL7; /* !< Offset: 0x01C PIN Select7 (R/W) */
Kovalev_D 23:12e6183f04d4 178 __IO uint32_t PINSEL8; /* !< Offset: 0x020 PIN Select8 (R/W) */
Kovalev_D 23:12e6183f04d4 179 __IO uint32_t PINSEL9; /* !< Offset: 0x024 PIN Select9 (R/W) */
Kovalev_D 23:12e6183f04d4 180 __IO uint32_t PINSEL10; /* !< Offset: 0x028 PIN Select20 (R/W) */
Kovalev_D 23:12e6183f04d4 181 uint32_t RESERVED0[5];
Kovalev_D 23:12e6183f04d4 182 __IO uint32_t PINMODE0; /* !< Offset: 0x040 PIN Mode0 (R/W) */
Kovalev_D 23:12e6183f04d4 183 __IO uint32_t PINMODE1; /* !< Offset: 0x044 PIN Mode1 (R/W) */
Kovalev_D 23:12e6183f04d4 184 __IO uint32_t PINMODE2; /* !< Offset: 0x048 PIN Mode2 (R/W) */
Kovalev_D 23:12e6183f04d4 185 __IO uint32_t PINMODE3; /* !< Offset: 0x04C PIN Mode3 (R/W) */
Kovalev_D 23:12e6183f04d4 186 __IO uint32_t PINMODE4; /* !< Offset: 0x050 PIN Mode4 (R/W) */
Kovalev_D 23:12e6183f04d4 187 __IO uint32_t PINMODE5; /* !< Offset: 0x054 PIN Mode5 (R/W) */
Kovalev_D 23:12e6183f04d4 188 __IO uint32_t PINMODE6; /* !< Offset: 0x058 PIN Mode6 (R/W) */
Kovalev_D 23:12e6183f04d4 189 __IO uint32_t PINMODE7; /* !< Offset: 0x05C PIN Mode7 (R/W) */
Kovalev_D 23:12e6183f04d4 190 __IO uint32_t PINMODE8; /* !< Offset: 0x060 PIN Mode8 (R/W) */
Kovalev_D 23:12e6183f04d4 191 __IO uint32_t PINMODE9; /* !< Offset: 0x064 PIN Mode9 (R/W) */
Kovalev_D 23:12e6183f04d4 192 __IO uint32_t PINMODE_OD0; /* !< Offset: 0x068 Open Drain PIN Mode0 (R/W) */
Kovalev_D 23:12e6183f04d4 193 __IO uint32_t PINMODE_OD1; /* !< Offset: 0x06C Open Drain PIN Mode1 (R/W) */
Kovalev_D 23:12e6183f04d4 194 __IO uint32_t PINMODE_OD2; /* !< Offset: 0x070 Open Drain PIN Mode2 (R/W) */
Kovalev_D 23:12e6183f04d4 195 __IO uint32_t PINMODE_OD3; /* !< Offset: 0x074 Open Drain PIN Mode3 (R/W) */
Kovalev_D 23:12e6183f04d4 196 __IO uint32_t PINMODE_OD4; /* !< Offset: 0x078 Open Drain PIN Mode4 (R/W) */
Kovalev_D 23:12e6183f04d4 197 __IO uint32_t I2CPADCFG; /* !< Offset: 0x07C I2C Pad Configure (R/W) */
Kovalev_D 23:12e6183f04d4 198 } LPC_PINCON_TypeDef;
Kovalev_D 23:12e6183f04d4 199
Kovalev_D 23:12e6183f04d4 200 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
Kovalev_D 23:12e6183f04d4 201 /** @brief General Purpose Input/Output (GPIO) register structure definition */
Kovalev_D 23:12e6183f04d4 202 typedef struct
Kovalev_D 23:12e6183f04d4 203 {
Kovalev_D 23:12e6183f04d4 204 union {
Kovalev_D 23:12e6183f04d4 205 __IO uint32_t FIODIR; /* !< Offset: 0x00 Port direction (R/W) */
Kovalev_D 23:12e6183f04d4 206 struct {
Kovalev_D 23:12e6183f04d4 207 __IO uint16_t FIODIRL;
Kovalev_D 23:12e6183f04d4 208 __IO uint16_t FIODIRH;
Kovalev_D 23:12e6183f04d4 209 };
Kovalev_D 23:12e6183f04d4 210 struct {
Kovalev_D 23:12e6183f04d4 211 __IO uint8_t FIODIR0;
Kovalev_D 23:12e6183f04d4 212 __IO uint8_t FIODIR1;
Kovalev_D 23:12e6183f04d4 213 __IO uint8_t FIODIR2;
Kovalev_D 23:12e6183f04d4 214 __IO uint8_t FIODIR3;
Kovalev_D 23:12e6183f04d4 215 };
Kovalev_D 23:12e6183f04d4 216 };
Kovalev_D 23:12e6183f04d4 217 uint32_t RESERVED0[3];
Kovalev_D 23:12e6183f04d4 218 union {
Kovalev_D 23:12e6183f04d4 219 __IO uint32_t FIOMASK; /* !< Offset: 0x10 Port mask (R/W) */
Kovalev_D 23:12e6183f04d4 220 struct {
Kovalev_D 23:12e6183f04d4 221 __IO uint16_t FIOMASKL;
Kovalev_D 23:12e6183f04d4 222 __IO uint16_t FIOMASKH;
Kovalev_D 23:12e6183f04d4 223 };
Kovalev_D 23:12e6183f04d4 224 struct {
Kovalev_D 23:12e6183f04d4 225 __IO uint8_t FIOMASK0;
Kovalev_D 23:12e6183f04d4 226 __IO uint8_t FIOMASK1;
Kovalev_D 23:12e6183f04d4 227 __IO uint8_t FIOMASK2;
Kovalev_D 23:12e6183f04d4 228 __IO uint8_t FIOMASK3;
Kovalev_D 23:12e6183f04d4 229 };
Kovalev_D 23:12e6183f04d4 230 };
Kovalev_D 23:12e6183f04d4 231 union {
Kovalev_D 23:12e6183f04d4 232 __IO uint32_t FIOPIN; /* !< Offset: 0x14 Port value (R/W) */
Kovalev_D 23:12e6183f04d4 233 struct {
Kovalev_D 23:12e6183f04d4 234 __IO uint16_t FIOPINL;
Kovalev_D 23:12e6183f04d4 235 __IO uint16_t FIOPINH;
Kovalev_D 23:12e6183f04d4 236 };
Kovalev_D 23:12e6183f04d4 237 struct {
Kovalev_D 23:12e6183f04d4 238 __IO uint8_t FIOPIN0;
Kovalev_D 23:12e6183f04d4 239 __IO uint8_t FIOPIN1;
Kovalev_D 23:12e6183f04d4 240 __IO uint8_t FIOPIN2;
Kovalev_D 23:12e6183f04d4 241 __IO uint8_t FIOPIN3;
Kovalev_D 23:12e6183f04d4 242 };
Kovalev_D 23:12e6183f04d4 243 };
Kovalev_D 23:12e6183f04d4 244 union {
Kovalev_D 23:12e6183f04d4 245 __IO uint32_t FIOSET; /* !< Offset: 0x18 Port output set (R/W) */
Kovalev_D 23:12e6183f04d4 246 struct {
Kovalev_D 23:12e6183f04d4 247 __IO uint16_t FIOSETL;
Kovalev_D 23:12e6183f04d4 248 __IO uint16_t FIOSETH;
Kovalev_D 23:12e6183f04d4 249 };
Kovalev_D 23:12e6183f04d4 250 struct {
Kovalev_D 23:12e6183f04d4 251 __IO uint8_t FIOSET0;
Kovalev_D 23:12e6183f04d4 252 __IO uint8_t FIOSET1;
Kovalev_D 23:12e6183f04d4 253 __IO uint8_t FIOSET2;
Kovalev_D 23:12e6183f04d4 254 __IO uint8_t FIOSET3;
Kovalev_D 23:12e6183f04d4 255 };
Kovalev_D 23:12e6183f04d4 256 };
Kovalev_D 23:12e6183f04d4 257 union {
Kovalev_D 23:12e6183f04d4 258 __O uint32_t FIOCLR; /* !< Offset: 0x1C Port output clear (R/W) */
Kovalev_D 23:12e6183f04d4 259 struct {
Kovalev_D 23:12e6183f04d4 260 __O uint16_t FIOCLRL;
Kovalev_D 23:12e6183f04d4 261 __O uint16_t FIOCLRH;
Kovalev_D 23:12e6183f04d4 262 };
Kovalev_D 23:12e6183f04d4 263 struct {
Kovalev_D 23:12e6183f04d4 264 __O uint8_t FIOCLR0;
Kovalev_D 23:12e6183f04d4 265 __O uint8_t FIOCLR1;
Kovalev_D 23:12e6183f04d4 266 __O uint8_t FIOCLR2;
Kovalev_D 23:12e6183f04d4 267 __O uint8_t FIOCLR3;
Kovalev_D 23:12e6183f04d4 268 };
Kovalev_D 23:12e6183f04d4 269 };
Kovalev_D 23:12e6183f04d4 270 } LPC_GPIO_TypeDef;
Kovalev_D 23:12e6183f04d4 271
Kovalev_D 23:12e6183f04d4 272 /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
Kovalev_D 23:12e6183f04d4 273 typedef struct
Kovalev_D 23:12e6183f04d4 274 {
Kovalev_D 23:12e6183f04d4 275 __I uint32_t IntStatus; /*!< Offset: 0x000 (R/ ) GPIO overall Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 276 __I uint32_t IO0IntStatR; /*!< Offset: 0x004 (R/ ) GPIO Interrupt Status Register 0 for Rising edge */
Kovalev_D 23:12e6183f04d4 277 __I uint32_t IO0IntStatF; /*!< Offset: 0x008 (R/ ) GPIO Interrupt Status Register 0 for Falling edge */
Kovalev_D 23:12e6183f04d4 278 __O uint32_t IO0IntClr; /*!< Offset: 0x00C (R/W) GPIO Interrupt Clear Register 0 */
Kovalev_D 23:12e6183f04d4 279 __IO uint32_t IO0IntEnR; /*!< Offset: 0x010 ( /W) GPIO Interrupt Enable Register 0 for Rising edge */
Kovalev_D 23:12e6183f04d4 280 __IO uint32_t IO0IntEnF; /*!< Offset: 0x014 (R/W) GPIO Interrupt Enable Register 0 for Falling edge */
Kovalev_D 23:12e6183f04d4 281 uint32_t RESERVED0[3];
Kovalev_D 23:12e6183f04d4 282 __I uint32_t IO2IntStatR; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Rising edge */
Kovalev_D 23:12e6183f04d4 283 __I uint32_t IO2IntStatF; /*!< Offset: 0x000 (R/ ) GPIO Interrupt Status Register 2 for Falling edge */
Kovalev_D 23:12e6183f04d4 284 __O uint32_t IO2IntClr; /*!< Offset: 0x000 ( /W) GPIO Interrupt Clear Register 2 */
Kovalev_D 23:12e6183f04d4 285 __IO uint32_t IO2IntEnR; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Rising edge */
Kovalev_D 23:12e6183f04d4 286 __IO uint32_t IO2IntEnF; /*!< Offset: 0x000 (R/W) GPIO Interrupt Enable Register 2 for Falling edge */
Kovalev_D 23:12e6183f04d4 287 } LPC_GPIOINT_TypeDef;
Kovalev_D 23:12e6183f04d4 288
Kovalev_D 23:12e6183f04d4 289 /*------------- Timer (TIM) --------------------------------------------------*/
Kovalev_D 23:12e6183f04d4 290 /** @brief Timer (TIM) register structure definition */
Kovalev_D 23:12e6183f04d4 291 typedef struct
Kovalev_D 23:12e6183f04d4 292 {
Kovalev_D 23:12e6183f04d4 293 __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
Kovalev_D 23:12e6183f04d4 294 __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register */
Kovalev_D 23:12e6183f04d4 295 __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
Kovalev_D 23:12e6183f04d4 296 __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
Kovalev_D 23:12e6183f04d4 297 __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
Kovalev_D 23:12e6183f04d4 298 __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
Kovalev_D 23:12e6183f04d4 299 __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
Kovalev_D 23:12e6183f04d4 300 __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
Kovalev_D 23:12e6183f04d4 301 __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
Kovalev_D 23:12e6183f04d4 302 __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
Kovalev_D 23:12e6183f04d4 303 __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
Kovalev_D 23:12e6183f04d4 304 __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
Kovalev_D 23:12e6183f04d4 305 __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register */
Kovalev_D 23:12e6183f04d4 306 uint32_t RESERVED0[2];
Kovalev_D 23:12e6183f04d4 307 __IO uint32_t EMR; /*!< Offset: 0x03C (R/W) External Match Register */
Kovalev_D 23:12e6183f04d4 308 uint32_t RESERVED1[12];
Kovalev_D 23:12e6183f04d4 309 __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
Kovalev_D 23:12e6183f04d4 310 } LPC_TIM_TypeDef;
Kovalev_D 23:12e6183f04d4 311
Kovalev_D 23:12e6183f04d4 312 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
Kovalev_D 23:12e6183f04d4 313 /** @brief Pulse-Width Modulation (PWM) register structure definition */
Kovalev_D 23:12e6183f04d4 314 typedef struct
Kovalev_D 23:12e6183f04d4 315 {
Kovalev_D 23:12e6183f04d4 316 __IO uint32_t IR; /*!< Offset: 0x000 (R/W) Interrupt Register */
Kovalev_D 23:12e6183f04d4 317 __IO uint32_t TCR; /*!< Offset: 0x004 (R/W) Timer Control Register. Register */
Kovalev_D 23:12e6183f04d4 318 __IO uint32_t TC; /*!< Offset: 0x008 (R/W) Timer Counter Register */
Kovalev_D 23:12e6183f04d4 319 __IO uint32_t PR; /*!< Offset: 0x00C (R/W) Prescale Register */
Kovalev_D 23:12e6183f04d4 320 __IO uint32_t PC; /*!< Offset: 0x010 (R/W) Prescale Counter Register */
Kovalev_D 23:12e6183f04d4 321 __IO uint32_t MCR; /*!< Offset: 0x014 (R/W) Match Control Register */
Kovalev_D 23:12e6183f04d4 322 __IO uint32_t MR0; /*!< Offset: 0x018 (R/W) Match Register 0 */
Kovalev_D 23:12e6183f04d4 323 __IO uint32_t MR1; /*!< Offset: 0x01C (R/W) Match Register 1 */
Kovalev_D 23:12e6183f04d4 324 __IO uint32_t MR2; /*!< Offset: 0x020 (R/W) Match Register 2 */
Kovalev_D 23:12e6183f04d4 325 __IO uint32_t MR3; /*!< Offset: 0x024 (R/W) Match Register 3 */
Kovalev_D 23:12e6183f04d4 326 __IO uint32_t CCR; /*!< Offset: 0x028 (R/W) Capture Control Register */
Kovalev_D 23:12e6183f04d4 327 __I uint32_t CR0; /*!< Offset: 0x02C (R/ ) Capture Register 0 */
Kovalev_D 23:12e6183f04d4 328 __I uint32_t CR1; /*!< Offset: 0x030 (R/ ) Capture Register 1 */
Kovalev_D 23:12e6183f04d4 329 __I uint32_t CR2; /*!< Offset: 0x034 (R/ ) Capture Register 2 */
Kovalev_D 23:12e6183f04d4 330 __I uint32_t CR3; /*!< Offset: 0x038 (R/ ) Capture Register 3 */
Kovalev_D 23:12e6183f04d4 331 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 332 __IO uint32_t MR4; /*!< Offset: 0x040 (R/W) Match Register 4 */
Kovalev_D 23:12e6183f04d4 333 __IO uint32_t MR5; /*!< Offset: 0x044 (R/W) Match Register 5 */
Kovalev_D 23:12e6183f04d4 334 __IO uint32_t MR6; /*!< Offset: 0x048 (R/W) Match Register 6 */
Kovalev_D 23:12e6183f04d4 335 __IO uint32_t PCR; /*!< Offset: 0x04C (R/W) PWM Control Register */
Kovalev_D 23:12e6183f04d4 336 __IO uint32_t LER; /*!< Offset: 0x050 (R/W) Load Enable Register */
Kovalev_D 23:12e6183f04d4 337 uint32_t RESERVED1[7];
Kovalev_D 23:12e6183f04d4 338 __IO uint32_t CTCR; /*!< Offset: 0x070 (R/W) Count Control Register */
Kovalev_D 23:12e6183f04d4 339 } LPC_PWM_TypeDef;
Kovalev_D 23:12e6183f04d4 340
Kovalev_D 23:12e6183f04d4 341 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
Kovalev_D 23:12e6183f04d4 342 /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
Kovalev_D 23:12e6183f04d4 343 typedef struct
Kovalev_D 23:12e6183f04d4 344 {
Kovalev_D 23:12e6183f04d4 345 union {
Kovalev_D 23:12e6183f04d4 346 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
Kovalev_D 23:12e6183f04d4 347 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
Kovalev_D 23:12e6183f04d4 348 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
Kovalev_D 23:12e6183f04d4 349 };
Kovalev_D 23:12e6183f04d4 350 union {
Kovalev_D 23:12e6183f04d4 351 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
Kovalev_D 23:12e6183f04d4 352 __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register (R/W) */
Kovalev_D 23:12e6183f04d4 353 };
Kovalev_D 23:12e6183f04d4 354 union {
Kovalev_D 23:12e6183f04d4 355 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
Kovalev_D 23:12e6183f04d4 356 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
Kovalev_D 23:12e6183f04d4 357 };
Kovalev_D 23:12e6183f04d4 358 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 359 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 360 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
Kovalev_D 23:12e6183f04d4 361 uint32_t RESERVED1;
Kovalev_D 23:12e6183f04d4 362 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
Kovalev_D 23:12e6183f04d4 363 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 364 __IO uint32_t ICR; /*!< Offset: 0x024 IrDA Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 365 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
Kovalev_D 23:12e6183f04d4 366 uint32_t RESERVED2;
Kovalev_D 23:12e6183f04d4 367 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
Kovalev_D 23:12e6183f04d4 368 } LPC_UART_TypeDef;
Kovalev_D 23:12e6183f04d4 369
Kovalev_D 23:12e6183f04d4 370 /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
Kovalev_D 23:12e6183f04d4 371 typedef struct
Kovalev_D 23:12e6183f04d4 372 {
Kovalev_D 23:12e6183f04d4 373 union {
Kovalev_D 23:12e6183f04d4 374 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
Kovalev_D 23:12e6183f04d4 375 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
Kovalev_D 23:12e6183f04d4 376 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
Kovalev_D 23:12e6183f04d4 377 };
Kovalev_D 23:12e6183f04d4 378 union {
Kovalev_D 23:12e6183f04d4 379 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
Kovalev_D 23:12e6183f04d4 380 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
Kovalev_D 23:12e6183f04d4 381 };
Kovalev_D 23:12e6183f04d4 382 union {
Kovalev_D 23:12e6183f04d4 383 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
Kovalev_D 23:12e6183f04d4 384 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
Kovalev_D 23:12e6183f04d4 385 };
Kovalev_D 23:12e6183f04d4 386 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 387 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
Kovalev_D 23:12e6183f04d4 388 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
Kovalev_D 23:12e6183f04d4 389 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
Kovalev_D 23:12e6183f04d4 390 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
Kovalev_D 23:12e6183f04d4 391 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 392 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 393 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
Kovalev_D 23:12e6183f04d4 394 uint32_t RESERVED1;
Kovalev_D 23:12e6183f04d4 395 __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
Kovalev_D 23:12e6183f04d4 396 uint32_t RESERVED2[6];
Kovalev_D 23:12e6183f04d4 397 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 398 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
Kovalev_D 23:12e6183f04d4 399 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
Kovalev_D 23:12e6183f04d4 400 } LPC_UART1_TypeDef;
Kovalev_D 23:12e6183f04d4 401
Kovalev_D 23:12e6183f04d4 402 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
Kovalev_D 23:12e6183f04d4 403 /** @brief Serial Peripheral Interface (SPI) register structure definition */
Kovalev_D 23:12e6183f04d4 404 typedef struct
Kovalev_D 23:12e6183f04d4 405 {
Kovalev_D 23:12e6183f04d4 406 __IO uint32_t SPCR; /*!< Offset: 0x000 SPI Control Register (R/W) */
Kovalev_D 23:12e6183f04d4 407 __I uint32_t SPSR; /*!< Offset: 0x004 SPI Status Register (R/) */
Kovalev_D 23:12e6183f04d4 408 __IO uint32_t SPDR; /*!< Offset: 0x008 SPI Data Register (R/W) */
Kovalev_D 23:12e6183f04d4 409 __IO uint32_t SPCCR; /*!< Offset: 0x00C SPI Clock Counter Register (R/W) */
Kovalev_D 23:12e6183f04d4 410 uint32_t RESERVED0[3];
Kovalev_D 23:12e6183f04d4 411 __IO uint32_t SPINT; /*!< Offset: 0x01C SPI Interrupt Flag Register (R/W) */
Kovalev_D 23:12e6183f04d4 412 } LPC_SPI_TypeDef;
Kovalev_D 23:12e6183f04d4 413
Kovalev_D 23:12e6183f04d4 414 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
Kovalev_D 23:12e6183f04d4 415 /** @brief Synchronous Serial Communication (SSP) register structure definition */
Kovalev_D 23:12e6183f04d4 416 typedef struct
Kovalev_D 23:12e6183f04d4 417 {
Kovalev_D 23:12e6183f04d4 418 __IO uint32_t CR0; /*!< Offset: 0x000 (R/W) Control Register 0 */
Kovalev_D 23:12e6183f04d4 419 __IO uint32_t CR1; /*!< Offset: 0x004 (R/W) Control Register 1 */
Kovalev_D 23:12e6183f04d4 420 __IO uint32_t DR; /*!< Offset: 0x008 (R/W) Data Register */
Kovalev_D 23:12e6183f04d4 421 __I uint32_t SR; /*!< Offset: 0x00C (R/ ) Status Register */
Kovalev_D 23:12e6183f04d4 422 __IO uint32_t CPSR; /*!< Offset: 0x010 (R/W) Clock Prescale Register */
Kovalev_D 23:12e6183f04d4 423 __IO uint32_t IMSC; /*!< Offset: 0x014 (R/W) Interrupt Mask Set and Clear Register */
Kovalev_D 23:12e6183f04d4 424 __IO uint32_t RIS; /*!< Offset: 0x018 (R/W) Raw Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 425 __IO uint32_t MIS; /*!< Offset: 0x01C (R/W) Masked Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 426 __IO uint32_t ICR; /*!< Offset: 0x020 (R/W) SSPICR Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 427 __IO uint32_t DMACR; /*!< Offset: 0x024 (R/W) DMA Control Register */
Kovalev_D 23:12e6183f04d4 428 } LPC_SSP_TypeDef;
Kovalev_D 23:12e6183f04d4 429
Kovalev_D 23:12e6183f04d4 430 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
Kovalev_D 23:12e6183f04d4 431 /** @brief Inter-Integrated Circuit (I2C) register structure definition */
Kovalev_D 23:12e6183f04d4 432 typedef struct
Kovalev_D 23:12e6183f04d4 433 {
Kovalev_D 23:12e6183f04d4 434 __IO uint32_t CONSET; /*!< Offset: 0x000 (R/W) I2C Control Set Register */
Kovalev_D 23:12e6183f04d4 435 __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) I2C Status Register */
Kovalev_D 23:12e6183f04d4 436 __IO uint32_t DAT; /*!< Offset: 0x008 (R/W) I2C Data Register */
Kovalev_D 23:12e6183f04d4 437 __IO uint32_t ADR0; /*!< Offset: 0x00C (R/W) I2C Slave Address Register 0 */
Kovalev_D 23:12e6183f04d4 438 __IO uint32_t SCLH; /*!< Offset: 0x010 (R/W) SCH Duty Cycle Register High Half Word */
Kovalev_D 23:12e6183f04d4 439 __IO uint32_t SCLL; /*!< Offset: 0x014 (R/W) SCL Duty Cycle Register Low Half Word */
Kovalev_D 23:12e6183f04d4 440 __O uint32_t CONCLR; /*!< Offset: 0x018 (R/W) I2C Control Clear Register */
Kovalev_D 23:12e6183f04d4 441 __IO uint32_t MMCTRL; /*!< Offset: 0x01C (R/W) Monitor mode control register */
Kovalev_D 23:12e6183f04d4 442 __IO uint32_t ADR1; /*!< Offset: 0x020 (R/W) I2C Slave Address Register 1 */
Kovalev_D 23:12e6183f04d4 443 __IO uint32_t ADR2; /*!< Offset: 0x024 (R/W) I2C Slave Address Register 2 */
Kovalev_D 23:12e6183f04d4 444 __IO uint32_t ADR3; /*!< Offset: 0x028 (R/W) I2C Slave Address Register 3 */
Kovalev_D 23:12e6183f04d4 445 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C (R/ ) Data buffer Register */
Kovalev_D 23:12e6183f04d4 446 __IO uint32_t MASK0; /*!< Offset: 0x030 (R/W) I2C Slave address mask register 0 */
Kovalev_D 23:12e6183f04d4 447 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) I2C Slave address mask register 1 */
Kovalev_D 23:12e6183f04d4 448 __IO uint32_t MASK2; /*!< Offset: 0x038 (R/W) I2C Slave address mask register 2 */
Kovalev_D 23:12e6183f04d4 449 __IO uint32_t MASK3; /*!< Offset: 0x03C (R/W) I2C Slave address mask register 3 */
Kovalev_D 23:12e6183f04d4 450 } LPC_I2C_TypeDef;
Kovalev_D 23:12e6183f04d4 451
Kovalev_D 23:12e6183f04d4 452 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
Kovalev_D 23:12e6183f04d4 453 /** @brief Inter IC Sound (I2S) register structure definition */
Kovalev_D 23:12e6183f04d4 454 typedef struct
Kovalev_D 23:12e6183f04d4 455 {
Kovalev_D 23:12e6183f04d4 456 __IO uint32_t DAO; /*!< Offset: 0x000 (R/W) Digital Audio Output Register */
Kovalev_D 23:12e6183f04d4 457 __IO uint32_t DAI; /*!< Offset: 0x004 (R/W) Digital Audio Input Register */
Kovalev_D 23:12e6183f04d4 458 __O uint32_t TXFIFO; /*!< Offset: 0x008 ( /W) Transmit FIFO */
Kovalev_D 23:12e6183f04d4 459 __I uint32_t RXFIFO; /*!< Offset: 0x00C (R/ ) Receive FIFO */
Kovalev_D 23:12e6183f04d4 460 __I uint32_t STATE; /*!< Offset: 0x010 (R/W) Status Feedback Register */
Kovalev_D 23:12e6183f04d4 461 __IO uint32_t DMA1; /*!< Offset: 0x014 (R/W) DMA Configuration Register 1 */
Kovalev_D 23:12e6183f04d4 462 __IO uint32_t DMA2; /*!< Offset: 0x018 (R/W) DMA Configuration Register 2 */
Kovalev_D 23:12e6183f04d4 463 __IO uint32_t IRQ; /*!< Offset: 0x01C (R/W) Interrupt Request Control Register */
Kovalev_D 23:12e6183f04d4 464 __IO uint32_t TXRATE; /*!< Offset: 0x020 (R/W) Transmit reference clock divider Register */
Kovalev_D 23:12e6183f04d4 465 __IO uint32_t RXRATE; /*!< Offset: 0x024 (R/W) Receive reference clock divider Register */
Kovalev_D 23:12e6183f04d4 466 __IO uint32_t TXBITRATE; /*!< Offset: 0x028 (R/W) Transmit bit rate divider Register */
Kovalev_D 23:12e6183f04d4 467 __IO uint32_t RXBITRATE; /*!< Offset: 0x02C (R/W) Receive bit rate divider Register */
Kovalev_D 23:12e6183f04d4 468 __IO uint32_t TXMODE; /*!< Offset: 0x030 (R/W) Transmit mode control Register */
Kovalev_D 23:12e6183f04d4 469 __IO uint32_t RXMODE; /*!< Offset: 0x034 (R/W) Receive mode control Register */
Kovalev_D 23:12e6183f04d4 470 } LPC_I2S_TypeDef;
Kovalev_D 23:12e6183f04d4 471
Kovalev_D 23:12e6183f04d4 472 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
Kovalev_D 23:12e6183f04d4 473 /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
Kovalev_D 23:12e6183f04d4 474 typedef struct
Kovalev_D 23:12e6183f04d4 475 {
Kovalev_D 23:12e6183f04d4 476 __IO uint32_t RICOMPVAL;
Kovalev_D 23:12e6183f04d4 477 __IO uint32_t RIMASK;
Kovalev_D 23:12e6183f04d4 478 __IO uint32_t RICTRL;
Kovalev_D 23:12e6183f04d4 479 __IO uint32_t RICOUNTER;
Kovalev_D 23:12e6183f04d4 480 } LPC_RIT_TypeDef;
Kovalev_D 23:12e6183f04d4 481
Kovalev_D 23:12e6183f04d4 482 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
Kovalev_D 23:12e6183f04d4 483 /** @brief Real-Time Clock (RTC) register structure definition */
Kovalev_D 23:12e6183f04d4 484 typedef struct
Kovalev_D 23:12e6183f04d4 485 {
Kovalev_D 23:12e6183f04d4 486 __IO uint32_t ILR; /*!< Offset: 0x000 (R/W) Interrupt Location Register */
Kovalev_D 23:12e6183f04d4 487 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 488 __IO uint32_t CCR; /*!< Offset: 0x008 (R/W) Clock Control Register */
Kovalev_D 23:12e6183f04d4 489 __IO uint32_t CIIR; /*!< Offset: 0x00C (R/W) Counter Increment Interrupt Register */
Kovalev_D 23:12e6183f04d4 490 __IO uint32_t AMR; /*!< Offset: 0x010 (R/W) Alarm Mask Register */
Kovalev_D 23:12e6183f04d4 491 __I uint32_t CTIME0; /*!< Offset: 0x014 (R/ ) Consolidated Time Register 0 */
Kovalev_D 23:12e6183f04d4 492 __I uint32_t CTIME1; /*!< Offset: 0x018 (R/ ) Consolidated Time Register 1 */
Kovalev_D 23:12e6183f04d4 493 __I uint32_t CTIME2; /*!< Offset: 0x01C (R/ ) Consolidated Time Register 2 */
Kovalev_D 23:12e6183f04d4 494 __IO uint32_t SEC; /*!< Offset: 0x020 (R/W) Seconds Counter Register */
Kovalev_D 23:12e6183f04d4 495 __IO uint32_t MIN; /*!< Offset: 0x024 (R/W) Minutes Register */
Kovalev_D 23:12e6183f04d4 496 __IO uint32_t HOUR; /*!< Offset: 0x028 (R/W) Hours Register */
Kovalev_D 23:12e6183f04d4 497 __IO uint32_t DOM; /*!< Offset: 0x02C (R/W) Day of Month Register */
Kovalev_D 23:12e6183f04d4 498 __IO uint32_t DOW; /*!< Offset: 0x030 (R/W) Day of Week Register */
Kovalev_D 23:12e6183f04d4 499 __IO uint32_t DOY; /*!< Offset: 0x034 (R/W) Day of Year Register */
Kovalev_D 23:12e6183f04d4 500 __IO uint32_t MONTH; /*!< Offset: 0x038 (R/W) Months Register */
Kovalev_D 23:12e6183f04d4 501 __IO uint32_t YEAR; /*!< Offset: 0x03C (R/W) Years Register */
Kovalev_D 23:12e6183f04d4 502 __IO uint32_t CALIBRATION; /*!< Offset: 0x040 (R/W) Calibration Value Register */
Kovalev_D 23:12e6183f04d4 503 __IO uint32_t GPREG0; /*!< Offset: 0x044 (R/W) General Purpose Register 0 */
Kovalev_D 23:12e6183f04d4 504 __IO uint32_t GPREG1; /*!< Offset: 0x048 (R/W) General Purpose Register 1 */
Kovalev_D 23:12e6183f04d4 505 __IO uint32_t GPREG2; /*!< Offset: 0x04C (R/W) General Purpose Register 2 */
Kovalev_D 23:12e6183f04d4 506 __IO uint32_t GPREG3; /*!< Offset: 0x050 (R/W) General Purpose Register 3 */
Kovalev_D 23:12e6183f04d4 507 __IO uint32_t GPREG4; /*!< Offset: 0x054 (R/W) General Purpose Register 4 */
Kovalev_D 23:12e6183f04d4 508 __IO uint32_t RTC_AUXEN; /*!< Offset: 0x058 (R/W) RTC Auxiliary Enable Register */
Kovalev_D 23:12e6183f04d4 509 __IO uint32_t RTC_AUX; /*!< Offset: 0x05C (R/W) RTC Auxiliary Control Register */
Kovalev_D 23:12e6183f04d4 510 __IO uint32_t ALSEC; /*!< Offset: 0x060 (R/W) Alarm value for Seconds */
Kovalev_D 23:12e6183f04d4 511 __IO uint32_t ALMIN; /*!< Offset: 0x064 (R/W) Alarm value for Minutes */
Kovalev_D 23:12e6183f04d4 512 __IO uint32_t ALHOUR; /*!< Offset: 0x068 (R/W) Alarm value for Hours */
Kovalev_D 23:12e6183f04d4 513 __IO uint32_t ALDOM; /*!< Offset: 0x06C (R/W) Alarm value for Day of Month */
Kovalev_D 23:12e6183f04d4 514 __IO uint32_t ALDOW; /*!< Offset: 0x070 (R/W) Alarm value for Day of Week */
Kovalev_D 23:12e6183f04d4 515 __IO uint32_t ALDOY; /*!< Offset: 0x074 (R/W) Alarm value for Day of Year */
Kovalev_D 23:12e6183f04d4 516 __IO uint32_t ALMON; /*!< Offset: 0x078 (R/W) Alarm value for Months */
Kovalev_D 23:12e6183f04d4 517 __IO uint32_t ALYEAR; /*!< Offset: 0x07C (R/W) Alarm value for Year */
Kovalev_D 23:12e6183f04d4 518 } LPC_RTC_TypeDef;
Kovalev_D 23:12e6183f04d4 519
Kovalev_D 23:12e6183f04d4 520 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
Kovalev_D 23:12e6183f04d4 521 /** @brief Watchdog Timer (WDT) register structure definition */
Kovalev_D 23:12e6183f04d4 522 typedef struct
Kovalev_D 23:12e6183f04d4 523 {
Kovalev_D 23:12e6183f04d4 524 __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) Watchdog mode Register */
Kovalev_D 23:12e6183f04d4 525 __IO uint32_t TC; /*!< Offset: 0x004 (R/W) Watchdog timer constant Register */
Kovalev_D 23:12e6183f04d4 526 __O uint32_t FEED; /*!< Offset: 0x008 ( /W) Watchdog feed sequence Register */
Kovalev_D 23:12e6183f04d4 527 __I uint32_t TV; /*!< Offset: 0x00C (R/ ) Watchdog timer value Register */
Kovalev_D 23:12e6183f04d4 528 __IO uint32_t WDCLKSEL;
Kovalev_D 23:12e6183f04d4 529 } LPC_WDT_TypeDef;
Kovalev_D 23:12e6183f04d4 530
Kovalev_D 23:12e6183f04d4 531 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
Kovalev_D 23:12e6183f04d4 532 /** @brief Analog-to-Digital Converter (ADC) register structure definition */
Kovalev_D 23:12e6183f04d4 533 typedef struct
Kovalev_D 23:12e6183f04d4 534 {
Kovalev_D 23:12e6183f04d4 535 __IO uint32_t CR; /*!< Offset: 0x000 (R/W) A/D Control Register */
Kovalev_D 23:12e6183f04d4 536 __IO uint32_t GDR; /*!< Offset: 0x004 (R/W) A/D Global Data Register */
Kovalev_D 23:12e6183f04d4 537 uint32_t RESERVED0;
Kovalev_D 23:12e6183f04d4 538 __IO uint32_t INTEN; /*!< Offset: 0x00C (R/W) A/D Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 539 __I uint32_t DR[8]; /*!< Offset: 0x010 (R/ ) A/D Channel # Data Register */
Kovalev_D 23:12e6183f04d4 540 __I uint32_t STAT; /*!< Offset: 0x030 (R/ ) A/D Status Register */
Kovalev_D 23:12e6183f04d4 541 __IO uint32_t ADTRM; /*!< Offset: 0x034 (R/W) ADC trim Register */
Kovalev_D 23:12e6183f04d4 542 } LPC_ADC_TypeDef;
Kovalev_D 23:12e6183f04d4 543
Kovalev_D 23:12e6183f04d4 544 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
Kovalev_D 23:12e6183f04d4 545 /** @brief Digital-to-Analog Converter (DAC) register structure definition */
Kovalev_D 23:12e6183f04d4 546 typedef struct
Kovalev_D 23:12e6183f04d4 547 {
Kovalev_D 23:12e6183f04d4 548 __IO uint32_t CR; /*!< Offset: 0x000 (R/W) D/A Converter Register */
Kovalev_D 23:12e6183f04d4 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) DAC Control register */
Kovalev_D 23:12e6183f04d4 550 __IO uint32_t CNTVAL; /*!< Offset: 0x008 (R/W) DAC Counter Value Register */
Kovalev_D 23:12e6183f04d4 551 } LPC_DAC_TypeDef;
Kovalev_D 23:12e6183f04d4 552
Kovalev_D 23:12e6183f04d4 553 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
Kovalev_D 23:12e6183f04d4 554 /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
Kovalev_D 23:12e6183f04d4 555 typedef struct
Kovalev_D 23:12e6183f04d4 556 {
Kovalev_D 23:12e6183f04d4 557 __I uint32_t CON; /*!< Offset: 0x000 (R/ ) PWM Control read address Register */
Kovalev_D 23:12e6183f04d4 558 __O uint32_t CON_SET; /*!< Offset: 0x004 ( /W) PWM Control set address Register */
Kovalev_D 23:12e6183f04d4 559 __O uint32_t CON_CLR; /*!< Offset: 0x008 ( /W) PWM Control clear address Register */
Kovalev_D 23:12e6183f04d4 560 __I uint32_t CAPCON; /*!< Offset: 0x00C (R/ ) Capture Control read address Register */
Kovalev_D 23:12e6183f04d4 561 __O uint32_t CAPCON_SET; /*!< Offset: 0x010 ( /W) Capture Control set address Register */
Kovalev_D 23:12e6183f04d4 562 __O uint32_t CAPCON_CLR; /*!< Offset: 0x014 ( /W) Event Control clear address Register */
Kovalev_D 23:12e6183f04d4 563 __IO uint32_t TC0; /*!< Offset: 0x018 (R/W) Timer Counter Register, channel 0 */
Kovalev_D 23:12e6183f04d4 564 __IO uint32_t TC1; /*!< Offset: 0x01C (R/W) Timer Counter Register, channel 1 */
Kovalev_D 23:12e6183f04d4 565 __IO uint32_t TC2; /*!< Offset: 0x020 (R/W) Timer Counter Register, channel 2 */
Kovalev_D 23:12e6183f04d4 566 __IO uint32_t LIM0; /*!< Offset: 0x024 (R/W) Limit Register, channel 0 */
Kovalev_D 23:12e6183f04d4 567 __IO uint32_t LIM1; /*!< Offset: 0x028 (R/W) Limit Register, channel 1 */
Kovalev_D 23:12e6183f04d4 568 __IO uint32_t LIM2; /*!< Offset: 0x02C (R/W) Limit Register, channel 2 */
Kovalev_D 23:12e6183f04d4 569 __IO uint32_t MAT0; /*!< Offset: 0x030 (R/W) Match Register, channel 0 */
Kovalev_D 23:12e6183f04d4 570 __IO uint32_t MAT1; /*!< Offset: 0x034 (R/W) Match Register, channel 1 */
Kovalev_D 23:12e6183f04d4 571 __IO uint32_t MAT2; /*!< Offset: 0x038 (R/W) Match Register, channel 2 */
Kovalev_D 23:12e6183f04d4 572 __IO uint32_t DT; /*!< Offset: 0x03C (R/W) Dead time Register */
Kovalev_D 23:12e6183f04d4 573 __IO uint32_t CP; /*!< Offset: 0x040 (R/W) Commutation Pattern Register */
Kovalev_D 23:12e6183f04d4 574 __IO uint32_t CAP0; /*!< Offset: 0x044 (R/W) Capture Register, channel 0 */
Kovalev_D 23:12e6183f04d4 575 __IO uint32_t CAP1; /*!< Offset: 0x048 (R/W) Capture Register, channel 1 */
Kovalev_D 23:12e6183f04d4 576 __IO uint32_t CAP2; /*!< Offset: 0x04C (R/W) Capture Register, channel 2 */
Kovalev_D 23:12e6183f04d4 577 __I uint32_t INTEN; /*!< Offset: 0x050 (R/ ) Interrupt Enable read Register */
Kovalev_D 23:12e6183f04d4 578 __O uint32_t INTEN_SET; /*!< Offset: 0x054 ( /W) Interrupt Enable set address Register */
Kovalev_D 23:12e6183f04d4 579 __O uint32_t INTEN_CLR; /*!< Offset: 0x058 ( /W) Interrupt Enable clear address Register */
Kovalev_D 23:12e6183f04d4 580 __I uint32_t CNTCON; /*!< Offset: 0x05C (R/ ) Count Control read address Register */
Kovalev_D 23:12e6183f04d4 581 __O uint32_t CNTCON_SET; /*!< Offset: 0x060 ( /W) Count Control set address Register */
Kovalev_D 23:12e6183f04d4 582 __O uint32_t CNTCON_CLR; /*!< Offset: 0x064 ( /W) Count Control clear address Register */
Kovalev_D 23:12e6183f04d4 583 __I uint32_t INTF; /*!< Offset: 0x068 (R/ ) Interrupt flags read address Register */
Kovalev_D 23:12e6183f04d4 584 __O uint32_t INTF_SET; /*!< Offset: 0x06C ( /W) Interrupt flags set address Register */
Kovalev_D 23:12e6183f04d4 585 __O uint32_t INTF_CLR; /*!< Offset: 0x070 ( /W) Interrupt flags clear address Register */
Kovalev_D 23:12e6183f04d4 586 __O uint32_t CAP_CLR; /*!< Offset: 0x074 ( /W) Capture clear address Register */
Kovalev_D 23:12e6183f04d4 587 } LPC_MCPWM_TypeDef;
Kovalev_D 23:12e6183f04d4 588
Kovalev_D 23:12e6183f04d4 589 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
Kovalev_D 23:12e6183f04d4 590 /** @brief Quadrature Encoder Interface (QEI) register structure definition */
Kovalev_D 23:12e6183f04d4 591 typedef struct
Kovalev_D 23:12e6183f04d4 592 {
Kovalev_D 23:12e6183f04d4 593 __O uint32_t CON; /*!< Offset: 0x000 ( /W) Control Register */
Kovalev_D 23:12e6183f04d4 594 __I uint32_t STAT; /*!< Offset: 0x004 (R/ ) Encoder Status Register */
Kovalev_D 23:12e6183f04d4 595 __IO uint32_t CONF; /*!< Offset: 0x008 (R/W) Configuration Register */
Kovalev_D 23:12e6183f04d4 596 __I uint32_t POS; /*!< Offset: 0x00C (R/ ) Position Register */
Kovalev_D 23:12e6183f04d4 597 __IO uint32_t MAXPOS; /*!< Offset: 0x010 (R/W) Maximum position Register */
Kovalev_D 23:12e6183f04d4 598 __IO uint32_t CMPOS0; /*!< Offset: 0x014 (R/W) Position compare Register 0 */
Kovalev_D 23:12e6183f04d4 599 __IO uint32_t CMPOS1; /*!< Offset: 0x018 (R/W) Position compare Register 1 */
Kovalev_D 23:12e6183f04d4 600 __IO uint32_t CMPOS2; /*!< Offset: 0x01C (R/W) Position compare Register 2 */
Kovalev_D 23:12e6183f04d4 601 __I uint32_t INXCNT; /*!< Offset: 0x020 (R/ ) Index count Register */
Kovalev_D 23:12e6183f04d4 602 __IO uint32_t INXCMP0; /*!< Offset: 0x024 (R/W) Index compare Register 0 */
Kovalev_D 23:12e6183f04d4 603 __IO uint32_t LOAD; /*!< Offset: 0x028 (R/W) Velocity timer reload Register */
Kovalev_D 23:12e6183f04d4 604 __I uint32_t TIME; /*!< Offset: 0x02C (R/ ) Velocity timer Register */
Kovalev_D 23:12e6183f04d4 605 __I uint32_t VEL; /*!< Offset: 0x030 (R/ ) Velocity counter Register */
Kovalev_D 23:12e6183f04d4 606 __I uint32_t CAP; /*!< Offset: 0x034 (R/ ) Velocity capture Register */
Kovalev_D 23:12e6183f04d4 607 __IO uint32_t VELCOMP; /*!< Offset: 0x038 (R/W) Velocity compare Register */
Kovalev_D 23:12e6183f04d4 608 __IO uint32_t FILTER;
Kovalev_D 23:12e6183f04d4 609 uint32_t RESERVED0[998];
Kovalev_D 23:12e6183f04d4 610 __O uint32_t IEC; /*!< Offset: 0xFD8 ( /W) Interrupt enable clear Register */
Kovalev_D 23:12e6183f04d4 611 __O uint32_t IES; /*!< Offset: 0xFDC ( /W) Interrupt enable set Register */
Kovalev_D 23:12e6183f04d4 612 __I uint32_t INTSTAT; /*!< Offset: 0xFE0 (R/ ) Interrupt status Register */
Kovalev_D 23:12e6183f04d4 613 __I uint32_t IE; /*!< Offset: 0xFE4 (R/ ) Interrupt enable Register */
Kovalev_D 23:12e6183f04d4 614 __O uint32_t CLR; /*!< Offset: 0xFE8 ( /W) Interrupt status clear Register */
Kovalev_D 23:12e6183f04d4 615 __O uint32_t SET; /*!< Offset: 0xFEC ( /W) Interrupt status set Register */
Kovalev_D 23:12e6183f04d4 616 } LPC_QEI_TypeDef;
Kovalev_D 23:12e6183f04d4 617
Kovalev_D 23:12e6183f04d4 618 /*------------- Controller Area Network (CAN) --------------------------------*/
Kovalev_D 23:12e6183f04d4 619 /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
Kovalev_D 23:12e6183f04d4 620 typedef struct
Kovalev_D 23:12e6183f04d4 621 {
Kovalev_D 23:12e6183f04d4 622 __IO uint32_t mask[512]; /*!< Offset: 0x000 (R/W) Acceptance Filter RAM */
Kovalev_D 23:12e6183f04d4 623 } LPC_CANAF_RAM_TypeDef;
Kovalev_D 23:12e6183f04d4 624
Kovalev_D 23:12e6183f04d4 625 /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
Kovalev_D 23:12e6183f04d4 626 typedef struct /* Acceptance Filter Registers */
Kovalev_D 23:12e6183f04d4 627 {
Kovalev_D 23:12e6183f04d4 628 __IO uint32_t AFMR; /*!< Offset: 0x000 (R/W) Acceptance Filter Register */
Kovalev_D 23:12e6183f04d4 629 __IO uint32_t SFF_sa; /*!< Offset: 0x004 (R/W) Standard Frame Individual Start Address Register */
Kovalev_D 23:12e6183f04d4 630 __IO uint32_t SFF_GRP_sa; /*!< Offset: 0x008 (R/W) Standard Frame Group Start Address Register */
Kovalev_D 23:12e6183f04d4 631 __IO uint32_t EFF_sa; /*!< Offset: 0x00C (R/W) Extended Frame Start Address Register */
Kovalev_D 23:12e6183f04d4 632 __IO uint32_t EFF_GRP_sa; /*!< Offset: 0x010 (R/W) Extended Frame Group Start Address Register */
Kovalev_D 23:12e6183f04d4 633 __IO uint32_t ENDofTable; /*!< Offset: 0x014 (R/W) End of AF Tables Register */
Kovalev_D 23:12e6183f04d4 634 __I uint32_t LUTerrAd; /*!< Offset: 0x018 (R/ ) LUT Error Address Register */
Kovalev_D 23:12e6183f04d4 635 __I uint32_t LUTerr; /*!< Offset: 0x01C (R/ ) LUT Error Register */
Kovalev_D 23:12e6183f04d4 636 __IO uint32_t FCANIE; /*!< Offset: 0x020 (R/W) Global FullCANInterrupt Enable Register */
Kovalev_D 23:12e6183f04d4 637 __IO uint32_t FCANIC0; /*!< Offset: 0x024 (R/W) FullCAN Interrupt and Capture Register 0 */
Kovalev_D 23:12e6183f04d4 638 __IO uint32_t FCANIC1; /*!< Offset: 0x028 (R/W) FullCAN Interrupt and Capture Register 1 */
Kovalev_D 23:12e6183f04d4 639 } LPC_CANAF_TypeDef;
Kovalev_D 23:12e6183f04d4 640
Kovalev_D 23:12e6183f04d4 641 /** @brief Controller Area Network Central (CANCR) register structure definition */
Kovalev_D 23:12e6183f04d4 642 typedef struct /* Central Registers */
Kovalev_D 23:12e6183f04d4 643 {
Kovalev_D 23:12e6183f04d4 644 __I uint32_t TxSR; /*!< Offset: 0x000 (R/ ) CAN Central Transmit Status Register */
Kovalev_D 23:12e6183f04d4 645 __I uint32_t RxSR; /*!< Offset: 0x004 (R/ ) CAN Central Receive Status Register */
Kovalev_D 23:12e6183f04d4 646 __I uint32_t MSR; /*!< Offset: 0x008 (R/ ) CAN Central Miscellaneous Register */
Kovalev_D 23:12e6183f04d4 647 } LPC_CANCR_TypeDef;
Kovalev_D 23:12e6183f04d4 648
Kovalev_D 23:12e6183f04d4 649 /** @brief Controller Area Network Controller (CAN) register structure definition */
Kovalev_D 23:12e6183f04d4 650 typedef struct /* Controller Registers */
Kovalev_D 23:12e6183f04d4 651 {
Kovalev_D 23:12e6183f04d4 652 __IO uint32_t MOD; /*!< Offset: 0x000 (R/W) CAN Mode Register */
Kovalev_D 23:12e6183f04d4 653 __O uint32_t CMR; /*!< Offset: 0x004 ( /W) CAN Command Register */
Kovalev_D 23:12e6183f04d4 654 __IO uint32_t GSR; /*!< Offset: 0x008 (R/W) CAN Global Status Register */
Kovalev_D 23:12e6183f04d4 655 __I uint32_t ICR; /*!< Offset: 0x00C (R/ ) CAN Interrupt and Capture Register */
Kovalev_D 23:12e6183f04d4 656 __IO uint32_t IER; /*!< Offset: 0x010 (R/W) CAN Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 657 __IO uint32_t BTR; /*!< Offset: 0x014 (R/W) CAN Bus Timing Register */
Kovalev_D 23:12e6183f04d4 658 __IO uint32_t EWL; /*!< Offset: 0x018 (R/W) CAN Error Warning Limit Register */
Kovalev_D 23:12e6183f04d4 659 __I uint32_t SR; /*!< Offset: 0x01C (R/ ) CAN Status Register */
Kovalev_D 23:12e6183f04d4 660 __IO uint32_t RFS; /*!< Offset: 0x020 (R/W) CAN Receive Frame Status Register */
Kovalev_D 23:12e6183f04d4 661 __IO uint32_t RID; /*!< Offset: 0x024 (R/W) CAN Receive Identifier Register */
Kovalev_D 23:12e6183f04d4 662 __IO uint32_t RDA; /*!< Offset: 0x028 (R/W) CAN Receive Data Register A */
Kovalev_D 23:12e6183f04d4 663 __IO uint32_t RDB; /*!< Offset: 0x02C (R/W) CAN Receive Data Register B */
Kovalev_D 23:12e6183f04d4 664 __IO uint32_t TFI1; /*!< Offset: 0x030 (R/W) CAN Transmit Frame Information Register 1 */
Kovalev_D 23:12e6183f04d4 665 __IO uint32_t TID1; /*!< Offset: 0x034 (R/W) CAN Transmit Identifier Register 1 */
Kovalev_D 23:12e6183f04d4 666 __IO uint32_t TDA1; /*!< Offset: 0x038 (R/W) CAN Transmit Data Register A 1 */
Kovalev_D 23:12e6183f04d4 667 __IO uint32_t TDB1; /*!< Offset: 0x03C (R/W) CAN Transmit Data Register B 1 */
Kovalev_D 23:12e6183f04d4 668 __IO uint32_t TFI2; /*!< Offset: 0x040 (R/W) CAN Transmit Frame Information Register 2 */
Kovalev_D 23:12e6183f04d4 669 __IO uint32_t TID2; /*!< Offset: 0x044 (R/W) CAN Transmit Identifier Register 2 */
Kovalev_D 23:12e6183f04d4 670 __IO uint32_t TDA2; /*!< Offset: 0x048 (R/W) CAN Transmit Data Register A 2 */
Kovalev_D 23:12e6183f04d4 671 __IO uint32_t TDB2; /*!< Offset: 0x04C (R/W) CAN Transmit Data Register B 2 */
Kovalev_D 23:12e6183f04d4 672 __IO uint32_t TFI3; /*!< Offset: 0x050 (R/W) CAN Transmit Frame Information Register 3 */
Kovalev_D 23:12e6183f04d4 673 __IO uint32_t TID3; /*!< Offset: 0x054 (R/W) CAN Transmit Identifier Register 3 */
Kovalev_D 23:12e6183f04d4 674 __IO uint32_t TDA3; /*!< Offset: 0x058 (R/W) CAN Transmit Data Register A 3 */
Kovalev_D 23:12e6183f04d4 675 __IO uint32_t TDB3; /*!< Offset: 0x05C (R/W) CAN Transmit Data Register B 3 */
Kovalev_D 23:12e6183f04d4 676 } LPC_CAN_TypeDef;
Kovalev_D 23:12e6183f04d4 677
Kovalev_D 23:12e6183f04d4 678 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
Kovalev_D 23:12e6183f04d4 679 /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
Kovalev_D 23:12e6183f04d4 680 typedef struct /* Common Registers */
Kovalev_D 23:12e6183f04d4 681 {
Kovalev_D 23:12e6183f04d4 682 __I uint32_t IntStat; /*!< Offset: 0x000 (R/ ) DMA Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 683 __I uint32_t IntTCStat; /*!< Offset: 0x004 (R/ ) DMA Interrupt Terminal Count Request Status Register */
Kovalev_D 23:12e6183f04d4 684 __O uint32_t IntTCClear; /*!< Offset: 0x008 ( /W) DMA Interrupt Terminal Count Request Clear Register */
Kovalev_D 23:12e6183f04d4 685 __I uint32_t IntErrStat; /*!< Offset: 0x00C (R/ ) DMA Interrupt Error Status Register */
Kovalev_D 23:12e6183f04d4 686 __O uint32_t IntErrClr; /*!< Offset: 0x010 ( /W) DMA Interrupt Error Clear Register */
Kovalev_D 23:12e6183f04d4 687 __I uint32_t RawIntTCStat; /*!< Offset: 0x014 (R/ ) DMA Raw Interrupt Terminal Count Status Register */
Kovalev_D 23:12e6183f04d4 688 __I uint32_t RawIntErrStat; /*!< Offset: 0x018 (R/ ) DMA Raw Error Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 689 __I uint32_t EnbldChns; /*!< Offset: 0x01C (R/ ) DMA Enabled Channel Register */
Kovalev_D 23:12e6183f04d4 690 __IO uint32_t SoftBReq; /*!< Offset: 0x020 (R/W) DMA Software Burst Request Register */
Kovalev_D 23:12e6183f04d4 691 __IO uint32_t SoftSReq; /*!< Offset: 0x024 (R/W) DMA Software Single Request Register */
Kovalev_D 23:12e6183f04d4 692 __IO uint32_t SoftLBReq; /*!< Offset: 0x028 (R/W) DMA Software Last Burst Request Register */
Kovalev_D 23:12e6183f04d4 693 __IO uint32_t SoftLSReq; /*!< Offset: 0x02C (R/W) DMA Software Last Single Request Register */
Kovalev_D 23:12e6183f04d4 694 __IO uint32_t Config; /*!< Offset: 0x030 (R/W) DMA Configuration Register */
Kovalev_D 23:12e6183f04d4 695 __IO uint32_t Sync; /*!< Offset: 0x034 (R/W) DMA Synchronization Register */
Kovalev_D 23:12e6183f04d4 696 } LPC_GPDMA_TypeDef;
Kovalev_D 23:12e6183f04d4 697
Kovalev_D 23:12e6183f04d4 698 /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
Kovalev_D 23:12e6183f04d4 699 typedef struct /* Channel Registers */
Kovalev_D 23:12e6183f04d4 700 {
Kovalev_D 23:12e6183f04d4 701 __IO uint32_t CSrcAddr; /*!< Offset: 0x000 (R/W) DMA Channel # Source Address Register */
Kovalev_D 23:12e6183f04d4 702 __IO uint32_t CDestAddr; /*!< Offset: 0x004 (R/W) DMA Channel # Destination Address Register */
Kovalev_D 23:12e6183f04d4 703 __IO uint32_t CLLI; /*!< Offset: 0x008 (R/W) DMA Channel # Linked List Item Register */
Kovalev_D 23:12e6183f04d4 704 __IO uint32_t CControl; /*!< Offset: 0x00C (R/W) DMA Channel # Control Register */
Kovalev_D 23:12e6183f04d4 705 __IO uint32_t CConfig; /*!< Offset: 0x010 (R/W) DMA Channel # Configuration Register */
Kovalev_D 23:12e6183f04d4 706 } LPC_GPDMACH_TypeDef;
Kovalev_D 23:12e6183f04d4 707
Kovalev_D 23:12e6183f04d4 708 /*------------- Universal Serial Bus (USB) -----------------------------------*/
Kovalev_D 23:12e6183f04d4 709 /** @brief Universal Serial Bus (USB) register structure definition */
Kovalev_D 23:12e6183f04d4 710 typedef struct
Kovalev_D 23:12e6183f04d4 711 {
Kovalev_D 23:12e6183f04d4 712 __I uint32_t Revision; /*!< Offset: 0x000 (R/ ) Revision Register */
Kovalev_D 23:12e6183f04d4 713 __IO uint32_t Control; /*!< Offset: 0x004 (R/W) Control Register */
Kovalev_D 23:12e6183f04d4 714 __IO uint32_t CommandStatus; /*!< Offset: 0x008 (R/W) Command / Status Register */
Kovalev_D 23:12e6183f04d4 715 __IO uint32_t InterruptStatus; /*!< Offset: 0x00C (R/W) Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 716 __IO uint32_t InterruptEnable; /*!< Offset: 0x010 (R/W) Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 717 __IO uint32_t InterruptDisable; /*!< Offset: 0x014 (R/W) Interrupt Disable Register */
Kovalev_D 23:12e6183f04d4 718 __IO uint32_t HCCA; /*!< Offset: 0x018 (R/W) Host Controller communication Area Register */
Kovalev_D 23:12e6183f04d4 719 __I uint32_t PeriodCurrentED; /*!< Offset: 0x01C (R/ ) Register */
Kovalev_D 23:12e6183f04d4 720 __IO uint32_t ControlHeadED; /*!< Offset: 0x020 (R/W) Register */
Kovalev_D 23:12e6183f04d4 721 __IO uint32_t ControlCurrentED; /*!< Offset: 0x024 (R/W) Register */
Kovalev_D 23:12e6183f04d4 722 __IO uint32_t BulkHeadED; /*!< Offset: 0x028 (R/W) Register */
Kovalev_D 23:12e6183f04d4 723 __IO uint32_t BulkCurrentED; /*!< Offset: 0x02C (R/W) Register */
Kovalev_D 23:12e6183f04d4 724 __I uint32_t DoneHead; /*!< Offset: 0x030 (R/ ) Register */
Kovalev_D 23:12e6183f04d4 725 __IO uint32_t FmInterval; /*!< Offset: 0x034 (R/W) Register */
Kovalev_D 23:12e6183f04d4 726 __I uint32_t FmRemaining; /*!< Offset: 0x038 (R/ ) Register */
Kovalev_D 23:12e6183f04d4 727 __I uint32_t FmNumber; /*!< Offset: 0x03C (R/ ) Register */
Kovalev_D 23:12e6183f04d4 728 __IO uint32_t PeriodicStart; /*!< Offset: 0x040 (R/W) Register */
Kovalev_D 23:12e6183f04d4 729 __IO uint32_t LSTreshold; /*!< Offset: 0x044 (R/W) Register */
Kovalev_D 23:12e6183f04d4 730 __IO uint32_t RhDescriptorA; /*!< Offset: 0x048 (R/W) Register */
Kovalev_D 23:12e6183f04d4 731 __IO uint32_t RhDescriptorB; /*!< Offset: 0x04C (R/W) Register */
Kovalev_D 23:12e6183f04d4 732 __IO uint32_t RhStatus; /*!< Offset: 0x050 (R/W) Register */
Kovalev_D 23:12e6183f04d4 733 __IO uint32_t RhPortStatus1; /*!< Offset: 0x054 (R/W) Register */
Kovalev_D 23:12e6183f04d4 734 __IO uint32_t RhPortStatus2; /*!< Offset: 0x05C (R/W) Register */
Kovalev_D 23:12e6183f04d4 735 uint32_t RESERVED0[40];
Kovalev_D 23:12e6183f04d4 736 __I uint32_t Module_ID; /*!< Offset: 0x0FC (R/ ) Module ID / Version Reverence ID Register */
Kovalev_D 23:12e6183f04d4 737 /* USB On-The-Go Registers */
Kovalev_D 23:12e6183f04d4 738 __I uint32_t IntSt; /*!< Offset: 0x100 (R/ ) OTG Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 739 __IO uint32_t IntEn; /*!< Offset: 0x104 (R/W) OTG Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 740 __O uint32_t IntSet; /*!< Offset: 0x108 ( /W) OTG Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 741 __O uint32_t IntClr; /*!< Offset: 0x10C ( /W) OTG Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 742 __IO uint32_t StCtrl; /*!< Offset: 0x110 (R/W) OTG Status and Control Register */
Kovalev_D 23:12e6183f04d4 743 __IO uint32_t Tmr; /*!< Offset: 0x114 (R/W) OTG Timer Register */
Kovalev_D 23:12e6183f04d4 744 uint32_t RESERVED1[58];
Kovalev_D 23:12e6183f04d4 745 /* USB Device Interrupt Registers */
Kovalev_D 23:12e6183f04d4 746 __I uint32_t DevIntSt; /*!< Offset: 0x200 (R/ ) USB Device Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 747 __IO uint32_t DevIntEn; /*!< Offset: 0x204 (R/W) USB Device Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 748 __O uint32_t DevIntClr; /*!< Offset: 0x208 ( /W) USB Device Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 749 __O uint32_t DevIntSet; /*!< Offset: 0x20C ( /W) USB Device Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 750 /* USB Device SIE Command Registers */
Kovalev_D 23:12e6183f04d4 751 __O uint32_t CmdCode; /*!< Offset: 0x210 (R/W) USB Command Code Register */
Kovalev_D 23:12e6183f04d4 752 __I uint32_t CmdData; /*!< Offset: 0x214 (R/W) USB Command Data Register */
Kovalev_D 23:12e6183f04d4 753 /* USB Device Transfer Registers */
Kovalev_D 23:12e6183f04d4 754 __I uint32_t RxData; /*!< Offset: 0x218 (R/ ) USB Receive Data Register */
Kovalev_D 23:12e6183f04d4 755 __O uint32_t TxData; /*!< Offset: 0x21C ( /W) USB Transmit Data Register */
Kovalev_D 23:12e6183f04d4 756 __I uint32_t RxPLen; /*!< Offset: 0x220 (R/ ) USB Receive Packet Length Register */
Kovalev_D 23:12e6183f04d4 757 __O uint32_t TxPLen; /*!< Offset: 0x224 ( /W) USB Transmit Packet Length Register */
Kovalev_D 23:12e6183f04d4 758 __IO uint32_t Ctrl; /*!< Offset: 0x228 (R/W) USB Control Register */
Kovalev_D 23:12e6183f04d4 759 __O uint32_t DevIntPri; /*!< Offset: 0x22C (R/W) USB Device Interrupt Priority Register */
Kovalev_D 23:12e6183f04d4 760 /* USB Device Endpoint Interrupt Regs */
Kovalev_D 23:12e6183f04d4 761 __I uint32_t EpIntSt; /*!< Offset: 0x230 (R/ ) USB Endpoint Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 762 __IO uint32_t EpIntEn; /*!< Offset: 0x234 (R/W) USB Endpoint Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 763 __O uint32_t EpIntClr; /*!< Offset: 0x238 ( /W) USB Endpoint Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 764 __O uint32_t EpIntSet; /*!< Offset: 0x23C ( /W) USB Endpoint Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 765 __O uint32_t EpIntPri; /*!< Offset: 0x240 ( /W) USB Endpoint Interrupt Priority Register */
Kovalev_D 23:12e6183f04d4 766 /* USB Device Endpoint Realization Reg*/
Kovalev_D 23:12e6183f04d4 767 __IO uint32_t ReEp; /*!< Offset: 0x244 (R/W) USB Realize Endpoint Register */
Kovalev_D 23:12e6183f04d4 768 __O uint32_t EpInd; /*!< Offset: 0x248 ( /W) USB Endpoint Index Register */
Kovalev_D 23:12e6183f04d4 769 __IO uint32_t MaxPSize; /*!< Offset: 0x24C (R/W) USB MaxPacketSize Register */
Kovalev_D 23:12e6183f04d4 770 /* USB Device DMA Registers */
Kovalev_D 23:12e6183f04d4 771 __I uint32_t DMARSt; /*!< Offset: 0x250 (R/ ) USB DMA Request Status Register */
Kovalev_D 23:12e6183f04d4 772 __O uint32_t DMARClr; /*!< Offset: 0x254 ( /W) USB DMA Request Clear Register */
Kovalev_D 23:12e6183f04d4 773 __O uint32_t DMARSet; /*!< Offset: 0x258 ( /W) USB DMA Request Set Register */
Kovalev_D 23:12e6183f04d4 774 uint32_t RESERVED2[9];
Kovalev_D 23:12e6183f04d4 775 __IO uint32_t UDCAH; /*!< Offset: 0x280 (R/W) USB UDCA Head Register */
Kovalev_D 23:12e6183f04d4 776 __I uint32_t EpDMASt; /*!< Offset: 0x284 (R/ ) USB EP DMA Status Register */
Kovalev_D 23:12e6183f04d4 777 __O uint32_t EpDMAEn; /*!< Offset: 0x288 ( /W) USB EP DMA Enable Register */
Kovalev_D 23:12e6183f04d4 778 __O uint32_t EpDMADis; /*!< Offset: 0x28C ( /W) USB EP DMA Disable Register */
Kovalev_D 23:12e6183f04d4 779 __I uint32_t DMAIntSt; /*!< Offset: 0x290 (R/ ) USB DMA Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 780 __IO uint32_t DMAIntEn; /*!< Offset: 0x294 (R/W) USB DMA Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 781 uint32_t RESERVED3[2];
Kovalev_D 23:12e6183f04d4 782 __I uint32_t EoTIntSt; /*!< Offset: 0x2A0 (R/ ) USB End of Transfer Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 783 __O uint32_t EoTIntClr; /*!< Offset: 0x2A4 ( /W) USB End of Transfer Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 784 __O uint32_t EoTIntSet; /*!< Offset: 0x2A8 ( /W) USB End of Transfer Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 785 __I uint32_t NDDRIntSt; /*!< Offset: 0x2AC (R/ ) USB New DD Request Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 786 __O uint32_t NDDRIntClr; /*!< Offset: 0x2B0 ( /W) USB New DD Request Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 787 __O uint32_t NDDRIntSet; /*!< Offset: 0x2B4 ( /W) USB New DD Request Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 788 __I uint32_t SysErrIntSt; /*!< Offset: 0x2B8 (R/ ) USB System Error Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 789 __O uint32_t SysErrIntClr; /*!< Offset: 0x2BC ( /W) USB System Error Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 790 __O uint32_t SysErrIntSet; /*!< Offset: 0x2C0 ( /W) USB System Error Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 791 uint32_t RESERVED4[15];
Kovalev_D 23:12e6183f04d4 792 /* USB OTG I2C Registers */
Kovalev_D 23:12e6183f04d4 793 union {
Kovalev_D 23:12e6183f04d4 794 __I uint32_t I2C_RX; /*!< Offset: 0x300 (R/ ) OTG I2C Receive Register */
Kovalev_D 23:12e6183f04d4 795 __O uint32_t I2C_TX; /*!< Offset: 0x300 ( /W) OTG I2C Transmit Register */
Kovalev_D 23:12e6183f04d4 796 };
Kovalev_D 23:12e6183f04d4 797 __I uint32_t I2C_STS; /*!< Offset: 0x304 (R/ ) OTG I2C Status Register */
Kovalev_D 23:12e6183f04d4 798 __IO uint32_t I2C_CTL; /*!< Offset: 0x308 (R/W) OTG I2C Control Register */
Kovalev_D 23:12e6183f04d4 799 __IO uint32_t I2C_CLKHI; /*!< Offset: 0x30C (R/W) OTG I2C Clock High Register */
Kovalev_D 23:12e6183f04d4 800 __O uint32_t I2C_CLKLO; /*!< Offset: 0x310 ( /W) OTG I2C Clock Low Register */
Kovalev_D 23:12e6183f04d4 801 uint32_t RESERVED5[824];
Kovalev_D 23:12e6183f04d4 802 /* USB Clock Control Registers */
Kovalev_D 23:12e6183f04d4 803 union {
Kovalev_D 23:12e6183f04d4 804 __IO uint32_t USBClkCtrl; /*!< Offset: 0xFF4 (R/W) OTG clock controller Register */
Kovalev_D 23:12e6183f04d4 805 __IO uint32_t OTGClkCtrl; /*!< Offset: 0xFF4 (R/W) USB clock controller Register */
Kovalev_D 23:12e6183f04d4 806 };
Kovalev_D 23:12e6183f04d4 807 union {
Kovalev_D 23:12e6183f04d4 808 __I uint32_t USBClkSt; /*!< Offset: 0xFF8 (R/ ) OTG clock status Register */
Kovalev_D 23:12e6183f04d4 809 __I uint32_t OTGClkSt; /*!< Offset: 0xFF8 (R/ ) USB clock status Register */
Kovalev_D 23:12e6183f04d4 810 };
Kovalev_D 23:12e6183f04d4 811 } LPC_USB_TypeDef;
Kovalev_D 23:12e6183f04d4 812
Kovalev_D 23:12e6183f04d4 813 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
Kovalev_D 23:12e6183f04d4 814 /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
Kovalev_D 23:12e6183f04d4 815 typedef struct
Kovalev_D 23:12e6183f04d4 816 {
Kovalev_D 23:12e6183f04d4 817 __IO uint32_t MAC1; /*!< Offset: 0x000 (R/W) MAC Configuration Register 1 */
Kovalev_D 23:12e6183f04d4 818 __IO uint32_t MAC2; /*!< Offset: 0x004 (R/W) MAC Configuration Register 2 */
Kovalev_D 23:12e6183f04d4 819 __IO uint32_t IPGT; /*!< Offset: 0x008 (R/W) Back-to-Back Inter-Packet-Gap Register */
Kovalev_D 23:12e6183f04d4 820 __IO uint32_t IPGR; /*!< Offset: 0x00C (R/W) Non Back-to-Back Inter-Packet-Gap Register */
Kovalev_D 23:12e6183f04d4 821 __IO uint32_t CLRT; /*!< Offset: 0x010 (R/W) Collision Window / Retry Register */
Kovalev_D 23:12e6183f04d4 822 __IO uint32_t MAXF; /*!< Offset: 0x014 (R/W) Maximum Frame Register */
Kovalev_D 23:12e6183f04d4 823 __IO uint32_t SUPP; /*!< Offset: 0x018 (R/W) PHY Support Register */
Kovalev_D 23:12e6183f04d4 824 __IO uint32_t TEST; /*!< Offset: 0x01C (R/W) Test Register */
Kovalev_D 23:12e6183f04d4 825 __IO uint32_t MCFG; /*!< Offset: 0x020 (R/W) MII Mgmt Configuration Register */
Kovalev_D 23:12e6183f04d4 826 __IO uint32_t MCMD; /*!< Offset: 0x024 (R/W) MII Mgmt Command Register */
Kovalev_D 23:12e6183f04d4 827 __IO uint32_t MADR; /*!< Offset: 0x028 (R/W) MII Mgmt Address Register */
Kovalev_D 23:12e6183f04d4 828 __O uint32_t MWTD; /*!< Offset: 0x02C ( /W) MII Mgmt Write Data Register */
Kovalev_D 23:12e6183f04d4 829 __I uint32_t MRDD; /*!< Offset: 0x030 (R/ ) MII Mgmt Read Data Register */
Kovalev_D 23:12e6183f04d4 830 __I uint32_t MIND; /*!< Offset: 0x034 (R/ ) MII Mgmt Indicators Register */
Kovalev_D 23:12e6183f04d4 831 uint32_t RESERVED0[2];
Kovalev_D 23:12e6183f04d4 832 __IO uint32_t SA0; /*!< Offset: 0x040 (R/W) Station Address 0 Register */
Kovalev_D 23:12e6183f04d4 833 __IO uint32_t SA1; /*!< Offset: 0x044 (R/W) Station Address 1 Register */
Kovalev_D 23:12e6183f04d4 834 __IO uint32_t SA2; /*!< Offset: 0x048 (R/W) Station Address 2 Register */
Kovalev_D 23:12e6183f04d4 835 uint32_t RESERVED1[45];
Kovalev_D 23:12e6183f04d4 836 __IO uint32_t Command; /*!< Offset: 0x100 (R/W) Command Register */
Kovalev_D 23:12e6183f04d4 837 __I uint32_t Status; /*!< Offset: 0x104 (R/ ) Status Register */
Kovalev_D 23:12e6183f04d4 838 __IO uint32_t RxDescriptor; /*!< Offset: 0x108 (R/W) Receive Descriptor Base Address Register */
Kovalev_D 23:12e6183f04d4 839 __IO uint32_t RxStatus; /*!< Offset: 0x10C (R/W) Receive Status Base Address Register */
Kovalev_D 23:12e6183f04d4 840 __IO uint32_t RxDescriptorNumber; /*!< Offset: 0x110 (R/W) Receive Number of Descriptors Register */
Kovalev_D 23:12e6183f04d4 841 __I uint32_t RxProduceIndex; /*!< Offset: 0x114 (R/ ) Receive Produce Index Register */
Kovalev_D 23:12e6183f04d4 842 __IO uint32_t RxConsumeIndex; /*!< Offset: 0x118 (R/W) Receive Consume Index Register */
Kovalev_D 23:12e6183f04d4 843 __IO uint32_t TxDescriptor; /*!< Offset: 0x11C (R/W) Transmit Descriptor Base Address Register */
Kovalev_D 23:12e6183f04d4 844 __IO uint32_t TxStatus; /*!< Offset: 0x120 (R/W) Transmit Status Base Address Register */
Kovalev_D 23:12e6183f04d4 845 __IO uint32_t TxDescriptorNumber; /*!< Offset: 0x124 (R/W) Transmit Number of Descriptors Register */
Kovalev_D 23:12e6183f04d4 846 __IO uint32_t TxProduceIndex; /*!< Offset: 0x128 (R/W) Transmit Produce Index Register */
Kovalev_D 23:12e6183f04d4 847 __I uint32_t TxConsumeIndex; /*!< Offset: 0x12C (R/ ) Transmit Consume Index Register */
Kovalev_D 23:12e6183f04d4 848 uint32_t RESERVED2[10];
Kovalev_D 23:12e6183f04d4 849 __I uint32_t TSV0; /*!< Offset: 0x158 (R/ ) Transmit Status Vector 0 Register */
Kovalev_D 23:12e6183f04d4 850 __I uint32_t TSV1; /*!< Offset: 0x15C (R/ ) Transmit Status Vector 1 Register */
Kovalev_D 23:12e6183f04d4 851 __I uint32_t RSV; /*!< Offset: 0x160 (R/ ) Receive Status Vector Register */
Kovalev_D 23:12e6183f04d4 852 uint32_t RESERVED3[3];
Kovalev_D 23:12e6183f04d4 853 __IO uint32_t FlowControlCounter; /*!< Offset: 0x170 (R/W) Flow Control Counter Register */
Kovalev_D 23:12e6183f04d4 854 __I uint32_t FlowControlStatus; /*!< Offset: 0x174 (R/ ) Flow Control Status egister */
Kovalev_D 23:12e6183f04d4 855 uint32_t RESERVED4[34];
Kovalev_D 23:12e6183f04d4 856 __IO uint32_t RxFilterCtrl; /*!< Offset: 0x200 (R/W) Receive Filter Control Register */
Kovalev_D 23:12e6183f04d4 857 __I uint32_t RxFilterWoLStatus; /*!< Offset: 0x204 (R/ ) Receive Filter WoL Status Register */
Kovalev_D 23:12e6183f04d4 858 __O uint32_t RxFilterWoLClear; /*!< Offset: 0x208 ( /W) Receive Filter WoL Clear Register */
Kovalev_D 23:12e6183f04d4 859 uint32_t RESERVED5;
Kovalev_D 23:12e6183f04d4 860 __IO uint32_t HashFilterL; /*!< Offset: 0x210 (R/W) Hash Filter Table LSBs Register */
Kovalev_D 23:12e6183f04d4 861 __IO uint32_t HashFilterH; /*!< Offset: 0x214 (R/W) Hash Filter Table MSBs Register */
Kovalev_D 23:12e6183f04d4 862 uint32_t RESERVED6[882];
Kovalev_D 23:12e6183f04d4 863 __I uint32_t IntStatus; /*!< Offset: 0xFE0 (R/ ) Interrupt Status Register */
Kovalev_D 23:12e6183f04d4 864 __IO uint32_t IntEnable; /*!< Offset: 0xFE4 (R/W) Interrupt Enable Register */
Kovalev_D 23:12e6183f04d4 865 __O uint32_t IntClear; /*!< Offset: 0xFE8 ( /W) Interrupt Clear Register */
Kovalev_D 23:12e6183f04d4 866 __O uint32_t IntSet; /*!< Offset: 0xFEC ( /W) Interrupt Set Register */
Kovalev_D 23:12e6183f04d4 867 uint32_t RESERVED7;
Kovalev_D 23:12e6183f04d4 868 __IO uint32_t PowerDown; /*!< Offset: 0xFF4 (R/W) Power-Down Register */
Kovalev_D 23:12e6183f04d4 869 } LPC_EMAC_TypeDef;
Kovalev_D 23:12e6183f04d4 870
Kovalev_D 23:12e6183f04d4 871 #if defined ( __CC_ARM )
Kovalev_D 23:12e6183f04d4 872 #pragma no_anon_unions
Kovalev_D 23:12e6183f04d4 873 #endif
Kovalev_D 23:12e6183f04d4 874
Kovalev_D 23:12e6183f04d4 875
Kovalev_D 23:12e6183f04d4 876 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 877 /* Peripheral memory map */
Kovalev_D 23:12e6183f04d4 878 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 879 /* Base addresses */
Kovalev_D 23:12e6183f04d4 880 #define LPC_FLASH_BASE (0x00000000UL)
Kovalev_D 23:12e6183f04d4 881 #define LPC_RAM_BASE (0x10000000UL)
Kovalev_D 23:12e6183f04d4 882 #ifdef __LPC17XX_REV00
Kovalev_D 23:12e6183f04d4 883 #define LPC_AHBRAM0_BASE (0x20000000UL)
Kovalev_D 23:12e6183f04d4 884 #define LPC_AHBRAM1_BASE (0x20004000UL)
Kovalev_D 23:12e6183f04d4 885 #else
Kovalev_D 23:12e6183f04d4 886 #define LPC_AHBRAM0_BASE (0x2007C000UL)
Kovalev_D 23:12e6183f04d4 887 #define LPC_AHBRAM1_BASE (0x20080000UL)
Kovalev_D 23:12e6183f04d4 888 #endif
Kovalev_D 23:12e6183f04d4 889 #define LPC_GPIO_BASE (0x2009C000UL)
Kovalev_D 23:12e6183f04d4 890 #define LPC_APB0_BASE (0x40000000UL)
Kovalev_D 23:12e6183f04d4 891 #define LPC_APB1_BASE (0x40080000UL)
Kovalev_D 23:12e6183f04d4 892 #define LPC_AHB_BASE (0x50000000UL)
Kovalev_D 23:12e6183f04d4 893 #define LPC_CM3_BASE (0xE0000000UL)
Kovalev_D 23:12e6183f04d4 894
Kovalev_D 23:12e6183f04d4 895 /* APB0 peripherals */
Kovalev_D 23:12e6183f04d4 896 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
Kovalev_D 23:12e6183f04d4 897 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
Kovalev_D 23:12e6183f04d4 898 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
Kovalev_D 23:12e6183f04d4 899 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
Kovalev_D 23:12e6183f04d4 900 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
Kovalev_D 23:12e6183f04d4 901 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
Kovalev_D 23:12e6183f04d4 902 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
Kovalev_D 23:12e6183f04d4 903 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
Kovalev_D 23:12e6183f04d4 904 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
Kovalev_D 23:12e6183f04d4 905 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
Kovalev_D 23:12e6183f04d4 906 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
Kovalev_D 23:12e6183f04d4 907 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
Kovalev_D 23:12e6183f04d4 908 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
Kovalev_D 23:12e6183f04d4 909 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
Kovalev_D 23:12e6183f04d4 910 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
Kovalev_D 23:12e6183f04d4 911 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
Kovalev_D 23:12e6183f04d4 912 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
Kovalev_D 23:12e6183f04d4 913 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
Kovalev_D 23:12e6183f04d4 914 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
Kovalev_D 23:12e6183f04d4 915
Kovalev_D 23:12e6183f04d4 916 /* APB1 peripherals */
Kovalev_D 23:12e6183f04d4 917 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
Kovalev_D 23:12e6183f04d4 918 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
Kovalev_D 23:12e6183f04d4 919 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
Kovalev_D 23:12e6183f04d4 920 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
Kovalev_D 23:12e6183f04d4 921 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
Kovalev_D 23:12e6183f04d4 922 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
Kovalev_D 23:12e6183f04d4 923 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
Kovalev_D 23:12e6183f04d4 924 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
Kovalev_D 23:12e6183f04d4 925 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
Kovalev_D 23:12e6183f04d4 926 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
Kovalev_D 23:12e6183f04d4 927 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
Kovalev_D 23:12e6183f04d4 928 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
Kovalev_D 23:12e6183f04d4 929
Kovalev_D 23:12e6183f04d4 930 /* AHB peripherals */
Kovalev_D 23:12e6183f04d4 931 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
Kovalev_D 23:12e6183f04d4 932 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
Kovalev_D 23:12e6183f04d4 933 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
Kovalev_D 23:12e6183f04d4 934 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
Kovalev_D 23:12e6183f04d4 935 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
Kovalev_D 23:12e6183f04d4 936 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
Kovalev_D 23:12e6183f04d4 937 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
Kovalev_D 23:12e6183f04d4 938 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
Kovalev_D 23:12e6183f04d4 939 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
Kovalev_D 23:12e6183f04d4 940 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
Kovalev_D 23:12e6183f04d4 941 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
Kovalev_D 23:12e6183f04d4 942
Kovalev_D 23:12e6183f04d4 943 /* GPIOs */
Kovalev_D 23:12e6183f04d4 944 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
Kovalev_D 23:12e6183f04d4 945 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
Kovalev_D 23:12e6183f04d4 946 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
Kovalev_D 23:12e6183f04d4 947 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
Kovalev_D 23:12e6183f04d4 948 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
Kovalev_D 23:12e6183f04d4 949
Kovalev_D 23:12e6183f04d4 950
Kovalev_D 23:12e6183f04d4 951 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 952 /* Peripheral declaration */
Kovalev_D 23:12e6183f04d4 953 /******************************************************************************/
Kovalev_D 23:12e6183f04d4 954 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
Kovalev_D 23:12e6183f04d4 955 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
Kovalev_D 23:12e6183f04d4 956 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
Kovalev_D 23:12e6183f04d4 957 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
Kovalev_D 23:12e6183f04d4 958 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
Kovalev_D 23:12e6183f04d4 959 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
Kovalev_D 23:12e6183f04d4 960 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
Kovalev_D 23:12e6183f04d4 961 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
Kovalev_D 23:12e6183f04d4 962 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
Kovalev_D 23:12e6183f04d4 963 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
Kovalev_D 23:12e6183f04d4 964 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
Kovalev_D 23:12e6183f04d4 965 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
Kovalev_D 23:12e6183f04d4 966 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
Kovalev_D 23:12e6183f04d4 967 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
Kovalev_D 23:12e6183f04d4 968 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
Kovalev_D 23:12e6183f04d4 969 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
Kovalev_D 23:12e6183f04d4 970 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
Kovalev_D 23:12e6183f04d4 971 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
Kovalev_D 23:12e6183f04d4 972 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
Kovalev_D 23:12e6183f04d4 973 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
Kovalev_D 23:12e6183f04d4 974 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
Kovalev_D 23:12e6183f04d4 975 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
Kovalev_D 23:12e6183f04d4 976 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
Kovalev_D 23:12e6183f04d4 977 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
Kovalev_D 23:12e6183f04d4 978 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
Kovalev_D 23:12e6183f04d4 979 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
Kovalev_D 23:12e6183f04d4 980 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
Kovalev_D 23:12e6183f04d4 981 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
Kovalev_D 23:12e6183f04d4 982 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
Kovalev_D 23:12e6183f04d4 983 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
Kovalev_D 23:12e6183f04d4 984 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
Kovalev_D 23:12e6183f04d4 985 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
Kovalev_D 23:12e6183f04d4 986 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
Kovalev_D 23:12e6183f04d4 987 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
Kovalev_D 23:12e6183f04d4 988 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
Kovalev_D 23:12e6183f04d4 989 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
Kovalev_D 23:12e6183f04d4 990 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
Kovalev_D 23:12e6183f04d4 991 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
Kovalev_D 23:12e6183f04d4 992 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
Kovalev_D 23:12e6183f04d4 993 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
Kovalev_D 23:12e6183f04d4 994 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
Kovalev_D 23:12e6183f04d4 995 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
Kovalev_D 23:12e6183f04d4 996 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
Kovalev_D 23:12e6183f04d4 997 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
Kovalev_D 23:12e6183f04d4 998 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
Kovalev_D 23:12e6183f04d4 999 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
Kovalev_D 23:12e6183f04d4 1000 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
Kovalev_D 23:12e6183f04d4 1001
Kovalev_D 23:12e6183f04d4 1002
Kovalev_D 23:12e6183f04d4 1003 /**
Kovalev_D 23:12e6183f04d4 1004 * @}
Kovalev_D 23:12e6183f04d4 1005 */
Kovalev_D 23:12e6183f04d4 1006
Kovalev_D 23:12e6183f04d4 1007 #endif // __LPC17xx_H__