LPC_SC_TypeDef Struct Reference
[LPC17xx_System]

Offset: 0x110 (R/W) CAN Sleep Clear Register

Definition at line 144 of file LPC17xx.h.

Offset: 0x114 (R/W) CAN Wake-up Flags Register

Definition at line 145 of file LPC17xx.h.

Offset: 0x104 (R/W) CPU Clock Configure Register

Definition at line 141 of file LPC17xx.h.

Offset: 0x1C8 (R/W) Clock Output Configuration Register

Definition at line 161 of file LPC17xx.h.

Offset: 0x10C (R/W) Clock Source Select Register

Definition at line 143 of file LPC17xx.h.

Offset: 0x1C4 (R/W) DMA Request Select Register

Definition at line 160 of file LPC17xx.h.

Offset: 0x140 (R/W) External Interrupt Flag Register

Definition at line 147 of file LPC17xx.h.

Offset: 0x148 (R/W) External Interrupt Mode Register

Definition at line 149 of file LPC17xx.h.

Offset: 0x14C (R/W) External Interrupt Polarity Register

Definition at line 150 of file LPC17xx.h.

Offset: 0x000 (R/W) Flash Accelerator Configuration Register

Definition at line 126 of file LPC17xx.h.

Offset: 0x1A8 (R/W) Peripheral Clock Select 0 Register

Definition at line 156 of file LPC17xx.h.

Offset: 0x1AC (R/W) Peripheral Clock Select 1 Register

Definition at line 157 of file LPC17xx.h.

Offset: 0x0C0 (R/W) Power Control Register

Definition at line 138 of file LPC17xx.h.

Offset: 0x0C4 (R/W) Power Control for Peripherals Register

Definition at line 139 of file LPC17xx.h.

Offset: 0x084 (R/W) PLL0 Configuration Register

Definition at line 129 of file LPC17xx.h.

Offset: 0x080 (R/W) PLL0 Control Register

Definition at line 128 of file LPC17xx.h.

Offset: 0x08C ( /W) PLL0 Feed Register

Definition at line 131 of file LPC17xx.h.

Offset: 0x088 (R/ ) PLL0 Status Register

Definition at line 130 of file LPC17xx.h.

Offset: 0x0A4 (R/W) PLL1 Configuration Register

Definition at line 134 of file LPC17xx.h.

Offset: 0x0A0 (R/W) PLL1 Control Register

Definition at line 133 of file LPC17xx.h.

Offset: 0x0AC ( /W) PLL1 Feed Register

Definition at line 136 of file LPC17xx.h.

Offset: 0x0A8 (R/ ) PLL1 Status Register

Definition at line 135 of file LPC17xx.h.

Offset: 0x180 (R/W) Reset Source Identification Register

Definition at line 152 of file LPC17xx.h.

Offset: 0x1A0 (R/W) System Controls and Status Register

Definition at line 154 of file LPC17xx.h.

Offset: 0x108 (R/W) USB Clock Configure Register

Definition at line 142 of file LPC17xx.h.

Offset: 0x1C0 (R/W) USB Interrupt Status Register

Definition at line 159 of file LPC17xx.h.