Dmitry Kovalev
fork
Diff: system_LPC17xx.c
- Revision:
- 135:c1e30e0e8949
- Parent:
- 134:caf4c9cd5052
- Child:
- 136:19b9e6abb86f
--- a/system_LPC17xx.c Thu Apr 14 14:13:18 2016 +0000
+++ b/system_LPC17xx.c Thu Apr 14 16:48:48 2016 +0000
@@ -9,9 +9,9 @@
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
@@ -287,12 +287,12 @@
//нам нужно 921600* 16 = 14 745 000, теперб выбираем делитель уартовский 7 = 103 219 200, дибо 8 = 117 964 800
//1 выбираем второе 117 964 800 округляем до 100 000 (для второго таймера) 118 000. таку. частоту нужно на входе УАРТА.
-//118 * 3 = 354, 118 * 4 = 472.
+//118 * 3 = 354, 118 * 4 = 472.
// 354 / "3" = 118
//попробуем с 474 >> умножитель на 59 и делитель на 3 => 12 * 2 * ("58" + 1) / ("2" + 1) = 472.
// 472 / "4" = 118
-
+
// с другой стороны не рекомендуют частоты выше 100 (120 только для 1769 или чото там еще )
// 103,200 => *3 = 309.6; * 4 = 412,8.
// 412,8 умножитель на 86 и делитель на 5 => 12 * 2 * ("85" + 1) / ("4" + 1) = 412,8. !!!!!наверно можно остоновиься и попробовать!!!!!!!!
@@ -461,6 +461,7 @@
// 0011 Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
// 0100 Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.
// 0101 Flash accesses use 6 CPU clocks. This “safe” setting will work under any conditions. Other Intended for potential future higher speed devices.
+
// 31:16 - Reserved. The value read from a reserved bit is not defined. NA
#define FLASHCFG_Val 0x0000303A//5 CPU clocks required for flash access 30720
@@ -476,55 +477,55 @@
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x00000030))
- #error "SCS: Invalid values of reserved bits!"
+#error "SCS: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
- #error "CLKSRCSEL: Value out of range!"
+#error "CLKSRCSEL: Value out of range!"
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
- #error "PLL0CFG: Invalid values of reserved bits!"
+#error "PLL0CFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
- #error "PLL1CFG: Invalid values of reserved bits!"
+#error "PLL1CFG: Invalid values of reserved bits!"
#endif
#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
- #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
+#error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
#endif
#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
- #error "USBCLKCFG: Invalid values of reserved bits!"
+#error "USBCLKCFG: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
- #error "PCLKSEL0: Invalid values of reserved bits!"
+#error "PCLKSEL0: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
- #error "PCLKSEL1: Invalid values of reserved bits!"
+#error "PCLKSEL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PCONP_Val), 0x10100821))
- #error "PCONP: Invalid values of reserved bits!"
+#error "PCONP: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
- #error "CLKOUTCFG: Invalid values of reserved bits!"
+#error "CLKOUTCFG: Invalid values of reserved bits!"
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
- #error "FLASHCFG: Invalid values of reserved bits!"
+#error "FLASHCFG: Invalid values of reserved bits!"
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
-
+
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
@@ -537,27 +538,27 @@
/* F_cco0 = (2 * M * F_in) / N */
#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
-#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
+#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
/* Determine core clock frequency according to settings */
- #if (PLL0_SETUP)
- #if ((CLKSRCSEL_Val & 0x03) == 1)
- #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
- #elif ((CLKSRCSEL_Val & 0x03) == 2)
- #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
- #else
- #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
- #endif
- #else
- #if ((CLKSRCSEL_Val & 0x03) == 1)
- #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
- #elif ((CLKSRCSEL_Val & 0x03) == 2)
- #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
- #else
- #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
- #endif
- #endif
+#if (PLL0_SETUP)
+#if ((CLKSRCSEL_Val & 0x03) == 1)
+#define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+#elif ((CLKSRCSEL_Val & 0x03) == 2)
+#define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+#else
+#define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+#endif
+#else
+#if ((CLKSRCSEL_Val & 0x03) == 1)
+#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+#elif ((CLKSRCSEL_Val & 0x03) == 2)
+#define __CORE_CLK (RTC_CLK / __CCLK_DIV)
+#else
+#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+#endif
+#endif
/*----------------------------------------------------------------------------
@@ -572,43 +573,43 @@
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate1 (void) /* Get Core Clock Frequency */
{
- /* Determine clock frequency according to clock register values */
- if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Int. RC oscillator => PLL0 */
- case 3: /* Reserved, default to Int. RC */
- SystemCoreClock1 = (IRC_OSC *
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemCoreClock1 = (OSC_CLK * //it is our case osc_clk = 12 MHz
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider
- ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock)
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemCoreClock1 = (RTC_CLK *
- ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock1 = (IRC_OSC *
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock1 = (OSC_CLK * //it is our case osc_clk = 12 MHz
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock)
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock1 = (RTC_CLK *
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
}
- } else {
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Int. RC oscillator => PLL0 */
- case 3: /* Reserved, default to Int. RC */
- SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- }
- }
}
@@ -623,77 +624,75 @@
*/
void SystemInit1 (void)
{
-
+#if (CLOCK_SETUP) /* Clock Setup */
+ //Init system control and status register
+ LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz)
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
-#if (CLOCK_SETUP) /* Clock Setup */
- //Init system control and status register
- LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz)
- if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
- while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
- }
-
- //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output
- LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz)
+ //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output
+ LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz)
#if (PLL0_SETUP)
- //Init Clock Source Select register
- LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source
- //Init PLL0 Configuration register
- LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz
- //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG
- //registers into the shadow registers that actually affect PLL0 operation.
- //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
- //Init PLL0 Control register
- // bit 0 - PLL0 Enable
- // bit 1 - PLL0 connect
- LPC_SC->PLL0CON = 0x01;//PLL0 Enable
- //Update shadow registers to settings take effect
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
- //PLL0 Status register
- // bits 0...14 - Read-back for the PLL0 Multiplier value
- // bits 16...23 - Read-back for the PLL0 Pre-Divider value
- // bit 24 - Read-back for the PLL0 Enable bit
- // bit 25 - Read-back for the PLL0 Connect bit
- // bit 26 - Reflects the PLL0 Lock status: 1 - locked
- while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0)
+ //Init Clock Source Select register
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source
+ //Init PLL0 Configuration register
+ LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz
+ //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG
+ //registers into the shadow registers that actually affect PLL0 operation.
+ //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ //Init PLL0 Control register
+ // bit 0 - PLL0 Enable
+ // bit 1 - PLL0 connect
+ LPC_SC->PLL0CON = 0x01;//PLL0 Enable
+ //Update shadow registers to settings take effect
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ //PLL0 Status register
+ // bits 0...14 - Read-back for the PLL0 Multiplier value
+ // bits 16...23 - Read-back for the PLL0 Pre-Divider value
+ // bit 24 - Read-back for the PLL0 Enable bit
+ // bit 25 - Read-back for the PLL0 Connect bit
+ // bit 26 - Reflects the PLL0 Lock status: 1 - locked
+ while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0)
- LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
- while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT)
+ LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT)
#endif
#if (PLL1_SETUP)
- LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
+ LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
- LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
- while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
- LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
- while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
#else
- LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
#endif
- LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
- LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
- LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
- LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
- LPC_SC->FLASHCFG = FLASHCFG_Val;
+ LPC_SC->FLASHCFG = FLASHCFG_Val;
#endif
}
@@ -708,88 +707,88 @@
#if (CLOCK_SETUP) /* Clock Setup */
- LPC_SC->SCS = SCS_Val;
- if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
- while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
- }
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
- LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
- LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
- LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
#if (PLL0_SETUP)
- LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
- LPC_SC->PLL0CFG = PLL0CFG_Val;
- LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
- while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
- LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
#endif
#if (PLL1_SETUP)
- LPC_SC->PLL1CFG = PLL1CFG_Val;
- LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
- while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
- LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
#else
- LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
#endif
- LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
- LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+ LPC_SC->CLKOUTCFG = 0x0000303A;//CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
- /* Determine clock frequency according to clock register values */
- if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Internal RC oscillator => PLL0 */
- case 3: /* Reserved, default to Internal RC */
- SystemFrequency = (IRC_OSC *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemFrequency = (OSC_CLK *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemFrequency = (RTC_CLK *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = (IRC_OSC *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = (OSC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = (RTC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
}
- } else {
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Internal RC oscillator => PLL0 */
- case 3: /* Reserved, default to Internal RC */
- SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- }
- }
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
- LPC_SC->FLASHCFG = FLASHCFG_Val;
+ LPC_SC->FLASHCFG = FLASHCFG_Val;
#endif
}
@@ -807,91 +806,91 @@
{
-
+
#if (CLOCK_SETUP) /* Clock Setup */
- LPC_SC->SCS = SCS_Val;
- if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
- while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
- }
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
- LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
- LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
- LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
#if (PLL0_SETUP)
- LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
- LPC_SC->PLL0CFG = PLL0CFG_Val;
- LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
- while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+ LPC_SC->CLKSRCSEL = 0; CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
- LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
- LPC_SC->PLL0FEED = 0xAA;
- LPC_SC->PLL0FEED = 0x55;
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
#endif
#if (PLL1_SETUP)
- LPC_SC->PLL1CFG = PLL1CFG_Val;
- LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
- while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
- LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
- LPC_SC->PLL1FEED = 0xAA;
- LPC_SC->PLL1FEED = 0x55;
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
#else
- LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
#endif
- LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
- LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
#endif
- /* Determine clock frequency according to clock register values */
- if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Internal RC oscillator => PLL0 */
- case 3: /* Reserved, default to Internal RC */
- SystemFrequency = (IRC_OSC *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemFrequency = (OSC_CLK *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemFrequency = (RTC_CLK *
- (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
- (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
- ((LPC_SC->CCLKCFG & 0xFF)+ 1));
- break;
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24)&3)==3) {/* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = (IRC_OSC *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = (OSC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = (RTC_CLK *
+ (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Internal RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Internal RC */
+ SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
}
- } else {
- switch (LPC_SC->CLKSRCSEL & 0x03) {
- case 0: /* Internal RC oscillator => PLL0 */
- case 3: /* Reserved, default to Internal RC */
- SystemFrequency = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 1: /* Main oscillator => PLL0 */
- SystemFrequency = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- case 2: /* RTC oscillator => PLL0 */
- SystemFrequency = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
- break;
- }
- }
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
- LPC_SC->FLASHCFG = FLASHCFG_Val;
+ LPC_SC->FLASHCFG = FLASHCFG_Val;
#endif