Diff: system_LPC17xx.c

Revision:

12:74bd0ecf7f83

Parent:

2:2d0b80ed9216

Child:

44:80289a836583

--- a/system_LPC17xx.c	Mon Feb 01 16:40:49 2016 +0000
+++ b/system_LPC17xx.c	Tue Feb 02 14:42:57 2016 +0000
@@ -422,32 +422,32 @@
 /*----------------------------------------------------------------------------
   Clock Variable definitions
  *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t SystemCoreClock1 = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
 
 
 /*----------------------------------------------------------------------------
   Clock functions
  *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+void SystemCoreClockUpdate1 (void)            /* Get Core Clock Frequency      */
 {
   /* Determine clock frequency according to clock register values             */
   if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
     switch (LPC_SC->CLKSRCSEL & 0x03) {
       case 0:                                /* Int. RC oscillator => PLL0    */
       case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = (IRC_OSC * 
+        SystemCoreClock1 = (IRC_OSC * 
                           ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
         break;
       case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = (OSC_CLK *         //it is our case osc_clk = 12 MHz
+        SystemCoreClock1 = (OSC_CLK *         //it is our case osc_clk = 12 MHz
                           ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /	//PLL0 multiplier value
                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /	//PLL0 pre-divider
                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));				//divider for CCLK (SystemCoreClock)
         break;
       case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = (RTC_CLK * 
+        SystemCoreClock1 = (RTC_CLK * 
                           ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
                           (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
                           ((LPC_SC->CCLKCFG & 0xFF)+ 1));
@@ -457,13 +457,13 @@
     switch (LPC_SC->CLKSRCSEL & 0x03) {
       case 0:                                /* Int. RC oscillator => PLL0    */
       case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
         break;
       case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
         break;
       case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+        SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
         break;
     }
   }
@@ -479,7 +479,7 @@
  * @brief  Setup the microcontroller system.
  *         Initialize the System.
  */
-void SystemInit (void)
+void SystemInit1 (void)
 {
 #if (CLOCK_SETUP)                       /* Clock Setup                        */
   LPC_SC->SCS       = SCS_Val;