Diff: system_LPC17xx.c

Revision:

214:4c70e452c491

Parent:

164:6f43f85fdd8d

--- a/system_LPC17xx.c	Wed Jul 26 13:24:39 2017 +0000
+++ b/system_LPC17xx.c	Wed Aug 16 09:00:25 2017 +0000
@@ -359,7 +359,7 @@
 //  10 PCLK_peripheral = CCLK/2
 //  11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.
 //#define PCLKSEL0_Val          0x00000010//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
-  #define PCLKSEL0_Val          0x00000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
+  #define PCLKSEL0_Val          0x40000150//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
 //#define PCLKSEL0_Val          0x000003d0//Peripheral clock selection for TIMER1 - CCLK, other peripherals - CCLK/4
 //Peripheral Clock Selection register 1
 //  1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00