Dmitry Kovalev / Mbed 2 deprecated LG2

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Dependencies:   mbed

Fork of LG by igor Apu

system_LPC17xx.c@44:80289a836583, 2016-02-09 (annotated)

Committer:
Diletant
Date:
Tue Feb 09 07:47:33 2016 +0000
Revision:
44:80289a836583
Parent:
12:74bd0ecf7f83
Child:
46:2670fa0fcebc
Comments added for SystemInit1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
igor_v 2:2d0b80ed9216 1 /**************************************************************************//**
igor_v 2:2d0b80ed9216 2 * @file system_LPC17xx.c
igor_v 2:2d0b80ed9216 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
igor_v 2:2d0b80ed9216 4 * for the NXP LPC17xx Device Series
igor_v 2:2d0b80ed9216 5 * @version V1.03
igor_v 2:2d0b80ed9216 6 * @date 07. October 2009
igor_v 2:2d0b80ed9216 7 *
igor_v 2:2d0b80ed9216 8 * @note
igor_v 2:2d0b80ed9216 9 * Copyright (C) 2009 ARM Limited. All rights reserved.
igor_v 2:2d0b80ed9216 10 *
igor_v 2:2d0b80ed9216 11 * @par
igor_v 2:2d0b80ed9216 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
igor_v 2:2d0b80ed9216 13 * processor based microcontrollers. This file can be freely distributed
igor_v 2:2d0b80ed9216 14 * within development tools that are supporting such ARM based processors.
igor_v 2:2d0b80ed9216 15 *
igor_v 2:2d0b80ed9216 16 * @par
igor_v 2:2d0b80ed9216 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
igor_v 2:2d0b80ed9216 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
igor_v 2:2d0b80ed9216 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
igor_v 2:2d0b80ed9216 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
igor_v 2:2d0b80ed9216 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
igor_v 2:2d0b80ed9216 22 *
igor_v 2:2d0b80ed9216 23 ******************************************************************************/
igor_v 2:2d0b80ed9216 24
igor_v 2:2d0b80ed9216 25
igor_v 2:2d0b80ed9216 26 #include <stdint.h>
igor_v 2:2d0b80ed9216 27 #include "LPC17xx.h"
igor_v 2:2d0b80ed9216 28
igor_v 2:2d0b80ed9216 29 /*
igor_v 2:2d0b80ed9216 30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
igor_v 2:2d0b80ed9216 31 */
igor_v 2:2d0b80ed9216 32
igor_v 2:2d0b80ed9216 33 /*--------------------- Clock Configuration ----------------------------------
igor_v 2:2d0b80ed9216 34 //
igor_v 2:2d0b80ed9216 35 // <e> Clock Configuration
igor_v 2:2d0b80ed9216 36 // <h> System Controls and Status Register (SCS)
igor_v 2:2d0b80ed9216 37 // <o1.4> OSCRANGE: Main Oscillator Range Select
igor_v 2:2d0b80ed9216 38 // <0=> 1 MHz to 20 MHz
igor_v 2:2d0b80ed9216 39 // <1=> 15 MHz to 24 MHz
igor_v 2:2d0b80ed9216 40 // <e1.5> OSCEN: Main Oscillator Enable
igor_v 2:2d0b80ed9216 41 // </e>
igor_v 2:2d0b80ed9216 42 // </h>
igor_v 2:2d0b80ed9216 43 //
igor_v 2:2d0b80ed9216 44 // <h> Clock Source Select Register (CLKSRCSEL)
igor_v 2:2d0b80ed9216 45 // <o2.0..1> CLKSRC: PLL Clock Source Selection
igor_v 2:2d0b80ed9216 46 // <0=> Internal RC oscillator
igor_v 2:2d0b80ed9216 47 // <1=> Main oscillator
igor_v 2:2d0b80ed9216 48 // <2=> RTC oscillator
igor_v 2:2d0b80ed9216 49 // </h>
igor_v 2:2d0b80ed9216 50 //
igor_v 2:2d0b80ed9216 51 // <e3> PLL0 Configuration (Main PLL)
igor_v 2:2d0b80ed9216 52 // <h> PLL0 Configuration Register (PLL0CFG)
igor_v 2:2d0b80ed9216 53 // <i> F_cco0 = (2 * M * F_in) / N
igor_v 2:2d0b80ed9216 54 // <i> F_in must be in the range of 32 kHz to 50 MHz
igor_v 2:2d0b80ed9216 55 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
igor_v 2:2d0b80ed9216 56 // <o4.0..14> MSEL: PLL Multiplier Selection
igor_v 2:2d0b80ed9216 57 // <6-32768><#-1>
igor_v 2:2d0b80ed9216 58 // <i> M Value
igor_v 2:2d0b80ed9216 59 // <o4.16..23> NSEL: PLL Divider Selection
igor_v 2:2d0b80ed9216 60 // <1-256><#-1>
igor_v 2:2d0b80ed9216 61 // <i> N Value
igor_v 2:2d0b80ed9216 62 // </h>
igor_v 2:2d0b80ed9216 63 // </e>
igor_v 2:2d0b80ed9216 64 //
igor_v 2:2d0b80ed9216 65 // <e5> PLL1 Configuration (USB PLL)
igor_v 2:2d0b80ed9216 66 // <h> PLL1 Configuration Register (PLL1CFG)
igor_v 2:2d0b80ed9216 67 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
igor_v 2:2d0b80ed9216 68 // <i> F_cco1 = F_osc * M * 2 * P
igor_v 2:2d0b80ed9216 69 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
igor_v 2:2d0b80ed9216 70 // <o6.0..4> MSEL: PLL Multiplier Selection
igor_v 2:2d0b80ed9216 71 // <1-32><#-1>
igor_v 2:2d0b80ed9216 72 // <i> M Value (for USB maximum value is 4)
igor_v 2:2d0b80ed9216 73 // <o6.5..6> PSEL: PLL Divider Selection
igor_v 2:2d0b80ed9216 74 // <0=> 1
igor_v 2:2d0b80ed9216 75 // <1=> 2
igor_v 2:2d0b80ed9216 76 // <2=> 4
igor_v 2:2d0b80ed9216 77 // <3=> 8
igor_v 2:2d0b80ed9216 78 // <i> P Value
igor_v 2:2d0b80ed9216 79 // </h>
igor_v 2:2d0b80ed9216 80 // </e>
igor_v 2:2d0b80ed9216 81 //
igor_v 2:2d0b80ed9216 82 // <h> CPU Clock Configuration Register (CCLKCFG)
igor_v 2:2d0b80ed9216 83 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
igor_v 2:2d0b80ed9216 84 // <3-256><#-1>
igor_v 2:2d0b80ed9216 85 // </h>
igor_v 2:2d0b80ed9216 86 //
igor_v 2:2d0b80ed9216 87 // <h> USB Clock Configuration Register (USBCLKCFG)
igor_v 2:2d0b80ed9216 88 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
igor_v 2:2d0b80ed9216 89 // <0-15>
igor_v 2:2d0b80ed9216 90 // <i> Divide is USBSEL + 1
igor_v 2:2d0b80ed9216 91 // </h>
igor_v 2:2d0b80ed9216 92 //
igor_v 2:2d0b80ed9216 93 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
igor_v 2:2d0b80ed9216 94 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
igor_v 2:2d0b80ed9216 95 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 96 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 97 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 98 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 99 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
igor_v 2:2d0b80ed9216 100 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 101 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 102 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 103 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 104 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
igor_v 2:2d0b80ed9216 105 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 106 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 107 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 108 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 109 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
igor_v 2:2d0b80ed9216 110 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 111 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 112 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 113 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 114 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
igor_v 2:2d0b80ed9216 115 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 116 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 117 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 118 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 119 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
igor_v 2:2d0b80ed9216 120 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 121 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 122 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 123 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 124 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
igor_v 2:2d0b80ed9216 125 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 126 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 127 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 128 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 129 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
igor_v 2:2d0b80ed9216 130 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 131 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 132 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 133 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 134 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
igor_v 2:2d0b80ed9216 135 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 136 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 137 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 138 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 139 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
igor_v 2:2d0b80ed9216 140 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 141 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 142 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 143 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 144 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
igor_v 2:2d0b80ed9216 145 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 146 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 147 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 148 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 149 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
igor_v 2:2d0b80ed9216 150 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 151 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 152 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 153 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 154 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
igor_v 2:2d0b80ed9216 155 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 156 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 157 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 158 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 159 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
igor_v 2:2d0b80ed9216 160 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 161 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 162 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 163 // <3=> Pclk = Hclk / 6
igor_v 2:2d0b80ed9216 164 // </h>
igor_v 2:2d0b80ed9216 165 //
igor_v 2:2d0b80ed9216 166 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
igor_v 2:2d0b80ed9216 167 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
igor_v 2:2d0b80ed9216 168 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 169 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 170 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 171 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 172 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
igor_v 2:2d0b80ed9216 173 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 174 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 175 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 176 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 177 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
igor_v 2:2d0b80ed9216 178 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 179 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 180 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 181 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 182 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
igor_v 2:2d0b80ed9216 183 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 184 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 185 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 186 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 187 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
igor_v 2:2d0b80ed9216 188 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 189 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 190 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 191 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 192 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
igor_v 2:2d0b80ed9216 193 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 194 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 195 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 196 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 197 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
igor_v 2:2d0b80ed9216 198 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 199 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 200 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 201 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 202 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
igor_v 2:2d0b80ed9216 203 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 204 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 205 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 206 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 207 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
igor_v 2:2d0b80ed9216 208 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 209 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 210 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 211 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 212 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
igor_v 2:2d0b80ed9216 213 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 214 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 215 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 216 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 217 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
igor_v 2:2d0b80ed9216 218 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 219 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 220 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 221 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 222 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
igor_v 2:2d0b80ed9216 223 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 224 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 225 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 226 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 227 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
igor_v 2:2d0b80ed9216 228 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 229 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 230 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 231 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 232 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
igor_v 2:2d0b80ed9216 233 // <0=> Pclk = Cclk / 4
igor_v 2:2d0b80ed9216 234 // <1=> Pclk = Cclk
igor_v 2:2d0b80ed9216 235 // <2=> Pclk = Cclk / 2
igor_v 2:2d0b80ed9216 236 // <3=> Pclk = Hclk / 8
igor_v 2:2d0b80ed9216 237 // </h>
igor_v 2:2d0b80ed9216 238 //
igor_v 2:2d0b80ed9216 239 // <h> Power Control for Peripherals Register (PCONP)
igor_v 2:2d0b80ed9216 240 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
igor_v 2:2d0b80ed9216 241 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
igor_v 2:2d0b80ed9216 242 // <o11.3> PCUART0: UART 0 power/clock enable
igor_v 2:2d0b80ed9216 243 // <o11.4> PCUART1: UART 1 power/clock enable
igor_v 2:2d0b80ed9216 244 // <o11.6> PCPWM1: PWM 1 power/clock enable
igor_v 2:2d0b80ed9216 245 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
igor_v 2:2d0b80ed9216 246 // <o11.8> PCSPI: SPI interface power/clock enable
igor_v 2:2d0b80ed9216 247 // <o11.9> PCRTC: RTC power/clock enable
igor_v 2:2d0b80ed9216 248 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
igor_v 2:2d0b80ed9216 249 // <o11.12> PCAD: A/D converter power/clock enable
igor_v 2:2d0b80ed9216 250 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
igor_v 2:2d0b80ed9216 251 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
igor_v 2:2d0b80ed9216 252 // <o11.15> PCGPIO: GPIOs power/clock enable
igor_v 2:2d0b80ed9216 253 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
igor_v 2:2d0b80ed9216 254 // <o11.17> PCMC: Motor control PWM power/clock enable
igor_v 2:2d0b80ed9216 255 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
igor_v 2:2d0b80ed9216 256 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
igor_v 2:2d0b80ed9216 257 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
igor_v 2:2d0b80ed9216 258 // <o11.22> PCTIM2: Timer 2 power/clock enable
igor_v 2:2d0b80ed9216 259 // <o11.23> PCTIM3: Timer 3 power/clock enable
igor_v 2:2d0b80ed9216 260 // <o11.24> PCUART2: UART 2 power/clock enable
igor_v 2:2d0b80ed9216 261 // <o11.25> PCUART3: UART 3 power/clock enable
igor_v 2:2d0b80ed9216 262 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
igor_v 2:2d0b80ed9216 263 // <o11.27> PCI2S: I2S interface power/clock enable
igor_v 2:2d0b80ed9216 264 // <o11.29> PCGPDMA: GP DMA function power/clock enable
igor_v 2:2d0b80ed9216 265 // <o11.30> PCENET: Ethernet block power/clock enable
igor_v 2:2d0b80ed9216 266 // <o11.31> PCUSB: USB interface power/clock enable
igor_v 2:2d0b80ed9216 267 // </h>
igor_v 2:2d0b80ed9216 268 //
igor_v 2:2d0b80ed9216 269 // <h> Clock Output Configuration Register (CLKOUTCFG)
igor_v 2:2d0b80ed9216 270 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
igor_v 2:2d0b80ed9216 271 // <0=> CPU clock
igor_v 2:2d0b80ed9216 272 // <1=> Main oscillator
igor_v 2:2d0b80ed9216 273 // <2=> Internal RC oscillator
igor_v 2:2d0b80ed9216 274 // <3=> USB clock
igor_v 2:2d0b80ed9216 275 // <4=> RTC oscillator
igor_v 2:2d0b80ed9216 276 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
igor_v 2:2d0b80ed9216 277 // <1-16><#-1>
igor_v 2:2d0b80ed9216 278 // <o12.8> CLKOUT_EN: CLKOUT enable control
igor_v 2:2d0b80ed9216 279 // </h>
igor_v 2:2d0b80ed9216 280 //
igor_v 2:2d0b80ed9216 281 // </e>
igor_v 2:2d0b80ed9216 282 */
Diletant 44:80289a836583 283
igor_v 2:2d0b80ed9216 284 #define CLOCK_SETUP 1
Diletant 44:80289a836583 285 //System control - system control and status register:
Diletant 44:80289a836583 286 // bit 4 - main oscillator range:
Diletant 44:80289a836583 287 // 0 - 1...20MHz
Diletant 44:80289a836583 288 // 1 - 15...25MHz
Diletant 44:80289a836583 289 // bit 5 - main oscillator enable
Diletant 44:80289a836583 290 // 0 - disabled
Diletant 44:80289a836583 291 // 1 - enabled
Diletant 44:80289a836583 292 // bit 6 - main oscillator status
Diletant 44:80289a836583 293 // 0 - not ready
Diletant 44:80289a836583 294 // 1 - ready
Diletant 44:80289a836583 295 #define SCS_Val 0x00000020 //Enable main oscillator,1...20MHz
Diletant 44:80289a836583 296 //Clock Source Select register
Diletant 44:80289a836583 297 // bits 0-1:
Diletant 44:80289a836583 298 // 00 - Selects the Internal RC oscillator as the PLL0 clock source (default)
Diletant 44:80289a836583 299 // 01 - Selects the main oscillator as the PLL0 clock source
Diletant 44:80289a836583 300 // 10 - Selects the RTC oscillator as the PLL0 clock source
Diletant 44:80289a836583 301 // 11 - Reserved, do not use this setting
Diletant 44:80289a836583 302 #define CLKSRCSEL_Val 0x00000001//Select the main oscillator as the PLL0 clock source
igor_v 2:2d0b80ed9216 303 #define PLL0_SETUP 1
Diletant 44:80289a836583 304 //PLL0 Configuration register
Diletant 44:80289a836583 305 // bits 0...14 - PLL0 multiplier value minus 1. Supported multiplier M range 6...512
Diletant 44:80289a836583 306 // bits 16...23 - PLL0 Pre-Divider value minus 1. Supported divider N range 1...32
Diletant 44:80289a836583 307 // Fcc0 = (2 * M * Fin) / N
Diletant 44:80289a836583 308 #define PLL0CFG_Val 0x00050063//M - 100, N - 6, output = 2 * 100 * 12MHz / 6 = 400MHz
igor_v 2:2d0b80ed9216 309 #define PLL1_SETUP 1
Diletant 44:80289a836583 310 #define PLL1CFG_Val 0x00000023//M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
Diletant 44:80289a836583 311 //CPU Clock Configure Register
Diletant 44:80289a836583 312 #define CCLKCFG_Val 0x00000003 //Divide by 4
Diletant 44:80289a836583 313 //USB Clock Configuration register
Diletant 44:80289a836583 314 // bits 0...3
Diletant 44:80289a836583 315 // 5 - PLL0 output is divided by 6. PLL0 output must be 288 MHz
Diletant 44:80289a836583 316 // 7 - PLL0 output is divided by 8. PLL0 output must be 384 MHz
Diletant 44:80289a836583 317 // 9 - PLL0 output is divided by 10. PLL0 output must be 480 MHz
Diletant 44:80289a836583 318 #define USBCLKCFG_Val 0x00000000//default
Diletant 44:80289a836583 319 //Peripheral Clock Selection register 0
Diletant 44:80289a836583 320 // 1:0 PCLK_WDT Peripheral clock selection for WDT. 00
Diletant 44:80289a836583 321 // 3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00
Diletant 44:80289a836583 322 // 5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00
Diletant 44:80289a836583 323 // 7:6 PCLK_UART0 Peripheral clock selection for UART0. 00
Diletant 44:80289a836583 324 // 9:8 PCLK_UART1 Peripheral clock selection for UART1. 00
Diletant 44:80289a836583 325 // 11:10 - Reserved. NA
Diletant 44:80289a836583 326 // 13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00
Diletant 44:80289a836583 327 // 15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00
Diletant 44:80289a836583 328 // 17:16 PCLK_SPI Peripheral clock selection for SPI. 00
Diletant 44:80289a836583 329 // 19:18 - Reserved. NA
Diletant 44:80289a836583 330 // 21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00
Diletant 44:80289a836583 331 // 23:22 PCLK_DAC Peripheral clock selection for DAC. 00
Diletant 44:80289a836583 332 // 25:24 PCLK_ADC Peripheral clock selection for ADC. 00
Diletant 44:80289a836583 333 // 27:26 PCLK_CAN1 Peripheral clock selection for CAN1.[1] 00
Diletant 44:80289a836583 334 // 29:28 PCLK_CAN2 Peripheral clock selection for CAN2.[1] 00
Diletant 44:80289a836583 335 // 31:30 PCLK_ACF Peripheral clock selection for CAN acceptance filtering
Diletant 44:80289a836583 336 // bits values:
Diletant 44:80289a836583 337 // 00 PCLK_peripheral = CCLK/4
Diletant 44:80289a836583 338 // 01 PCLK_peripheral = CCLK
Diletant 44:80289a836583 339 // 10 PCLK_peripheral = CCLK/2
Diletant 44:80289a836583 340 // 11 PCLK_peripheral = CCLK/8, except for CAN1, CAN2, and CAN filtering when “11” selects = CCLK/6.
Diletant 44:80289a836583 341 #define PCLKSEL0_Val 0x00000010//Peripheral clock selection for TIMER1 - CCLK
Diletant 44:80289a836583 342 //Peripheral Clock Selection register 1
Diletant 44:80289a836583 343 // 1:0 PCLK_QEI Peripheral clock selection for the Quadrature Encoder Interface.00
Diletant 44:80289a836583 344 // 3:2 PCLK_GPIOINT Peripheral clock selection for GPIO interrupts. 00
Diletant 44:80289a836583 345 // 5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00
Diletant 44:80289a836583 346 // 7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00
Diletant 44:80289a836583 347 // 9:8 - Reserved. NA
Diletant 44:80289a836583 348 // 11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00
Diletant 44:80289a836583 349 // 13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00
Diletant 44:80289a836583 350 // 15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00
Diletant 44:80289a836583 351 // 17:16 PCLK_UART2 Peripheral clock selection for UART2. 00
Diletant 44:80289a836583 352 // 19:18 PCLK_UART3 Peripheral clock selection for UART3. 00
Diletant 44:80289a836583 353 // 21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00
Diletant 44:80289a836583 354 // 23:22 PCLK_I2S Peripheral clock selection for I2S. 00
Diletant 44:80289a836583 355 // 25:24 - Reserved. NA
Diletant 44:80289a836583 356 // 27:26 PCLK_RIT Peripheral clock selection for Repetitive Interrupt Timer. 00
Diletant 44:80289a836583 357 // 29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00
Diletant 44:80289a836583 358 // 31:30 PCLK_MC Peripheral clock selection for the Motor Control PWM
igor_v 2:2d0b80ed9216 359 #define PCLKSEL1_Val 0x00000000
igor_v 2:2d0b80ed9216 360 #define PCONP_Val 0x046887DE
igor_v 2:2d0b80ed9216 361 #define CLKOUTCFG_Val 0x00000000
igor_v 2:2d0b80ed9216 362
igor_v 2:2d0b80ed9216 363
igor_v 2:2d0b80ed9216 364 /*--------------------- Flash Accelerator Configuration ----------------------
igor_v 2:2d0b80ed9216 365 //
igor_v 2:2d0b80ed9216 366 // <e> Flash Accelerator Configuration
igor_v 2:2d0b80ed9216 367 // <o1.0..1> FETCHCFG: Fetch Configuration
igor_v 2:2d0b80ed9216 368 // <0=> Instruction fetches from flash are not buffered
igor_v 2:2d0b80ed9216 369 // <1=> One buffer is used for all instruction fetch buffering
igor_v 2:2d0b80ed9216 370 // <2=> All buffers may be used for instruction fetch buffering
igor_v 2:2d0b80ed9216 371 // <3=> Reserved (do not use this setting)
igor_v 2:2d0b80ed9216 372 // <o1.2..3> DATACFG: Data Configuration
igor_v 2:2d0b80ed9216 373 // <0=> Data accesses from flash are not buffered
igor_v 2:2d0b80ed9216 374 // <1=> One buffer is used for all data access buffering
igor_v 2:2d0b80ed9216 375 // <2=> All buffers may be used for data access buffering
igor_v 2:2d0b80ed9216 376 // <3=> Reserved (do not use this setting)
igor_v 2:2d0b80ed9216 377 // <o1.4> ACCEL: Acceleration Enable
igor_v 2:2d0b80ed9216 378 // <o1.5> PREFEN: Prefetch Enable
igor_v 2:2d0b80ed9216 379 // <o1.6> PREFOVR: Prefetch Override
igor_v 2:2d0b80ed9216 380 // <o1.12..15> FLASHTIM: Flash Access Time
igor_v 2:2d0b80ed9216 381 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
igor_v 2:2d0b80ed9216 382 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
igor_v 2:2d0b80ed9216 383 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
igor_v 2:2d0b80ed9216 384 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
igor_v 2:2d0b80ed9216 385 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
igor_v 2:2d0b80ed9216 386 // <5=> 6 CPU clocks (for any CPU clock)
igor_v 2:2d0b80ed9216 387 // </e>
igor_v 2:2d0b80ed9216 388 */
igor_v 2:2d0b80ed9216 389 #define FLASH_SETUP 1
igor_v 2:2d0b80ed9216 390 #define FLASHCFG_Val 0x0000303A
igor_v 2:2d0b80ed9216 391
igor_v 2:2d0b80ed9216 392 /*
igor_v 2:2d0b80ed9216 393 //-------- <<< end of configuration section >>> ------------------------------
igor_v 2:2d0b80ed9216 394 */
igor_v 2:2d0b80ed9216 395
igor_v 2:2d0b80ed9216 396 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 397 Check the register settings
igor_v 2:2d0b80ed9216 398 *----------------------------------------------------------------------------*/
igor_v 2:2d0b80ed9216 399 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
igor_v 2:2d0b80ed9216 400 #define CHECK_RSVD(val, mask) (val & mask)
igor_v 2:2d0b80ed9216 401
igor_v 2:2d0b80ed9216 402 /* Clock Configuration -------------------------------------------------------*/
igor_v 2:2d0b80ed9216 403 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
igor_v 2:2d0b80ed9216 404 #error "SCS: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 405 #endif
igor_v 2:2d0b80ed9216 406
igor_v 2:2d0b80ed9216 407 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
igor_v 2:2d0b80ed9216 408 #error "CLKSRCSEL: Value out of range!"
igor_v 2:2d0b80ed9216 409 #endif
igor_v 2:2d0b80ed9216 410
igor_v 2:2d0b80ed9216 411 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
igor_v 2:2d0b80ed9216 412 #error "PLL0CFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 413 #endif
igor_v 2:2d0b80ed9216 414
igor_v 2:2d0b80ed9216 415 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
igor_v 2:2d0b80ed9216 416 #error "PLL1CFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 417 #endif
igor_v 2:2d0b80ed9216 418
igor_v 2:2d0b80ed9216 419 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
igor_v 2:2d0b80ed9216 420 #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
igor_v 2:2d0b80ed9216 421 #endif
igor_v 2:2d0b80ed9216 422
igor_v 2:2d0b80ed9216 423 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
igor_v 2:2d0b80ed9216 424 #error "USBCLKCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 425 #endif
igor_v 2:2d0b80ed9216 426
igor_v 2:2d0b80ed9216 427 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
igor_v 2:2d0b80ed9216 428 #error "PCLKSEL0: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 429 #endif
igor_v 2:2d0b80ed9216 430
igor_v 2:2d0b80ed9216 431 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
igor_v 2:2d0b80ed9216 432 #error "PCLKSEL1: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 433 #endif
igor_v 2:2d0b80ed9216 434
igor_v 2:2d0b80ed9216 435 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
igor_v 2:2d0b80ed9216 436 #error "PCONP: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 437 #endif
igor_v 2:2d0b80ed9216 438
igor_v 2:2d0b80ed9216 439 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
igor_v 2:2d0b80ed9216 440 #error "CLKOUTCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 441 #endif
igor_v 2:2d0b80ed9216 442
igor_v 2:2d0b80ed9216 443 /* Flash Accelerator Configuration -------------------------------------------*/
igor_v 2:2d0b80ed9216 444 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
igor_v 2:2d0b80ed9216 445 #error "FLASHCFG: Invalid values of reserved bits!"
igor_v 2:2d0b80ed9216 446 #endif
igor_v 2:2d0b80ed9216 447
igor_v 2:2d0b80ed9216 448
igor_v 2:2d0b80ed9216 449 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 450 DEFINES
igor_v 2:2d0b80ed9216 451 *----------------------------------------------------------------------------*/
igor_v 2:2d0b80ed9216 452
igor_v 2:2d0b80ed9216 453 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 454 Define clocks
igor_v 2:2d0b80ed9216 455 *----------------------------------------------------------------------------*/
igor_v 2:2d0b80ed9216 456 #define XTAL (12000000UL) /* Oscillator frequency */
igor_v 2:2d0b80ed9216 457 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
igor_v 2:2d0b80ed9216 458 #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
igor_v 2:2d0b80ed9216 459 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
igor_v 2:2d0b80ed9216 460
igor_v 2:2d0b80ed9216 461
igor_v 2:2d0b80ed9216 462 /* F_cco0 = (2 * M * F_in) / N */
igor_v 2:2d0b80ed9216 463 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
igor_v 2:2d0b80ed9216 464 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
igor_v 2:2d0b80ed9216 465 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
igor_v 2:2d0b80ed9216 466 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
igor_v 2:2d0b80ed9216 467
igor_v 2:2d0b80ed9216 468 /* Determine core clock frequency according to settings */
igor_v 2:2d0b80ed9216 469 #if (PLL0_SETUP)
igor_v 2:2d0b80ed9216 470 #if ((CLKSRCSEL_Val & 0x03) == 1)
igor_v 2:2d0b80ed9216 471 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
igor_v 2:2d0b80ed9216 472 #elif ((CLKSRCSEL_Val & 0x03) == 2)
igor_v 2:2d0b80ed9216 473 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
igor_v 2:2d0b80ed9216 474 #else
igor_v 2:2d0b80ed9216 475 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
igor_v 2:2d0b80ed9216 476 #endif
igor_v 2:2d0b80ed9216 477 #else
igor_v 2:2d0b80ed9216 478 #if ((CLKSRCSEL_Val & 0x03) == 1)
igor_v 2:2d0b80ed9216 479 #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
igor_v 2:2d0b80ed9216 480 #elif ((CLKSRCSEL_Val & 0x03) == 2)
igor_v 2:2d0b80ed9216 481 #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
igor_v 2:2d0b80ed9216 482 #else
igor_v 2:2d0b80ed9216 483 #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
igor_v 2:2d0b80ed9216 484 #endif
igor_v 2:2d0b80ed9216 485 #endif
igor_v 2:2d0b80ed9216 486
igor_v 2:2d0b80ed9216 487
igor_v 2:2d0b80ed9216 488 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 489 Clock Variable definitions
igor_v 2:2d0b80ed9216 490 *----------------------------------------------------------------------------*/
igor_v 12:74bd0ecf7f83 491 uint32_t SystemCoreClock1 = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
igor_v 2:2d0b80ed9216 492
igor_v 2:2d0b80ed9216 493
igor_v 2:2d0b80ed9216 494 /*----------------------------------------------------------------------------
igor_v 2:2d0b80ed9216 495 Clock functions
igor_v 2:2d0b80ed9216 496 *----------------------------------------------------------------------------*/
igor_v 12:74bd0ecf7f83 497 void SystemCoreClockUpdate1 (void) /* Get Core Clock Frequency */
igor_v 2:2d0b80ed9216 498 {
igor_v 2:2d0b80ed9216 499 /* Determine clock frequency according to clock register values */
igor_v 2:2d0b80ed9216 500 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
igor_v 2:2d0b80ed9216 501 switch (LPC_SC->CLKSRCSEL & 0x03) {
igor_v 2:2d0b80ed9216 502 case 0: /* Int. RC oscillator => PLL0 */
igor_v 2:2d0b80ed9216 503 case 3: /* Reserved, default to Int. RC */
igor_v 12:74bd0ecf7f83 504 SystemCoreClock1 = (IRC_OSC *
igor_v 2:2d0b80ed9216 505 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
igor_v 2:2d0b80ed9216 506 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
igor_v 2:2d0b80ed9216 507 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
igor_v 2:2d0b80ed9216 508 break;
igor_v 2:2d0b80ed9216 509 case 1: /* Main oscillator => PLL0 */
igor_v 12:74bd0ecf7f83 510 SystemCoreClock1 = (OSC_CLK * //it is our case osc_clk = 12 MHz
igor_v 2:2d0b80ed9216 511 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / //PLL0 multiplier value
igor_v 2:2d0b80ed9216 512 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / //PLL0 pre-divider
igor_v 2:2d0b80ed9216 513 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); //divider for CCLK (SystemCoreClock)
igor_v 2:2d0b80ed9216 514 break;
igor_v 2:2d0b80ed9216 515 case 2: /* RTC oscillator => PLL0 */
igor_v 12:74bd0ecf7f83 516 SystemCoreClock1 = (RTC_CLK *
igor_v 2:2d0b80ed9216 517 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
igor_v 2:2d0b80ed9216 518 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
igor_v 2:2d0b80ed9216 519 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
igor_v 2:2d0b80ed9216 520 break;
igor_v 2:2d0b80ed9216 521 }
igor_v 2:2d0b80ed9216 522 } else {
igor_v 2:2d0b80ed9216 523 switch (LPC_SC->CLKSRCSEL & 0x03) {
igor_v 2:2d0b80ed9216 524 case 0: /* Int. RC oscillator => PLL0 */
igor_v 2:2d0b80ed9216 525 case 3: /* Reserved, default to Int. RC */
igor_v 12:74bd0ecf7f83 526 SystemCoreClock1 = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
igor_v 2:2d0b80ed9216 527 break;
igor_v 2:2d0b80ed9216 528 case 1: /* Main oscillator => PLL0 */
igor_v 12:74bd0ecf7f83 529 SystemCoreClock1 = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
igor_v 2:2d0b80ed9216 530 break;
igor_v 2:2d0b80ed9216 531 case 2: /* RTC oscillator => PLL0 */
igor_v 12:74bd0ecf7f83 532 SystemCoreClock1 = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
igor_v 2:2d0b80ed9216 533 break;
igor_v 2:2d0b80ed9216 534 }
igor_v 2:2d0b80ed9216 535 }
igor_v 2:2d0b80ed9216 536
igor_v 2:2d0b80ed9216 537 }
igor_v 2:2d0b80ed9216 538
igor_v 2:2d0b80ed9216 539 /**
igor_v 2:2d0b80ed9216 540 * Initialize the system
igor_v 2:2d0b80ed9216 541 *
igor_v 2:2d0b80ed9216 542 * @param none
igor_v 2:2d0b80ed9216 543 * @return none
igor_v 2:2d0b80ed9216 544 *
igor_v 2:2d0b80ed9216 545 * @brief Setup the microcontroller system.
igor_v 2:2d0b80ed9216 546 * Initialize the System.
igor_v 2:2d0b80ed9216 547 */
igor_v 12:74bd0ecf7f83 548 void SystemInit1 (void)
igor_v 2:2d0b80ed9216 549 {
igor_v 2:2d0b80ed9216 550 #if (CLOCK_SETUP) /* Clock Setup */
Diletant 44:80289a836583 551 //Init system control and status register
Diletant 44:80289a836583 552 LPC_SC->SCS = SCS_Val;//0x20 - enable main oscillator,1...20MHz (12MHz)
igor_v 2:2d0b80ed9216 553 if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
igor_v 2:2d0b80ed9216 554 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
igor_v 2:2d0b80ed9216 555 }
igor_v 2:2d0b80ed9216 556
Diletant 44:80289a836583 557 //Init CPU Clock Configure Register - select the divide value for creating the CPU clock (CCLK) from the PLL0 output
Diletant 44:80289a836583 558 LPC_SC->CCLKCFG = CCLKCFG_Val; //3 - divide to 4 (3MHz)
igor_v 2:2d0b80ed9216 559
igor_v 2:2d0b80ed9216 560 #if (PLL0_SETUP)
Diletant 44:80289a836583 561 //Init Clock Source Select register
Diletant 44:80289a836583 562 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;//1 - Select the main oscillator as the PLL0 clock source
Diletant 44:80289a836583 563 //Init PLL0 Configuration register
Diletant 44:80289a836583 564 LPC_SC->PLL0CFG = PLL0CFG_Val;//0x00050063: M - 100, N - 6, PLL0output = 2 * 100 * 12MHz / 6 = 400MHz, CPU clock 100MHz
Diletant 44:80289a836583 565 //Init PLL0 Feed Register. This register enables loading of the PLL0 control and configuration information from the PLL0CON and PLL0CFG
Diletant 44:80289a836583 566 //registers into the shadow registers that actually affect PLL0 operation.
Diletant 44:80289a836583 567 //Write 0xAA and 0x55 sequentially to update shadow registers and settings to take effect
igor_v 2:2d0b80ed9216 568 LPC_SC->PLL0FEED = 0xAA;
igor_v 2:2d0b80ed9216 569 LPC_SC->PLL0FEED = 0x55;
Diletant 44:80289a836583 570 //Init PLL0 Control register
Diletant 44:80289a836583 571 // bit 0 - PLL0 Enable
Diletant 44:80289a836583 572 // bit 1 - PLL0 connect
Diletant 44:80289a836583 573 LPC_SC->PLL0CON = 0x01;//PLL0 Enable
Diletant 44:80289a836583 574 //Update shadow registers to settings take effect
igor_v 2:2d0b80ed9216 575 LPC_SC->PLL0FEED = 0xAA;
igor_v 2:2d0b80ed9216 576 LPC_SC->PLL0FEED = 0x55;
Diletant 44:80289a836583 577 //PLL0 Status register
Diletant 44:80289a836583 578 // bits 0...14 - Read-back for the PLL0 Multiplier value
Diletant 44:80289a836583 579 // bits 16...23 - Read-back for the PLL0 Pre-Divider value
Diletant 44:80289a836583 580 // bit 24 - Read-back for the PLL0 Enable bit
Diletant 44:80289a836583 581 // bit 25 - Read-back for the PLL0 Connect bit
Diletant 44:80289a836583 582 // bit 26 - Reflects the PLL0 Lock status: 1 - locked
Diletant 44:80289a836583 583 while (!(LPC_SC->PLL0STAT & (1<<26)));//Wait while PLL0 locked (PLOCK0)
igor_v 2:2d0b80ed9216 584
Diletant 44:80289a836583 585 LPC_SC->PLL0CON = 0x03;//PLL0 Enable & Connect
igor_v 2:2d0b80ed9216 586 LPC_SC->PLL0FEED = 0xAA;
igor_v 2:2d0b80ed9216 587 LPC_SC->PLL0FEED = 0x55;
Diletant 44:80289a836583 588 while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait while PLL0 connected (PLLC0_STAT & PLLE0_STAT)
igor_v 2:2d0b80ed9216 589 #endif
igor_v 2:2d0b80ed9216 590
igor_v 2:2d0b80ed9216 591 #if (PLL1_SETUP)
Diletant 44:80289a836583 592 LPC_SC->PLL1CFG = PLL1CFG_Val;//0x23 M - 36, N - 1, output = 2 * 36 * 12MHz / 1 = 864MHz?
igor_v 2:2d0b80ed9216 593 LPC_SC->PLL1FEED = 0xAA;
igor_v 2:2d0b80ed9216 594 LPC_SC->PLL1FEED = 0x55;
igor_v 2:2d0b80ed9216 595
igor_v 2:2d0b80ed9216 596 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
igor_v 2:2d0b80ed9216 597 LPC_SC->PLL1FEED = 0xAA;
igor_v 2:2d0b80ed9216 598 LPC_SC->PLL1FEED = 0x55;
igor_v 2:2d0b80ed9216 599 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
igor_v 2:2d0b80ed9216 600
igor_v 2:2d0b80ed9216 601 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
igor_v 2:2d0b80ed9216 602 LPC_SC->PLL1FEED = 0xAA;
igor_v 2:2d0b80ed9216 603 LPC_SC->PLL1FEED = 0x55;
igor_v 2:2d0b80ed9216 604 while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
igor_v 2:2d0b80ed9216 605 #else
igor_v 2:2d0b80ed9216 606 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
igor_v 2:2d0b80ed9216 607 #endif
igor_v 2:2d0b80ed9216 608
igor_v 2:2d0b80ed9216 609 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
igor_v 2:2d0b80ed9216 610 LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
igor_v 2:2d0b80ed9216 611
igor_v 2:2d0b80ed9216 612 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
igor_v 2:2d0b80ed9216 613
igor_v 2:2d0b80ed9216 614 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
igor_v 2:2d0b80ed9216 615 #endif
igor_v 2:2d0b80ed9216 616
igor_v 2:2d0b80ed9216 617 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
igor_v 2:2d0b80ed9216 618 LPC_SC->FLASHCFG = FLASHCFG_Val;
igor_v 2:2d0b80ed9216 619 #endif
igor_v 2:2d0b80ed9216 620 }
igor_v 2:2d0b80ed9216 621