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el_lin.h
00001 /**--------------File Info--------------------------------------------------------------------------------- 00002 ** File name: el_lin.h 00003 ** Last modified Date: 2011-08-22 00004 ** Last Version: V1.00 00005 ** Descriptions: 00006 ** 00007 **-------------------------------------------------------------------------------------------------------- 00008 ** Created by: Electrooptika incor. 00009 ** Created date: 2011-08-22 00010 ** Version: V1.00 00011 ** 00012 **-------------------------------------------------------------------------------------------------------- 00013 *********************************************************************************************************/ 00014 #ifndef __DMA_H 00015 #define __DMA_H 00016 00017 00018 00019 #define STRT_ERR 0x0080 //e. error of the start bit //r. ошибка старт-бита 00020 #define STOP_ERR 0x0040 //e. error of the stop bit //r. ошибка стоп-бита 00021 #define SIZE_ERR 0x0004 //e. size of the received data packet mismatches the agreement //r. размер принятого пакета не соответствует соглашению 00022 #define LCC_ERR 0x0002 //e. checksum has not coincided //r. не совпала контрольная сумма 00023 #define NO_CMD_ERR 0x0100 //e. in the received packet there is no attribute of command //r. в принятом пакете нет признака команды 00024 #define CODE_ERR 0x0200 //e. unknown code of a command //r. неизвестный код команды 00025 #define MODE_ERR 0x0400 //e. code of a command mismatches a current mode //r. код команды не соответствует текущему режиму 00026 #define PARAM_ERR 0x0800 //e. parameters of a command was set incorrectly //r. неверно заданные параметры команды 00027 #define MAXSIZE_ERR 0x1000 //e. receiver buffer overflow //r. переполнение буфера приемника 00028 #define ADDR_ERR 0x2000 //e. incorrect address of the device //r. неверный адрес устройства 00029 #define READ_ERR 0x4000 //e. stop of link because of untimely data read //r. останов связи несвоевременным чтением данных 00030 #define WASQ_ERR 0x8000 //e. error of waiting of authentic answer //r. ошибка ожидания достоверного ответа 00031 00032 #define Trm_En_Rd 0x0080 //e. a mask of permission/readiness of transmitter of the 2 line //r. маска разрешения/готовности передатчика линии 2 00033 #define Rcv_Rdy 0x0040 //e. a mask of the readiness bit of the receiver //r. маска бита готовности приемника 00034 #define Rcv_Ferr 0x0020 //e. a mask of the "format error" bit //r. маска бита "ошибка формата" 00035 #define Rcv_Tout 0x0010 //e. a mask of the "time-out" bit //r. маска бита "тайм-аут" 00036 #define Rcv_Rful 0x0008 //e. a mask of the "stack is full" bit //r. маска бита "стек полон" 00037 00038 00039 #define FIFOs_En 0x00000001 00040 #define RX_FIFO_Reset 0x00000002 00041 #define TX_FIFO_Reset 0x00000004 00042 #define DMA_Mode_UART 0x00000008 00043 #define RX_TrigLvl_1 0x00000000 00044 #define RX_TrigLvl_4 0x00000040 00045 #define RX_TrigLvl_8 0x00000080 00046 #define RX_TrigLvl_14 0x000000C0 00047 00048 #define word_length_8 0x00000003 00049 00050 #define one_stop_bit 0x00000000 00051 00052 #define no_parity 0x00000000 00053 00054 #define back_trans_dis 0x00000000 00055 00056 #define DLAB_access 0x00000080 00057 00058 #define TRANS_SHIFT_BUF_EMPTY 0x00000040 00059 #define DMA_BUSY 0x00020000 00060 #define RecievBufEmpty 0x00000001 00061 #define DIS_ALL_INT 0x00000000 00062 #define RBR_IntEnabl 0x00000001 00063 /* Second half of the second RAM is used for GPDMA operation. */ 00064 00065 #define DMA_UART0_TX 8 00066 #define DMA_UART0_RX 9 00067 #define DMA_UART1_TX 10 00068 #define DMA_UART1_RX 11 00069 #define DMA_UART2_TX 12 00070 #define DMA_UART2_RX 13 00071 #define DMA_UART3_TX 14 00072 #define DMA_UART3_RX 15 00073 00074 #define DMA_MEMORY 0 00075 #define SrcDMA_UART0_RX DMA_UART0_RX << 1 00076 #define SrcDMA_UART0_TX DMA_UART0_TX << 1 00077 #define SrcDMA_UART1_TX DMA_UART1_TX << 1 00078 #define DstDMA_UART0_TX DMA_UART0_TX << 6 00079 #define DstDMA_UART1_TX DMA_UART1_TX << 6 00080 #define DstDMA_UART0_RX DMA_UART0_RX << 6 00081 #define SrcDMA_UART1_RX DMA_UART1_RX << 1 00082 #define DstDMA_UART1_RX DMA_UART1_RX << 6 00083 00084 /* UART0 TX and RX */ 00085 #define UART0_DMA_TX_SRC 0x2007C800 /* starting addr of DATA register in UART0 */ 00086 #define UART0_DMA_TX_DST LPC_UART0_BASE 00087 #define UART0_DMA_RX_SRC LPC_UART0_BASE 00088 #define UART0_DMA_RX_DST 0x2007C900 00089 00090 #define UART2_DMA_TX_DST LPC_UART2_BASE 00091 #define UART1_DMA_TX_DST LPC_UART1_BASE 00092 00093 #define GPDMA_POWER_ON 0x20000000 00094 00095 #define UART_REQ 0x00000000 00096 00097 //To clear particular DMA TC-interrupts 00098 #define DMA0_IntTCClear 0x00000001 00099 #define DMA1_IntTCClear 0x00000002 00100 #define DMA2_IntTCClear 0x00000004 00101 #define DMA3_IntTCClear 0x00000008 00102 #define DMA4_IntTCClear 0x00000010 00103 #define DMA5_IntTCClear 0x00000020 00104 #define DMA6_IntTCClear 0x00000040 00105 #define DMA7_IntTCClear 0x00000080 00106 00107 //To clear particular DMA Error-interrupts 00108 #define DMA0_IntErrClear 0x00000001 00109 #define DMA1_IntErrClear 0x00000002 00110 #define DMA2_IntErrClear 0x00000004 00111 #define DMA3_IntErrClear 0x00000008 00112 #define DMA4_IntErrClear 0x00000010 00113 #define DMA5_IntErrClear 0x00000020 00114 #define DMA6_IntErrClear 0x00000040 00115 #define DMA7_IntErrClear 0x00000080 00116 #define DMACH1_IntTCPend 0x00000002 00117 00118 #define DMA_ControllerEn 0x00000001 00119 00120 #define DMA_AHB_Little 0x00000000 00121 #define DMA_AHB_Big 0x00000002 00122 00123 #define SrcBSize_1 0x00000000 00124 #define SrcBSize_4 0x00001000 00125 #define SrcBSize_8 0x00002000 00126 #define SrcBSize_16 0x00003000 00127 #define SrcBSize_32 0x00004000 00128 #define SrcBSize_64 0x00005000 00129 #define SrcBSize_128 0x00006000 00130 #define SrcBSize_256 0x00007000 00131 00132 #define DstBSize_1 0x00000000 00133 #define DstBSize_4 0x00008000 00134 #define DstBSize_8 0x00010000 00135 #define DstBSize_16 0x00018000 00136 #define DstBSize_32 0x00020000 00137 #define DstBSize_64 0x00028000 00138 #define DstBSize_128 0x00030000 00139 #define DstBSize_256 0x00038000 00140 00141 #define SrcWidth_8b 0x00000000 00142 #define SrcWidth_16b 0x00020000 00143 #define SrcWidth_32b 0x00040000 00144 00145 #define DstWidth_8b 0x00000000 00146 #define DstWidth_16b 0x00200000 00147 #define DstWidth_32b 0x00400000 00148 00149 #define SrcInc 0x04000000 00150 #define SrcFixed 0x00000000 00151 00152 #define DstInc 0x08000000 00153 #define DstFixed 0x00000000 00154 00155 #define TCIntEnabl 0x80000000 00156 #define TCIntDisabl 0x00000000 00157 00158 #define DMAChannelEn 0x00000001 00159 #define DMAChannelDis 0x00000000 00160 00161 #define CH2_ENABLED 0x00000004 00162 00163 #define DONtMaskTCInt 0x00008000 00164 #define MaskTCInt 0x00000000 00165 #define DONtMaskErrInt 0x00004000 00166 #define MaskErrInt 0x00000000 00167 00168 #define INT_DMA_Disabl 0x04000000 00169 /* DMA mode */ 00170 #define M2M 0x00 00171 #define M2P 0x01 00172 #define P2M 0x02 00173 #define P2P 0x03 00174 00175 #define Sp38400 0x00000 00176 #define Sp115200 0x00010 00177 #define Sp460800 0x00020 00178 #define Sp921600 0x00030 00179 00180 extern unsigned int trm_num_byt; 00181 extern unsigned int rcv_num_byt; 00182 extern unsigned int rcv_Rdy; 00183 extern char trm_buf[64]; 00184 extern char rcv_buf[64]; 00185 extern char rcv_copy[64]; 00186 extern unsigned int trm_cycl; 00187 extern unsigned int num_of_par; 00188 extern void* addr_param[16]; 00189 extern unsigned int size_param[16]; 00190 extern unsigned int trm_rate; 00191 extern unsigned int trm_cycl; 00192 extern unsigned int rcv_num_byt_old; 00193 extern int rcv_byt_copy; 00194 extern unsigned int trm_ena; 00195 extern int cycl_phase; 00196 extern unsigned int line_err; 00197 extern unsigned int line_sts; 00198 extern int rx_buf_copy; 00199 extern char zeros; 00200 extern unsigned int SystemCoreClock; 00201 00202 extern void DMA_Init(void); 00203 extern void transm_DAT(void); 00204 extern void Line_1_Rcv(void); 00205 00206 extern void UARTInit(void); 00207 extern void UART1_Init(void); 00208 //extern int UART0_SendByte(int); 00209 extern int UART1_SendByte(int); 00210 extern void UART_SwitchSpeed(unsigned); 00211 extern void UART_DMA_Init(void); 00212 extern void SystemCoreClockUpdate (void); 00213 00214 #endif /* end __DMA_H */ 00215
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