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core_cm3.c
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00001 /**************************************************************************//** 00002 * @file core_cm3.c 00003 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File 00004 * @version V1.30 00005 * @date 30. October 2009 00006 * 00007 * @note 00008 * Copyright (C) 2009 ARM Limited. All rights reserved. 00009 * 00010 * @par 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * @par 00016 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00017 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00018 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00019 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00020 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00021 * 00022 ******************************************************************************/ 00023 00024 #include <stdint.h> 00025 00026 /* define compiler specific symbols */ 00027 #if defined ( __CC_ARM ) 00028 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00029 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00030 00031 #elif defined ( __ICCARM__ ) 00032 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00033 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 00034 00035 #elif defined ( __GNUC__ ) 00036 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00037 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00038 00039 #elif defined ( __TASKING__ ) 00040 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00041 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00042 00043 #endif 00044 00045 00046 /* ################### Compiler specific Intrinsics ########################### */ 00047 00048 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 00049 /* ARM armcc specific functions */ 00050 00051 /** 00052 * @brief Return the Process Stack Pointer 00053 * 00054 * @return ProcessStackPointer 00055 * 00056 * Return the actual process stack pointer 00057 */ 00058 __ASM uint32_t __get_PSP(void) 00059 { 00060 mrs r0, psp 00061 bx lr 00062 } 00063 00064 /** 00065 * @brief Set the Process Stack Pointer 00066 * 00067 * @param topOfProcStack Process Stack Pointer 00068 * 00069 * Assign the value ProcessStackPointer to the MSP 00070 * (process stack pointer) Cortex processor register 00071 */ 00072 __ASM void __set_PSP(uint32_t topOfProcStack) 00073 { 00074 msr psp, r0 00075 bx lr 00076 } 00077 00078 /** 00079 * @brief Return the Main Stack Pointer 00080 * 00081 * @return Main Stack Pointer 00082 * 00083 * Return the current value of the MSP (main stack pointer) 00084 * Cortex processor register 00085 */ 00086 __ASM uint32_t __get_MSP(void) 00087 { 00088 mrs r0, msp 00089 bx lr 00090 } 00091 00092 /** 00093 * @brief Set the Main Stack Pointer 00094 * 00095 * @param topOfMainStack Main Stack Pointer 00096 * 00097 * Assign the value mainStackPointer to the MSP 00098 * (main stack pointer) Cortex processor register 00099 */ 00100 __ASM void __set_MSP(uint32_t mainStackPointer) 00101 { 00102 msr msp, r0 00103 bx lr 00104 } 00105 00106 /** 00107 * @brief Reverse byte order in unsigned short value 00108 * 00109 * @param value value to reverse 00110 * @return reversed value 00111 * 00112 * Reverse byte order in unsigned short value 00113 */ 00114 __ASM uint32_t __REV16(uint16_t value) 00115 { 00116 rev16 r0, r0 00117 bx lr 00118 } 00119 00120 /** 00121 * @brief Reverse byte order in signed short value with sign extension to integer 00122 * 00123 * @param value value to reverse 00124 * @return reversed value 00125 * 00126 * Reverse byte order in signed short value with sign extension to integer 00127 */ 00128 __ASM int32_t __REVSH(int16_t value) 00129 { 00130 revsh r0, r0 00131 bx lr 00132 } 00133 00134 00135 #if (__ARMCC_VERSION < 400000) 00136 00137 /** 00138 * @brief Remove the exclusive lock created by ldrex 00139 * 00140 * Removes the exclusive lock which is created by ldrex. 00141 */ 00142 __ASM void __CLREX(void) 00143 { 00144 clrex 00145 } 00146 00147 /** 00148 * @brief Return the Base Priority value 00149 * 00150 * @return BasePriority 00151 * 00152 * Return the content of the base priority register 00153 */ 00154 __ASM uint32_t __get_BASEPRI(void) 00155 { 00156 mrs r0, basepri 00157 bx lr 00158 } 00159 00160 /** 00161 * @brief Set the Base Priority value 00162 * 00163 * @param basePri BasePriority 00164 * 00165 * Set the base priority register 00166 */ 00167 __ASM void __set_BASEPRI(uint32_t basePri) 00168 { 00169 msr basepri, r0 00170 bx lr 00171 } 00172 00173 /** 00174 * @brief Return the Priority Mask value 00175 * 00176 * @return PriMask 00177 * 00178 * Return state of the priority mask bit from the priority mask register 00179 */ 00180 __ASM uint32_t __get_PRIMASK(void) 00181 { 00182 mrs r0, primask 00183 bx lr 00184 } 00185 00186 /** 00187 * @brief Set the Priority Mask value 00188 * 00189 * @param priMask PriMask 00190 * 00191 * Set the priority mask bit in the priority mask register 00192 */ 00193 __ASM void __set_PRIMASK(uint32_t priMask) 00194 { 00195 msr primask, r0 00196 bx lr 00197 } 00198 00199 /** 00200 * @brief Return the Fault Mask value 00201 * 00202 * @return FaultMask 00203 * 00204 * Return the content of the fault mask register 00205 */ 00206 __ASM uint32_t __get_FAULTMASK(void) 00207 { 00208 mrs r0, faultmask 00209 bx lr 00210 } 00211 00212 /** 00213 * @brief Set the Fault Mask value 00214 * 00215 * @param faultMask faultMask value 00216 * 00217 * Set the fault mask register 00218 */ 00219 __ASM void __set_FAULTMASK(uint32_t faultMask) 00220 { 00221 msr faultmask, r0 00222 bx lr 00223 } 00224 00225 /** 00226 * @brief Return the Control Register value 00227 * 00228 * @return Control value 00229 * 00230 * Return the content of the control register 00231 */ 00232 __ASM uint32_t __get_CONTROL(void) 00233 { 00234 mrs r0, control 00235 bx lr 00236 } 00237 00238 /** 00239 * @brief Set the Control Register value 00240 * 00241 * @param control Control value 00242 * 00243 * Set the control register 00244 */ 00245 __ASM void __set_CONTROL(uint32_t control) 00246 { 00247 msr control, r0 00248 bx lr 00249 } 00250 00251 #endif /* __ARMCC_VERSION */ 00252 00253 00254 00255 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ 00256 /* IAR iccarm specific functions */ 00257 #pragma diag_suppress=Pe940 00258 00259 /** 00260 * @brief Return the Process Stack Pointer 00261 * 00262 * @return ProcessStackPointer 00263 * 00264 * Return the actual process stack pointer 00265 */ 00266 uint32_t __get_PSP(void) 00267 { 00268 __ASM("mrs r0, psp"); 00269 __ASM("bx lr"); 00270 } 00271 00272 /** 00273 * @brief Set the Process Stack Pointer 00274 * 00275 * @param topOfProcStack Process Stack Pointer 00276 * 00277 * Assign the value ProcessStackPointer to the MSP 00278 * (process stack pointer) Cortex processor register 00279 */ 00280 void __set_PSP(uint32_t topOfProcStack) 00281 { 00282 __ASM("msr psp, r0"); 00283 __ASM("bx lr"); 00284 } 00285 00286 /** 00287 * @brief Return the Main Stack Pointer 00288 * 00289 * @return Main Stack Pointer 00290 * 00291 * Return the current value of the MSP (main stack pointer) 00292 * Cortex processor register 00293 */ 00294 uint32_t __get_MSP(void) 00295 { 00296 __ASM("mrs r0, msp"); 00297 __ASM("bx lr"); 00298 } 00299 00300 /** 00301 * @brief Set the Main Stack Pointer 00302 * 00303 * @param topOfMainStack Main Stack Pointer 00304 * 00305 * Assign the value mainStackPointer to the MSP 00306 * (main stack pointer) Cortex processor register 00307 */ 00308 void __set_MSP(uint32_t topOfMainStack) 00309 { 00310 __ASM("msr msp, r0"); 00311 __ASM("bx lr"); 00312 } 00313 00314 /** 00315 * @brief Reverse byte order in unsigned short value 00316 * 00317 * @param value value to reverse 00318 * @return reversed value 00319 * 00320 * Reverse byte order in unsigned short value 00321 */ 00322 uint32_t __REV16(uint16_t value) 00323 { 00324 __ASM("rev16 r0, r0"); 00325 __ASM("bx lr"); 00326 } 00327 00328 /** 00329 * @brief Reverse bit order of value 00330 * 00331 * @param value value to reverse 00332 * @return reversed value 00333 * 00334 * Reverse bit order of value 00335 */ 00336 uint32_t __RBIT(uint32_t value) 00337 { 00338 __ASM("rbit r0, r0"); 00339 __ASM("bx lr"); 00340 } 00341 00342 /** 00343 * @brief LDR Exclusive (8 bit) 00344 * 00345 * @param *addr address pointer 00346 * @return value of (*address) 00347 * 00348 * Exclusive LDR command for 8 bit values) 00349 */ 00350 uint8_t __LDREXB(uint8_t *addr) 00351 { 00352 __ASM("ldrexb r0, [r0]"); 00353 __ASM("bx lr"); 00354 } 00355 00356 /** 00357 * @brief LDR Exclusive (16 bit) 00358 * 00359 * @param *addr address pointer 00360 * @return value of (*address) 00361 * 00362 * Exclusive LDR command for 16 bit values 00363 */ 00364 uint16_t __LDREXH(uint16_t *addr) 00365 { 00366 __ASM("ldrexh r0, [r0]"); 00367 __ASM("bx lr"); 00368 } 00369 00370 /** 00371 * @brief LDR Exclusive (32 bit) 00372 * 00373 * @param *addr address pointer 00374 * @return value of (*address) 00375 * 00376 * Exclusive LDR command for 32 bit values 00377 */ 00378 uint32_t __LDREXW(uint32_t *addr) 00379 { 00380 __ASM("ldrex r0, [r0]"); 00381 __ASM("bx lr"); 00382 } 00383 00384 /** 00385 * @brief STR Exclusive (8 bit) 00386 * 00387 * @param value value to store 00388 * @param *addr address pointer 00389 * @return successful / failed 00390 * 00391 * Exclusive STR command for 8 bit values 00392 */ 00393 uint32_t __STREXB(uint8_t value, uint8_t *addr) 00394 { 00395 __ASM("strexb r0, r0, [r1]"); 00396 __ASM("bx lr"); 00397 } 00398 00399 /** 00400 * @brief STR Exclusive (16 bit) 00401 * 00402 * @param value value to store 00403 * @param *addr address pointer 00404 * @return successful / failed 00405 * 00406 * Exclusive STR command for 16 bit values 00407 */ 00408 uint32_t __STREXH(uint16_t value, uint16_t *addr) 00409 { 00410 __ASM("strexh r0, r0, [r1]"); 00411 __ASM("bx lr"); 00412 } 00413 00414 /** 00415 * @brief STR Exclusive (32 bit) 00416 * 00417 * @param value value to store 00418 * @param *addr address pointer 00419 * @return successful / failed 00420 * 00421 * Exclusive STR command for 32 bit values 00422 */ 00423 uint32_t __STREXW(uint32_t value, uint32_t *addr) 00424 { 00425 __ASM("strex r0, r0, [r1]"); 00426 __ASM("bx lr"); 00427 } 00428 00429 #pragma diag_default=Pe940 00430 00431 00432 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ 00433 /* GNU gcc specific functions */ 00434 00435 /** 00436 * @brief Return the Process Stack Pointer 00437 * 00438 * @return ProcessStackPointer 00439 * 00440 * Return the actual process stack pointer 00441 */ 00442 uint32_t __get_PSP(void) __attribute__( ( naked ) ); 00443 uint32_t __get_PSP(void) 00444 { 00445 uint32_t result=0; 00446 00447 __ASM volatile ("MRS %0, psp\n\t" 00448 "MOV r0, %0 \n\t" 00449 "BX lr \n\t" : "=r" (result) ); 00450 return(result); 00451 } 00452 00453 /** 00454 * @brief Set the Process Stack Pointer 00455 * 00456 * @param topOfProcStack Process Stack Pointer 00457 * 00458 * Assign the value ProcessStackPointer to the MSP 00459 * (process stack pointer) Cortex processor register 00460 */ 00461 void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); 00462 void __set_PSP(uint32_t topOfProcStack) 00463 { 00464 __ASM volatile ("MSR psp, %0\n\t" 00465 "BX lr \n\t" : : "r" (topOfProcStack) ); 00466 } 00467 00468 /** 00469 * @brief Return the Main Stack Pointer 00470 * 00471 * @return Main Stack Pointer 00472 * 00473 * Return the current value of the MSP (main stack pointer) 00474 * Cortex processor register 00475 */ 00476 uint32_t __get_MSP(void) __attribute__( ( naked ) ); 00477 uint32_t __get_MSP(void) 00478 { 00479 uint32_t result=0; 00480 00481 __ASM volatile ("MRS %0, msp\n\t" 00482 "MOV r0, %0 \n\t" 00483 "BX lr \n\t" : "=r" (result) ); 00484 return(result); 00485 } 00486 00487 /** 00488 * @brief Set the Main Stack Pointer 00489 * 00490 * @param topOfMainStack Main Stack Pointer 00491 * 00492 * Assign the value mainStackPointer to the MSP 00493 * (main stack pointer) Cortex processor register 00494 */ 00495 void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); 00496 void __set_MSP(uint32_t topOfMainStack) 00497 { 00498 __ASM volatile ("MSR msp, %0\n\t" 00499 "BX lr \n\t" : : "r" (topOfMainStack) ); 00500 } 00501 00502 /** 00503 * @brief Return the Base Priority value 00504 * 00505 * @return BasePriority 00506 * 00507 * Return the content of the base priority register 00508 */ 00509 uint32_t __get_BASEPRI(void) 00510 { 00511 uint32_t result=0; 00512 00513 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 00514 return(result); 00515 } 00516 00517 /** 00518 * @brief Set the Base Priority value 00519 * 00520 * @param basePri BasePriority 00521 * 00522 * Set the base priority register 00523 */ 00524 void __set_BASEPRI(uint32_t value) 00525 { 00526 __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 00527 } 00528 00529 /** 00530 * @brief Return the Priority Mask value 00531 * 00532 * @return PriMask 00533 * 00534 * Return state of the priority mask bit from the priority mask register 00535 */ 00536 uint32_t __get_PRIMASK(void) 00537 { 00538 uint32_t result=0; 00539 00540 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 00541 return(result); 00542 } 00543 00544 /** 00545 * @brief Set the Priority Mask value 00546 * 00547 * @param priMask PriMask 00548 * 00549 * Set the priority mask bit in the priority mask register 00550 */ 00551 void __set_PRIMASK(uint32_t priMask) 00552 { 00553 __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 00554 } 00555 00556 /** 00557 * @brief Return the Fault Mask value 00558 * 00559 * @return FaultMask 00560 * 00561 * Return the content of the fault mask register 00562 */ 00563 uint32_t __get_FAULTMASK(void) 00564 { 00565 uint32_t result=0; 00566 00567 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 00568 return(result); 00569 } 00570 00571 /** 00572 * @brief Set the Fault Mask value 00573 * 00574 * @param faultMask faultMask value 00575 * 00576 * Set the fault mask register 00577 */ 00578 void __set_FAULTMASK(uint32_t faultMask) 00579 { 00580 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 00581 } 00582 00583 /** 00584 * @brief Return the Control Register value 00585 * 00586 * @return Control value 00587 * 00588 * Return the content of the control register 00589 */ 00590 uint32_t __get_CONTROL(void) 00591 { 00592 uint32_t result=0; 00593 00594 __ASM volatile ("MRS %0, control" : "=r" (result) ); 00595 return(result); 00596 } 00597 00598 /** 00599 * @brief Set the Control Register value 00600 * 00601 * @param control Control value 00602 * 00603 * Set the control register 00604 */ 00605 void __set_CONTROL(uint32_t control) 00606 { 00607 __ASM volatile ("MSR control, %0" : : "r" (control) ); 00608 } 00609 00610 00611 /** 00612 * @brief Reverse byte order in integer value 00613 * 00614 * @param value value to reverse 00615 * @return reversed value 00616 * 00617 * Reverse byte order in integer value 00618 */ 00619 uint32_t __REV(uint32_t value) 00620 { 00621 uint32_t result=0; 00622 00623 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); 00624 return(result); 00625 } 00626 00627 /** 00628 * @brief Reverse byte order in unsigned short value 00629 * 00630 * @param value value to reverse 00631 * @return reversed value 00632 * 00633 * Reverse byte order in unsigned short value 00634 */ 00635 uint32_t __REV16(uint16_t value) 00636 { 00637 uint32_t result=0; 00638 00639 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); 00640 return(result); 00641 } 00642 00643 /** 00644 * @brief Reverse byte order in signed short value with sign extension to integer 00645 * 00646 * @param value value to reverse 00647 * @return reversed value 00648 * 00649 * Reverse byte order in signed short value with sign extension to integer 00650 */ 00651 int32_t __REVSH(int16_t value) 00652 { 00653 uint32_t result=0; 00654 00655 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); 00656 return(result); 00657 } 00658 00659 /** 00660 * @brief Reverse bit order of value 00661 * 00662 * @param value value to reverse 00663 * @return reversed value 00664 * 00665 * Reverse bit order of value 00666 */ 00667 uint32_t __RBIT(uint32_t value) 00668 { 00669 uint32_t result=0; 00670 00671 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 00672 return(result); 00673 } 00674 00675 /** 00676 * @brief LDR Exclusive (8 bit) 00677 * 00678 * @param *addr address pointer 00679 * @return value of (*address) 00680 * 00681 * Exclusive LDR command for 8 bit value 00682 */ 00683 uint8_t __LDREXB(uint8_t *addr) 00684 { 00685 uint8_t result=0; 00686 00687 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); 00688 return(result); 00689 } 00690 00691 /** 00692 * @brief LDR Exclusive (16 bit) 00693 * 00694 * @param *addr address pointer 00695 * @return value of (*address) 00696 * 00697 * Exclusive LDR command for 16 bit values 00698 */ 00699 uint16_t __LDREXH(uint16_t *addr) 00700 { 00701 uint16_t result=0; 00702 00703 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); 00704 return(result); 00705 } 00706 00707 /** 00708 * @brief LDR Exclusive (32 bit) 00709 * 00710 * @param *addr address pointer 00711 * @return value of (*address) 00712 * 00713 * Exclusive LDR command for 32 bit values 00714 */ 00715 uint32_t __LDREXW(uint32_t *addr) 00716 { 00717 uint32_t result=0; 00718 00719 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); 00720 return(result); 00721 } 00722 00723 /** 00724 * @brief STR Exclusive (8 bit) 00725 * 00726 * @param value value to store 00727 * @param *addr address pointer 00728 * @return successful / failed 00729 * 00730 * Exclusive STR command for 8 bit values 00731 */ 00732 uint32_t __STREXB(uint8_t value, uint8_t *addr) 00733 { 00734 uint32_t result=0; 00735 00736 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 00737 return(result); 00738 } 00739 00740 /** 00741 * @brief STR Exclusive (16 bit) 00742 * 00743 * @param value value to store 00744 * @param *addr address pointer 00745 * @return successful / failed 00746 * 00747 * Exclusive STR command for 16 bit values 00748 */ 00749 uint32_t __STREXH(uint16_t value, uint16_t *addr) 00750 { 00751 uint32_t result=0; 00752 00753 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 00754 return(result); 00755 } 00756 00757 /** 00758 * @brief STR Exclusive (32 bit) 00759 * 00760 * @param value value to store 00761 * @param *addr address pointer 00762 * @return successful / failed 00763 * 00764 * Exclusive STR command for 32 bit values 00765 */ 00766 uint32_t __STREXW(uint32_t value, uint32_t *addr) 00767 { 00768 uint32_t result=0; 00769 00770 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 00771 return(result); 00772 } 00773 00774 00775 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ 00776 /* TASKING carm specific functions */ 00777 00778 /* 00779 * The CMSIS functions have been implemented as intrinsics in the compiler. 00780 * Please use "carm -?i" to get an up to date list of all instrinsics, 00781 * Including the CMSIS ones. 00782 */ 00783 00784 #endif 00785
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