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core_sc300.h

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00001 /**************************************************************************//**
00002  * @file     core_sc300.h
00003  * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
00004  * @version  V5.0.2
00005  * @date     13. February 2017
00006  ******************************************************************************/
00007 /*
00008  * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
00009  *
00010  * SPDX-License-Identifier: Apache-2.0
00011  *
00012  * Licensed under the Apache License, Version 2.0 (the License); you may
00013  * not use this file except in compliance with the License.
00014  * You may obtain a copy of the License at
00015  *
00016  * www.apache.org/licenses/LICENSE-2.0
00017  *
00018  * Unless required by applicable law or agreed to in writing, software
00019  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00020  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00021  * See the License for the specific language governing permissions and
00022  * limitations under the License.
00023  */
00024 
00025 #if   defined ( __ICCARM__ )
00026  #pragma system_include         /* treat file as system include file for MISRA check */
00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
00028   #pragma clang system_header   /* treat file as system include file */
00029 #endif
00030 
00031 #ifndef __CORE_SC300_H_GENERIC
00032 #define __CORE_SC300_H_GENERIC
00033 
00034 #include <stdint.h>
00035 
00036 #ifdef __cplusplus
00037  extern "C" {
00038 #endif
00039 
00040 /**
00041   \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00042   CMSIS violates the following MISRA-C:2004 rules:
00043 
00044    \li Required Rule 8.5, object/function definition in header file.<br>
00045      Function definitions in header files are used to allow 'inlining'.
00046 
00047    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00048      Unions are used for effective representation of core registers.
00049 
00050    \li Advisory Rule 19.7, Function-like macro defined.<br>
00051      Function-like macros are used to allow more efficient code.
00052  */
00053 
00054 
00055 /*******************************************************************************
00056  *                 CMSIS definitions
00057  ******************************************************************************/
00058 /**
00059   \ingroup SC3000
00060   @{
00061  */
00062 
00063 /*  CMSIS SC300 definitions */
00064 #define __SC300_CMSIS_VERSION_MAIN  ( 5U)                                    /*!< [31:16] CMSIS HAL main version */
00065 #define __SC300_CMSIS_VERSION_SUB   ( 0U)                                    /*!< [15:0]  CMSIS HAL sub version */
00066 #define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
00067                                       __SC300_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
00068 
00069 #define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
00070 
00071 /** __FPU_USED indicates whether an FPU is used or not.
00072     This core does not support an FPU at all
00073 */
00074 #define __FPU_USED       0U
00075 
00076 #if defined ( __CC_ARM )
00077   #if defined __TARGET_FPU_VFP
00078     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00079   #endif
00080 
00081 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
00082   #if defined __ARM_PCS_VFP
00083     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00084   #endif
00085 
00086 #elif defined ( __GNUC__ )
00087   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00088     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00089   #endif
00090 
00091 #elif defined ( __ICCARM__ )
00092   #if defined __ARMVFP__
00093     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00094   #endif
00095 
00096 #elif defined ( __TI_ARM__ )
00097   #if defined __TI_VFP_SUPPORT__
00098     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00099   #endif
00100 
00101 #elif defined ( __TASKING__ )
00102   #if defined __FPU_VFP__
00103     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00104   #endif
00105 
00106 #elif defined ( __CSMC__ )
00107   #if ( __CSMC__ & 0x400U)
00108     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00109   #endif
00110 
00111 #endif
00112 
00113 #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
00114 
00115 
00116 #ifdef __cplusplus
00117 }
00118 #endif
00119 
00120 #endif /* __CORE_SC300_H_GENERIC */
00121 
00122 #ifndef __CMSIS_GENERIC
00123 
00124 #ifndef __CORE_SC300_H_DEPENDANT
00125 #define __CORE_SC300_H_DEPENDANT
00126 
00127 #ifdef __cplusplus
00128  extern "C" {
00129 #endif
00130 
00131 /* check device defines and use defaults */
00132 #if defined __CHECK_DEVICE_DEFINES
00133   #ifndef __SC300_REV
00134     #define __SC300_REV               0x0000U
00135     #warning "__SC300_REV not defined in device header file; using default!"
00136   #endif
00137 
00138   #ifndef __MPU_PRESENT
00139     #define __MPU_PRESENT             0U
00140     #warning "__MPU_PRESENT not defined in device header file; using default!"
00141   #endif
00142 
00143   #ifndef __NVIC_PRIO_BITS
00144     #define __NVIC_PRIO_BITS          3U
00145     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00146   #endif
00147 
00148   #ifndef __Vendor_SysTickConfig
00149     #define __Vendor_SysTickConfig    0U
00150     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00151   #endif
00152 #endif
00153 
00154 /* IO definitions (access restrictions to peripheral registers) */
00155 /**
00156     \defgroup CMSIS_glob_defs CMSIS Global Defines
00157 
00158     <strong>IO Type Qualifiers</strong> are used
00159     \li to specify the access to peripheral variables.
00160     \li for automatic generation of peripheral register debug information.
00161 */
00162 #ifdef __cplusplus
00163   #define   __I     volatile             /*!< Defines 'read only' permissions */
00164 #else
00165   #define   __I     volatile const       /*!< Defines 'read only' permissions */
00166 #endif
00167 #define     __O     volatile             /*!< Defines 'write only' permissions */
00168 #define     __IO    volatile             /*!< Defines 'read / write' permissions */
00169 
00170 /* following defines should be used for structure members */
00171 #define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
00172 #define     __OM     volatile            /*! Defines 'write only' structure member permissions */
00173 #define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
00174 
00175 /*@} end of group SC300 */
00176 
00177 
00178 
00179 /*******************************************************************************
00180  *                 Register Abstraction
00181   Core Register contain:
00182   - Core Register
00183   - Core NVIC Register
00184   - Core SCB Register
00185   - Core SysTick Register
00186   - Core Debug Register
00187   - Core MPU Register
00188  ******************************************************************************/
00189 /**
00190   \defgroup CMSIS_core_register Defines and Type Definitions
00191   \brief Type definitions and defines for Cortex-M processor based devices.
00192 */
00193 
00194 /**
00195   \ingroup    CMSIS_core_register
00196   \defgroup   CMSIS_CORE  Status and Control Registers
00197   \brief      Core Register type definitions.
00198   @{
00199  */
00200 
00201 /**
00202   \brief  Union type to access the Application Program Status Register (APSR).
00203  */
00204 typedef union
00205 {
00206   struct
00207   {
00208     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
00209     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
00210     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00211     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00212     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00213     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00214   } b;                                   /*!< Structure used for bit  access */
00215   uint32_t w;                            /*!< Type      used for word access */
00216 } APSR_Type;
00217 
00218 /* APSR Register Definitions */
00219 #define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
00220 #define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
00221 
00222 #define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
00223 #define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
00224 
00225 #define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
00226 #define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
00227 
00228 #define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
00229 #define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
00230 
00231 #define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
00232 #define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
00233 
00234 
00235 /**
00236   \brief  Union type to access the Interrupt Program Status Register (IPSR).
00237  */
00238 typedef union
00239 {
00240   struct
00241   {
00242     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00243     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
00244   } b;                                   /*!< Structure used for bit  access */
00245   uint32_t w;                            /*!< Type      used for word access */
00246 } IPSR_Type;
00247 
00248 /* IPSR Register Definitions */
00249 #define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
00250 #define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
00251 
00252 
00253 /**
00254   \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00255  */
00256 typedef union
00257 {
00258   struct
00259   {
00260     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
00261     uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
00262     uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
00263     uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
00264     uint32_t T:1;                        /*!< bit:     24  Thumb bit */
00265     uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
00266     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
00267     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
00268     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
00269     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
00270     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
00271   } b;                                   /*!< Structure used for bit  access */
00272   uint32_t w;                            /*!< Type      used for word access */
00273 } xPSR_Type;
00274 
00275 /* xPSR Register Definitions */
00276 #define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
00277 #define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
00278 
00279 #define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
00280 #define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
00281 
00282 #define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
00283 #define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
00284 
00285 #define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
00286 #define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
00287 
00288 #define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
00289 #define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
00290 
00291 #define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
00292 #define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
00293 
00294 #define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
00295 #define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
00296 
00297 #define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
00298 #define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
00299 
00300 #define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
00301 #define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
00302 
00303 
00304 /**
00305   \brief  Union type to access the Control Registers (CONTROL).
00306  */
00307 typedef union
00308 {
00309   struct
00310   {
00311     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00312     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
00313     uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
00314   } b;                                   /*!< Structure used for bit  access */
00315   uint32_t w;                            /*!< Type      used for word access */
00316 } CONTROL_Type;
00317 
00318 /* CONTROL Register Definitions */
00319 #define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
00320 #define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
00321 
00322 #define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
00323 #define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
00324 
00325 /*@} end of group CMSIS_CORE */
00326 
00327 
00328 /**
00329   \ingroup    CMSIS_core_register
00330   \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00331   \brief      Type definitions for the NVIC Registers
00332   @{
00333  */
00334 
00335 /**
00336   \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00337  */
00338 typedef struct
00339 {
00340   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
00341         uint32_t RESERVED0[24U];
00342   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
00343         uint32_t RSERVED1[24U];
00344   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
00345         uint32_t RESERVED2[24U];
00346   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
00347         uint32_t RESERVED3[24U];
00348   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
00349         uint32_t RESERVED4[56U];
00350   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00351         uint32_t RESERVED5[644U];
00352   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
00353 }  NVIC_Type;
00354 
00355 /* Software Triggered Interrupt Register Definitions */
00356 #define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
00357 #define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
00358 
00359 /*@} end of group CMSIS_NVIC */
00360 
00361 
00362 /**
00363   \ingroup  CMSIS_core_register
00364   \defgroup CMSIS_SCB     System Control Block (SCB)
00365   \brief    Type definitions for the System Control Block Registers
00366   @{
00367  */
00368 
00369 /**
00370   \brief  Structure type to access the System Control Block (SCB).
00371  */
00372 typedef struct
00373 {
00374   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
00375   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
00376   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
00377   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
00378   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
00379   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
00380   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00381   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
00382   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
00383   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
00384   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
00385   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
00386   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
00387   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
00388   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
00389   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
00390   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
00391   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
00392   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
00393         uint32_t RESERVED0[5U];
00394   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
00395         uint32_t RESERVED1[129U];
00396   __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
00397 } SCB_Type;
00398 
00399 /* SCB CPUID Register Definitions */
00400 #define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
00401 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00402 
00403 #define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
00404 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00405 
00406 #define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
00407 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00408 
00409 #define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
00410 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00411 
00412 #define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
00413 #define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
00414 
00415 /* SCB Interrupt Control State Register Definitions */
00416 #define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
00417 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00418 
00419 #define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
00420 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00421 
00422 #define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
00423 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00424 
00425 #define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
00426 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00427 
00428 #define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
00429 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00430 
00431 #define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
00432 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00433 
00434 #define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
00435 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00436 
00437 #define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
00438 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00439 
00440 #define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
00441 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00442 
00443 #define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
00444 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
00445 
00446 /* SCB Vector Table Offset Register Definitions */
00447 #define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
00448 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00449 
00450 #define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
00451 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
00452 
00453 /* SCB Application Interrupt and Reset Control Register Definitions */
00454 #define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
00455 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00456 
00457 #define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
00458 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00459 
00460 #define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
00461 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00462 
00463 #define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
00464 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00465 
00466 #define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
00467 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00468 
00469 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
00470 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00471 
00472 #define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
00473 #define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
00474 
00475 /* SCB System Control Register Definitions */
00476 #define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
00477 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00478 
00479 #define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
00480 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00481 
00482 #define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
00483 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00484 
00485 /* SCB Configuration Control Register Definitions */
00486 #define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
00487 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00488 
00489 #define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
00490 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00491 
00492 #define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
00493 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00494 
00495 #define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
00496 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00497 
00498 #define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
00499 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00500 
00501 #define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
00502 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
00503 
00504 /* SCB System Handler Control and State Register Definitions */
00505 #define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
00506 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00507 
00508 #define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
00509 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00510 
00511 #define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
00512 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00513 
00514 #define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
00515 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00516 
00517 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
00518 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00519 
00520 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
00521 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00522 
00523 #define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
00524 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00525 
00526 #define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
00527 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00528 
00529 #define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
00530 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00531 
00532 #define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
00533 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00534 
00535 #define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
00536 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00537 
00538 #define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
00539 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00540 
00541 #define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
00542 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00543 
00544 #define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
00545 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
00546 
00547 /* SCB Configurable Fault Status Register Definitions */
00548 #define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
00549 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00550 
00551 #define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
00552 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00553 
00554 #define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00555 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00556 
00557 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
00558 #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
00559 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
00560 
00561 #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
00562 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
00563 
00564 #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
00565 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
00566 
00567 #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
00568 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
00569 
00570 #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
00571 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
00572 
00573 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
00574 #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
00575 #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
00576 
00577 #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
00578 #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
00579 
00580 #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
00581 #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
00582 
00583 #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
00584 #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
00585 
00586 #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
00587 #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
00588 
00589 #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
00590 #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
00591 
00592 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
00593 #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
00594 #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
00595 
00596 #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
00597 #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
00598 
00599 #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
00600 #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
00601 
00602 #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
00603 #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
00604 
00605 #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
00606 #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
00607 
00608 #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
00609 #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
00610 
00611 /* SCB Hard Fault Status Register Definitions */
00612 #define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
00613 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00614 
00615 #define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
00616 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00617 
00618 #define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
00619 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00620 
00621 /* SCB Debug Fault Status Register Definitions */
00622 #define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
00623 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00624 
00625 #define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
00626 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00627 
00628 #define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
00629 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00630 
00631 #define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
00632 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00633 
00634 #define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
00635 #define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
00636 
00637 /*@} end of group CMSIS_SCB */
00638 
00639 
00640 /**
00641   \ingroup  CMSIS_core_register
00642   \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00643   \brief    Type definitions for the System Control and ID Register not in the SCB
00644   @{
00645  */
00646 
00647 /**
00648   \brief  Structure type to access the System Control and ID Register not in the SCB.
00649  */
00650 typedef struct
00651 {
00652         uint32_t RESERVED0[1U];
00653   __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
00654         uint32_t RESERVED1[1U];
00655 } SCnSCB_Type;
00656 
00657 /* Interrupt Controller Type Register Definitions */
00658 #define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
00659 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
00660 
00661 /*@} end of group CMSIS_SCnotSCB */
00662 
00663 
00664 /**
00665   \ingroup  CMSIS_core_register
00666   \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00667   \brief    Type definitions for the System Timer Registers.
00668   @{
00669  */
00670 
00671 /**
00672   \brief  Structure type to access the System Timer (SysTick).
00673  */
00674 typedef struct
00675 {
00676   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00677   __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
00678   __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
00679   __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
00680 } SysTick_Type;
00681 
00682 /* SysTick Control / Status Register Definitions */
00683 #define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
00684 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00685 
00686 #define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
00687 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00688 
00689 #define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
00690 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00691 
00692 #define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
00693 #define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
00694 
00695 /* SysTick Reload Register Definitions */
00696 #define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
00697 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
00698 
00699 /* SysTick Current Register Definitions */
00700 #define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
00701 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
00702 
00703 /* SysTick Calibration Register Definitions */
00704 #define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
00705 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00706 
00707 #define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
00708 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00709 
00710 #define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
00711 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
00712 
00713 /*@} end of group CMSIS_SysTick */
00714 
00715 
00716 /**
00717   \ingroup  CMSIS_core_register
00718   \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00719   \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
00720   @{
00721  */
00722 
00723 /**
00724   \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00725  */
00726 typedef struct
00727 {
00728   __OM  union
00729   {
00730     __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
00731     __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
00732     __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
00733   }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
00734         uint32_t RESERVED0[864U];
00735   __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
00736         uint32_t RESERVED1[15U];
00737   __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
00738         uint32_t RESERVED2[15U];
00739   __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
00740         uint32_t RESERVED3[29U];
00741   __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
00742   __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
00743   __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
00744         uint32_t RESERVED4[43U];
00745   __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
00746   __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
00747         uint32_t RESERVED5[6U];
00748   __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00749   __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00750   __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00751   __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00752   __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00753   __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00754   __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00755   __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00756   __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00757   __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00758   __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00759   __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00760 } ITM_Type;
00761 
00762 /* ITM Trace Privilege Register Definitions */
00763 #define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
00764 #define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
00765 
00766 /* ITM Trace Control Register Definitions */
00767 #define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
00768 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00769 
00770 #define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
00771 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00772 
00773 #define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
00774 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00775 
00776 #define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
00777 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00778 
00779 #define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
00780 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00781 
00782 #define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
00783 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00784 
00785 #define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
00786 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00787 
00788 #define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
00789 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00790 
00791 #define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
00792 #define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
00793 
00794 /* ITM Integration Write Register Definitions */
00795 #define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
00796 #define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
00797 
00798 /* ITM Integration Read Register Definitions */
00799 #define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
00800 #define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
00801 
00802 /* ITM Integration Mode Control Register Definitions */
00803 #define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
00804 #define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
00805 
00806 /* ITM Lock Status Register Definitions */
00807 #define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
00808 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00809 
00810 #define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
00811 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00812 
00813 #define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
00814 #define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
00815 
00816 /*@}*/ /* end of group CMSIS_ITM */
00817 
00818 
00819 /**
00820   \ingroup  CMSIS_core_register
00821   \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00822   \brief    Type definitions for the Data Watchpoint and Trace (DWT)
00823   @{
00824  */
00825 
00826 /**
00827   \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00828  */
00829 typedef struct
00830 {
00831   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
00832   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
00833   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
00834   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
00835   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
00836   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
00837   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
00838   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
00839   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
00840   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
00841   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
00842         uint32_t RESERVED0[1U];
00843   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
00844   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
00845   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
00846         uint32_t RESERVED1[1U];
00847   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
00848   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
00849   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
00850         uint32_t RESERVED2[1U];
00851   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
00852   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
00853   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
00854 } DWT_Type;
00855 
00856 /* DWT Control Register Definitions */
00857 #define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
00858 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00859 
00860 #define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
00861 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00862 
00863 #define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
00864 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00865 
00866 #define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
00867 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00868 
00869 #define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
00870 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00871 
00872 #define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
00873 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00874 
00875 #define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
00876 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00877 
00878 #define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
00879 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00880 
00881 #define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
00882 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00883 
00884 #define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
00885 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00886 
00887 #define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
00888 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00889 
00890 #define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
00891 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00892 
00893 #define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
00894 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00895 
00896 #define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
00897 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00898 
00899 #define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
00900 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00901 
00902 #define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
00903 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00904 
00905 #define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
00906 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00907 
00908 #define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
00909 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
00910 
00911 /* DWT CPI Count Register Definitions */
00912 #define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
00913 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
00914 
00915 /* DWT Exception Overhead Count Register Definitions */
00916 #define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
00917 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
00918 
00919 /* DWT Sleep Count Register Definitions */
00920 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
00921 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00922 
00923 /* DWT LSU Count Register Definitions */
00924 #define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
00925 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
00926 
00927 /* DWT Folded-instruction Count Register Definitions */
00928 #define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
00929 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
00930 
00931 /* DWT Comparator Mask Register Definitions */
00932 #define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
00933 #define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
00934 
00935 /* DWT Comparator Function Register Definitions */
00936 #define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
00937 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00938 
00939 #define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
00940 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00941 
00942 #define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
00943 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00944 
00945 #define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
00946 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00947 
00948 #define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
00949 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00950 
00951 #define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
00952 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00953 
00954 #define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
00955 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00956 
00957 #define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
00958 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00959 
00960 #define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
00961 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
00962 
00963 /*@}*/ /* end of group CMSIS_DWT */
00964 
00965 
00966 /**
00967   \ingroup  CMSIS_core_register
00968   \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00969   \brief    Type definitions for the Trace Port Interface (TPI)
00970   @{
00971  */
00972 
00973 /**
00974   \brief  Structure type to access the Trace Port Interface Register (TPI).
00975  */
00976 typedef struct
00977 {
00978   __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
00979   __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00980         uint32_t RESERVED0[2U];
00981   __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00982         uint32_t RESERVED1[55U];
00983   __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00984         uint32_t RESERVED2[131U];
00985   __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00986   __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00987   __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00988         uint32_t RESERVED3[759U];
00989   __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00990   __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00991   __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00992         uint32_t RESERVED4[1U];
00993   __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00994   __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00995   __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00996         uint32_t RESERVED5[39U];
00997   __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00998   __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00999         uint32_t RESERVED7[8U];
01000   __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
01001   __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
01002 } TPI_Type;
01003 
01004 /* TPI Asynchronous Clock Prescaler Register Definitions */
01005 #define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
01006 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
01007 
01008 /* TPI Selected Pin Protocol Register Definitions */
01009 #define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
01010 #define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
01011 
01012 /* TPI Formatter and Flush Status Register Definitions */
01013 #define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
01014 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
01015 
01016 #define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
01017 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
01018 
01019 #define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
01020 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
01021 
01022 #define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
01023 #define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
01024 
01025 /* TPI Formatter and Flush Control Register Definitions */
01026 #define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
01027 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
01028 
01029 #define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
01030 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
01031 
01032 /* TPI TRIGGER Register Definitions */
01033 #define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
01034 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
01035 
01036 /* TPI Integration ETM Data Register Definitions (FIFO0) */
01037 #define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
01038 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
01039 
01040 #define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
01041 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
01042 
01043 #define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
01044 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
01045 
01046 #define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
01047 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
01048 
01049 #define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
01050 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
01051 
01052 #define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
01053 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
01054 
01055 #define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
01056 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
01057 
01058 /* TPI ITATBCTR2 Register Definitions */
01059 #define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
01060 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
01061 
01062 /* TPI Integration ITM Data Register Definitions (FIFO1) */
01063 #define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
01064 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
01065 
01066 #define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
01067 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
01068 
01069 #define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
01070 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
01071 
01072 #define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
01073 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
01074 
01075 #define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
01076 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
01077 
01078 #define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
01079 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01080 
01081 #define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
01082 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
01083 
01084 /* TPI ITATBCTR0 Register Definitions */
01085 #define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
01086 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
01087 
01088 /* TPI Integration Mode Control Register Definitions */
01089 #define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
01090 #define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
01091 
01092 /* TPI DEVID Register Definitions */
01093 #define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
01094 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01095 
01096 #define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
01097 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01098 
01099 #define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
01100 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01101 
01102 #define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
01103 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01104 
01105 #define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
01106 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01107 
01108 #define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
01109 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
01110 
01111 /* TPI DEVTYPE Register Definitions */
01112 #define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
01113 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01114 
01115 #define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
01116 #define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
01117 
01118 /*@}*/ /* end of group CMSIS_TPI */
01119 
01120 
01121 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
01122 /**
01123   \ingroup  CMSIS_core_register
01124   \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01125   \brief    Type definitions for the Memory Protection Unit (MPU)
01126   @{
01127  */
01128 
01129 /**
01130   \brief  Structure type to access the Memory Protection Unit (MPU).
01131  */
01132 typedef struct
01133 {
01134   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
01135   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
01136   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
01137   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
01138   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
01139   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
01140   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01141   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
01142   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01143   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
01144   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01145 } MPU_Type;
01146 
01147 /* MPU Type Register Definitions */
01148 #define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
01149 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01150 
01151 #define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
01152 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01153 
01154 #define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
01155 #define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
01156 
01157 /* MPU Control Register Definitions */
01158 #define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
01159 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01160 
01161 #define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
01162 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01163 
01164 #define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
01165 #define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
01166 
01167 /* MPU Region Number Register Definitions */
01168 #define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
01169 #define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
01170 
01171 /* MPU Region Base Address Register Definitions */
01172 #define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
01173 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01174 
01175 #define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
01176 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01177 
01178 #define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
01179 #define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
01180 
01181 /* MPU Region Attribute and Size Register Definitions */
01182 #define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
01183 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01184 
01185 #define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
01186 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01187 
01188 #define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
01189 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01190 
01191 #define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
01192 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01193 
01194 #define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
01195 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01196 
01197 #define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
01198 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01199 
01200 #define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
01201 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01202 
01203 #define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
01204 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01205 
01206 #define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
01207 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01208 
01209 #define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
01210 #define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
01211 
01212 /*@} end of group CMSIS_MPU */
01213 #endif
01214 
01215 
01216 /**
01217   \ingroup  CMSIS_core_register
01218   \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01219   \brief    Type definitions for the Core Debug Registers
01220   @{
01221  */
01222 
01223 /**
01224   \brief  Structure type to access the Core Debug Register (CoreDebug).
01225  */
01226 typedef struct
01227 {
01228   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
01229   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
01230   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
01231   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01232 } CoreDebug_Type;
01233 
01234 /* Debug Halting Control and Status Register Definitions */
01235 #define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
01236 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01237 
01238 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
01239 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01240 
01241 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01242 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01243 
01244 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
01245 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01246 
01247 #define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
01248 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01249 
01250 #define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
01251 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01252 
01253 #define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
01254 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01255 
01256 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01257 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01258 
01259 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
01260 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01261 
01262 #define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
01263 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01264 
01265 #define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
01266 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01267 
01268 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01269 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01270 
01271 /* Debug Core Register Selector Register Definitions */
01272 #define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
01273 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01274 
01275 #define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
01276 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
01277 
01278 /* Debug Exception and Monitor Control Register Definitions */
01279 #define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
01280 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01281 
01282 #define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
01283 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01284 
01285 #define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
01286 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01287 
01288 #define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
01289 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01290 
01291 #define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
01292 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01293 
01294 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
01295 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01296 
01297 #define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
01298 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01299 
01300 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
01301 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01302 
01303 #define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
01304 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01305 
01306 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
01307 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01308 
01309 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01310 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01311 
01312 #define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
01313 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01314 
01315 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
01316 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01317 
01318 /*@} end of group CMSIS_CoreDebug */
01319 
01320 
01321 /**
01322   \ingroup    CMSIS_core_register
01323   \defgroup   CMSIS_core_bitfield     Core register bit field macros
01324   \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
01325   @{
01326  */
01327 
01328 /**
01329   \brief   Mask and shift a bit field value for use in a register bit range.
01330   \param[in] field  Name of the register bit field.
01331   \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
01332   \return           Masked and shifted value.
01333 */
01334 #define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
01335 
01336 /**
01337   \brief     Mask and shift a register value to extract a bit filed value.
01338   \param[in] field  Name of the register bit field.
01339   \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
01340   \return           Masked and shifted bit field value.
01341 */
01342 #define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
01343 
01344 /*@} end of group CMSIS_core_bitfield */
01345 
01346 
01347 /**
01348   \ingroup    CMSIS_core_register
01349   \defgroup   CMSIS_core_base     Core Definitions
01350   \brief      Definitions for base addresses, unions, and structures.
01351   @{
01352  */
01353 
01354 /* Memory mapping of Core Hardware */
01355 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
01356 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
01357 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
01358 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
01359 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
01360 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
01361 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
01362 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
01363 
01364 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01365 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
01366 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
01367 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
01368 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
01369 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
01370 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
01371 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
01372 
01373 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
01374   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
01375   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
01376 #endif
01377 
01378 /*@} */
01379 
01380 
01381 
01382 /*******************************************************************************
01383  *                Hardware Abstraction Layer
01384   Core Function Interface contains:
01385   - Core NVIC Functions
01386   - Core SysTick Functions
01387   - Core Debug Functions
01388   - Core Register Access Functions
01389  ******************************************************************************/
01390 /**
01391   \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01392 */
01393 
01394 
01395 
01396 /* ##########################   NVIC functions  #################################### */
01397 /**
01398   \ingroup  CMSIS_Core_FunctionInterface
01399   \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01400   \brief    Functions that manage interrupts and exceptions via the NVIC.
01401   @{
01402  */
01403 
01404 #ifdef CMSIS_NVIC_VIRTUAL
01405   #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
01406     #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
01407   #endif
01408   #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
01409 #else
01410   #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
01411   #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
01412   #define NVIC_EnableIRQ              __NVIC_EnableIRQ
01413   #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
01414   #define NVIC_DisableIRQ             __NVIC_DisableIRQ
01415   #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
01416   #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
01417   #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
01418   #define NVIC_GetActive              __NVIC_GetActive
01419   #define NVIC_SetPriority            __NVIC_SetPriority
01420   #define NVIC_GetPriority            __NVIC_GetPriority
01421   #define NVIC_SystemReset            __NVIC_SystemReset
01422 #endif /* CMSIS_NVIC_VIRTUAL */
01423 
01424 #ifdef CMSIS_VECTAB_VIRTUAL
01425   #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01426     #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
01427   #endif
01428   #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
01429 #else
01430   #define NVIC_SetVector              __NVIC_SetVector
01431   #define NVIC_GetVector              __NVIC_GetVector
01432 #endif  /* (CMSIS_VECTAB_VIRTUAL) */
01433 
01434 #define NVIC_USER_IRQ_OFFSET          16
01435 
01436 
01437 
01438 /**
01439   \brief   Set Priority Grouping
01440   \details Sets the priority grouping field using the required unlock sequence.
01441            The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01442            Only values from 0..7 are used.
01443            In case of a conflict between priority grouping and available
01444            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01445   \param [in]      PriorityGroup  Priority grouping field.
01446  */
01447 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01448 {
01449   uint32_t reg_value;
01450   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
01451 
01452   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01453   reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
01454   reg_value  =  (reg_value                                   |
01455                 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
01456                 (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
01457   SCB->AIRCR =  reg_value;
01458 }
01459 
01460 
01461 /**
01462   \brief   Get Priority Grouping
01463   \details Reads the priority grouping field from the NVIC Interrupt Controller.
01464   \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01465  */
01466 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
01467 {
01468   return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
01469 }
01470 
01471 
01472 /**
01473   \brief   Enable Interrupt
01474   \details Enables a device specific interrupt in the NVIC interrupt controller.
01475   \param [in]      IRQn  Device specific interrupt number.
01476   \note    IRQn must not be negative.
01477  */
01478 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
01479 {
01480   if ((int32_t)(IRQn) >= 0)
01481   {
01482     NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01483   }
01484 }
01485 
01486 
01487 /**
01488   \brief   Get Interrupt Enable status
01489   \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
01490   \param [in]      IRQn  Device specific interrupt number.
01491   \return             0  Interrupt is not enabled.
01492   \return             1  Interrupt is enabled.
01493   \note    IRQn must not be negative.
01494  */
01495 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
01496 {
01497   if ((int32_t)(IRQn) >= 0)
01498   {
01499     return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01500   }
01501   else
01502   {
01503     return(0U);
01504   }
01505 }
01506 
01507 
01508 /**
01509   \brief   Disable Interrupt
01510   \details Disables a device specific interrupt in the NVIC interrupt controller.
01511   \param [in]      IRQn  Device specific interrupt number.
01512   \note    IRQn must not be negative.
01513  */
01514 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
01515 {
01516   if ((int32_t)(IRQn) >= 0)
01517   {
01518     NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01519     __DSB();
01520     __ISB();
01521   }
01522 }
01523 
01524 
01525 /**
01526   \brief   Get Pending Interrupt
01527   \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
01528   \param [in]      IRQn  Device specific interrupt number.
01529   \return             0  Interrupt status is not pending.
01530   \return             1  Interrupt status is pending.
01531   \note    IRQn must not be negative.
01532  */
01533 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
01534 {
01535   if ((int32_t)(IRQn) >= 0)
01536   {
01537     return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01538   }
01539   else
01540   {
01541     return(0U);
01542   }
01543 }
01544 
01545 
01546 /**
01547   \brief   Set Pending Interrupt
01548   \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
01549   \param [in]      IRQn  Device specific interrupt number.
01550   \note    IRQn must not be negative.
01551  */
01552 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
01553 {
01554   if ((int32_t)(IRQn) >= 0)
01555   {
01556     NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01557   }
01558 }
01559 
01560 
01561 /**
01562   \brief   Clear Pending Interrupt
01563   \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
01564   \param [in]      IRQn  Device specific interrupt number.
01565   \note    IRQn must not be negative.
01566  */
01567 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01568 {
01569   if ((int32_t)(IRQn) >= 0)
01570   {
01571     NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
01572   }
01573 }
01574 
01575 
01576 /**
01577   \brief   Get Active Interrupt
01578   \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
01579   \param [in]      IRQn  Device specific interrupt number.
01580   \return             0  Interrupt status is not active.
01581   \return             1  Interrupt status is active.
01582   \note    IRQn must not be negative.
01583  */
01584 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
01585 {
01586   if ((int32_t)(IRQn) >= 0)
01587   {
01588     return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
01589   }
01590   else
01591   {
01592     return(0U);
01593   }
01594 }
01595 
01596 
01597 /**
01598   \brief   Set Interrupt Priority
01599   \details Sets the priority of a device specific interrupt or a processor exception.
01600            The interrupt number can be positive to specify a device specific interrupt,
01601            or negative to specify a processor exception.
01602   \param [in]      IRQn  Interrupt number.
01603   \param [in]  priority  Priority to set.
01604   \note    The priority cannot be set for every processor exception.
01605  */
01606 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01607 {
01608   if ((int32_t)(IRQn) >= 0)
01609   {
01610     NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01611   }
01612   else
01613   {
01614     SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
01615   }
01616 }
01617 
01618 
01619 /**
01620   \brief   Get Interrupt Priority
01621   \details Reads the priority of a device specific interrupt or a processor exception.
01622            The interrupt number can be positive to specify a device specific interrupt,
01623            or negative to specify a processor exception.
01624   \param [in]   IRQn  Interrupt number.
01625   \return             Interrupt Priority.
01626                       Value is aligned automatically to the implemented priority bits of the microcontroller.
01627  */
01628 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
01629 {
01630 
01631   if ((int32_t)(IRQn) >= 0)
01632   {
01633     return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
01634   }
01635   else
01636   {
01637     return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
01638   }
01639 }
01640 
01641 
01642 /**
01643   \brief   Encode Priority
01644   \details Encodes the priority for an interrupt with the given priority group,
01645            preemptive priority value, and subpriority value.
01646            In case of a conflict between priority grouping and available
01647            priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01648   \param [in]     PriorityGroup  Used priority group.
01649   \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01650   \param [in]       SubPriority  Subpriority value (starting from 0).
01651   \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01652  */
01653 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01654 {
01655   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01656   uint32_t PreemptPriorityBits;
01657   uint32_t SubPriorityBits;
01658 
01659   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01660   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01661 
01662   return (
01663            ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
01664            ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
01665          );
01666 }
01667 
01668 
01669 /**
01670   \brief   Decode Priority
01671   \details Decodes an interrupt priority value with a given priority group to
01672            preemptive priority value and subpriority value.
01673            In case of a conflict between priority grouping and available
01674            priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
01675   \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01676   \param [in]     PriorityGroup  Used priority group.
01677   \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01678   \param [out]     pSubPriority  Subpriority value (starting from 0).
01679  */
01680 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
01681 {
01682   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
01683   uint32_t PreemptPriorityBits;
01684   uint32_t SubPriorityBits;
01685 
01686   PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
01687   SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
01688 
01689   *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
01690   *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
01691 }
01692 
01693 
01694 /**
01695   \brief   Set Interrupt Vector
01696   \details Sets an interrupt vector in SRAM based interrupt vector table.
01697            The interrupt number can be positive to specify a device specific interrupt,
01698            or negative to specify a processor exception.
01699            VTOR must been relocated to SRAM before.
01700   \param [in]   IRQn      Interrupt number
01701   \param [in]   vector    Address of interrupt handler function
01702  */
01703 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
01704 {
01705   uint32_t *vectors = (uint32_t *)SCB->VTOR;
01706   vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
01707 }
01708 
01709 
01710 /**
01711   \brief   Get Interrupt Vector
01712   \details Reads an interrupt vector from interrupt vector table.
01713            The interrupt number can be positive to specify a device specific interrupt,
01714            or negative to specify a processor exception.
01715   \param [in]   IRQn      Interrupt number.
01716   \return                 Address of interrupt handler function
01717  */
01718 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
01719 {
01720   uint32_t *vectors = (uint32_t *)SCB->VTOR;
01721   return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
01722 }
01723 
01724 
01725 /**
01726   \brief   System Reset
01727   \details Initiates a system reset request to reset the MCU.
01728  */
01729 __STATIC_INLINE void __NVIC_SystemReset(void)
01730 {
01731   __DSB();                                                          /* Ensure all outstanding memory accesses included
01732                                                                        buffered write are completed before reset */
01733   SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
01734                            (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01735                             SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
01736   __DSB();                                                          /* Ensure completion of memory access */
01737 
01738   for(;;)                                                           /* wait until reset */
01739   {
01740     __NOP();
01741   }
01742 }
01743 
01744 /*@} end of CMSIS_Core_NVICFunctions */
01745 
01746 
01747 /* ##########################  FPU functions  #################################### */
01748 /**
01749   \ingroup  CMSIS_Core_FunctionInterface
01750   \defgroup CMSIS_Core_FpuFunctions FPU Functions
01751   \brief    Function that provides FPU type.
01752   @{
01753  */
01754 
01755 /**
01756   \brief   get FPU type
01757   \details returns the FPU type
01758   \returns
01759    - \b  0: No FPU
01760    - \b  1: Single precision FPU
01761    - \b  2: Double + Single precision FPU
01762  */
01763 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
01764 {
01765     return 0U;           /* No FPU */
01766 }
01767 
01768 
01769 /*@} end of CMSIS_Core_FpuFunctions */
01770 
01771 
01772 
01773 /* ##################################    SysTick function  ############################################ */
01774 /**
01775   \ingroup  CMSIS_Core_FunctionInterface
01776   \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01777   \brief    Functions that configure the System.
01778   @{
01779  */
01780 
01781 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
01782 
01783 /**
01784   \brief   System Tick Configuration
01785   \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
01786            Counter is in free running mode to generate periodic interrupts.
01787   \param [in]  ticks  Number of ticks between two interrupts.
01788   \return          0  Function succeeded.
01789   \return          1  Function failed.
01790   \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01791            function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01792            must contain a vendor-specific implementation of this function.
01793  */
01794 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01795 {
01796   if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
01797   {
01798     return (1UL);                                                   /* Reload value impossible */
01799   }
01800 
01801   SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
01802   NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
01803   SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
01804   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01805                    SysTick_CTRL_TICKINT_Msk   |
01806                    SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
01807   return (0UL);                                                     /* Function successful */
01808 }
01809 
01810 #endif
01811 
01812 /*@} end of CMSIS_Core_SysTickFunctions */
01813 
01814 
01815 
01816 /* ##################################### Debug In/Output function ########################################### */
01817 /**
01818   \ingroup  CMSIS_Core_FunctionInterface
01819   \defgroup CMSIS_core_DebugFunctions ITM Functions
01820   \brief    Functions that access the ITM debug interface.
01821   @{
01822  */
01823 
01824 extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
01825 #define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01826 
01827 
01828 /**
01829   \brief   ITM Send Character
01830   \details Transmits a character via the ITM channel 0, and
01831            \li Just returns when no debugger is connected that has booked the output.
01832            \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01833   \param [in]     ch  Character to transmit.
01834   \returns            Character to transmit.
01835  */
01836 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01837 {
01838   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
01839       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
01840   {
01841     while (ITM->PORT[0U].u32 == 0UL)
01842     {
01843       __NOP();
01844     }
01845     ITM->PORT[0U].u8 = (uint8_t)ch;
01846   }
01847   return (ch);
01848 }
01849 
01850 
01851 /**
01852   \brief   ITM Receive Character
01853   \details Inputs a character via the external variable \ref ITM_RxBuffer.
01854   \return             Received character.
01855   \return         -1  No character pending.
01856  */
01857 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
01858 {
01859   int32_t ch = -1;                           /* no character available */
01860 
01861   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
01862   {
01863     ch = ITM_RxBuffer;
01864     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01865   }
01866 
01867   return (ch);
01868 }
01869 
01870 
01871 /**
01872   \brief   ITM Check Character
01873   \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01874   \return          0  No character available.
01875   \return          1  Character available.
01876  */
01877 __STATIC_INLINE int32_t ITM_CheckChar (void)
01878 {
01879 
01880   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
01881   {
01882     return (0);                              /* no character available */
01883   }
01884   else
01885   {
01886     return (1);                              /*    character available */
01887   }
01888 }
01889 
01890 /*@} end of CMSIS_core_DebugFunctions */
01891 
01892 
01893 
01894 
01895 #ifdef __cplusplus
01896 }
01897 #endif
01898 
01899 #endif /* __CORE_SC300_H_DEPENDANT */
01900 
01901 #endif /* __CMSIS_GENERIC */