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core_cm4.h
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00001 /**************************************************************************//** 00002 * @file core_cm4.h 00003 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File 00004 * @version V5.0.2 00005 * @date 13. February 2017 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM4_H_GENERIC 00032 #define __CORE_CM4_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M4 00060 @{ 00061 */ 00062 00063 /* CMSIS CM4 definitions */ 00064 #define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ 00065 #define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ 00066 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ 00067 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00068 00069 #define __CORTEX_M (4U) /*!< Cortex-M Core */ 00070 00071 /** __FPU_USED indicates whether an FPU is used or not. 00072 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. 00073 */ 00074 #if defined ( __CC_ARM ) 00075 #if defined __TARGET_FPU_VFP 00076 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00077 #define __FPU_USED 1U 00078 #else 00079 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00080 #define __FPU_USED 0U 00081 #endif 00082 #else 00083 #define __FPU_USED 0U 00084 #endif 00085 00086 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00087 #if defined __ARM_PCS_VFP 00088 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00089 #define __FPU_USED 1U 00090 #else 00091 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00092 #define __FPU_USED 0U 00093 #endif 00094 #else 00095 #define __FPU_USED 0U 00096 #endif 00097 00098 #elif defined ( __GNUC__ ) 00099 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00101 #define __FPU_USED 1U 00102 #else 00103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00104 #define __FPU_USED 0U 00105 #endif 00106 #else 00107 #define __FPU_USED 0U 00108 #endif 00109 00110 #elif defined ( __ICCARM__ ) 00111 #if defined __ARMVFP__ 00112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00113 #define __FPU_USED 1U 00114 #else 00115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00116 #define __FPU_USED 0U 00117 #endif 00118 #else 00119 #define __FPU_USED 0U 00120 #endif 00121 00122 #elif defined ( __TI_ARM__ ) 00123 #if defined __TI_VFP_SUPPORT__ 00124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00125 #define __FPU_USED 1U 00126 #else 00127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #define __FPU_USED 0U 00129 #endif 00130 #else 00131 #define __FPU_USED 0U 00132 #endif 00133 00134 #elif defined ( __TASKING__ ) 00135 #if defined __FPU_VFP__ 00136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00137 #define __FPU_USED 1U 00138 #else 00139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00140 #define __FPU_USED 0U 00141 #endif 00142 #else 00143 #define __FPU_USED 0U 00144 #endif 00145 00146 #elif defined ( __CSMC__ ) 00147 #if ( __CSMC__ & 0x400U) 00148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) 00149 #define __FPU_USED 1U 00150 #else 00151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00152 #define __FPU_USED 0U 00153 #endif 00154 #else 00155 #define __FPU_USED 0U 00156 #endif 00157 00158 #endif 00159 00160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00161 00162 00163 #ifdef __cplusplus 00164 } 00165 #endif 00166 00167 #endif /* __CORE_CM4_H_GENERIC */ 00168 00169 #ifndef __CMSIS_GENERIC 00170 00171 #ifndef __CORE_CM4_H_DEPENDANT 00172 #define __CORE_CM4_H_DEPENDANT 00173 00174 #ifdef __cplusplus 00175 extern "C" { 00176 #endif 00177 00178 /* check device defines and use defaults */ 00179 #if defined __CHECK_DEVICE_DEFINES 00180 #ifndef __CM4_REV 00181 #define __CM4_REV 0x0000U 00182 #warning "__CM4_REV not defined in device header file; using default!" 00183 #endif 00184 00185 #ifndef __FPU_PRESENT 00186 #define __FPU_PRESENT 0U 00187 #warning "__FPU_PRESENT not defined in device header file; using default!" 00188 #endif 00189 00190 #ifndef __MPU_PRESENT 00191 #define __MPU_PRESENT 0U 00192 #warning "__MPU_PRESENT not defined in device header file; using default!" 00193 #endif 00194 00195 #ifndef __NVIC_PRIO_BITS 00196 #define __NVIC_PRIO_BITS 3U 00197 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00198 #endif 00199 00200 #ifndef __Vendor_SysTickConfig 00201 #define __Vendor_SysTickConfig 0U 00202 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00203 #endif 00204 #endif 00205 00206 /* IO definitions (access restrictions to peripheral registers) */ 00207 /** 00208 \defgroup CMSIS_glob_defs CMSIS Global Defines 00209 00210 <strong>IO Type Qualifiers</strong> are used 00211 \li to specify the access to peripheral variables. 00212 \li for automatic generation of peripheral register debug information. 00213 */ 00214 #ifdef __cplusplus 00215 #define __I volatile /*!< Defines 'read only' permissions */ 00216 #else 00217 #define __I volatile const /*!< Defines 'read only' permissions */ 00218 #endif 00219 #define __O volatile /*!< Defines 'write only' permissions */ 00220 #define __IO volatile /*!< Defines 'read / write' permissions */ 00221 00222 /* following defines should be used for structure members */ 00223 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00224 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00225 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00226 00227 /*@} end of group Cortex_M4 */ 00228 00229 00230 00231 /******************************************************************************* 00232 * Register Abstraction 00233 Core Register contain: 00234 - Core Register 00235 - Core NVIC Register 00236 - Core SCB Register 00237 - Core SysTick Register 00238 - Core Debug Register 00239 - Core MPU Register 00240 - Core FPU Register 00241 ******************************************************************************/ 00242 /** 00243 \defgroup CMSIS_core_register Defines and Type Definitions 00244 \brief Type definitions and defines for Cortex-M processor based devices. 00245 */ 00246 00247 /** 00248 \ingroup CMSIS_core_register 00249 \defgroup CMSIS_CORE Status and Control Registers 00250 \brief Core Register type definitions. 00251 @{ 00252 */ 00253 00254 /** 00255 \brief Union type to access the Application Program Status Register (APSR). 00256 */ 00257 typedef union 00258 { 00259 struct 00260 { 00261 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00262 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00263 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00264 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00265 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00266 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00267 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00268 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00269 } b; /*!< Structure used for bit access */ 00270 uint32_t w; /*!< Type used for word access */ 00271 } APSR_Type; 00272 00273 /* APSR Register Definitions */ 00274 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00275 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00276 00277 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00278 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00279 00280 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00281 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00282 00283 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00284 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00285 00286 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00287 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00288 00289 #define APSR_GE_Pos 16U /*!< APSR: GE Position */ 00290 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ 00291 00292 00293 /** 00294 \brief Union type to access the Interrupt Program Status Register (IPSR). 00295 */ 00296 typedef union 00297 { 00298 struct 00299 { 00300 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00301 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00302 } b; /*!< Structure used for bit access */ 00303 uint32_t w; /*!< Type used for word access */ 00304 } IPSR_Type; 00305 00306 /* IPSR Register Definitions */ 00307 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00308 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00309 00310 00311 /** 00312 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00313 */ 00314 typedef union 00315 { 00316 struct 00317 { 00318 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00319 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00320 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00321 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00322 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00323 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00324 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00325 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00326 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00327 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00328 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00329 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00330 } b; /*!< Structure used for bit access */ 00331 uint32_t w; /*!< Type used for word access */ 00332 } xPSR_Type; 00333 00334 /* xPSR Register Definitions */ 00335 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00336 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00337 00338 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00339 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00340 00341 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00342 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00343 00344 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00345 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00346 00347 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00348 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00349 00350 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00351 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00352 00353 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00354 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00355 00356 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ 00357 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ 00358 00359 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00360 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00361 00362 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00363 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00364 00365 00366 /** 00367 \brief Union type to access the Control Registers (CONTROL). 00368 */ 00369 typedef union 00370 { 00371 struct 00372 { 00373 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00374 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00375 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00376 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00377 } b; /*!< Structure used for bit access */ 00378 uint32_t w; /*!< Type used for word access */ 00379 } CONTROL_Type; 00380 00381 /* CONTROL Register Definitions */ 00382 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ 00383 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ 00384 00385 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00386 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00387 00388 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00389 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00390 00391 /*@} end of group CMSIS_CORE */ 00392 00393 00394 /** 00395 \ingroup CMSIS_core_register 00396 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00397 \brief Type definitions for the NVIC Registers 00398 @{ 00399 */ 00400 00401 /** 00402 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00403 */ 00404 typedef struct 00405 { 00406 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00407 uint32_t RESERVED0[24U]; 00408 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00409 uint32_t RSERVED1[24U]; 00410 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00411 uint32_t RESERVED2[24U]; 00412 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00413 uint32_t RESERVED3[24U]; 00414 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00415 uint32_t RESERVED4[56U]; 00416 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00417 uint32_t RESERVED5[644U]; 00418 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00419 } NVIC_Type; 00420 00421 /* Software Triggered Interrupt Register Definitions */ 00422 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00423 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00424 00425 /*@} end of group CMSIS_NVIC */ 00426 00427 00428 /** 00429 \ingroup CMSIS_core_register 00430 \defgroup CMSIS_SCB System Control Block (SCB) 00431 \brief Type definitions for the System Control Block Registers 00432 @{ 00433 */ 00434 00435 /** 00436 \brief Structure type to access the System Control Block (SCB). 00437 */ 00438 typedef struct 00439 { 00440 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00441 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00442 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00443 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00444 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00445 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00446 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00447 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00448 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00449 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00450 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00451 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00452 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00453 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00454 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00455 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00456 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00457 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00458 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00459 uint32_t RESERVED0[5U]; 00460 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00461 } SCB_Type; 00462 00463 /* SCB CPUID Register Definitions */ 00464 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00465 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00466 00467 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00468 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00469 00470 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00471 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00472 00473 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00474 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00475 00476 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00477 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00478 00479 /* SCB Interrupt Control State Register Definitions */ 00480 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00481 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00482 00483 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00484 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00485 00486 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00487 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00488 00489 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00490 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00491 00492 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00493 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00494 00495 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00496 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00497 00498 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00499 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00500 00501 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00502 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00503 00504 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00505 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00506 00507 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00508 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00509 00510 /* SCB Vector Table Offset Register Definitions */ 00511 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00512 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00513 00514 /* SCB Application Interrupt and Reset Control Register Definitions */ 00515 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00516 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00517 00518 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00519 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00520 00521 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00522 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00523 00524 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00525 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00526 00527 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00528 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00529 00530 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00531 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00532 00533 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00534 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00535 00536 /* SCB System Control Register Definitions */ 00537 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00538 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00539 00540 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00541 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00542 00543 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00544 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00545 00546 /* SCB Configuration Control Register Definitions */ 00547 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00548 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00549 00550 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00551 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00552 00553 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00554 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00555 00556 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00557 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00558 00559 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00560 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00561 00562 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00563 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00564 00565 /* SCB System Handler Control and State Register Definitions */ 00566 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00567 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00568 00569 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00570 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00571 00572 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00573 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00574 00575 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00576 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00577 00578 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00579 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00580 00581 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00582 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00583 00584 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00585 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00586 00587 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00588 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00589 00590 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00591 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00592 00593 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00594 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00595 00596 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00597 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00598 00599 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00600 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00601 00602 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00603 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00604 00605 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00606 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00607 00608 /* SCB Configurable Fault Status Register Definitions */ 00609 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00610 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00611 00612 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00613 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00614 00615 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00616 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00617 00618 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00619 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00620 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00621 00622 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ 00623 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ 00624 00625 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00626 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00627 00628 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00629 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00630 00631 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00632 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00633 00634 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00635 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00636 00637 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00638 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00639 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00640 00641 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ 00642 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ 00643 00644 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00645 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00646 00647 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00648 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00649 00650 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00651 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00652 00653 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00654 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00655 00656 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00657 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00658 00659 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00660 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00661 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00662 00663 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00664 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00665 00666 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00667 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00668 00669 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00670 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00671 00672 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00673 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00674 00675 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00676 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00677 00678 /* SCB Hard Fault Status Register Definitions */ 00679 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00680 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00681 00682 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00683 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00684 00685 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00686 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00687 00688 /* SCB Debug Fault Status Register Definitions */ 00689 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00690 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00691 00692 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00693 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00694 00695 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00696 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00697 00698 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00699 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00700 00701 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00702 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00703 00704 /*@} end of group CMSIS_SCB */ 00705 00706 00707 /** 00708 \ingroup CMSIS_core_register 00709 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00710 \brief Type definitions for the System Control and ID Register not in the SCB 00711 @{ 00712 */ 00713 00714 /** 00715 \brief Structure type to access the System Control and ID Register not in the SCB. 00716 */ 00717 typedef struct 00718 { 00719 uint32_t RESERVED0[1U]; 00720 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00721 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00722 } SCnSCB_Type; 00723 00724 /* Interrupt Controller Type Register Definitions */ 00725 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00726 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00727 00728 /* Auxiliary Control Register Definitions */ 00729 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ 00730 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ 00731 00732 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ 00733 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ 00734 00735 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00736 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00737 00738 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 00739 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00740 00741 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00742 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00743 00744 /*@} end of group CMSIS_SCnotSCB */ 00745 00746 00747 /** 00748 \ingroup CMSIS_core_register 00749 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00750 \brief Type definitions for the System Timer Registers. 00751 @{ 00752 */ 00753 00754 /** 00755 \brief Structure type to access the System Timer (SysTick). 00756 */ 00757 typedef struct 00758 { 00759 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00760 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00761 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00762 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00763 } SysTick_Type; 00764 00765 /* SysTick Control / Status Register Definitions */ 00766 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00767 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00768 00769 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00770 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00771 00772 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00773 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00774 00775 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00776 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00777 00778 /* SysTick Reload Register Definitions */ 00779 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00780 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00781 00782 /* SysTick Current Register Definitions */ 00783 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00784 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00785 00786 /* SysTick Calibration Register Definitions */ 00787 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00788 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00789 00790 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00791 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00792 00793 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00794 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00795 00796 /*@} end of group CMSIS_SysTick */ 00797 00798 00799 /** 00800 \ingroup CMSIS_core_register 00801 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00802 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00803 @{ 00804 */ 00805 00806 /** 00807 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00808 */ 00809 typedef struct 00810 { 00811 __OM union 00812 { 00813 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00814 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00815 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00816 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00817 uint32_t RESERVED0[864U]; 00818 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00819 uint32_t RESERVED1[15U]; 00820 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00821 uint32_t RESERVED2[15U]; 00822 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00823 uint32_t RESERVED3[29U]; 00824 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00825 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00826 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00827 uint32_t RESERVED4[43U]; 00828 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00829 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00830 uint32_t RESERVED5[6U]; 00831 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00832 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00833 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00834 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00835 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00836 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00837 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00838 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00839 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00840 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00841 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00842 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00843 } ITM_Type; 00844 00845 /* ITM Trace Privilege Register Definitions */ 00846 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 00847 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00848 00849 /* ITM Trace Control Register Definitions */ 00850 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 00851 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00852 00853 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 00854 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00855 00856 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 00857 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00858 00859 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 00860 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00861 00862 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 00863 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00864 00865 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 00866 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00867 00868 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 00869 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00870 00871 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 00872 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00873 00874 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 00875 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 00876 00877 /* ITM Integration Write Register Definitions */ 00878 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 00879 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 00880 00881 /* ITM Integration Read Register Definitions */ 00882 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 00883 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 00884 00885 /* ITM Integration Mode Control Register Definitions */ 00886 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 00887 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 00888 00889 /* ITM Lock Status Register Definitions */ 00890 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 00891 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00892 00893 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 00894 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00895 00896 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 00897 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 00898 00899 /*@}*/ /* end of group CMSIS_ITM */ 00900 00901 00902 /** 00903 \ingroup CMSIS_core_register 00904 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00905 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00906 @{ 00907 */ 00908 00909 /** 00910 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00911 */ 00912 typedef struct 00913 { 00914 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00915 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00916 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00917 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00918 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00919 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00920 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00921 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00922 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00923 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00924 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00925 uint32_t RESERVED0[1U]; 00926 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00927 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00928 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00929 uint32_t RESERVED1[1U]; 00930 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00931 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00932 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00933 uint32_t RESERVED2[1U]; 00934 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00935 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00936 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00937 } DWT_Type; 00938 00939 /* DWT Control Register Definitions */ 00940 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00941 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00942 00943 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00944 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00945 00946 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00947 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00948 00949 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00950 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00951 00952 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00953 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00954 00955 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 00956 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00957 00958 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 00959 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00960 00961 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 00962 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00963 00964 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 00965 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00966 00967 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 00968 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00969 00970 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 00971 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00972 00973 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 00974 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00975 00976 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 00977 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00978 00979 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 00980 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00981 00982 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 00983 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00984 00985 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 00986 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00987 00988 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 00989 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00990 00991 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 00992 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 00993 00994 /* DWT CPI Count Register Definitions */ 00995 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 00996 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 00997 00998 /* DWT Exception Overhead Count Register Definitions */ 00999 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 01000 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 01001 01002 /* DWT Sleep Count Register Definitions */ 01003 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 01004 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 01005 01006 /* DWT LSU Count Register Definitions */ 01007 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 01008 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 01009 01010 /* DWT Folded-instruction Count Register Definitions */ 01011 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 01012 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 01013 01014 /* DWT Comparator Mask Register Definitions */ 01015 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 01016 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 01017 01018 /* DWT Comparator Function Register Definitions */ 01019 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 01020 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 01021 01022 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 01023 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 01024 01025 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 01026 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 01027 01028 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 01029 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 01030 01031 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 01032 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 01033 01034 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 01035 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 01036 01037 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 01038 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 01039 01040 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 01041 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 01042 01043 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 01044 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 01045 01046 /*@}*/ /* end of group CMSIS_DWT */ 01047 01048 01049 /** 01050 \ingroup CMSIS_core_register 01051 \defgroup CMSIS_TPI Trace Port Interface (TPI) 01052 \brief Type definitions for the Trace Port Interface (TPI) 01053 @{ 01054 */ 01055 01056 /** 01057 \brief Structure type to access the Trace Port Interface Register (TPI). 01058 */ 01059 typedef struct 01060 { 01061 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 01062 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 01063 uint32_t RESERVED0[2U]; 01064 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01065 uint32_t RESERVED1[55U]; 01066 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01067 uint32_t RESERVED2[131U]; 01068 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01069 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01070 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01071 uint32_t RESERVED3[759U]; 01072 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01073 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01074 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01075 uint32_t RESERVED4[1U]; 01076 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01077 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01078 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01079 uint32_t RESERVED5[39U]; 01080 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01081 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01082 uint32_t RESERVED7[8U]; 01083 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01084 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01085 } TPI_Type; 01086 01087 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01088 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01089 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01090 01091 /* TPI Selected Pin Protocol Register Definitions */ 01092 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01093 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01094 01095 /* TPI Formatter and Flush Status Register Definitions */ 01096 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01097 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01098 01099 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01100 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01101 01102 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01103 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01104 01105 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01106 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01107 01108 /* TPI Formatter and Flush Control Register Definitions */ 01109 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01110 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01111 01112 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01113 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01114 01115 /* TPI TRIGGER Register Definitions */ 01116 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01117 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01118 01119 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01120 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01121 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01122 01123 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01124 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01125 01126 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01127 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01128 01129 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01130 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01131 01132 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01133 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01134 01135 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01136 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01137 01138 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01139 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01140 01141 /* TPI ITATBCTR2 Register Definitions */ 01142 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 01143 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01144 01145 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01146 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01147 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01148 01149 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01150 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01151 01152 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01153 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01154 01155 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01156 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01157 01158 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01159 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01160 01161 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01162 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01163 01164 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01165 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01166 01167 /* TPI ITATBCTR0 Register Definitions */ 01168 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 01169 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01170 01171 /* TPI Integration Mode Control Register Definitions */ 01172 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01173 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01174 01175 /* TPI DEVID Register Definitions */ 01176 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01177 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01178 01179 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01180 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01181 01182 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01183 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01184 01185 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01186 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01187 01188 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01189 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01190 01191 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01192 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01193 01194 /* TPI DEVTYPE Register Definitions */ 01195 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 01196 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01197 01198 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 01199 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01200 01201 /*@}*/ /* end of group CMSIS_TPI */ 01202 01203 01204 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01205 /** 01206 \ingroup CMSIS_core_register 01207 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01208 \brief Type definitions for the Memory Protection Unit (MPU) 01209 @{ 01210 */ 01211 01212 /** 01213 \brief Structure type to access the Memory Protection Unit (MPU). 01214 */ 01215 typedef struct 01216 { 01217 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01218 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01219 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01220 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01221 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01222 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01223 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01224 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01225 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01226 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01227 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01228 } MPU_Type; 01229 01230 /* MPU Type Register Definitions */ 01231 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01232 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01233 01234 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01235 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01236 01237 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01238 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01239 01240 /* MPU Control Register Definitions */ 01241 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01242 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01243 01244 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01245 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01246 01247 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01248 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01249 01250 /* MPU Region Number Register Definitions */ 01251 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01252 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01253 01254 /* MPU Region Base Address Register Definitions */ 01255 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01256 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01257 01258 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01259 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01260 01261 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01262 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01263 01264 /* MPU Region Attribute and Size Register Definitions */ 01265 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01266 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01267 01268 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01269 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01270 01271 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01272 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01273 01274 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01275 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01276 01277 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01278 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01279 01280 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01281 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01282 01283 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01284 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01285 01286 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01287 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01288 01289 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01290 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01291 01292 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01293 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01294 01295 /*@} end of group CMSIS_MPU */ 01296 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ 01297 01298 01299 /** 01300 \ingroup CMSIS_core_register 01301 \defgroup CMSIS_FPU Floating Point Unit (FPU) 01302 \brief Type definitions for the Floating Point Unit (FPU) 01303 @{ 01304 */ 01305 01306 /** 01307 \brief Structure type to access the Floating Point Unit (FPU). 01308 */ 01309 typedef struct 01310 { 01311 uint32_t RESERVED0[1U]; 01312 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ 01313 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ 01314 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ 01315 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ 01316 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ 01317 } FPU_Type; 01318 01319 /* Floating-Point Context Control Register Definitions */ 01320 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ 01321 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ 01322 01323 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ 01324 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ 01325 01326 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ 01327 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ 01328 01329 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ 01330 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ 01331 01332 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ 01333 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ 01334 01335 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ 01336 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ 01337 01338 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ 01339 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ 01340 01341 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ 01342 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ 01343 01344 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ 01345 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ 01346 01347 /* Floating-Point Context Address Register Definitions */ 01348 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ 01349 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ 01350 01351 /* Floating-Point Default Status Control Register Definitions */ 01352 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ 01353 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ 01354 01355 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ 01356 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ 01357 01358 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ 01359 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ 01360 01361 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ 01362 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ 01363 01364 /* Media and FP Feature Register 0 Definitions */ 01365 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ 01366 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ 01367 01368 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ 01369 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ 01370 01371 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ 01372 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ 01373 01374 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ 01375 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ 01376 01377 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ 01378 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ 01379 01380 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ 01381 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ 01382 01383 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ 01384 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ 01385 01386 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ 01387 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ 01388 01389 /* Media and FP Feature Register 1 Definitions */ 01390 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ 01391 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ 01392 01393 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 01394 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 01395 01396 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 01397 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 01398 01399 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 01400 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ 01401 01402 /*@} end of group CMSIS_FPU */ 01403 01404 01405 /** 01406 \ingroup CMSIS_core_register 01407 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01408 \brief Type definitions for the Core Debug Registers 01409 @{ 01410 */ 01411 01412 /** 01413 \brief Structure type to access the Core Debug Register (CoreDebug). 01414 */ 01415 typedef struct 01416 { 01417 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01418 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01419 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01420 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01421 } CoreDebug_Type; 01422 01423 /* Debug Halting Control and Status Register Definitions */ 01424 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01425 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01426 01427 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01428 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01429 01430 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01431 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01432 01433 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01434 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01435 01436 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01437 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01438 01439 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01440 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01441 01442 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01443 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01444 01445 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01446 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01447 01448 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01449 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01450 01451 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01452 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01453 01454 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01455 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01456 01457 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01458 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01459 01460 /* Debug Core Register Selector Register Definitions */ 01461 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01462 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01463 01464 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01465 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01466 01467 /* Debug Exception and Monitor Control Register Definitions */ 01468 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01469 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01470 01471 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01472 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01473 01474 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01475 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01476 01477 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01478 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01479 01480 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01481 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01482 01483 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01484 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01485 01486 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01487 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01488 01489 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01490 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01491 01492 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01493 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01494 01495 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01496 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01497 01498 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01499 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01500 01501 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01502 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01503 01504 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01505 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01506 01507 /*@} end of group CMSIS_CoreDebug */ 01508 01509 01510 /** 01511 \ingroup CMSIS_core_register 01512 \defgroup CMSIS_core_bitfield Core register bit field macros 01513 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01514 @{ 01515 */ 01516 01517 /** 01518 \brief Mask and shift a bit field value for use in a register bit range. 01519 \param[in] field Name of the register bit field. 01520 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01521 \return Masked and shifted value. 01522 */ 01523 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01524 01525 /** 01526 \brief Mask and shift a register value to extract a bit filed value. 01527 \param[in] field Name of the register bit field. 01528 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01529 \return Masked and shifted bit field value. 01530 */ 01531 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01532 01533 /*@} end of group CMSIS_core_bitfield */ 01534 01535 01536 /** 01537 \ingroup CMSIS_core_register 01538 \defgroup CMSIS_core_base Core Definitions 01539 \brief Definitions for base addresses, unions, and structures. 01540 @{ 01541 */ 01542 01543 /* Memory mapping of Core Hardware */ 01544 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01545 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01546 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01547 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01548 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01549 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01550 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01551 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01552 01553 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01554 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01555 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01556 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01557 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01558 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01559 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01560 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01561 01562 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01563 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01564 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01565 #endif 01566 01567 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ 01568 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ 01569 01570 /*@} */ 01571 01572 01573 01574 /******************************************************************************* 01575 * Hardware Abstraction Layer 01576 Core Function Interface contains: 01577 - Core NVIC Functions 01578 - Core SysTick Functions 01579 - Core Debug Functions 01580 - Core Register Access Functions 01581 ******************************************************************************/ 01582 /** 01583 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01584 */ 01585 01586 01587 01588 /* ########################## NVIC functions #################################### */ 01589 /** 01590 \ingroup CMSIS_Core_FunctionInterface 01591 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01592 \brief Functions that manage interrupts and exceptions via the NVIC. 01593 @{ 01594 */ 01595 01596 #ifdef CMSIS_NVIC_VIRTUAL 01597 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01598 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01599 #endif 01600 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01601 #else 01602 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01603 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01604 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01605 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01606 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01607 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01608 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01609 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01610 #define NVIC_GetActive __NVIC_GetActive 01611 #define NVIC_SetPriority __NVIC_SetPriority 01612 #define NVIC_GetPriority __NVIC_GetPriority 01613 #define NVIC_SystemReset __NVIC_SystemReset 01614 #endif /* CMSIS_NVIC_VIRTUAL */ 01615 01616 #ifdef CMSIS_VECTAB_VIRTUAL 01617 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01618 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01619 #endif 01620 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01621 #else 01622 #define NVIC_SetVector __NVIC_SetVector 01623 #define NVIC_GetVector __NVIC_GetVector 01624 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01625 01626 #define NVIC_USER_IRQ_OFFSET 16 01627 01628 01629 01630 /** 01631 \brief Set Priority Grouping 01632 \details Sets the priority grouping field using the required unlock sequence. 01633 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01634 Only values from 0..7 are used. 01635 In case of a conflict between priority grouping and available 01636 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01637 \param [in] PriorityGroup Priority grouping field. 01638 */ 01639 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01640 { 01641 uint32_t reg_value; 01642 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01643 01644 reg_value = SCB->AIRCR; /* read old register configuration */ 01645 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01646 reg_value = (reg_value | 01647 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01648 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 01649 SCB->AIRCR = reg_value; 01650 } 01651 01652 01653 /** 01654 \brief Get Priority Grouping 01655 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01656 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01657 */ 01658 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01659 { 01660 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01661 } 01662 01663 01664 /** 01665 \brief Enable Interrupt 01666 \details Enables a device specific interrupt in the NVIC interrupt controller. 01667 \param [in] IRQn Device specific interrupt number. 01668 \note IRQn must not be negative. 01669 */ 01670 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01671 { 01672 if ((int32_t)(IRQn) >= 0) 01673 { 01674 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01675 } 01676 } 01677 01678 01679 /** 01680 \brief Get Interrupt Enable status 01681 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01682 \param [in] IRQn Device specific interrupt number. 01683 \return 0 Interrupt is not enabled. 01684 \return 1 Interrupt is enabled. 01685 \note IRQn must not be negative. 01686 */ 01687 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01688 { 01689 if ((int32_t)(IRQn) >= 0) 01690 { 01691 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01692 } 01693 else 01694 { 01695 return(0U); 01696 } 01697 } 01698 01699 01700 /** 01701 \brief Disable Interrupt 01702 \details Disables a device specific interrupt in the NVIC interrupt controller. 01703 \param [in] IRQn Device specific interrupt number. 01704 \note IRQn must not be negative. 01705 */ 01706 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01707 { 01708 if ((int32_t)(IRQn) >= 0) 01709 { 01710 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01711 __DSB(); 01712 __ISB(); 01713 } 01714 } 01715 01716 01717 /** 01718 \brief Get Pending Interrupt 01719 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01720 \param [in] IRQn Device specific interrupt number. 01721 \return 0 Interrupt status is not pending. 01722 \return 1 Interrupt status is pending. 01723 \note IRQn must not be negative. 01724 */ 01725 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01726 { 01727 if ((int32_t)(IRQn) >= 0) 01728 { 01729 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01730 } 01731 else 01732 { 01733 return(0U); 01734 } 01735 } 01736 01737 01738 /** 01739 \brief Set Pending Interrupt 01740 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01741 \param [in] IRQn Device specific interrupt number. 01742 \note IRQn must not be negative. 01743 */ 01744 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01745 { 01746 if ((int32_t)(IRQn) >= 0) 01747 { 01748 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01749 } 01750 } 01751 01752 01753 /** 01754 \brief Clear Pending Interrupt 01755 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01756 \param [in] IRQn Device specific interrupt number. 01757 \note IRQn must not be negative. 01758 */ 01759 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01760 { 01761 if ((int32_t)(IRQn) >= 0) 01762 { 01763 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01764 } 01765 } 01766 01767 01768 /** 01769 \brief Get Active Interrupt 01770 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01771 \param [in] IRQn Device specific interrupt number. 01772 \return 0 Interrupt status is not active. 01773 \return 1 Interrupt status is active. 01774 \note IRQn must not be negative. 01775 */ 01776 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01777 { 01778 if ((int32_t)(IRQn) >= 0) 01779 { 01780 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01781 } 01782 else 01783 { 01784 return(0U); 01785 } 01786 } 01787 01788 01789 /** 01790 \brief Set Interrupt Priority 01791 \details Sets the priority of a device specific interrupt or a processor exception. 01792 The interrupt number can be positive to specify a device specific interrupt, 01793 or negative to specify a processor exception. 01794 \param [in] IRQn Interrupt number. 01795 \param [in] priority Priority to set. 01796 \note The priority cannot be set for every processor exception. 01797 */ 01798 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01799 { 01800 if ((int32_t)(IRQn) >= 0) 01801 { 01802 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01803 } 01804 else 01805 { 01806 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01807 } 01808 } 01809 01810 01811 /** 01812 \brief Get Interrupt Priority 01813 \details Reads the priority of a device specific interrupt or a processor exception. 01814 The interrupt number can be positive to specify a device specific interrupt, 01815 or negative to specify a processor exception. 01816 \param [in] IRQn Interrupt number. 01817 \return Interrupt Priority. 01818 Value is aligned automatically to the implemented priority bits of the microcontroller. 01819 */ 01820 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01821 { 01822 01823 if ((int32_t)(IRQn) >= 0) 01824 { 01825 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 01826 } 01827 else 01828 { 01829 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 01830 } 01831 } 01832 01833 01834 /** 01835 \brief Encode Priority 01836 \details Encodes the priority for an interrupt with the given priority group, 01837 preemptive priority value, and subpriority value. 01838 In case of a conflict between priority grouping and available 01839 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01840 \param [in] PriorityGroup Used priority group. 01841 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01842 \param [in] SubPriority Subpriority value (starting from 0). 01843 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01844 */ 01845 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01846 { 01847 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01848 uint32_t PreemptPriorityBits; 01849 uint32_t SubPriorityBits; 01850 01851 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01852 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01853 01854 return ( 01855 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01856 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01857 ); 01858 } 01859 01860 01861 /** 01862 \brief Decode Priority 01863 \details Decodes an interrupt priority value with a given priority group to 01864 preemptive priority value and subpriority value. 01865 In case of a conflict between priority grouping and available 01866 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01867 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01868 \param [in] PriorityGroup Used priority group. 01869 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01870 \param [out] pSubPriority Subpriority value (starting from 0). 01871 */ 01872 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01873 { 01874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01875 uint32_t PreemptPriorityBits; 01876 uint32_t SubPriorityBits; 01877 01878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01880 01881 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01882 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01883 } 01884 01885 01886 /** 01887 \brief Set Interrupt Vector 01888 \details Sets an interrupt vector in SRAM based interrupt vector table. 01889 The interrupt number can be positive to specify a device specific interrupt, 01890 or negative to specify a processor exception. 01891 VTOR must been relocated to SRAM before. 01892 \param [in] IRQn Interrupt number 01893 \param [in] vector Address of interrupt handler function 01894 */ 01895 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01896 { 01897 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01898 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01899 } 01900 01901 01902 /** 01903 \brief Get Interrupt Vector 01904 \details Reads an interrupt vector from interrupt vector table. 01905 The interrupt number can be positive to specify a device specific interrupt, 01906 or negative to specify a processor exception. 01907 \param [in] IRQn Interrupt number. 01908 \return Address of interrupt handler function 01909 */ 01910 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01911 { 01912 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01913 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01914 } 01915 01916 01917 /** 01918 \brief System Reset 01919 \details Initiates a system reset request to reset the MCU. 01920 */ 01921 __STATIC_INLINE void __NVIC_SystemReset(void) 01922 { 01923 __DSB(); /* Ensure all outstanding memory accesses included 01924 buffered write are completed before reset */ 01925 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01926 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01927 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01928 __DSB(); /* Ensure completion of memory access */ 01929 01930 for(;;) /* wait until reset */ 01931 { 01932 __NOP(); 01933 } 01934 } 01935 01936 /*@} end of CMSIS_Core_NVICFunctions */ 01937 01938 01939 /* ########################## FPU functions #################################### */ 01940 /** 01941 \ingroup CMSIS_Core_FunctionInterface 01942 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01943 \brief Function that provides FPU type. 01944 @{ 01945 */ 01946 01947 /** 01948 \brief get FPU type 01949 \details returns the FPU type 01950 \returns 01951 - \b 0: No FPU 01952 - \b 1: Single precision FPU 01953 - \b 2: Double + Single precision FPU 01954 */ 01955 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01956 { 01957 uint32_t mvfr0; 01958 01959 mvfr0 = FPU->MVFR0; 01960 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) 01961 { 01962 return 1U; /* Single precision FPU */ 01963 } 01964 else 01965 { 01966 return 0U; /* No FPU */ 01967 } 01968 } 01969 01970 01971 /*@} end of CMSIS_Core_FpuFunctions */ 01972 01973 01974 01975 /* ################################## SysTick function ############################################ */ 01976 /** 01977 \ingroup CMSIS_Core_FunctionInterface 01978 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01979 \brief Functions that configure the System. 01980 @{ 01981 */ 01982 01983 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01984 01985 /** 01986 \brief System Tick Configuration 01987 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01988 Counter is in free running mode to generate periodic interrupts. 01989 \param [in] ticks Number of ticks between two interrupts. 01990 \return 0 Function succeeded. 01991 \return 1 Function failed. 01992 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01993 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01994 must contain a vendor-specific implementation of this function. 01995 */ 01996 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01997 { 01998 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01999 { 02000 return (1UL); /* Reload value impossible */ 02001 } 02002 02003 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 02004 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 02005 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 02006 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 02007 SysTick_CTRL_TICKINT_Msk | 02008 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 02009 return (0UL); /* Function successful */ 02010 } 02011 02012 #endif 02013 02014 /*@} end of CMSIS_Core_SysTickFunctions */ 02015 02016 02017 02018 /* ##################################### Debug In/Output function ########################################### */ 02019 /** 02020 \ingroup CMSIS_Core_FunctionInterface 02021 \defgroup CMSIS_core_DebugFunctions ITM Functions 02022 \brief Functions that access the ITM debug interface. 02023 @{ 02024 */ 02025 02026 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 02027 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 02028 02029 02030 /** 02031 \brief ITM Send Character 02032 \details Transmits a character via the ITM channel 0, and 02033 \li Just returns when no debugger is connected that has booked the output. 02034 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 02035 \param [in] ch Character to transmit. 02036 \returns Character to transmit. 02037 */ 02038 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 02039 { 02040 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 02041 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 02042 { 02043 while (ITM->PORT[0U].u32 == 0UL) 02044 { 02045 __NOP(); 02046 } 02047 ITM->PORT[0U].u8 = (uint8_t)ch; 02048 } 02049 return (ch); 02050 } 02051 02052 02053 /** 02054 \brief ITM Receive Character 02055 \details Inputs a character via the external variable \ref ITM_RxBuffer. 02056 \return Received character. 02057 \return -1 No character pending. 02058 */ 02059 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 02060 { 02061 int32_t ch = -1; /* no character available */ 02062 02063 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 02064 { 02065 ch = ITM_RxBuffer; 02066 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 02067 } 02068 02069 return (ch); 02070 } 02071 02072 02073 /** 02074 \brief ITM Check Character 02075 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 02076 \return 0 No character available. 02077 \return 1 Character available. 02078 */ 02079 __STATIC_INLINE int32_t ITM_CheckChar (void) 02080 { 02081 02082 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 02083 { 02084 return (0); /* no character available */ 02085 } 02086 else 02087 { 02088 return (1); /* character available */ 02089 } 02090 } 02091 02092 /*@} end of CMSIS_core_DebugFunctions */ 02093 02094 02095 02096 02097 #ifdef __cplusplus 02098 } 02099 #endif 02100 02101 #endif /* __CORE_CM4_H_DEPENDANT */ 02102 02103 #endif /* __CMSIS_GENERIC */
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