Martin Kojtal
forked
Embed:
(wiki syntax)
Show/hide line numbers
core_cm3.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file core_cm3.h 00003 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 00004 * @version V5.0.2 00005 * @date 13. February 2017 00006 ******************************************************************************/ 00007 /* 00008 * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 00009 * 00010 * SPDX-License-Identifier: Apache-2.0 00011 * 00012 * Licensed under the Apache License, Version 2.0 (the License); you may 00013 * not use this file except in compliance with the License. 00014 * You may obtain a copy of the License at 00015 * 00016 * www.apache.org/licenses/LICENSE-2.0 00017 * 00018 * Unless required by applicable law or agreed to in writing, software 00019 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 00020 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00021 * See the License for the specific language governing permissions and 00022 * limitations under the License. 00023 */ 00024 00025 #if defined ( __ICCARM__ ) 00026 #pragma system_include /* treat file as system include file for MISRA check */ 00027 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00028 #pragma clang system_header /* treat file as system include file */ 00029 #endif 00030 00031 #ifndef __CORE_CM3_H_GENERIC 00032 #define __CORE_CM3_H_GENERIC 00033 00034 #include <stdint.h> 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /** 00041 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00042 CMSIS violates the following MISRA-C:2004 rules: 00043 00044 \li Required Rule 8.5, object/function definition in header file.<br> 00045 Function definitions in header files are used to allow 'inlining'. 00046 00047 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00048 Unions are used for effective representation of core registers. 00049 00050 \li Advisory Rule 19.7, Function-like macro defined.<br> 00051 Function-like macros are used to allow more efficient code. 00052 */ 00053 00054 00055 /******************************************************************************* 00056 * CMSIS definitions 00057 ******************************************************************************/ 00058 /** 00059 \ingroup Cortex_M3 00060 @{ 00061 */ 00062 00063 /* CMSIS CM3 definitions */ 00064 #define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ 00065 #define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ 00066 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ 00067 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00068 00069 #define __CORTEX_M (3U) /*!< Cortex-M Core */ 00070 00071 /** __FPU_USED indicates whether an FPU is used or not. 00072 This core does not support an FPU at all 00073 */ 00074 #define __FPU_USED 0U 00075 00076 #if defined ( __CC_ARM ) 00077 #if defined __TARGET_FPU_VFP 00078 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00079 #endif 00080 00081 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 00082 #if defined __ARM_PCS_VFP 00083 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00084 #endif 00085 00086 #elif defined ( __GNUC__ ) 00087 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00088 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00089 #endif 00090 00091 #elif defined ( __ICCARM__ ) 00092 #if defined __ARMVFP__ 00093 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00094 #endif 00095 00096 #elif defined ( __TI_ARM__ ) 00097 #if defined __TI_VFP_SUPPORT__ 00098 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00099 #endif 00100 00101 #elif defined ( __TASKING__ ) 00102 #if defined __FPU_VFP__ 00103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00104 #endif 00105 00106 #elif defined ( __CSMC__ ) 00107 #if ( __CSMC__ & 0x400U) 00108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00109 #endif 00110 00111 #endif 00112 00113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 00114 00115 00116 #ifdef __cplusplus 00117 } 00118 #endif 00119 00120 #endif /* __CORE_CM3_H_GENERIC */ 00121 00122 #ifndef __CMSIS_GENERIC 00123 00124 #ifndef __CORE_CM3_H_DEPENDANT 00125 #define __CORE_CM3_H_DEPENDANT 00126 00127 #ifdef __cplusplus 00128 extern "C" { 00129 #endif 00130 00131 /* check device defines and use defaults */ 00132 #if defined __CHECK_DEVICE_DEFINES 00133 #ifndef __CM3_REV 00134 #define __CM3_REV 0x0200U 00135 #warning "__CM3_REV not defined in device header file; using default!" 00136 #endif 00137 00138 #ifndef __MPU_PRESENT 00139 #define __MPU_PRESENT 0U 00140 #warning "__MPU_PRESENT not defined in device header file; using default!" 00141 #endif 00142 00143 #ifndef __NVIC_PRIO_BITS 00144 #define __NVIC_PRIO_BITS 3U 00145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00146 #endif 00147 00148 #ifndef __Vendor_SysTickConfig 00149 #define __Vendor_SysTickConfig 0U 00150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00151 #endif 00152 #endif 00153 00154 /* IO definitions (access restrictions to peripheral registers) */ 00155 /** 00156 \defgroup CMSIS_glob_defs CMSIS Global Defines 00157 00158 <strong>IO Type Qualifiers</strong> are used 00159 \li to specify the access to peripheral variables. 00160 \li for automatic generation of peripheral register debug information. 00161 */ 00162 #ifdef __cplusplus 00163 #define __I volatile /*!< Defines 'read only' permissions */ 00164 #else 00165 #define __I volatile const /*!< Defines 'read only' permissions */ 00166 #endif 00167 #define __O volatile /*!< Defines 'write only' permissions */ 00168 #define __IO volatile /*!< Defines 'read / write' permissions */ 00169 00170 /* following defines should be used for structure members */ 00171 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 00172 #define __OM volatile /*! Defines 'write only' structure member permissions */ 00173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 00174 00175 /*@} end of group Cortex_M3 */ 00176 00177 00178 00179 /******************************************************************************* 00180 * Register Abstraction 00181 Core Register contain: 00182 - Core Register 00183 - Core NVIC Register 00184 - Core SCB Register 00185 - Core SysTick Register 00186 - Core Debug Register 00187 - Core MPU Register 00188 ******************************************************************************/ 00189 /** 00190 \defgroup CMSIS_core_register Defines and Type Definitions 00191 \brief Type definitions and defines for Cortex-M processor based devices. 00192 */ 00193 00194 /** 00195 \ingroup CMSIS_core_register 00196 \defgroup CMSIS_CORE Status and Control Registers 00197 \brief Core Register type definitions. 00198 @{ 00199 */ 00200 00201 /** 00202 \brief Union type to access the Application Program Status Register (APSR). 00203 */ 00204 typedef union 00205 { 00206 struct 00207 { 00208 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00209 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00214 } b; /*!< Structure used for bit access */ 00215 uint32_t w; /*!< Type used for word access */ 00216 } APSR_Type; 00217 00218 /* APSR Register Definitions */ 00219 #define APSR_N_Pos 31U /*!< APSR: N Position */ 00220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ 00221 00222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */ 00223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ 00224 00225 #define APSR_C_Pos 29U /*!< APSR: C Position */ 00226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ 00227 00228 #define APSR_V_Pos 28U /*!< APSR: V Position */ 00229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ 00230 00231 #define APSR_Q_Pos 27U /*!< APSR: Q Position */ 00232 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ 00233 00234 00235 /** 00236 \brief Union type to access the Interrupt Program Status Register (IPSR). 00237 */ 00238 typedef union 00239 { 00240 struct 00241 { 00242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00244 } b; /*!< Structure used for bit access */ 00245 uint32_t w; /*!< Type used for word access */ 00246 } IPSR_Type; 00247 00248 /* IPSR Register Definitions */ 00249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ 00250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ 00251 00252 00253 /** 00254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00255 */ 00256 typedef union 00257 { 00258 struct 00259 { 00260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00261 uint32_t _reserved0:1; /*!< bit: 9 Reserved */ 00262 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ 00263 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ 00264 uint32_t T:1; /*!< bit: 24 Thumb bit */ 00265 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ 00266 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00267 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00268 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00269 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00270 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00271 } b; /*!< Structure used for bit access */ 00272 uint32_t w; /*!< Type used for word access */ 00273 } xPSR_Type; 00274 00275 /* xPSR Register Definitions */ 00276 #define xPSR_N_Pos 31U /*!< xPSR: N Position */ 00277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ 00278 00279 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ 00280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ 00281 00282 #define xPSR_C_Pos 29U /*!< xPSR: C Position */ 00283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ 00284 00285 #define xPSR_V_Pos 28U /*!< xPSR: V Position */ 00286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ 00287 00288 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ 00289 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ 00290 00291 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ 00292 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ 00293 00294 #define xPSR_T_Pos 24U /*!< xPSR: T Position */ 00295 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ 00296 00297 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ 00298 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ 00299 00300 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ 00301 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ 00302 00303 00304 /** 00305 \brief Union type to access the Control Registers (CONTROL). 00306 */ 00307 typedef union 00308 { 00309 struct 00310 { 00311 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00312 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00313 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 00314 } b; /*!< Structure used for bit access */ 00315 uint32_t w; /*!< Type used for word access */ 00316 } CONTROL_Type; 00317 00318 /* CONTROL Register Definitions */ 00319 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ 00320 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ 00321 00322 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ 00323 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ 00324 00325 /*@} end of group CMSIS_CORE */ 00326 00327 00328 /** 00329 \ingroup CMSIS_core_register 00330 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00331 \brief Type definitions for the NVIC Registers 00332 @{ 00333 */ 00334 00335 /** 00336 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00337 */ 00338 typedef struct 00339 { 00340 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00341 uint32_t RESERVED0[24U]; 00342 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00343 uint32_t RSERVED1[24U]; 00344 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00345 uint32_t RESERVED2[24U]; 00346 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00347 uint32_t RESERVED3[24U]; 00348 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 00349 uint32_t RESERVED4[56U]; 00350 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 00351 uint32_t RESERVED5[644U]; 00352 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 00353 } NVIC_Type; 00354 00355 /* Software Triggered Interrupt Register Definitions */ 00356 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ 00357 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ 00358 00359 /*@} end of group CMSIS_NVIC */ 00360 00361 00362 /** 00363 \ingroup CMSIS_core_register 00364 \defgroup CMSIS_SCB System Control Block (SCB) 00365 \brief Type definitions for the System Control Block Registers 00366 @{ 00367 */ 00368 00369 /** 00370 \brief Structure type to access the System Control Block (SCB). 00371 */ 00372 typedef struct 00373 { 00374 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00375 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00376 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00377 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00378 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00379 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00380 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 00381 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00382 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 00383 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 00384 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 00385 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 00386 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 00387 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 00388 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 00389 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 00390 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 00391 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 00392 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 00393 uint32_t RESERVED0[5U]; 00394 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 00395 } SCB_Type; 00396 00397 /* SCB CPUID Register Definitions */ 00398 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ 00399 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00400 00401 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ 00402 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00403 00404 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ 00405 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00406 00407 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ 00408 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00409 00410 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ 00411 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ 00412 00413 /* SCB Interrupt Control State Register Definitions */ 00414 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ 00415 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00416 00417 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ 00418 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00419 00420 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ 00421 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00422 00423 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ 00424 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00425 00426 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ 00427 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00428 00429 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ 00430 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00431 00432 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ 00433 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00434 00435 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ 00436 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00437 00438 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ 00439 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 00440 00441 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ 00442 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ 00443 00444 /* SCB Vector Table Offset Register Definitions */ 00445 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ 00446 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ 00447 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ 00448 00449 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00450 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00451 #else 00452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ 00453 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00454 #endif 00455 00456 /* SCB Application Interrupt and Reset Control Register Definitions */ 00457 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ 00458 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00459 00460 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ 00461 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00462 00463 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ 00464 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00465 00466 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ 00467 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 00468 00469 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ 00470 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00471 00472 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00473 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00474 00475 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ 00476 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ 00477 00478 /* SCB System Control Register Definitions */ 00479 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ 00480 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00481 00482 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ 00483 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00484 00485 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ 00486 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00487 00488 /* SCB Configuration Control Register Definitions */ 00489 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ 00490 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00491 00492 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ 00493 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 00494 00495 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ 00496 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 00497 00498 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ 00499 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00500 00501 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ 00502 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 00503 00504 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ 00505 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ 00506 00507 /* SCB System Handler Control and State Register Definitions */ 00508 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ 00509 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 00510 00511 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ 00512 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 00513 00514 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ 00515 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 00516 00517 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ 00518 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00519 00520 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ 00521 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 00522 00523 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ 00524 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 00525 00526 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ 00527 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 00528 00529 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ 00530 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 00531 00532 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ 00533 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 00534 00535 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ 00536 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 00537 00538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ 00539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 00540 00541 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ 00542 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 00543 00544 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ 00545 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 00546 00547 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ 00548 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ 00549 00550 /* SCB Configurable Fault Status Register Definitions */ 00551 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ 00552 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 00553 00554 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ 00555 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 00556 00557 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 00558 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 00559 00560 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ 00561 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ 00562 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ 00563 00564 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ 00565 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ 00566 00567 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ 00568 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ 00569 00570 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ 00571 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ 00572 00573 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ 00574 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ 00575 00576 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ 00577 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ 00578 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ 00579 00580 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ 00581 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ 00582 00583 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ 00584 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ 00585 00586 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ 00587 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ 00588 00589 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ 00590 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ 00591 00592 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ 00593 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ 00594 00595 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ 00596 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ 00597 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ 00598 00599 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ 00600 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ 00601 00602 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ 00603 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ 00604 00605 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ 00606 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ 00607 00608 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ 00609 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ 00610 00611 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ 00612 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ 00613 00614 /* SCB Hard Fault Status Register Definitions */ 00615 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ 00616 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 00617 00618 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ 00619 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 00620 00621 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ 00622 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 00623 00624 /* SCB Debug Fault Status Register Definitions */ 00625 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 00626 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 00627 00628 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 00629 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 00630 00631 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 00632 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 00633 00634 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 00635 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 00636 00637 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ 00638 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ 00639 00640 /*@} end of group CMSIS_SCB */ 00641 00642 00643 /** 00644 \ingroup CMSIS_core_register 00645 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00646 \brief Type definitions for the System Control and ID Register not in the SCB 00647 @{ 00648 */ 00649 00650 /** 00651 \brief Structure type to access the System Control and ID Register not in the SCB. 00652 */ 00653 typedef struct 00654 { 00655 uint32_t RESERVED0[1U]; 00656 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 00657 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U) 00658 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00659 #else 00660 uint32_t RESERVED1[1U]; 00661 #endif 00662 } SCnSCB_Type; 00663 00664 /* Interrupt Controller Type Register Definitions */ 00665 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ 00666 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ 00667 00668 /* Auxiliary Control Register Definitions */ 00669 00670 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ 00671 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 00672 00673 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ 00674 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 00675 00676 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ 00677 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ 00678 00679 /*@} end of group CMSIS_SCnotSCB */ 00680 00681 00682 /** 00683 \ingroup CMSIS_core_register 00684 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00685 \brief Type definitions for the System Timer Registers. 00686 @{ 00687 */ 00688 00689 /** 00690 \brief Structure type to access the System Timer (SysTick). 00691 */ 00692 typedef struct 00693 { 00694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00695 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00696 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00698 } SysTick_Type; 00699 00700 /* SysTick Control / Status Register Definitions */ 00701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ 00702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00703 00704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ 00705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00706 00707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ 00708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00709 00710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ 00711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ 00712 00713 /* SysTick Reload Register Definitions */ 00714 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ 00715 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ 00716 00717 /* SysTick Current Register Definitions */ 00718 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ 00719 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ 00720 00721 /* SysTick Calibration Register Definitions */ 00722 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ 00723 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00724 00725 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ 00726 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00727 00728 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ 00729 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ 00730 00731 /*@} end of group CMSIS_SysTick */ 00732 00733 00734 /** 00735 \ingroup CMSIS_core_register 00736 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) 00737 \brief Type definitions for the Instrumentation Trace Macrocell (ITM) 00738 @{ 00739 */ 00740 00741 /** 00742 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 00743 */ 00744 typedef struct 00745 { 00746 __OM union 00747 { 00748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 00749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 00750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 00751 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 00752 uint32_t RESERVED0[864U]; 00753 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 00754 uint32_t RESERVED1[15U]; 00755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 00756 uint32_t RESERVED2[15U]; 00757 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 00758 uint32_t RESERVED3[29U]; 00759 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ 00760 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ 00761 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ 00762 uint32_t RESERVED4[43U]; 00763 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ 00764 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ 00765 uint32_t RESERVED5[6U]; 00766 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ 00767 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ 00768 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ 00769 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ 00770 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ 00771 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ 00772 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ 00773 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ 00774 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ 00775 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ 00776 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ 00777 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ 00778 } ITM_Type; 00779 00780 /* ITM Trace Privilege Register Definitions */ 00781 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 00782 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ 00783 00784 /* ITM Trace Control Register Definitions */ 00785 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ 00786 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 00787 00788 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ 00789 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 00790 00791 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ 00792 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 00793 00794 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ 00795 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 00796 00797 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ 00798 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 00799 00800 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ 00801 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ 00802 00803 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ 00804 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 00805 00806 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ 00807 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 00808 00809 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ 00810 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ 00811 00812 /* ITM Integration Write Register Definitions */ 00813 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ 00814 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ 00815 00816 /* ITM Integration Read Register Definitions */ 00817 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ 00818 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ 00819 00820 /* ITM Integration Mode Control Register Definitions */ 00821 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ 00822 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ 00823 00824 /* ITM Lock Status Register Definitions */ 00825 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ 00826 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ 00827 00828 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ 00829 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ 00830 00831 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ 00832 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ 00833 00834 /*@}*/ /* end of group CMSIS_ITM */ 00835 00836 00837 /** 00838 \ingroup CMSIS_core_register 00839 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) 00840 \brief Type definitions for the Data Watchpoint and Trace (DWT) 00841 @{ 00842 */ 00843 00844 /** 00845 \brief Structure type to access the Data Watchpoint and Trace Register (DWT). 00846 */ 00847 typedef struct 00848 { 00849 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ 00850 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ 00851 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ 00852 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ 00853 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ 00854 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ 00855 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ 00856 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 00857 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ 00858 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ 00859 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ 00860 uint32_t RESERVED0[1U]; 00861 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ 00862 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ 00863 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ 00864 uint32_t RESERVED1[1U]; 00865 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ 00866 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ 00867 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ 00868 uint32_t RESERVED2[1U]; 00869 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ 00870 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ 00871 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ 00872 } DWT_Type; 00873 00874 /* DWT Control Register Definitions */ 00875 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ 00876 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ 00877 00878 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ 00879 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ 00880 00881 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ 00882 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ 00883 00884 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ 00885 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ 00886 00887 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ 00888 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ 00889 00890 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ 00891 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ 00892 00893 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ 00894 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ 00895 00896 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ 00897 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ 00898 00899 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ 00900 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ 00901 00902 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ 00903 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ 00904 00905 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ 00906 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ 00907 00908 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ 00909 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ 00910 00911 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ 00912 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ 00913 00914 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ 00915 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ 00916 00917 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ 00918 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ 00919 00920 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ 00921 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ 00922 00923 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ 00924 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ 00925 00926 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ 00927 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ 00928 00929 /* DWT CPI Count Register Definitions */ 00930 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ 00931 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ 00932 00933 /* DWT Exception Overhead Count Register Definitions */ 00934 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ 00935 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ 00936 00937 /* DWT Sleep Count Register Definitions */ 00938 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ 00939 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ 00940 00941 /* DWT LSU Count Register Definitions */ 00942 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ 00943 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ 00944 00945 /* DWT Folded-instruction Count Register Definitions */ 00946 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ 00947 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ 00948 00949 /* DWT Comparator Mask Register Definitions */ 00950 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ 00951 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ 00952 00953 /* DWT Comparator Function Register Definitions */ 00954 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ 00955 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ 00956 00957 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ 00958 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ 00959 00960 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ 00961 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ 00962 00963 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ 00964 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ 00965 00966 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ 00967 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ 00968 00969 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ 00970 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ 00971 00972 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ 00973 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ 00974 00975 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ 00976 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ 00977 00978 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ 00979 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ 00980 00981 /*@}*/ /* end of group CMSIS_DWT */ 00982 00983 00984 /** 00985 \ingroup CMSIS_core_register 00986 \defgroup CMSIS_TPI Trace Port Interface (TPI) 00987 \brief Type definitions for the Trace Port Interface (TPI) 00988 @{ 00989 */ 00990 00991 /** 00992 \brief Structure type to access the Trace Port Interface Register (TPI). 00993 */ 00994 typedef struct 00995 { 00996 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 00997 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ 00998 uint32_t RESERVED0[2U]; 00999 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ 01000 uint32_t RESERVED1[55U]; 01001 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ 01002 uint32_t RESERVED2[131U]; 01003 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 01004 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ 01005 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ 01006 uint32_t RESERVED3[759U]; 01007 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ 01008 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ 01009 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ 01010 uint32_t RESERVED4[1U]; 01011 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ 01012 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ 01013 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ 01014 uint32_t RESERVED5[39U]; 01015 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ 01016 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ 01017 uint32_t RESERVED7[8U]; 01018 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ 01019 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ 01020 } TPI_Type; 01021 01022 /* TPI Asynchronous Clock Prescaler Register Definitions */ 01023 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ 01024 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ 01025 01026 /* TPI Selected Pin Protocol Register Definitions */ 01027 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ 01028 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ 01029 01030 /* TPI Formatter and Flush Status Register Definitions */ 01031 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ 01032 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ 01033 01034 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ 01035 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ 01036 01037 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ 01038 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ 01039 01040 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ 01041 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ 01042 01043 /* TPI Formatter and Flush Control Register Definitions */ 01044 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ 01045 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ 01046 01047 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ 01048 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ 01049 01050 /* TPI TRIGGER Register Definitions */ 01051 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ 01052 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ 01053 01054 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 01055 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ 01056 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ 01057 01058 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ 01059 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ 01060 01061 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ 01062 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ 01063 01064 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ 01065 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ 01066 01067 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ 01068 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ 01069 01070 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ 01071 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ 01072 01073 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ 01074 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ 01075 01076 /* TPI ITATBCTR2 Register Definitions */ 01077 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ 01078 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ 01079 01080 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 01081 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ 01082 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ 01083 01084 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ 01085 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ 01086 01087 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ 01088 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ 01089 01090 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ 01091 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ 01092 01093 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ 01094 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ 01095 01096 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ 01097 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ 01098 01099 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ 01100 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ 01101 01102 /* TPI ITATBCTR0 Register Definitions */ 01103 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ 01104 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ 01105 01106 /* TPI Integration Mode Control Register Definitions */ 01107 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ 01108 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ 01109 01110 /* TPI DEVID Register Definitions */ 01111 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ 01112 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ 01113 01114 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ 01115 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ 01116 01117 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ 01118 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ 01119 01120 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ 01121 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ 01122 01123 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ 01124 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ 01125 01126 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ 01127 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ 01128 01129 /* TPI DEVTYPE Register Definitions */ 01130 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ 01131 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ 01132 01133 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ 01134 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ 01135 01136 /*@}*/ /* end of group CMSIS_TPI */ 01137 01138 01139 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01140 /** 01141 \ingroup CMSIS_core_register 01142 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 01143 \brief Type definitions for the Memory Protection Unit (MPU) 01144 @{ 01145 */ 01146 01147 /** 01148 \brief Structure type to access the Memory Protection Unit (MPU). 01149 */ 01150 typedef struct 01151 { 01152 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 01153 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 01154 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 01155 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 01156 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 01157 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 01158 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 01159 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 01160 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 01161 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 01162 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 01163 } MPU_Type; 01164 01165 /* MPU Type Register Definitions */ 01166 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ 01167 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 01168 01169 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ 01170 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 01171 01172 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ 01173 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ 01174 01175 /* MPU Control Register Definitions */ 01176 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ 01177 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 01178 01179 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ 01180 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 01181 01182 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ 01183 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ 01184 01185 /* MPU Region Number Register Definitions */ 01186 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ 01187 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ 01188 01189 /* MPU Region Base Address Register Definitions */ 01190 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 01191 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 01192 01193 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 01194 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 01195 01196 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 01197 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ 01198 01199 /* MPU Region Attribute and Size Register Definitions */ 01200 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ 01201 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 01202 01203 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ 01204 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 01205 01206 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ 01207 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 01208 01209 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ 01210 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 01211 01212 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ 01213 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 01214 01215 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ 01216 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 01217 01218 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ 01219 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 01220 01221 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ 01222 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 01223 01224 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ 01225 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 01226 01227 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ 01228 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ 01229 01230 /*@} end of group CMSIS_MPU */ 01231 #endif 01232 01233 01234 /** 01235 \ingroup CMSIS_core_register 01236 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 01237 \brief Type definitions for the Core Debug Registers 01238 @{ 01239 */ 01240 01241 /** 01242 \brief Structure type to access the Core Debug Register (CoreDebug). 01243 */ 01244 typedef struct 01245 { 01246 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 01247 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 01248 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 01249 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 01250 } CoreDebug_Type; 01251 01252 /* Debug Halting Control and Status Register Definitions */ 01253 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ 01254 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 01255 01256 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ 01257 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 01258 01259 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 01260 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 01261 01262 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ 01263 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 01264 01265 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ 01266 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 01267 01268 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ 01269 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 01270 01271 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ 01272 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 01273 01274 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 01275 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 01276 01277 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ 01278 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 01279 01280 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ 01281 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 01282 01283 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ 01284 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 01285 01286 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 01287 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 01288 01289 /* Debug Core Register Selector Register Definitions */ 01290 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ 01291 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 01292 01293 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ 01294 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ 01295 01296 /* Debug Exception and Monitor Control Register Definitions */ 01297 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ 01298 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 01299 01300 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ 01301 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 01302 01303 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ 01304 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 01305 01306 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ 01307 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 01308 01309 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ 01310 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 01311 01312 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ 01313 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 01314 01315 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ 01316 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 01317 01318 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ 01319 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 01320 01321 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ 01322 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 01323 01324 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ 01325 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 01326 01327 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 01328 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 01329 01330 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ 01331 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 01332 01333 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ 01334 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 01335 01336 /*@} end of group CMSIS_CoreDebug */ 01337 01338 01339 /** 01340 \ingroup CMSIS_core_register 01341 \defgroup CMSIS_core_bitfield Core register bit field macros 01342 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 01343 @{ 01344 */ 01345 01346 /** 01347 \brief Mask and shift a bit field value for use in a register bit range. 01348 \param[in] field Name of the register bit field. 01349 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 01350 \return Masked and shifted value. 01351 */ 01352 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 01353 01354 /** 01355 \brief Mask and shift a register value to extract a bit filed value. 01356 \param[in] field Name of the register bit field. 01357 \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 01358 \return Masked and shifted bit field value. 01359 */ 01360 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 01361 01362 /*@} end of group CMSIS_core_bitfield */ 01363 01364 01365 /** 01366 \ingroup CMSIS_core_register 01367 \defgroup CMSIS_core_base Core Definitions 01368 \brief Definitions for base addresses, unions, and structures. 01369 @{ 01370 */ 01371 01372 /* Memory mapping of Core Hardware */ 01373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 01374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 01375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ 01376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ 01377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 01378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 01379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 01380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 01381 01382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 01383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 01384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 01385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 01386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 01387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ 01388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ 01389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 01390 01391 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) 01392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 01393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 01394 #endif 01395 01396 /*@} */ 01397 01398 01399 01400 /******************************************************************************* 01401 * Hardware Abstraction Layer 01402 Core Function Interface contains: 01403 - Core NVIC Functions 01404 - Core SysTick Functions 01405 - Core Debug Functions 01406 - Core Register Access Functions 01407 ******************************************************************************/ 01408 /** 01409 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 01410 */ 01411 01412 01413 01414 /* ########################## NVIC functions #################################### */ 01415 /** 01416 \ingroup CMSIS_Core_FunctionInterface 01417 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 01418 \brief Functions that manage interrupts and exceptions via the NVIC. 01419 @{ 01420 */ 01421 01422 #ifdef CMSIS_NVIC_VIRTUAL 01423 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 01424 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 01425 #endif 01426 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 01427 #else 01428 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 01429 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 01430 #define NVIC_EnableIRQ __NVIC_EnableIRQ 01431 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 01432 #define NVIC_DisableIRQ __NVIC_DisableIRQ 01433 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 01434 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 01435 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 01436 #define NVIC_GetActive __NVIC_GetActive 01437 #define NVIC_SetPriority __NVIC_SetPriority 01438 #define NVIC_GetPriority __NVIC_GetPriority 01439 #define NVIC_SystemReset __NVIC_SystemReset 01440 #endif /* CMSIS_NVIC_VIRTUAL */ 01441 01442 #ifdef CMSIS_VECTAB_VIRTUAL 01443 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01444 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 01445 #endif 01446 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 01447 #else 01448 #define NVIC_SetVector __NVIC_SetVector 01449 #define NVIC_GetVector __NVIC_GetVector 01450 #endif /* (CMSIS_VECTAB_VIRTUAL) */ 01451 01452 #define NVIC_USER_IRQ_OFFSET 16 01453 01454 01455 01456 /** 01457 \brief Set Priority Grouping 01458 \details Sets the priority grouping field using the required unlock sequence. 01459 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 01460 Only values from 0..7 are used. 01461 In case of a conflict between priority grouping and available 01462 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01463 \param [in] PriorityGroup Priority grouping field. 01464 */ 01465 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01466 { 01467 uint32_t reg_value; 01468 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01469 01470 reg_value = SCB->AIRCR; /* read old register configuration */ 01471 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 01472 reg_value = (reg_value | 01473 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01474 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 01475 SCB->AIRCR = reg_value; 01476 } 01477 01478 01479 /** 01480 \brief Get Priority Grouping 01481 \details Reads the priority grouping field from the NVIC Interrupt Controller. 01482 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). 01483 */ 01484 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) 01485 { 01486 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 01487 } 01488 01489 01490 /** 01491 \brief Enable Interrupt 01492 \details Enables a device specific interrupt in the NVIC interrupt controller. 01493 \param [in] IRQn Device specific interrupt number. 01494 \note IRQn must not be negative. 01495 */ 01496 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 01497 { 01498 if ((int32_t)(IRQn) >= 0) 01499 { 01500 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01501 } 01502 } 01503 01504 01505 /** 01506 \brief Get Interrupt Enable status 01507 \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 01508 \param [in] IRQn Device specific interrupt number. 01509 \return 0 Interrupt is not enabled. 01510 \return 1 Interrupt is enabled. 01511 \note IRQn must not be negative. 01512 */ 01513 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 01514 { 01515 if ((int32_t)(IRQn) >= 0) 01516 { 01517 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01518 } 01519 else 01520 { 01521 return(0U); 01522 } 01523 } 01524 01525 01526 /** 01527 \brief Disable Interrupt 01528 \details Disables a device specific interrupt in the NVIC interrupt controller. 01529 \param [in] IRQn Device specific interrupt number. 01530 \note IRQn must not be negative. 01531 */ 01532 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 01533 { 01534 if ((int32_t)(IRQn) >= 0) 01535 { 01536 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01537 __DSB(); 01538 __ISB(); 01539 } 01540 } 01541 01542 01543 /** 01544 \brief Get Pending Interrupt 01545 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. 01546 \param [in] IRQn Device specific interrupt number. 01547 \return 0 Interrupt status is not pending. 01548 \return 1 Interrupt status is pending. 01549 \note IRQn must not be negative. 01550 */ 01551 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) 01552 { 01553 if ((int32_t)(IRQn) >= 0) 01554 { 01555 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01556 } 01557 else 01558 { 01559 return(0U); 01560 } 01561 } 01562 01563 01564 /** 01565 \brief Set Pending Interrupt 01566 \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 01567 \param [in] IRQn Device specific interrupt number. 01568 \note IRQn must not be negative. 01569 */ 01570 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 01571 { 01572 if ((int32_t)(IRQn) >= 0) 01573 { 01574 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01575 } 01576 } 01577 01578 01579 /** 01580 \brief Clear Pending Interrupt 01581 \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 01582 \param [in] IRQn Device specific interrupt number. 01583 \note IRQn must not be negative. 01584 */ 01585 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01586 { 01587 if ((int32_t)(IRQn) >= 0) 01588 { 01589 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); 01590 } 01591 } 01592 01593 01594 /** 01595 \brief Get Active Interrupt 01596 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. 01597 \param [in] IRQn Device specific interrupt number. 01598 \return 0 Interrupt status is not active. 01599 \return 1 Interrupt status is active. 01600 \note IRQn must not be negative. 01601 */ 01602 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) 01603 { 01604 if ((int32_t)(IRQn) >= 0) 01605 { 01606 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); 01607 } 01608 else 01609 { 01610 return(0U); 01611 } 01612 } 01613 01614 01615 /** 01616 \brief Set Interrupt Priority 01617 \details Sets the priority of a device specific interrupt or a processor exception. 01618 The interrupt number can be positive to specify a device specific interrupt, 01619 or negative to specify a processor exception. 01620 \param [in] IRQn Interrupt number. 01621 \param [in] priority Priority to set. 01622 \note The priority cannot be set for every processor exception. 01623 */ 01624 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01625 { 01626 if ((int32_t)(IRQn) >= 0) 01627 { 01628 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01629 } 01630 else 01631 { 01632 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 01633 } 01634 } 01635 01636 01637 /** 01638 \brief Get Interrupt Priority 01639 \details Reads the priority of a device specific interrupt or a processor exception. 01640 The interrupt number can be positive to specify a device specific interrupt, 01641 or negative to specify a processor exception. 01642 \param [in] IRQn Interrupt number. 01643 \return Interrupt Priority. 01644 Value is aligned automatically to the implemented priority bits of the microcontroller. 01645 */ 01646 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 01647 { 01648 01649 if ((int32_t)(IRQn) >= 0) 01650 { 01651 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); 01652 } 01653 else 01654 { 01655 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); 01656 } 01657 } 01658 01659 01660 /** 01661 \brief Encode Priority 01662 \details Encodes the priority for an interrupt with the given priority group, 01663 preemptive priority value, and subpriority value. 01664 In case of a conflict between priority grouping and available 01665 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 01666 \param [in] PriorityGroup Used priority group. 01667 \param [in] PreemptPriority Preemptive priority value (starting from 0). 01668 \param [in] SubPriority Subpriority value (starting from 0). 01669 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). 01670 */ 01671 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01672 { 01673 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01674 uint32_t PreemptPriorityBits; 01675 uint32_t SubPriorityBits; 01676 01677 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01678 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01679 01680 return ( 01681 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 01682 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 01683 ); 01684 } 01685 01686 01687 /** 01688 \brief Decode Priority 01689 \details Decodes an interrupt priority value with a given priority group to 01690 preemptive priority value and subpriority value. 01691 In case of a conflict between priority grouping and available 01692 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 01693 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). 01694 \param [in] PriorityGroup Used priority group. 01695 \param [out] pPreemptPriority Preemptive priority value (starting from 0). 01696 \param [out] pSubPriority Subpriority value (starting from 0). 01697 */ 01698 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) 01699 { 01700 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 01701 uint32_t PreemptPriorityBits; 01702 uint32_t SubPriorityBits; 01703 01704 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 01705 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 01706 01707 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); 01708 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); 01709 } 01710 01711 01712 /** 01713 \brief Set Interrupt Vector 01714 \details Sets an interrupt vector in SRAM based interrupt vector table. 01715 The interrupt number can be positive to specify a device specific interrupt, 01716 or negative to specify a processor exception. 01717 VTOR must been relocated to SRAM before. 01718 \param [in] IRQn Interrupt number 01719 \param [in] vector Address of interrupt handler function 01720 */ 01721 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 01722 { 01723 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01724 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 01725 } 01726 01727 01728 /** 01729 \brief Get Interrupt Vector 01730 \details Reads an interrupt vector from interrupt vector table. 01731 The interrupt number can be positive to specify a device specific interrupt, 01732 or negative to specify a processor exception. 01733 \param [in] IRQn Interrupt number. 01734 \return Address of interrupt handler function 01735 */ 01736 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 01737 { 01738 uint32_t *vectors = (uint32_t *)SCB->VTOR; 01739 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 01740 } 01741 01742 01743 /** 01744 \brief System Reset 01745 \details Initiates a system reset request to reset the MCU. 01746 */ 01747 __STATIC_INLINE void __NVIC_SystemReset(void) 01748 { 01749 __DSB(); /* Ensure all outstanding memory accesses included 01750 buffered write are completed before reset */ 01751 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 01752 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01753 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ 01754 __DSB(); /* Ensure completion of memory access */ 01755 01756 for(;;) /* wait until reset */ 01757 { 01758 __NOP(); 01759 } 01760 } 01761 01762 /*@} end of CMSIS_Core_NVICFunctions */ 01763 01764 01765 /* ########################## FPU functions #################################### */ 01766 /** 01767 \ingroup CMSIS_Core_FunctionInterface 01768 \defgroup CMSIS_Core_FpuFunctions FPU Functions 01769 \brief Function that provides FPU type. 01770 @{ 01771 */ 01772 01773 /** 01774 \brief get FPU type 01775 \details returns the FPU type 01776 \returns 01777 - \b 0: No FPU 01778 - \b 1: Single precision FPU 01779 - \b 2: Double + Single precision FPU 01780 */ 01781 __STATIC_INLINE uint32_t SCB_GetFPUType(void) 01782 { 01783 return 0U; /* No FPU */ 01784 } 01785 01786 01787 /*@} end of CMSIS_Core_FpuFunctions */ 01788 01789 01790 01791 /* ################################## SysTick function ############################################ */ 01792 /** 01793 \ingroup CMSIS_Core_FunctionInterface 01794 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 01795 \brief Functions that configure the System. 01796 @{ 01797 */ 01798 01799 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 01800 01801 /** 01802 \brief System Tick Configuration 01803 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 01804 Counter is in free running mode to generate periodic interrupts. 01805 \param [in] ticks Number of ticks between two interrupts. 01806 \return 0 Function succeeded. 01807 \return 1 Function failed. 01808 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 01809 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 01810 must contain a vendor-specific implementation of this function. 01811 */ 01812 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01813 { 01814 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 01815 { 01816 return (1UL); /* Reload value impossible */ 01817 } 01818 01819 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 01820 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 01821 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 01822 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01823 SysTick_CTRL_TICKINT_Msk | 01824 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01825 return (0UL); /* Function successful */ 01826 } 01827 01828 #endif 01829 01830 /*@} end of CMSIS_Core_SysTickFunctions */ 01831 01832 01833 01834 /* ##################################### Debug In/Output function ########################################### */ 01835 /** 01836 \ingroup CMSIS_Core_FunctionInterface 01837 \defgroup CMSIS_core_DebugFunctions ITM Functions 01838 \brief Functions that access the ITM debug interface. 01839 @{ 01840 */ 01841 01842 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ 01843 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ 01844 01845 01846 /** 01847 \brief ITM Send Character 01848 \details Transmits a character via the ITM channel 0, and 01849 \li Just returns when no debugger is connected that has booked the output. 01850 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. 01851 \param [in] ch Character to transmit. 01852 \returns Character to transmit. 01853 */ 01854 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01855 { 01856 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ 01857 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ 01858 { 01859 while (ITM->PORT[0U].u32 == 0UL) 01860 { 01861 __NOP(); 01862 } 01863 ITM->PORT[0U].u8 = (uint8_t)ch; 01864 } 01865 return (ch); 01866 } 01867 01868 01869 /** 01870 \brief ITM Receive Character 01871 \details Inputs a character via the external variable \ref ITM_RxBuffer. 01872 \return Received character. 01873 \return -1 No character pending. 01874 */ 01875 __STATIC_INLINE int32_t ITM_ReceiveChar (void) 01876 { 01877 int32_t ch = -1; /* no character available */ 01878 01879 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) 01880 { 01881 ch = ITM_RxBuffer; 01882 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01883 } 01884 01885 return (ch); 01886 } 01887 01888 01889 /** 01890 \brief ITM Check Character 01891 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. 01892 \return 0 No character available. 01893 \return 1 Character available. 01894 */ 01895 __STATIC_INLINE int32_t ITM_CheckChar (void) 01896 { 01897 01898 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) 01899 { 01900 return (0); /* no character available */ 01901 } 01902 else 01903 { 01904 return (1); /* character available */ 01905 } 01906 } 01907 01908 /*@} end of CMSIS_core_DebugFunctions */ 01909 01910 01911 01912 01913 #ifdef __cplusplus 01914 } 01915 #endif 01916 01917 #endif /* __CORE_CM3_H_DEPENDANT */ 01918 01919 #endif /* __CMSIS_GENERIC */
Generated on Tue Jul 12 2022 16:02:32 by
1.7.2