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TARGET_NUCLEO_F103RB/stm32f10x_spi.h@102:d2e8fb00ad18, 2015-06-22 (annotated)

Committer:
JulienKern
Date:
Mon Jun 22 09:10:29 2015 +0000
Revision:
102:d2e8fb00ad18
Parent:
77:869cf507173a 
RPM + torque ok

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bogdanm 73:1efda918f0ba 1 /**
bogdanm 73:1efda918f0ba 2 ******************************************************************************
bogdanm 73:1efda918f0ba 3 * @file stm32f10x_spi.h
bogdanm 73:1efda918f0ba 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V3.6.1
emilmont 77:869cf507173a 6 * @date 05-March-2012
bogdanm 73:1efda918f0ba 7 * @brief This file contains all the functions prototypes for the SPI firmware
bogdanm 73:1efda918f0ba 8 * library.
bogdanm 76:824293ae5e43 9 *******************************************************************************
bogdanm 76:824293ae5e43 10 * Copyright (c) 2014, STMicroelectronics
bogdanm 76:824293ae5e43 11 * All rights reserved.
bogdanm 76:824293ae5e43 12 *
bogdanm 76:824293ae5e43 13 * Redistribution and use in source and binary forms, with or without
bogdanm 76:824293ae5e43 14 * modification, are permitted provided that the following conditions are met:
bogdanm 76:824293ae5e43 15 *
bogdanm 76:824293ae5e43 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 76:824293ae5e43 17 * this list of conditions and the following disclaimer.
bogdanm 76:824293ae5e43 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 76:824293ae5e43 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 76:824293ae5e43 20 * and/or other materials provided with the distribution.
bogdanm 76:824293ae5e43 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 76:824293ae5e43 22 * may be used to endorse or promote products derived from this software
bogdanm 76:824293ae5e43 23 * without specific prior written permission.
bogdanm 76:824293ae5e43 24 *
bogdanm 76:824293ae5e43 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 76:824293ae5e43 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 76:824293ae5e43 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 76:824293ae5e43 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 76:824293ae5e43 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 76:824293ae5e43 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 76:824293ae5e43 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 76:824293ae5e43 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 76:824293ae5e43 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 76:824293ae5e43 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 76:824293ae5e43 35 *******************************************************************************
bogdanm 76:824293ae5e43 36 */
bogdanm 73:1efda918f0ba 37
bogdanm 73:1efda918f0ba 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 73:1efda918f0ba 39 #ifndef __STM32F10x_SPI_H
bogdanm 73:1efda918f0ba 40 #define __STM32F10x_SPI_H
bogdanm 73:1efda918f0ba 41
bogdanm 73:1efda918f0ba 42 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 43 extern "C" {
bogdanm 73:1efda918f0ba 44 #endif
bogdanm 73:1efda918f0ba 45
bogdanm 73:1efda918f0ba 46 /* Includes ------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 47 #include "stm32f10x.h"
bogdanm 73:1efda918f0ba 48
bogdanm 73:1efda918f0ba 49 /** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm 73:1efda918f0ba 50 * @{
bogdanm 73:1efda918f0ba 51 */
bogdanm 73:1efda918f0ba 52
bogdanm 73:1efda918f0ba 53 /** @addtogroup SPI
bogdanm 73:1efda918f0ba 54 * @{
bogdanm 73:1efda918f0ba 55 */
bogdanm 73:1efda918f0ba 56
bogdanm 73:1efda918f0ba 57 /** @defgroup SPI_Exported_Types
bogdanm 73:1efda918f0ba 58 * @{
bogdanm 73:1efda918f0ba 59 */
bogdanm 73:1efda918f0ba 60
bogdanm 73:1efda918f0ba 61 /**
bogdanm 73:1efda918f0ba 62 * @brief SPI Init structure definition
bogdanm 73:1efda918f0ba 63 */
bogdanm 73:1efda918f0ba 64
bogdanm 73:1efda918f0ba 65 typedef struct
bogdanm 73:1efda918f0ba 66 {
bogdanm 73:1efda918f0ba 67 uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
bogdanm 73:1efda918f0ba 68 This parameter can be a value of @ref SPI_data_direction */
bogdanm 73:1efda918f0ba 69
bogdanm 73:1efda918f0ba 70 uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
bogdanm 73:1efda918f0ba 71 This parameter can be a value of @ref SPI_mode */
bogdanm 73:1efda918f0ba 72
bogdanm 73:1efda918f0ba 73 uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
bogdanm 73:1efda918f0ba 74 This parameter can be a value of @ref SPI_data_size */
bogdanm 73:1efda918f0ba 75
bogdanm 73:1efda918f0ba 76 uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
bogdanm 73:1efda918f0ba 77 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 73:1efda918f0ba 78
bogdanm 73:1efda918f0ba 79 uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
bogdanm 73:1efda918f0ba 80 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 73:1efda918f0ba 81
bogdanm 73:1efda918f0ba 82 uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 73:1efda918f0ba 83 hardware (NSS pin) or by software using the SSI bit.
bogdanm 73:1efda918f0ba 84 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 73:1efda918f0ba 85
bogdanm 73:1efda918f0ba 86 uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 73:1efda918f0ba 87 used to configure the transmit and receive SCK clock.
bogdanm 73:1efda918f0ba 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler.
bogdanm 73:1efda918f0ba 89 @note The communication clock is derived from the master
bogdanm 73:1efda918f0ba 90 clock. The slave clock does not need to be set. */
bogdanm 73:1efda918f0ba 91
bogdanm 73:1efda918f0ba 92 uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 73:1efda918f0ba 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 73:1efda918f0ba 94
bogdanm 73:1efda918f0ba 95 uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
bogdanm 73:1efda918f0ba 96 }SPI_InitTypeDef;
bogdanm 73:1efda918f0ba 97
bogdanm 73:1efda918f0ba 98 /**
bogdanm 73:1efda918f0ba 99 * @brief I2S Init structure definition
bogdanm 73:1efda918f0ba 100 */
bogdanm 73:1efda918f0ba 101
bogdanm 73:1efda918f0ba 102 typedef struct
bogdanm 73:1efda918f0ba 103 {
bogdanm 73:1efda918f0ba 104
bogdanm 73:1efda918f0ba 105 uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
bogdanm 73:1efda918f0ba 106 This parameter can be a value of @ref I2S_Mode */
bogdanm 73:1efda918f0ba 107
bogdanm 73:1efda918f0ba 108 uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
bogdanm 73:1efda918f0ba 109 This parameter can be a value of @ref I2S_Standard */
bogdanm 73:1efda918f0ba 110
bogdanm 73:1efda918f0ba 111 uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
bogdanm 73:1efda918f0ba 112 This parameter can be a value of @ref I2S_Data_Format */
bogdanm 73:1efda918f0ba 113
bogdanm 73:1efda918f0ba 114 uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
bogdanm 73:1efda918f0ba 115 This parameter can be a value of @ref I2S_MCLK_Output */
bogdanm 73:1efda918f0ba 116
bogdanm 73:1efda918f0ba 117 uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
bogdanm 73:1efda918f0ba 118 This parameter can be a value of @ref I2S_Audio_Frequency */
bogdanm 73:1efda918f0ba 119
bogdanm 73:1efda918f0ba 120 uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
bogdanm 73:1efda918f0ba 121 This parameter can be a value of @ref I2S_Clock_Polarity */
bogdanm 73:1efda918f0ba 122 }I2S_InitTypeDef;
bogdanm 73:1efda918f0ba 123
bogdanm 73:1efda918f0ba 124 /**
bogdanm 73:1efda918f0ba 125 * @}
bogdanm 73:1efda918f0ba 126 */
bogdanm 73:1efda918f0ba 127
bogdanm 73:1efda918f0ba 128 /** @defgroup SPI_Exported_Constants
bogdanm 73:1efda918f0ba 129 * @{
bogdanm 73:1efda918f0ba 130 */
bogdanm 73:1efda918f0ba 131
bogdanm 73:1efda918f0ba 132 #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
bogdanm 73:1efda918f0ba 133 ((PERIPH) == SPI2) || \
bogdanm 73:1efda918f0ba 134 ((PERIPH) == SPI3))
bogdanm 73:1efda918f0ba 135
bogdanm 73:1efda918f0ba 136 #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
bogdanm 73:1efda918f0ba 137 ((PERIPH) == SPI3))
bogdanm 73:1efda918f0ba 138
bogdanm 73:1efda918f0ba 139 /** @defgroup SPI_data_direction
bogdanm 73:1efda918f0ba 140 * @{
bogdanm 73:1efda918f0ba 141 */
bogdanm 73:1efda918f0ba 142
bogdanm 73:1efda918f0ba 143 #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 144 #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
bogdanm 73:1efda918f0ba 145 #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
bogdanm 73:1efda918f0ba 146 #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
bogdanm 73:1efda918f0ba 147 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
bogdanm 73:1efda918f0ba 148 ((MODE) == SPI_Direction_2Lines_RxOnly) || \
bogdanm 73:1efda918f0ba 149 ((MODE) == SPI_Direction_1Line_Rx) || \
bogdanm 73:1efda918f0ba 150 ((MODE) == SPI_Direction_1Line_Tx))
bogdanm 73:1efda918f0ba 151 /**
bogdanm 73:1efda918f0ba 152 * @}
bogdanm 73:1efda918f0ba 153 */
bogdanm 73:1efda918f0ba 154
bogdanm 73:1efda918f0ba 155 /** @defgroup SPI_mode
bogdanm 73:1efda918f0ba 156 * @{
bogdanm 73:1efda918f0ba 157 */
bogdanm 73:1efda918f0ba 158
bogdanm 73:1efda918f0ba 159 #define SPI_Mode_Master ((uint16_t)0x0104)
bogdanm 73:1efda918f0ba 160 #define SPI_Mode_Slave ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 161 #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
bogdanm 73:1efda918f0ba 162 ((MODE) == SPI_Mode_Slave))
bogdanm 73:1efda918f0ba 163 /**
bogdanm 73:1efda918f0ba 164 * @}
bogdanm 73:1efda918f0ba 165 */
bogdanm 73:1efda918f0ba 166
bogdanm 73:1efda918f0ba 167 /** @defgroup SPI_data_size
bogdanm 73:1efda918f0ba 168 * @{
bogdanm 73:1efda918f0ba 169 */
bogdanm 73:1efda918f0ba 170
bogdanm 73:1efda918f0ba 171 #define SPI_DataSize_16b ((uint16_t)0x0800)
bogdanm 73:1efda918f0ba 172 #define SPI_DataSize_8b ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 173 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
bogdanm 73:1efda918f0ba 174 ((DATASIZE) == SPI_DataSize_8b))
bogdanm 73:1efda918f0ba 175 /**
bogdanm 73:1efda918f0ba 176 * @}
bogdanm 73:1efda918f0ba 177 */
bogdanm 73:1efda918f0ba 178
bogdanm 73:1efda918f0ba 179 /** @defgroup SPI_Clock_Polarity
bogdanm 73:1efda918f0ba 180 * @{
bogdanm 73:1efda918f0ba 181 */
bogdanm 73:1efda918f0ba 182
bogdanm 73:1efda918f0ba 183 #define SPI_CPOL_Low ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 184 #define SPI_CPOL_High ((uint16_t)0x0002)
bogdanm 73:1efda918f0ba 185 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
bogdanm 73:1efda918f0ba 186 ((CPOL) == SPI_CPOL_High))
bogdanm 73:1efda918f0ba 187 /**
bogdanm 73:1efda918f0ba 188 * @}
bogdanm 73:1efda918f0ba 189 */
bogdanm 73:1efda918f0ba 190
bogdanm 73:1efda918f0ba 191 /** @defgroup SPI_Clock_Phase
bogdanm 73:1efda918f0ba 192 * @{
bogdanm 73:1efda918f0ba 193 */
bogdanm 73:1efda918f0ba 194
bogdanm 73:1efda918f0ba 195 #define SPI_CPHA_1Edge ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 196 #define SPI_CPHA_2Edge ((uint16_t)0x0001)
bogdanm 73:1efda918f0ba 197 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
bogdanm 73:1efda918f0ba 198 ((CPHA) == SPI_CPHA_2Edge))
bogdanm 73:1efda918f0ba 199 /**
bogdanm 73:1efda918f0ba 200 * @}
bogdanm 73:1efda918f0ba 201 */
bogdanm 73:1efda918f0ba 202
bogdanm 73:1efda918f0ba 203 /** @defgroup SPI_Slave_Select_management
bogdanm 73:1efda918f0ba 204 * @{
bogdanm 73:1efda918f0ba 205 */
bogdanm 73:1efda918f0ba 206
bogdanm 73:1efda918f0ba 207 #define SPI_NSS_Soft ((uint16_t)0x0200)
bogdanm 73:1efda918f0ba 208 #define SPI_NSS_Hard ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 209 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
bogdanm 73:1efda918f0ba 210 ((NSS) == SPI_NSS_Hard))
bogdanm 73:1efda918f0ba 211 /**
bogdanm 73:1efda918f0ba 212 * @}
bogdanm 73:1efda918f0ba 213 */
bogdanm 73:1efda918f0ba 214
bogdanm 73:1efda918f0ba 215 /** @defgroup SPI_BaudRate_Prescaler
bogdanm 73:1efda918f0ba 216 * @{
bogdanm 73:1efda918f0ba 217 */
bogdanm 73:1efda918f0ba 218
bogdanm 73:1efda918f0ba 219 #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 220 #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
bogdanm 73:1efda918f0ba 221 #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
bogdanm 73:1efda918f0ba 222 #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
bogdanm 73:1efda918f0ba 223 #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
bogdanm 73:1efda918f0ba 224 #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
bogdanm 73:1efda918f0ba 225 #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
bogdanm 73:1efda918f0ba 226 #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
bogdanm 73:1efda918f0ba 227 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
bogdanm 73:1efda918f0ba 228 ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
bogdanm 73:1efda918f0ba 229 ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
bogdanm 73:1efda918f0ba 230 ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
bogdanm 73:1efda918f0ba 231 ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
bogdanm 73:1efda918f0ba 232 ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
bogdanm 73:1efda918f0ba 233 ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
bogdanm 73:1efda918f0ba 234 ((PRESCALER) == SPI_BaudRatePrescaler_256))
bogdanm 73:1efda918f0ba 235 /**
bogdanm 73:1efda918f0ba 236 * @}
bogdanm 73:1efda918f0ba 237 */
bogdanm 73:1efda918f0ba 238
bogdanm 73:1efda918f0ba 239 /** @defgroup SPI_MSB_LSB_transmission
bogdanm 73:1efda918f0ba 240 * @{
bogdanm 73:1efda918f0ba 241 */
bogdanm 73:1efda918f0ba 242
bogdanm 73:1efda918f0ba 243 #define SPI_FirstBit_MSB ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 244 #define SPI_FirstBit_LSB ((uint16_t)0x0080)
bogdanm 73:1efda918f0ba 245 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
bogdanm 73:1efda918f0ba 246 ((BIT) == SPI_FirstBit_LSB))
bogdanm 73:1efda918f0ba 247 /**
bogdanm 73:1efda918f0ba 248 * @}
bogdanm 73:1efda918f0ba 249 */
bogdanm 73:1efda918f0ba 250
bogdanm 73:1efda918f0ba 251 /** @defgroup I2S_Mode
bogdanm 73:1efda918f0ba 252 * @{
bogdanm 73:1efda918f0ba 253 */
bogdanm 73:1efda918f0ba 254
bogdanm 73:1efda918f0ba 255 #define I2S_Mode_SlaveTx ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 256 #define I2S_Mode_SlaveRx ((uint16_t)0x0100)
bogdanm 73:1efda918f0ba 257 #define I2S_Mode_MasterTx ((uint16_t)0x0200)
bogdanm 73:1efda918f0ba 258 #define I2S_Mode_MasterRx ((uint16_t)0x0300)
bogdanm 73:1efda918f0ba 259 #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
bogdanm 73:1efda918f0ba 260 ((MODE) == I2S_Mode_SlaveRx) || \
bogdanm 73:1efda918f0ba 261 ((MODE) == I2S_Mode_MasterTx) || \
bogdanm 73:1efda918f0ba 262 ((MODE) == I2S_Mode_MasterRx) )
bogdanm 73:1efda918f0ba 263 /**
bogdanm 73:1efda918f0ba 264 * @}
bogdanm 73:1efda918f0ba 265 */
bogdanm 73:1efda918f0ba 266
bogdanm 73:1efda918f0ba 267 /** @defgroup I2S_Standard
bogdanm 73:1efda918f0ba 268 * @{
bogdanm 73:1efda918f0ba 269 */
bogdanm 73:1efda918f0ba 270
bogdanm 73:1efda918f0ba 271 #define I2S_Standard_Phillips ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 272 #define I2S_Standard_MSB ((uint16_t)0x0010)
bogdanm 73:1efda918f0ba 273 #define I2S_Standard_LSB ((uint16_t)0x0020)
bogdanm 73:1efda918f0ba 274 #define I2S_Standard_PCMShort ((uint16_t)0x0030)
bogdanm 73:1efda918f0ba 275 #define I2S_Standard_PCMLong ((uint16_t)0x00B0)
bogdanm 73:1efda918f0ba 276 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
bogdanm 73:1efda918f0ba 277 ((STANDARD) == I2S_Standard_MSB) || \
bogdanm 73:1efda918f0ba 278 ((STANDARD) == I2S_Standard_LSB) || \
bogdanm 73:1efda918f0ba 279 ((STANDARD) == I2S_Standard_PCMShort) || \
bogdanm 73:1efda918f0ba 280 ((STANDARD) == I2S_Standard_PCMLong))
bogdanm 73:1efda918f0ba 281 /**
bogdanm 73:1efda918f0ba 282 * @}
bogdanm 73:1efda918f0ba 283 */
bogdanm 73:1efda918f0ba 284
bogdanm 73:1efda918f0ba 285 /** @defgroup I2S_Data_Format
bogdanm 73:1efda918f0ba 286 * @{
bogdanm 73:1efda918f0ba 287 */
bogdanm 73:1efda918f0ba 288
bogdanm 73:1efda918f0ba 289 #define I2S_DataFormat_16b ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 290 #define I2S_DataFormat_16bextended ((uint16_t)0x0001)
bogdanm 73:1efda918f0ba 291 #define I2S_DataFormat_24b ((uint16_t)0x0003)
bogdanm 73:1efda918f0ba 292 #define I2S_DataFormat_32b ((uint16_t)0x0005)
bogdanm 73:1efda918f0ba 293 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
bogdanm 73:1efda918f0ba 294 ((FORMAT) == I2S_DataFormat_16bextended) || \
bogdanm 73:1efda918f0ba 295 ((FORMAT) == I2S_DataFormat_24b) || \
bogdanm 73:1efda918f0ba 296 ((FORMAT) == I2S_DataFormat_32b))
bogdanm 73:1efda918f0ba 297 /**
bogdanm 73:1efda918f0ba 298 * @}
bogdanm 73:1efda918f0ba 299 */
bogdanm 73:1efda918f0ba 300
bogdanm 73:1efda918f0ba 301 /** @defgroup I2S_MCLK_Output
bogdanm 73:1efda918f0ba 302 * @{
bogdanm 73:1efda918f0ba 303 */
bogdanm 73:1efda918f0ba 304
bogdanm 73:1efda918f0ba 305 #define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
bogdanm 73:1efda918f0ba 306 #define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 307 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
bogdanm 73:1efda918f0ba 308 ((OUTPUT) == I2S_MCLKOutput_Disable))
bogdanm 73:1efda918f0ba 309 /**
bogdanm 73:1efda918f0ba 310 * @}
bogdanm 73:1efda918f0ba 311 */
bogdanm 73:1efda918f0ba 312
bogdanm 73:1efda918f0ba 313 /** @defgroup I2S_Audio_Frequency
bogdanm 73:1efda918f0ba 314 * @{
bogdanm 73:1efda918f0ba 315 */
bogdanm 73:1efda918f0ba 316
bogdanm 73:1efda918f0ba 317 #define I2S_AudioFreq_192k ((uint32_t)192000)
bogdanm 73:1efda918f0ba 318 #define I2S_AudioFreq_96k ((uint32_t)96000)
bogdanm 73:1efda918f0ba 319 #define I2S_AudioFreq_48k ((uint32_t)48000)
bogdanm 73:1efda918f0ba 320 #define I2S_AudioFreq_44k ((uint32_t)44100)
bogdanm 73:1efda918f0ba 321 #define I2S_AudioFreq_32k ((uint32_t)32000)
bogdanm 73:1efda918f0ba 322 #define I2S_AudioFreq_22k ((uint32_t)22050)
bogdanm 73:1efda918f0ba 323 #define I2S_AudioFreq_16k ((uint32_t)16000)
bogdanm 73:1efda918f0ba 324 #define I2S_AudioFreq_11k ((uint32_t)11025)
bogdanm 73:1efda918f0ba 325 #define I2S_AudioFreq_8k ((uint32_t)8000)
bogdanm 73:1efda918f0ba 326 #define I2S_AudioFreq_Default ((uint32_t)2)
bogdanm 73:1efda918f0ba 327
bogdanm 73:1efda918f0ba 328 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
bogdanm 73:1efda918f0ba 329 ((FREQ) <= I2S_AudioFreq_192k)) || \
bogdanm 73:1efda918f0ba 330 ((FREQ) == I2S_AudioFreq_Default))
bogdanm 73:1efda918f0ba 331 /**
bogdanm 73:1efda918f0ba 332 * @}
bogdanm 73:1efda918f0ba 333 */
bogdanm 73:1efda918f0ba 334
bogdanm 73:1efda918f0ba 335 /** @defgroup I2S_Clock_Polarity
bogdanm 73:1efda918f0ba 336 * @{
bogdanm 73:1efda918f0ba 337 */
bogdanm 73:1efda918f0ba 338
bogdanm 73:1efda918f0ba 339 #define I2S_CPOL_Low ((uint16_t)0x0000)
bogdanm 73:1efda918f0ba 340 #define I2S_CPOL_High ((uint16_t)0x0008)
bogdanm 73:1efda918f0ba 341 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
bogdanm 73:1efda918f0ba 342 ((CPOL) == I2S_CPOL_High))
bogdanm 73:1efda918f0ba 343 /**
bogdanm 73:1efda918f0ba 344 * @}
bogdanm 73:1efda918f0ba 345 */
bogdanm 73:1efda918f0ba 346
bogdanm 73:1efda918f0ba 347 /** @defgroup SPI_I2S_DMA_transfer_requests
bogdanm 73:1efda918f0ba 348 * @{
bogdanm 73:1efda918f0ba 349 */
bogdanm 73:1efda918f0ba 350
bogdanm 73:1efda918f0ba 351 #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
bogdanm 73:1efda918f0ba 352 #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
bogdanm 73:1efda918f0ba 353 #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
bogdanm 73:1efda918f0ba 354 /**
bogdanm 73:1efda918f0ba 355 * @}
bogdanm 73:1efda918f0ba 356 */
bogdanm 73:1efda918f0ba 357
bogdanm 73:1efda918f0ba 358 /** @defgroup SPI_NSS_internal_software_management
bogdanm 73:1efda918f0ba 359 * @{
bogdanm 73:1efda918f0ba 360 */
bogdanm 73:1efda918f0ba 361
bogdanm 73:1efda918f0ba 362 #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
bogdanm 73:1efda918f0ba 363 #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
bogdanm 73:1efda918f0ba 364 #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
bogdanm 73:1efda918f0ba 365 ((INTERNAL) == SPI_NSSInternalSoft_Reset))
bogdanm 73:1efda918f0ba 366 /**
bogdanm 73:1efda918f0ba 367 * @}
bogdanm 73:1efda918f0ba 368 */
bogdanm 73:1efda918f0ba 369
bogdanm 73:1efda918f0ba 370 /** @defgroup SPI_CRC_Transmit_Receive
bogdanm 73:1efda918f0ba 371 * @{
bogdanm 73:1efda918f0ba 372 */
bogdanm 73:1efda918f0ba 373
bogdanm 73:1efda918f0ba 374 #define SPI_CRC_Tx ((uint8_t)0x00)
bogdanm 73:1efda918f0ba 375 #define SPI_CRC_Rx ((uint8_t)0x01)
bogdanm 73:1efda918f0ba 376 #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
bogdanm 73:1efda918f0ba 377 /**
bogdanm 73:1efda918f0ba 378 * @}
bogdanm 73:1efda918f0ba 379 */
bogdanm 73:1efda918f0ba 380
bogdanm 73:1efda918f0ba 381 /** @defgroup SPI_direction_transmit_receive
bogdanm 73:1efda918f0ba 382 * @{
bogdanm 73:1efda918f0ba 383 */
bogdanm 73:1efda918f0ba 384
bogdanm 73:1efda918f0ba 385 #define SPI_Direction_Rx ((uint16_t)0xBFFF)
bogdanm 73:1efda918f0ba 386 #define SPI_Direction_Tx ((uint16_t)0x4000)
bogdanm 73:1efda918f0ba 387 #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
bogdanm 73:1efda918f0ba 388 ((DIRECTION) == SPI_Direction_Tx))
bogdanm 73:1efda918f0ba 389 /**
bogdanm 73:1efda918f0ba 390 * @}
bogdanm 73:1efda918f0ba 391 */
bogdanm 73:1efda918f0ba 392
bogdanm 73:1efda918f0ba 393 /** @defgroup SPI_I2S_interrupts_definition
bogdanm 73:1efda918f0ba 394 * @{
bogdanm 73:1efda918f0ba 395 */
bogdanm 73:1efda918f0ba 396
bogdanm 73:1efda918f0ba 397 #define SPI_I2S_IT_TXE ((uint8_t)0x71)
bogdanm 73:1efda918f0ba 398 #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
bogdanm 73:1efda918f0ba 399 #define SPI_I2S_IT_ERR ((uint8_t)0x50)
bogdanm 73:1efda918f0ba 400 #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
bogdanm 73:1efda918f0ba 401 ((IT) == SPI_I2S_IT_RXNE) || \
bogdanm 73:1efda918f0ba 402 ((IT) == SPI_I2S_IT_ERR))
bogdanm 73:1efda918f0ba 403 #define SPI_I2S_IT_OVR ((uint8_t)0x56)
bogdanm 73:1efda918f0ba 404 #define SPI_IT_MODF ((uint8_t)0x55)
bogdanm 73:1efda918f0ba 405 #define SPI_IT_CRCERR ((uint8_t)0x54)
bogdanm 73:1efda918f0ba 406 #define I2S_IT_UDR ((uint8_t)0x53)
bogdanm 73:1efda918f0ba 407 #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
bogdanm 73:1efda918f0ba 408 #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
bogdanm 73:1efda918f0ba 409 ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \
bogdanm 73:1efda918f0ba 410 ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))
bogdanm 73:1efda918f0ba 411 /**
bogdanm 73:1efda918f0ba 412 * @}
bogdanm 73:1efda918f0ba 413 */
bogdanm 73:1efda918f0ba 414
bogdanm 73:1efda918f0ba 415 /** @defgroup SPI_I2S_flags_definition
bogdanm 73:1efda918f0ba 416 * @{
bogdanm 73:1efda918f0ba 417 */
bogdanm 73:1efda918f0ba 418
bogdanm 73:1efda918f0ba 419 #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
bogdanm 73:1efda918f0ba 420 #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
bogdanm 73:1efda918f0ba 421 #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
bogdanm 73:1efda918f0ba 422 #define I2S_FLAG_UDR ((uint16_t)0x0008)
bogdanm 73:1efda918f0ba 423 #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
bogdanm 73:1efda918f0ba 424 #define SPI_FLAG_MODF ((uint16_t)0x0020)
bogdanm 73:1efda918f0ba 425 #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
bogdanm 73:1efda918f0ba 426 #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
bogdanm 73:1efda918f0ba 427 #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
bogdanm 73:1efda918f0ba 428 #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
bogdanm 73:1efda918f0ba 429 ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
bogdanm 73:1efda918f0ba 430 ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
bogdanm 73:1efda918f0ba 431 ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))
bogdanm 73:1efda918f0ba 432 /**
bogdanm 73:1efda918f0ba 433 * @}
bogdanm 73:1efda918f0ba 434 */
bogdanm 73:1efda918f0ba 435
bogdanm 73:1efda918f0ba 436 /** @defgroup SPI_CRC_polynomial
bogdanm 73:1efda918f0ba 437 * @{
bogdanm 73:1efda918f0ba 438 */
bogdanm 73:1efda918f0ba 439
bogdanm 73:1efda918f0ba 440 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
bogdanm 73:1efda918f0ba 441 /**
bogdanm 73:1efda918f0ba 442 * @}
bogdanm 73:1efda918f0ba 443 */
bogdanm 73:1efda918f0ba 444
bogdanm 73:1efda918f0ba 445 /**
bogdanm 73:1efda918f0ba 446 * @}
bogdanm 73:1efda918f0ba 447 */
bogdanm 73:1efda918f0ba 448
bogdanm 73:1efda918f0ba 449 /** @defgroup SPI_Exported_Macros
bogdanm 73:1efda918f0ba 450 * @{
bogdanm 73:1efda918f0ba 451 */
bogdanm 73:1efda918f0ba 452
bogdanm 73:1efda918f0ba 453 /**
bogdanm 73:1efda918f0ba 454 * @}
bogdanm 73:1efda918f0ba 455 */
bogdanm 73:1efda918f0ba 456
bogdanm 73:1efda918f0ba 457 /** @defgroup SPI_Exported_Functions
bogdanm 73:1efda918f0ba 458 * @{
bogdanm 73:1efda918f0ba 459 */
bogdanm 73:1efda918f0ba 460
bogdanm 73:1efda918f0ba 461 void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
bogdanm 73:1efda918f0ba 462 void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
bogdanm 73:1efda918f0ba 463 void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
bogdanm 73:1efda918f0ba 464 void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
bogdanm 73:1efda918f0ba 465 void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
bogdanm 73:1efda918f0ba 466 void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 467 void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 468 void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
bogdanm 73:1efda918f0ba 469 void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
bogdanm 73:1efda918f0ba 470 void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
bogdanm 73:1efda918f0ba 471 uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
bogdanm 73:1efda918f0ba 472 void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
bogdanm 73:1efda918f0ba 473 void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 474 void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
bogdanm 73:1efda918f0ba 475 void SPI_TransmitCRC(SPI_TypeDef* SPIx);
bogdanm 73:1efda918f0ba 476 void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 477 uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
bogdanm 73:1efda918f0ba 478 uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
bogdanm 73:1efda918f0ba 479 void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
bogdanm 73:1efda918f0ba 480 FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
bogdanm 73:1efda918f0ba 481 void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
bogdanm 73:1efda918f0ba 482 ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
bogdanm 73:1efda918f0ba 483 void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
bogdanm 73:1efda918f0ba 484
bogdanm 73:1efda918f0ba 485 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 486 }
bogdanm 73:1efda918f0ba 487 #endif
bogdanm 73:1efda918f0ba 488
bogdanm 73:1efda918f0ba 489 #endif /*__STM32F10x_SPI_H */
bogdanm 73:1efda918f0ba 490 /**
bogdanm 73:1efda918f0ba 491 * @}
bogdanm 73:1efda918f0ba 492 */
bogdanm 73:1efda918f0ba 493
bogdanm 73:1efda918f0ba 494 /**
bogdanm 73:1efda918f0ba 495 * @}
bogdanm 73:1efda918f0ba 496 */
bogdanm 73:1efda918f0ba 497
bogdanm 73:1efda918f0ba 498 /**
bogdanm 73:1efda918f0ba 499 * @}
bogdanm 73:1efda918f0ba 500 */
bogdanm 73:1efda918f0ba 501
emilmont 77:869cf507173a 502 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/