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TARGET_NUCLEO_F103RB/stm32f10x_dma.h@102:d2e8fb00ad18, 2015-06-22 (annotated)

Committer:
JulienKern
Date:
Mon Jun 22 09:10:29 2015 +0000
Revision:
102:d2e8fb00ad18
Parent:
77:869cf507173a 
RPM + torque ok

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bogdanm 73:1efda918f0ba 1 /**
bogdanm 73:1efda918f0ba 2 ******************************************************************************
bogdanm 73:1efda918f0ba 3 * @file stm32f10x_dma.h
bogdanm 73:1efda918f0ba 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V3.6.1
emilmont 77:869cf507173a 6 * @date 05-March-2012
bogdanm 73:1efda918f0ba 7 * @brief This file contains all the functions prototypes for the DMA firmware
bogdanm 73:1efda918f0ba 8 * library.
bogdanm 76:824293ae5e43 9 *******************************************************************************
bogdanm 76:824293ae5e43 10 * Copyright (c) 2014, STMicroelectronics
bogdanm 76:824293ae5e43 11 * All rights reserved.
bogdanm 76:824293ae5e43 12 *
bogdanm 76:824293ae5e43 13 * Redistribution and use in source and binary forms, with or without
bogdanm 76:824293ae5e43 14 * modification, are permitted provided that the following conditions are met:
bogdanm 76:824293ae5e43 15 *
bogdanm 76:824293ae5e43 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 76:824293ae5e43 17 * this list of conditions and the following disclaimer.
bogdanm 76:824293ae5e43 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 76:824293ae5e43 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 76:824293ae5e43 20 * and/or other materials provided with the distribution.
bogdanm 76:824293ae5e43 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 76:824293ae5e43 22 * may be used to endorse or promote products derived from this software
bogdanm 76:824293ae5e43 23 * without specific prior written permission.
bogdanm 76:824293ae5e43 24 *
bogdanm 76:824293ae5e43 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 76:824293ae5e43 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 76:824293ae5e43 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 76:824293ae5e43 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 76:824293ae5e43 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 76:824293ae5e43 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 76:824293ae5e43 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 76:824293ae5e43 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 76:824293ae5e43 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 76:824293ae5e43 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 76:824293ae5e43 35 *******************************************************************************
bogdanm 76:824293ae5e43 36 */
bogdanm 73:1efda918f0ba 37
bogdanm 73:1efda918f0ba 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 73:1efda918f0ba 39 #ifndef __STM32F10x_DMA_H
bogdanm 73:1efda918f0ba 40 #define __STM32F10x_DMA_H
bogdanm 73:1efda918f0ba 41
bogdanm 73:1efda918f0ba 42 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 43 extern "C" {
bogdanm 73:1efda918f0ba 44 #endif
bogdanm 73:1efda918f0ba 45
bogdanm 73:1efda918f0ba 46 /* Includes ------------------------------------------------------------------*/
bogdanm 73:1efda918f0ba 47 #include "stm32f10x.h"
bogdanm 73:1efda918f0ba 48
bogdanm 73:1efda918f0ba 49 /** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm 73:1efda918f0ba 50 * @{
bogdanm 73:1efda918f0ba 51 */
bogdanm 73:1efda918f0ba 52
bogdanm 73:1efda918f0ba 53 /** @addtogroup DMA
bogdanm 73:1efda918f0ba 54 * @{
bogdanm 73:1efda918f0ba 55 */
bogdanm 73:1efda918f0ba 56
bogdanm 73:1efda918f0ba 57 /** @defgroup DMA_Exported_Types
bogdanm 73:1efda918f0ba 58 * @{
bogdanm 73:1efda918f0ba 59 */
bogdanm 73:1efda918f0ba 60
bogdanm 73:1efda918f0ba 61 /**
bogdanm 73:1efda918f0ba 62 * @brief DMA Init structure definition
bogdanm 73:1efda918f0ba 63 */
bogdanm 73:1efda918f0ba 64
bogdanm 73:1efda918f0ba 65 typedef struct
bogdanm 73:1efda918f0ba 66 {
bogdanm 73:1efda918f0ba 67 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
bogdanm 73:1efda918f0ba 68
bogdanm 73:1efda918f0ba 69 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
bogdanm 73:1efda918f0ba 70
bogdanm 73:1efda918f0ba 71 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
bogdanm 73:1efda918f0ba 72 This parameter can be a value of @ref DMA_data_transfer_direction */
bogdanm 73:1efda918f0ba 73
bogdanm 73:1efda918f0ba 74 uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
bogdanm 73:1efda918f0ba 75 The data unit is equal to the configuration set in DMA_PeripheralDataSize
bogdanm 73:1efda918f0ba 76 or DMA_MemoryDataSize members depending in the transfer direction. */
bogdanm 73:1efda918f0ba 77
bogdanm 73:1efda918f0ba 78 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
bogdanm 73:1efda918f0ba 79 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
bogdanm 73:1efda918f0ba 80
bogdanm 73:1efda918f0ba 81 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
bogdanm 73:1efda918f0ba 82 This parameter can be a value of @ref DMA_memory_incremented_mode */
bogdanm 73:1efda918f0ba 83
bogdanm 73:1efda918f0ba 84 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
bogdanm 73:1efda918f0ba 85 This parameter can be a value of @ref DMA_peripheral_data_size */
bogdanm 73:1efda918f0ba 86
bogdanm 73:1efda918f0ba 87 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
bogdanm 73:1efda918f0ba 88 This parameter can be a value of @ref DMA_memory_data_size */
bogdanm 73:1efda918f0ba 89
bogdanm 73:1efda918f0ba 90 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 73:1efda918f0ba 91 This parameter can be a value of @ref DMA_circular_normal_mode.
bogdanm 73:1efda918f0ba 92 @note: The circular buffer mode cannot be used if the memory-to-memory
bogdanm 73:1efda918f0ba 93 data transfer is configured on the selected Channel */
bogdanm 73:1efda918f0ba 94
bogdanm 73:1efda918f0ba 95 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 73:1efda918f0ba 96 This parameter can be a value of @ref DMA_priority_level */
bogdanm 73:1efda918f0ba 97
bogdanm 73:1efda918f0ba 98 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
bogdanm 73:1efda918f0ba 99 This parameter can be a value of @ref DMA_memory_to_memory */
bogdanm 73:1efda918f0ba 100 }DMA_InitTypeDef;
bogdanm 73:1efda918f0ba 101
bogdanm 73:1efda918f0ba 102 /**
bogdanm 73:1efda918f0ba 103 * @}
bogdanm 73:1efda918f0ba 104 */
bogdanm 73:1efda918f0ba 105
bogdanm 73:1efda918f0ba 106 /** @defgroup DMA_Exported_Constants
bogdanm 73:1efda918f0ba 107 * @{
bogdanm 73:1efda918f0ba 108 */
bogdanm 73:1efda918f0ba 109
bogdanm 73:1efda918f0ba 110 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
bogdanm 73:1efda918f0ba 111 ((PERIPH) == DMA1_Channel2) || \
bogdanm 73:1efda918f0ba 112 ((PERIPH) == DMA1_Channel3) || \
bogdanm 73:1efda918f0ba 113 ((PERIPH) == DMA1_Channel4) || \
bogdanm 73:1efda918f0ba 114 ((PERIPH) == DMA1_Channel5) || \
bogdanm 73:1efda918f0ba 115 ((PERIPH) == DMA1_Channel6) || \
bogdanm 73:1efda918f0ba 116 ((PERIPH) == DMA1_Channel7) || \
bogdanm 73:1efda918f0ba 117 ((PERIPH) == DMA2_Channel1) || \
bogdanm 73:1efda918f0ba 118 ((PERIPH) == DMA2_Channel2) || \
bogdanm 73:1efda918f0ba 119 ((PERIPH) == DMA2_Channel3) || \
bogdanm 73:1efda918f0ba 120 ((PERIPH) == DMA2_Channel4) || \
bogdanm 73:1efda918f0ba 121 ((PERIPH) == DMA2_Channel5))
bogdanm 73:1efda918f0ba 122
bogdanm 73:1efda918f0ba 123 /** @defgroup DMA_data_transfer_direction
bogdanm 73:1efda918f0ba 124 * @{
bogdanm 73:1efda918f0ba 125 */
bogdanm 73:1efda918f0ba 126
bogdanm 73:1efda918f0ba 127 #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 128 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 129 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
bogdanm 73:1efda918f0ba 130 ((DIR) == DMA_DIR_PeripheralSRC))
bogdanm 73:1efda918f0ba 131 /**
bogdanm 73:1efda918f0ba 132 * @}
bogdanm 73:1efda918f0ba 133 */
bogdanm 73:1efda918f0ba 134
bogdanm 73:1efda918f0ba 135 /** @defgroup DMA_peripheral_incremented_mode
bogdanm 73:1efda918f0ba 136 * @{
bogdanm 73:1efda918f0ba 137 */
bogdanm 73:1efda918f0ba 138
bogdanm 73:1efda918f0ba 139 #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 140 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 141 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
bogdanm 73:1efda918f0ba 142 ((STATE) == DMA_PeripheralInc_Disable))
bogdanm 73:1efda918f0ba 143 /**
bogdanm 73:1efda918f0ba 144 * @}
bogdanm 73:1efda918f0ba 145 */
bogdanm 73:1efda918f0ba 146
bogdanm 73:1efda918f0ba 147 /** @defgroup DMA_memory_incremented_mode
bogdanm 73:1efda918f0ba 148 * @{
bogdanm 73:1efda918f0ba 149 */
bogdanm 73:1efda918f0ba 150
bogdanm 73:1efda918f0ba 151 #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 152 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 153 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
bogdanm 73:1efda918f0ba 154 ((STATE) == DMA_MemoryInc_Disable))
bogdanm 73:1efda918f0ba 155 /**
bogdanm 73:1efda918f0ba 156 * @}
bogdanm 73:1efda918f0ba 157 */
bogdanm 73:1efda918f0ba 158
bogdanm 73:1efda918f0ba 159 /** @defgroup DMA_peripheral_data_size
bogdanm 73:1efda918f0ba 160 * @{
bogdanm 73:1efda918f0ba 161 */
bogdanm 73:1efda918f0ba 162
bogdanm 73:1efda918f0ba 163 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 164 #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 165 #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 166 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
bogdanm 73:1efda918f0ba 167 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
bogdanm 73:1efda918f0ba 168 ((SIZE) == DMA_PeripheralDataSize_Word))
bogdanm 73:1efda918f0ba 169 /**
bogdanm 73:1efda918f0ba 170 * @}
bogdanm 73:1efda918f0ba 171 */
bogdanm 73:1efda918f0ba 172
bogdanm 73:1efda918f0ba 173 /** @defgroup DMA_memory_data_size
bogdanm 73:1efda918f0ba 174 * @{
bogdanm 73:1efda918f0ba 175 */
bogdanm 73:1efda918f0ba 176
bogdanm 73:1efda918f0ba 177 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 178 #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 179 #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 180 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
bogdanm 73:1efda918f0ba 181 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
bogdanm 73:1efda918f0ba 182 ((SIZE) == DMA_MemoryDataSize_Word))
bogdanm 73:1efda918f0ba 183 /**
bogdanm 73:1efda918f0ba 184 * @}
bogdanm 73:1efda918f0ba 185 */
bogdanm 73:1efda918f0ba 186
bogdanm 73:1efda918f0ba 187 /** @defgroup DMA_circular_normal_mode
bogdanm 73:1efda918f0ba 188 * @{
bogdanm 73:1efda918f0ba 189 */
bogdanm 73:1efda918f0ba 190
bogdanm 73:1efda918f0ba 191 #define DMA_Mode_Circular ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 192 #define DMA_Mode_Normal ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 193 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
bogdanm 73:1efda918f0ba 194 /**
bogdanm 73:1efda918f0ba 195 * @}
bogdanm 73:1efda918f0ba 196 */
bogdanm 73:1efda918f0ba 197
bogdanm 73:1efda918f0ba 198 /** @defgroup DMA_priority_level
bogdanm 73:1efda918f0ba 199 * @{
bogdanm 73:1efda918f0ba 200 */
bogdanm 73:1efda918f0ba 201
bogdanm 73:1efda918f0ba 202 #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
bogdanm 73:1efda918f0ba 203 #define DMA_Priority_High ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 204 #define DMA_Priority_Medium ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 205 #define DMA_Priority_Low ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 206 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
bogdanm 73:1efda918f0ba 207 ((PRIORITY) == DMA_Priority_High) || \
bogdanm 73:1efda918f0ba 208 ((PRIORITY) == DMA_Priority_Medium) || \
bogdanm 73:1efda918f0ba 209 ((PRIORITY) == DMA_Priority_Low))
bogdanm 73:1efda918f0ba 210 /**
bogdanm 73:1efda918f0ba 211 * @}
bogdanm 73:1efda918f0ba 212 */
bogdanm 73:1efda918f0ba 213
bogdanm 73:1efda918f0ba 214 /** @defgroup DMA_memory_to_memory
bogdanm 73:1efda918f0ba 215 * @{
bogdanm 73:1efda918f0ba 216 */
bogdanm 73:1efda918f0ba 217
bogdanm 73:1efda918f0ba 218 #define DMA_M2M_Enable ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 219 #define DMA_M2M_Disable ((uint32_t)0x00000000)
bogdanm 73:1efda918f0ba 220 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
bogdanm 73:1efda918f0ba 221
bogdanm 73:1efda918f0ba 222 /**
bogdanm 73:1efda918f0ba 223 * @}
bogdanm 73:1efda918f0ba 224 */
bogdanm 73:1efda918f0ba 225
bogdanm 73:1efda918f0ba 226 /** @defgroup DMA_interrupts_definition
bogdanm 73:1efda918f0ba 227 * @{
bogdanm 73:1efda918f0ba 228 */
bogdanm 73:1efda918f0ba 229
bogdanm 73:1efda918f0ba 230 #define DMA_IT_TC ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 231 #define DMA_IT_HT ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 232 #define DMA_IT_TE ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 233 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
bogdanm 73:1efda918f0ba 234
bogdanm 73:1efda918f0ba 235 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
bogdanm 73:1efda918f0ba 236 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 237 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 238 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 239 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 240 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 241 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 242 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 243 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 244 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 245 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 246 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 247 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 248 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 249 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 250 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
bogdanm 73:1efda918f0ba 251 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
bogdanm 73:1efda918f0ba 252 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
bogdanm 73:1efda918f0ba 253 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
bogdanm 73:1efda918f0ba 254 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 255 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
bogdanm 73:1efda918f0ba 256 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
bogdanm 73:1efda918f0ba 257 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
bogdanm 73:1efda918f0ba 258 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
bogdanm 73:1efda918f0ba 259 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
bogdanm 73:1efda918f0ba 260 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
bogdanm 73:1efda918f0ba 261 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
bogdanm 73:1efda918f0ba 262 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
bogdanm 73:1efda918f0ba 263
bogdanm 73:1efda918f0ba 264 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
bogdanm 73:1efda918f0ba 265 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
bogdanm 73:1efda918f0ba 266 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
bogdanm 73:1efda918f0ba 267 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
bogdanm 73:1efda918f0ba 268 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
bogdanm 73:1efda918f0ba 269 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
bogdanm 73:1efda918f0ba 270 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
bogdanm 73:1efda918f0ba 271 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
bogdanm 73:1efda918f0ba 272 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
bogdanm 73:1efda918f0ba 273 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
bogdanm 73:1efda918f0ba 274 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
bogdanm 73:1efda918f0ba 275 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
bogdanm 73:1efda918f0ba 276 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
bogdanm 73:1efda918f0ba 277 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
bogdanm 73:1efda918f0ba 278 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
bogdanm 73:1efda918f0ba 279 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
bogdanm 73:1efda918f0ba 280 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
bogdanm 73:1efda918f0ba 281 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
bogdanm 73:1efda918f0ba 282 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
bogdanm 73:1efda918f0ba 283 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
bogdanm 73:1efda918f0ba 284
bogdanm 73:1efda918f0ba 285 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
bogdanm 73:1efda918f0ba 286
bogdanm 73:1efda918f0ba 287 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
bogdanm 73:1efda918f0ba 288 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
bogdanm 73:1efda918f0ba 289 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
bogdanm 73:1efda918f0ba 290 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
bogdanm 73:1efda918f0ba 291 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
bogdanm 73:1efda918f0ba 292 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
bogdanm 73:1efda918f0ba 293 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
bogdanm 73:1efda918f0ba 294 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
bogdanm 73:1efda918f0ba 295 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
bogdanm 73:1efda918f0ba 296 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
bogdanm 73:1efda918f0ba 297 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
bogdanm 73:1efda918f0ba 298 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
bogdanm 73:1efda918f0ba 299 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
bogdanm 73:1efda918f0ba 300 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
bogdanm 73:1efda918f0ba 301 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
bogdanm 73:1efda918f0ba 302 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
bogdanm 73:1efda918f0ba 303 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
bogdanm 73:1efda918f0ba 304 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
bogdanm 73:1efda918f0ba 305 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
bogdanm 73:1efda918f0ba 306 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
bogdanm 73:1efda918f0ba 307 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
bogdanm 73:1efda918f0ba 308 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
bogdanm 73:1efda918f0ba 309 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
bogdanm 73:1efda918f0ba 310 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
bogdanm 73:1efda918f0ba 311
bogdanm 73:1efda918f0ba 312 /**
bogdanm 73:1efda918f0ba 313 * @}
bogdanm 73:1efda918f0ba 314 */
bogdanm 73:1efda918f0ba 315
bogdanm 73:1efda918f0ba 316 /** @defgroup DMA_flags_definition
bogdanm 73:1efda918f0ba 317 * @{
bogdanm 73:1efda918f0ba 318 */
bogdanm 73:1efda918f0ba 319 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 73:1efda918f0ba 320 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 73:1efda918f0ba 321 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 73:1efda918f0ba 322 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 73:1efda918f0ba 323 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 73:1efda918f0ba 324 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 73:1efda918f0ba 325 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 73:1efda918f0ba 326 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 73:1efda918f0ba 327 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 73:1efda918f0ba 328 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 73:1efda918f0ba 329 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 73:1efda918f0ba 330 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 73:1efda918f0ba 331 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 73:1efda918f0ba 332 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 73:1efda918f0ba 333 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 73:1efda918f0ba 334 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 73:1efda918f0ba 335 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 73:1efda918f0ba 336 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 73:1efda918f0ba 337 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 73:1efda918f0ba 338 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 73:1efda918f0ba 339 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 73:1efda918f0ba 340 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 73:1efda918f0ba 341 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 73:1efda918f0ba 342 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 73:1efda918f0ba 343 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 73:1efda918f0ba 344 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 73:1efda918f0ba 345 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 73:1efda918f0ba 346 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 73:1efda918f0ba 347
bogdanm 73:1efda918f0ba 348 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
bogdanm 73:1efda918f0ba 349 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
bogdanm 73:1efda918f0ba 350 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
bogdanm 73:1efda918f0ba 351 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
bogdanm 73:1efda918f0ba 352 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
bogdanm 73:1efda918f0ba 353 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
bogdanm 73:1efda918f0ba 354 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
bogdanm 73:1efda918f0ba 355 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
bogdanm 73:1efda918f0ba 356 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
bogdanm 73:1efda918f0ba 357 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
bogdanm 73:1efda918f0ba 358 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
bogdanm 73:1efda918f0ba 359 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
bogdanm 73:1efda918f0ba 360 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
bogdanm 73:1efda918f0ba 361 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
bogdanm 73:1efda918f0ba 362 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
bogdanm 73:1efda918f0ba 363 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
bogdanm 73:1efda918f0ba 364 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
bogdanm 73:1efda918f0ba 365 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
bogdanm 73:1efda918f0ba 366 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
bogdanm 73:1efda918f0ba 367 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
bogdanm 73:1efda918f0ba 368
bogdanm 73:1efda918f0ba 369 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
bogdanm 73:1efda918f0ba 370
bogdanm 73:1efda918f0ba 371 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
bogdanm 73:1efda918f0ba 372 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
bogdanm 73:1efda918f0ba 373 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
bogdanm 73:1efda918f0ba 374 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
bogdanm 73:1efda918f0ba 375 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
bogdanm 73:1efda918f0ba 376 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
bogdanm 73:1efda918f0ba 377 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
bogdanm 73:1efda918f0ba 378 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
bogdanm 73:1efda918f0ba 379 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
bogdanm 73:1efda918f0ba 380 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
bogdanm 73:1efda918f0ba 381 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
bogdanm 73:1efda918f0ba 382 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
bogdanm 73:1efda918f0ba 383 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
bogdanm 73:1efda918f0ba 384 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
bogdanm 73:1efda918f0ba 385 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
bogdanm 73:1efda918f0ba 386 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
bogdanm 73:1efda918f0ba 387 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
bogdanm 73:1efda918f0ba 388 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
bogdanm 73:1efda918f0ba 389 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
bogdanm 73:1efda918f0ba 390 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
bogdanm 73:1efda918f0ba 391 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
bogdanm 73:1efda918f0ba 392 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
bogdanm 73:1efda918f0ba 393 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
bogdanm 73:1efda918f0ba 394 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
bogdanm 73:1efda918f0ba 395 /**
bogdanm 73:1efda918f0ba 396 * @}
bogdanm 73:1efda918f0ba 397 */
bogdanm 73:1efda918f0ba 398
bogdanm 73:1efda918f0ba 399 /** @defgroup DMA_Buffer_Size
bogdanm 73:1efda918f0ba 400 * @{
bogdanm 73:1efda918f0ba 401 */
bogdanm 73:1efda918f0ba 402
bogdanm 73:1efda918f0ba 403 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 73:1efda918f0ba 404
bogdanm 73:1efda918f0ba 405 /**
bogdanm 73:1efda918f0ba 406 * @}
bogdanm 73:1efda918f0ba 407 */
bogdanm 73:1efda918f0ba 408
bogdanm 73:1efda918f0ba 409 /**
bogdanm 73:1efda918f0ba 410 * @}
bogdanm 73:1efda918f0ba 411 */
bogdanm 73:1efda918f0ba 412
bogdanm 73:1efda918f0ba 413 /** @defgroup DMA_Exported_Macros
bogdanm 73:1efda918f0ba 414 * @{
bogdanm 73:1efda918f0ba 415 */
bogdanm 73:1efda918f0ba 416
bogdanm 73:1efda918f0ba 417 /**
bogdanm 73:1efda918f0ba 418 * @}
bogdanm 73:1efda918f0ba 419 */
bogdanm 73:1efda918f0ba 420
bogdanm 73:1efda918f0ba 421 /** @defgroup DMA_Exported_Functions
bogdanm 73:1efda918f0ba 422 * @{
bogdanm 73:1efda918f0ba 423 */
bogdanm 73:1efda918f0ba 424
bogdanm 73:1efda918f0ba 425 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 73:1efda918f0ba 426 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
bogdanm 73:1efda918f0ba 427 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
bogdanm 73:1efda918f0ba 428 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
bogdanm 73:1efda918f0ba 429 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
bogdanm 73:1efda918f0ba 430 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
bogdanm 73:1efda918f0ba 431 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
bogdanm 73:1efda918f0ba 432 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
bogdanm 73:1efda918f0ba 433 void DMA_ClearFlag(uint32_t DMAy_FLAG);
bogdanm 73:1efda918f0ba 434 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
bogdanm 73:1efda918f0ba 435 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
bogdanm 73:1efda918f0ba 436
bogdanm 73:1efda918f0ba 437 #ifdef __cplusplus
bogdanm 73:1efda918f0ba 438 }
bogdanm 73:1efda918f0ba 439 #endif
bogdanm 73:1efda918f0ba 440
bogdanm 73:1efda918f0ba 441 #endif /*__STM32F10x_DMA_H */
bogdanm 73:1efda918f0ba 442 /**
bogdanm 73:1efda918f0ba 443 * @}
bogdanm 73:1efda918f0ba 444 */
bogdanm 73:1efda918f0ba 445
bogdanm 73:1efda918f0ba 446 /**
bogdanm 73:1efda918f0ba 447 * @}
bogdanm 73:1efda918f0ba 448 */
bogdanm 73:1efda918f0ba 449
bogdanm 73:1efda918f0ba 450 /**
bogdanm 73:1efda918f0ba 451 * @}
bogdanm 73:1efda918f0ba 452 */
bogdanm 73:1efda918f0ba 453
emilmont 77:869cf507173a 454 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/