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TARGET_NUCLEO_F103RB/stm32f10x_tim.h@73:1efda918f0ba, 2013-12-09 (annotated)

Committer:: bogdanm
Date:: Mon Dec 09 18:43:03 2013 +0200
Revision:: 73:1efda918f0ba
Child:: 76:824293ae5e43

Release 73 of the mbed library



Main changes:



- added support for KL46Z and NUCLEO_F103RB

- STM32 USB device support

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	73:1efda918f0ba	1	/**
bogdanm	73:1efda918f0ba	2	******************************************************************************
bogdanm	73:1efda918f0ba	3	* @file stm32f10x_tim.h
bogdanm	73:1efda918f0ba	4	* @author MCD Application Team
bogdanm	73:1efda918f0ba	5	* @version V3.5.0
bogdanm	73:1efda918f0ba	6	* @date 11-March-2011
bogdanm	73:1efda918f0ba	7	* @brief This file contains all the functions prototypes for the TIM firmware
bogdanm	73:1efda918f0ba	8	* library.
bogdanm	73:1efda918f0ba	9	******************************************************************************
bogdanm	73:1efda918f0ba	10	* @attention
bogdanm	73:1efda918f0ba	11	*
bogdanm	73:1efda918f0ba	12	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
bogdanm	73:1efda918f0ba	13	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
bogdanm	73:1efda918f0ba	14	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
bogdanm	73:1efda918f0ba	15	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
bogdanm	73:1efda918f0ba	16	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
bogdanm	73:1efda918f0ba	17	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
bogdanm	73:1efda918f0ba	18	*
bogdanm	73:1efda918f0ba	19	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
bogdanm	73:1efda918f0ba	20	******************************************************************************
bogdanm	73:1efda918f0ba	21	*/
bogdanm	73:1efda918f0ba	22
bogdanm	73:1efda918f0ba	23	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	73:1efda918f0ba	24	#ifndef __STM32F10x_TIM_H
bogdanm	73:1efda918f0ba	25	#define __STM32F10x_TIM_H
bogdanm	73:1efda918f0ba	26
bogdanm	73:1efda918f0ba	27	#ifdef __cplusplus
bogdanm	73:1efda918f0ba	28	extern "C" {
bogdanm	73:1efda918f0ba	29	#endif
bogdanm	73:1efda918f0ba	30
bogdanm	73:1efda918f0ba	31	/* Includes ------------------------------------------------------------------*/
bogdanm	73:1efda918f0ba	32	#include "stm32f10x.h"
bogdanm	73:1efda918f0ba	33
bogdanm	73:1efda918f0ba	34	/** @addtogroup STM32F10x_StdPeriph_Driver
bogdanm	73:1efda918f0ba	35	* @{
bogdanm	73:1efda918f0ba	36	*/
bogdanm	73:1efda918f0ba	37
bogdanm	73:1efda918f0ba	38	/** @addtogroup TIM
bogdanm	73:1efda918f0ba	39	* @{
bogdanm	73:1efda918f0ba	40	*/
bogdanm	73:1efda918f0ba	41
bogdanm	73:1efda918f0ba	42	/** @defgroup TIM_Exported_Types
bogdanm	73:1efda918f0ba	43	* @{
bogdanm	73:1efda918f0ba	44	*/
bogdanm	73:1efda918f0ba	45
bogdanm	73:1efda918f0ba	46	/**
bogdanm	73:1efda918f0ba	47	* @brief TIM Time Base Init structure definition
bogdanm	73:1efda918f0ba	48	* @note This structure is used with all TIMx except for TIM6 and TIM7.
bogdanm	73:1efda918f0ba	49	*/
bogdanm	73:1efda918f0ba	50
bogdanm	73:1efda918f0ba	51	typedef struct
bogdanm	73:1efda918f0ba	52	{
bogdanm	73:1efda918f0ba	53	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	73:1efda918f0ba	54	This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm	73:1efda918f0ba	55
bogdanm	73:1efda918f0ba	56	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
bogdanm	73:1efda918f0ba	57	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	73:1efda918f0ba	58
bogdanm	73:1efda918f0ba	59	uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
bogdanm	73:1efda918f0ba	60	Auto-Reload Register at the next update event.
bogdanm	73:1efda918f0ba	61	This parameter must be a number between 0x0000 and 0xFFFF. */
bogdanm	73:1efda918f0ba	62
bogdanm	73:1efda918f0ba	63	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
bogdanm	73:1efda918f0ba	64	This parameter can be a value of @ref TIM_Clock_Division_CKD */
bogdanm	73:1efda918f0ba	65
bogdanm	73:1efda918f0ba	66	uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm	73:1efda918f0ba	67	reaches zero, an update event is generated and counting restarts
bogdanm	73:1efda918f0ba	68	from the RCR value (N).
bogdanm	73:1efda918f0ba	69	This means in PWM mode that (N+1) corresponds to:
bogdanm	73:1efda918f0ba	70	- the number of PWM periods in edge-aligned mode
bogdanm	73:1efda918f0ba	71	- the number of half PWM period in center-aligned mode
bogdanm	73:1efda918f0ba	72	This parameter must be a number between 0x00 and 0xFF.
bogdanm	73:1efda918f0ba	73	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	74	} TIM_TimeBaseInitTypeDef;
bogdanm	73:1efda918f0ba	75
bogdanm	73:1efda918f0ba	76	/**
bogdanm	73:1efda918f0ba	77	* @brief TIM Output Compare Init structure definition
bogdanm	73:1efda918f0ba	78	*/
bogdanm	73:1efda918f0ba	79
bogdanm	73:1efda918f0ba	80	typedef struct
bogdanm	73:1efda918f0ba	81	{
bogdanm	73:1efda918f0ba	82	uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
bogdanm	73:1efda918f0ba	83	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	73:1efda918f0ba	84
bogdanm	73:1efda918f0ba	85	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
bogdanm	73:1efda918f0ba	86	This parameter can be a value of @ref TIM_Output_Compare_state */
bogdanm	73:1efda918f0ba	87
bogdanm	73:1efda918f0ba	88	uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
bogdanm	73:1efda918f0ba	89	This parameter can be a value of @ref TIM_Output_Compare_N_state
bogdanm	73:1efda918f0ba	90	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	91
bogdanm	73:1efda918f0ba	92	uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	73:1efda918f0ba	93	This parameter can be a number between 0x0000 and 0xFFFF */
bogdanm	73:1efda918f0ba	94
bogdanm	73:1efda918f0ba	95	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
bogdanm	73:1efda918f0ba	96	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	73:1efda918f0ba	97
bogdanm	73:1efda918f0ba	98	uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm	73:1efda918f0ba	99	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm	73:1efda918f0ba	100	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	101
bogdanm	73:1efda918f0ba	102	uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	73:1efda918f0ba	103	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm	73:1efda918f0ba	104	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	105
bogdanm	73:1efda918f0ba	106	uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm	73:1efda918f0ba	107	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm	73:1efda918f0ba	108	@note This parameter is valid only for TIM1 and TIM8. */
bogdanm	73:1efda918f0ba	109	} TIM_OCInitTypeDef;
bogdanm	73:1efda918f0ba	110
bogdanm	73:1efda918f0ba	111	/**
bogdanm	73:1efda918f0ba	112	* @brief TIM Input Capture Init structure definition
bogdanm	73:1efda918f0ba	113	*/
bogdanm	73:1efda918f0ba	114
bogdanm	73:1efda918f0ba	115	typedef struct
bogdanm	73:1efda918f0ba	116	{
bogdanm	73:1efda918f0ba	117
bogdanm	73:1efda918f0ba	118	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
bogdanm	73:1efda918f0ba	119	This parameter can be a value of @ref TIM_Channel */
bogdanm	73:1efda918f0ba	120
bogdanm	73:1efda918f0ba	121	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	73:1efda918f0ba	122	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	73:1efda918f0ba	123
bogdanm	73:1efda918f0ba	124	uint16_t TIM_ICSelection; /*!< Specifies the input.
bogdanm	73:1efda918f0ba	125	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	73:1efda918f0ba	126
bogdanm	73:1efda918f0ba	127	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	73:1efda918f0ba	128	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	73:1efda918f0ba	129
bogdanm	73:1efda918f0ba	130	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
bogdanm	73:1efda918f0ba	131	This parameter can be a number between 0x0 and 0xF */
bogdanm	73:1efda918f0ba	132	} TIM_ICInitTypeDef;
bogdanm	73:1efda918f0ba	133
bogdanm	73:1efda918f0ba	134	/**
bogdanm	73:1efda918f0ba	135	* @brief BDTR structure definition
bogdanm	73:1efda918f0ba	136	* @note This structure is used only with TIM1 and TIM8.
bogdanm	73:1efda918f0ba	137	*/
bogdanm	73:1efda918f0ba	138
bogdanm	73:1efda918f0ba	139	typedef struct
bogdanm	73:1efda918f0ba	140	{
bogdanm	73:1efda918f0ba	141
bogdanm	73:1efda918f0ba	142	uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
bogdanm	73:1efda918f0ba	143	This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
bogdanm	73:1efda918f0ba	144
bogdanm	73:1efda918f0ba	145	uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
bogdanm	73:1efda918f0ba	146	This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
bogdanm	73:1efda918f0ba	147
bogdanm	73:1efda918f0ba	148	uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
bogdanm	73:1efda918f0ba	149	This parameter can be a value of @ref Lock_level */
bogdanm	73:1efda918f0ba	150
bogdanm	73:1efda918f0ba	151	uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
bogdanm	73:1efda918f0ba	152	switching-on of the outputs.
bogdanm	73:1efda918f0ba	153	This parameter can be a number between 0x00 and 0xFF */
bogdanm	73:1efda918f0ba	154
bogdanm	73:1efda918f0ba	155	uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
bogdanm	73:1efda918f0ba	156	This parameter can be a value of @ref Break_Input_enable_disable */
bogdanm	73:1efda918f0ba	157
bogdanm	73:1efda918f0ba	158	uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
bogdanm	73:1efda918f0ba	159	This parameter can be a value of @ref Break_Polarity */
bogdanm	73:1efda918f0ba	160
bogdanm	73:1efda918f0ba	161	uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
bogdanm	73:1efda918f0ba	162	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
bogdanm	73:1efda918f0ba	163	} TIM_BDTRInitTypeDef;
bogdanm	73:1efda918f0ba	164
bogdanm	73:1efda918f0ba	165	/** @defgroup TIM_Exported_constants
bogdanm	73:1efda918f0ba	166	* @{
bogdanm	73:1efda918f0ba	167	*/
bogdanm	73:1efda918f0ba	168
bogdanm	73:1efda918f0ba	169	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	170	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	171	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	172	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	173	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	174	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	175	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	176	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	177	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	178	((PERIPH) == TIM10)\|\| \
bogdanm	73:1efda918f0ba	179	((PERIPH) == TIM11)\|\| \
bogdanm	73:1efda918f0ba	180	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	181	((PERIPH) == TIM13)\|\| \
bogdanm	73:1efda918f0ba	182	((PERIPH) == TIM14)\|\| \
bogdanm	73:1efda918f0ba	183	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	184	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	185	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	186
bogdanm	73:1efda918f0ba	187	/* LIST1: TIM 1 and 8 */
bogdanm	73:1efda918f0ba	188	#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	189	((PERIPH) == TIM8))
bogdanm	73:1efda918f0ba	190
bogdanm	73:1efda918f0ba	191	/* LIST2: TIM 1, 8, 15 16 and 17 */
bogdanm	73:1efda918f0ba	192	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	193	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	194	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	195	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	196	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	197
bogdanm	73:1efda918f0ba	198	/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
bogdanm	73:1efda918f0ba	199	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	200	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	201	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	202	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	203	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	204	((PERIPH) == TIM8))
bogdanm	73:1efda918f0ba	205
bogdanm	73:1efda918f0ba	206	/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
bogdanm	73:1efda918f0ba	207	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	208	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	209	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	210	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	211	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	212	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	213	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	214	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	215	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	216
bogdanm	73:1efda918f0ba	217	/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
bogdanm	73:1efda918f0ba	218	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	219	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	220	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	221	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	222	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	223	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	224	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	225
bogdanm	73:1efda918f0ba	226	/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
bogdanm	73:1efda918f0ba	227	#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	228	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	229	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	230	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	231	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	232	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	233	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	234	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	235	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	236
bogdanm	73:1efda918f0ba	237	/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
bogdanm	73:1efda918f0ba	238	#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	239	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	240	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	241	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	242	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	243	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	244	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	245	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	246	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	247	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	248	((PERIPH) == TIM15))
bogdanm	73:1efda918f0ba	249
bogdanm	73:1efda918f0ba	250	/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
bogdanm	73:1efda918f0ba	251	#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	252	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	253	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	254	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	255	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	256	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	257	((PERIPH) == TIM9) \|\| \
bogdanm	73:1efda918f0ba	258	((PERIPH) == TIM10)\|\| \
bogdanm	73:1efda918f0ba	259	((PERIPH) == TIM11)\|\| \
bogdanm	73:1efda918f0ba	260	((PERIPH) == TIM12)\|\| \
bogdanm	73:1efda918f0ba	261	((PERIPH) == TIM13)\|\| \
bogdanm	73:1efda918f0ba	262	((PERIPH) == TIM14)\|\| \
bogdanm	73:1efda918f0ba	263	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	264	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	265	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	266
bogdanm	73:1efda918f0ba	267	/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
bogdanm	73:1efda918f0ba	268	#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
bogdanm	73:1efda918f0ba	269	((PERIPH) == TIM2) \|\| \
bogdanm	73:1efda918f0ba	270	((PERIPH) == TIM3) \|\| \
bogdanm	73:1efda918f0ba	271	((PERIPH) == TIM4) \|\| \
bogdanm	73:1efda918f0ba	272	((PERIPH) == TIM5) \|\| \
bogdanm	73:1efda918f0ba	273	((PERIPH) == TIM6) \|\| \
bogdanm	73:1efda918f0ba	274	((PERIPH) == TIM7) \|\| \
bogdanm	73:1efda918f0ba	275	((PERIPH) == TIM8) \|\| \
bogdanm	73:1efda918f0ba	276	((PERIPH) == TIM15)\|\| \
bogdanm	73:1efda918f0ba	277	((PERIPH) == TIM16)\|\| \
bogdanm	73:1efda918f0ba	278	((PERIPH) == TIM17))
bogdanm	73:1efda918f0ba	279
bogdanm	73:1efda918f0ba	280	/**
bogdanm	73:1efda918f0ba	281	* @}
bogdanm	73:1efda918f0ba	282	*/
bogdanm	73:1efda918f0ba	283
bogdanm	73:1efda918f0ba	284	/** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm	73:1efda918f0ba	285	* @{
bogdanm	73:1efda918f0ba	286	*/
bogdanm	73:1efda918f0ba	287
bogdanm	73:1efda918f0ba	288	#define TIM_OCMode_Timing ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	289	#define TIM_OCMode_Active ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	290	#define TIM_OCMode_Inactive ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	291	#define TIM_OCMode_Toggle ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	292	#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	293	#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	294	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
bogdanm	73:1efda918f0ba	295	((MODE) == TIM_OCMode_Active) \|\| \
bogdanm	73:1efda918f0ba	296	((MODE) == TIM_OCMode_Inactive) \|\| \
bogdanm	73:1efda918f0ba	297	((MODE) == TIM_OCMode_Toggle)\|\| \
bogdanm	73:1efda918f0ba	298	((MODE) == TIM_OCMode_PWM1) \|\| \
bogdanm	73:1efda918f0ba	299	((MODE) == TIM_OCMode_PWM2))
bogdanm	73:1efda918f0ba	300	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
bogdanm	73:1efda918f0ba	301	((MODE) == TIM_OCMode_Active) \|\| \
bogdanm	73:1efda918f0ba	302	((MODE) == TIM_OCMode_Inactive) \|\| \
bogdanm	73:1efda918f0ba	303	((MODE) == TIM_OCMode_Toggle)\|\| \
bogdanm	73:1efda918f0ba	304	((MODE) == TIM_OCMode_PWM1) \|\| \
bogdanm	73:1efda918f0ba	305	((MODE) == TIM_OCMode_PWM2) \|\| \
bogdanm	73:1efda918f0ba	306	((MODE) == TIM_ForcedAction_Active) \|\| \
bogdanm	73:1efda918f0ba	307	((MODE) == TIM_ForcedAction_InActive))
bogdanm	73:1efda918f0ba	308	/**
bogdanm	73:1efda918f0ba	309	* @}
bogdanm	73:1efda918f0ba	310	*/
bogdanm	73:1efda918f0ba	311
bogdanm	73:1efda918f0ba	312	/** @defgroup TIM_One_Pulse_Mode
bogdanm	73:1efda918f0ba	313	* @{
bogdanm	73:1efda918f0ba	314	*/
bogdanm	73:1efda918f0ba	315
bogdanm	73:1efda918f0ba	316	#define TIM_OPMode_Single ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	317	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	318	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
bogdanm	73:1efda918f0ba	319	((MODE) == TIM_OPMode_Repetitive))
bogdanm	73:1efda918f0ba	320	/**
bogdanm	73:1efda918f0ba	321	* @}
bogdanm	73:1efda918f0ba	322	*/
bogdanm	73:1efda918f0ba	323
bogdanm	73:1efda918f0ba	324	/** @defgroup TIM_Channel
bogdanm	73:1efda918f0ba	325	* @{
bogdanm	73:1efda918f0ba	326	*/
bogdanm	73:1efda918f0ba	327
bogdanm	73:1efda918f0ba	328	#define TIM_Channel_1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	329	#define TIM_Channel_2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	330	#define TIM_Channel_3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	331	#define TIM_Channel_4 ((uint16_t)0x000C)
bogdanm	73:1efda918f0ba	332	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	333	((CHANNEL) == TIM_Channel_2) \|\| \
bogdanm	73:1efda918f0ba	334	((CHANNEL) == TIM_Channel_3) \|\| \
bogdanm	73:1efda918f0ba	335	((CHANNEL) == TIM_Channel_4))
bogdanm	73:1efda918f0ba	336	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	337	((CHANNEL) == TIM_Channel_2))
bogdanm	73:1efda918f0ba	338	#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
bogdanm	73:1efda918f0ba	339	((CHANNEL) == TIM_Channel_2) \|\| \
bogdanm	73:1efda918f0ba	340	((CHANNEL) == TIM_Channel_3))
bogdanm	73:1efda918f0ba	341	/**
bogdanm	73:1efda918f0ba	342	* @}
bogdanm	73:1efda918f0ba	343	*/
bogdanm	73:1efda918f0ba	344
bogdanm	73:1efda918f0ba	345	/** @defgroup TIM_Clock_Division_CKD
bogdanm	73:1efda918f0ba	346	* @{
bogdanm	73:1efda918f0ba	347	*/
bogdanm	73:1efda918f0ba	348
bogdanm	73:1efda918f0ba	349	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	350	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	351	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	352	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
bogdanm	73:1efda918f0ba	353	((DIV) == TIM_CKD_DIV2) \|\| \
bogdanm	73:1efda918f0ba	354	((DIV) == TIM_CKD_DIV4))
bogdanm	73:1efda918f0ba	355	/**
bogdanm	73:1efda918f0ba	356	* @}
bogdanm	73:1efda918f0ba	357	*/
bogdanm	73:1efda918f0ba	358
bogdanm	73:1efda918f0ba	359	/** @defgroup TIM_Counter_Mode
bogdanm	73:1efda918f0ba	360	* @{
bogdanm	73:1efda918f0ba	361	*/
bogdanm	73:1efda918f0ba	362
bogdanm	73:1efda918f0ba	363	#define TIM_CounterMode_Up ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	364	#define TIM_CounterMode_Down ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	365	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	366	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	367	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	368	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
bogdanm	73:1efda918f0ba	369	((MODE) == TIM_CounterMode_Down) \|\| \
bogdanm	73:1efda918f0ba	370	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
bogdanm	73:1efda918f0ba	371	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
bogdanm	73:1efda918f0ba	372	((MODE) == TIM_CounterMode_CenterAligned3))
bogdanm	73:1efda918f0ba	373	/**
bogdanm	73:1efda918f0ba	374	* @}
bogdanm	73:1efda918f0ba	375	*/
bogdanm	73:1efda918f0ba	376
bogdanm	73:1efda918f0ba	377	/** @defgroup TIM_Output_Compare_Polarity
bogdanm	73:1efda918f0ba	378	* @{
bogdanm	73:1efda918f0ba	379	*/
bogdanm	73:1efda918f0ba	380
bogdanm	73:1efda918f0ba	381	#define TIM_OCPolarity_High ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	382	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	383	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
bogdanm	73:1efda918f0ba	384	((POLARITY) == TIM_OCPolarity_Low))
bogdanm	73:1efda918f0ba	385	/**
bogdanm	73:1efda918f0ba	386	* @}
bogdanm	73:1efda918f0ba	387	*/
bogdanm	73:1efda918f0ba	388
bogdanm	73:1efda918f0ba	389	/** @defgroup TIM_Output_Compare_N_Polarity
bogdanm	73:1efda918f0ba	390	* @{
bogdanm	73:1efda918f0ba	391	*/
bogdanm	73:1efda918f0ba	392
bogdanm	73:1efda918f0ba	393	#define TIM_OCNPolarity_High ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	394	#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	395	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) \|\| \
bogdanm	73:1efda918f0ba	396	((POLARITY) == TIM_OCNPolarity_Low))
bogdanm	73:1efda918f0ba	397	/**
bogdanm	73:1efda918f0ba	398	* @}
bogdanm	73:1efda918f0ba	399	*/
bogdanm	73:1efda918f0ba	400
bogdanm	73:1efda918f0ba	401	/** @defgroup TIM_Output_Compare_state
bogdanm	73:1efda918f0ba	402	* @{
bogdanm	73:1efda918f0ba	403	*/
bogdanm	73:1efda918f0ba	404
bogdanm	73:1efda918f0ba	405	#define TIM_OutputState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	406	#define TIM_OutputState_Enable ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	407	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
bogdanm	73:1efda918f0ba	408	((STATE) == TIM_OutputState_Enable))
bogdanm	73:1efda918f0ba	409	/**
bogdanm	73:1efda918f0ba	410	* @}
bogdanm	73:1efda918f0ba	411	*/
bogdanm	73:1efda918f0ba	412
bogdanm	73:1efda918f0ba	413	/** @defgroup TIM_Output_Compare_N_state
bogdanm	73:1efda918f0ba	414	* @{
bogdanm	73:1efda918f0ba	415	*/
bogdanm	73:1efda918f0ba	416
bogdanm	73:1efda918f0ba	417	#define TIM_OutputNState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	418	#define TIM_OutputNState_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	419	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) \|\| \
bogdanm	73:1efda918f0ba	420	((STATE) == TIM_OutputNState_Enable))
bogdanm	73:1efda918f0ba	421	/**
bogdanm	73:1efda918f0ba	422	* @}
bogdanm	73:1efda918f0ba	423	*/
bogdanm	73:1efda918f0ba	424
bogdanm	73:1efda918f0ba	425	/** @defgroup TIM_Capture_Compare_state
bogdanm	73:1efda918f0ba	426	* @{
bogdanm	73:1efda918f0ba	427	*/
bogdanm	73:1efda918f0ba	428
bogdanm	73:1efda918f0ba	429	#define TIM_CCx_Enable ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	430	#define TIM_CCx_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	431	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
bogdanm	73:1efda918f0ba	432	((CCX) == TIM_CCx_Disable))
bogdanm	73:1efda918f0ba	433	/**
bogdanm	73:1efda918f0ba	434	* @}
bogdanm	73:1efda918f0ba	435	*/
bogdanm	73:1efda918f0ba	436
bogdanm	73:1efda918f0ba	437	/** @defgroup TIM_Capture_Compare_N_state
bogdanm	73:1efda918f0ba	438	* @{
bogdanm	73:1efda918f0ba	439	*/
bogdanm	73:1efda918f0ba	440
bogdanm	73:1efda918f0ba	441	#define TIM_CCxN_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	442	#define TIM_CCxN_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	443	#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) \|\| \
bogdanm	73:1efda918f0ba	444	((CCXN) == TIM_CCxN_Disable))
bogdanm	73:1efda918f0ba	445	/**
bogdanm	73:1efda918f0ba	446	* @}
bogdanm	73:1efda918f0ba	447	*/
bogdanm	73:1efda918f0ba	448
bogdanm	73:1efda918f0ba	449	/** @defgroup Break_Input_enable_disable
bogdanm	73:1efda918f0ba	450	* @{
bogdanm	73:1efda918f0ba	451	*/
bogdanm	73:1efda918f0ba	452
bogdanm	73:1efda918f0ba	453	#define TIM_Break_Enable ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	454	#define TIM_Break_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	455	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) \|\| \
bogdanm	73:1efda918f0ba	456	((STATE) == TIM_Break_Disable))
bogdanm	73:1efda918f0ba	457	/**
bogdanm	73:1efda918f0ba	458	* @}
bogdanm	73:1efda918f0ba	459	*/
bogdanm	73:1efda918f0ba	460
bogdanm	73:1efda918f0ba	461	/** @defgroup Break_Polarity
bogdanm	73:1efda918f0ba	462	* @{
bogdanm	73:1efda918f0ba	463	*/
bogdanm	73:1efda918f0ba	464
bogdanm	73:1efda918f0ba	465	#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	466	#define TIM_BreakPolarity_High ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	467	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) \|\| \
bogdanm	73:1efda918f0ba	468	((POLARITY) == TIM_BreakPolarity_High))
bogdanm	73:1efda918f0ba	469	/**
bogdanm	73:1efda918f0ba	470	* @}
bogdanm	73:1efda918f0ba	471	*/
bogdanm	73:1efda918f0ba	472
bogdanm	73:1efda918f0ba	473	/** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm	73:1efda918f0ba	474	* @{
bogdanm	73:1efda918f0ba	475	*/
bogdanm	73:1efda918f0ba	476
bogdanm	73:1efda918f0ba	477	#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
bogdanm	73:1efda918f0ba	478	#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	479	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) \|\| \
bogdanm	73:1efda918f0ba	480	((STATE) == TIM_AutomaticOutput_Disable))
bogdanm	73:1efda918f0ba	481	/**
bogdanm	73:1efda918f0ba	482	* @}
bogdanm	73:1efda918f0ba	483	*/
bogdanm	73:1efda918f0ba	484
bogdanm	73:1efda918f0ba	485	/** @defgroup Lock_level
bogdanm	73:1efda918f0ba	486	* @{
bogdanm	73:1efda918f0ba	487	*/
bogdanm	73:1efda918f0ba	488
bogdanm	73:1efda918f0ba	489	#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	490	#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	491	#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	492	#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
bogdanm	73:1efda918f0ba	493	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) \|\| \
bogdanm	73:1efda918f0ba	494	((LEVEL) == TIM_LOCKLevel_1) \|\| \
bogdanm	73:1efda918f0ba	495	((LEVEL) == TIM_LOCKLevel_2) \|\| \
bogdanm	73:1efda918f0ba	496	((LEVEL) == TIM_LOCKLevel_3))
bogdanm	73:1efda918f0ba	497	/**
bogdanm	73:1efda918f0ba	498	* @}
bogdanm	73:1efda918f0ba	499	*/
bogdanm	73:1efda918f0ba	500
bogdanm	73:1efda918f0ba	501	/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm	73:1efda918f0ba	502	* @{
bogdanm	73:1efda918f0ba	503	*/
bogdanm	73:1efda918f0ba	504
bogdanm	73:1efda918f0ba	505	#define TIM_OSSIState_Enable ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	506	#define TIM_OSSIState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	507	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) \|\| \
bogdanm	73:1efda918f0ba	508	((STATE) == TIM_OSSIState_Disable))
bogdanm	73:1efda918f0ba	509	/**
bogdanm	73:1efda918f0ba	510	* @}
bogdanm	73:1efda918f0ba	511	*/
bogdanm	73:1efda918f0ba	512
bogdanm	73:1efda918f0ba	513	/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
bogdanm	73:1efda918f0ba	514	* @{
bogdanm	73:1efda918f0ba	515	*/
bogdanm	73:1efda918f0ba	516
bogdanm	73:1efda918f0ba	517	#define TIM_OSSRState_Enable ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	518	#define TIM_OSSRState_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	519	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) \|\| \
bogdanm	73:1efda918f0ba	520	((STATE) == TIM_OSSRState_Disable))
bogdanm	73:1efda918f0ba	521	/**
bogdanm	73:1efda918f0ba	522	* @}
bogdanm	73:1efda918f0ba	523	*/
bogdanm	73:1efda918f0ba	524
bogdanm	73:1efda918f0ba	525	/** @defgroup TIM_Output_Compare_Idle_State
bogdanm	73:1efda918f0ba	526	* @{
bogdanm	73:1efda918f0ba	527	*/
bogdanm	73:1efda918f0ba	528
bogdanm	73:1efda918f0ba	529	#define TIM_OCIdleState_Set ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	530	#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	531	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) \|\| \
bogdanm	73:1efda918f0ba	532	((STATE) == TIM_OCIdleState_Reset))
bogdanm	73:1efda918f0ba	533	/**
bogdanm	73:1efda918f0ba	534	* @}
bogdanm	73:1efda918f0ba	535	*/
bogdanm	73:1efda918f0ba	536
bogdanm	73:1efda918f0ba	537	/** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm	73:1efda918f0ba	538	* @{
bogdanm	73:1efda918f0ba	539	*/
bogdanm	73:1efda918f0ba	540
bogdanm	73:1efda918f0ba	541	#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	542	#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	543	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) \|\| \
bogdanm	73:1efda918f0ba	544	((STATE) == TIM_OCNIdleState_Reset))
bogdanm	73:1efda918f0ba	545	/**
bogdanm	73:1efda918f0ba	546	* @}
bogdanm	73:1efda918f0ba	547	*/
bogdanm	73:1efda918f0ba	548
bogdanm	73:1efda918f0ba	549	/** @defgroup TIM_Input_Capture_Polarity
bogdanm	73:1efda918f0ba	550	* @{
bogdanm	73:1efda918f0ba	551	*/
bogdanm	73:1efda918f0ba	552
bogdanm	73:1efda918f0ba	553	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	554	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	555	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
bogdanm	73:1efda918f0ba	556	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
bogdanm	73:1efda918f0ba	557	((POLARITY) == TIM_ICPolarity_Falling))
bogdanm	73:1efda918f0ba	558	#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
bogdanm	73:1efda918f0ba	559	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
bogdanm	73:1efda918f0ba	560	((POLARITY) == TIM_ICPolarity_BothEdge))
bogdanm	73:1efda918f0ba	561	/**
bogdanm	73:1efda918f0ba	562	* @}
bogdanm	73:1efda918f0ba	563	*/
bogdanm	73:1efda918f0ba	564
bogdanm	73:1efda918f0ba	565	/** @defgroup TIM_Input_Capture_Selection
bogdanm	73:1efda918f0ba	566	* @{
bogdanm	73:1efda918f0ba	567	*/
bogdanm	73:1efda918f0ba	568
bogdanm	73:1efda918f0ba	569	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	73:1efda918f0ba	570	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	73:1efda918f0ba	571	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	73:1efda918f0ba	572	connected to IC2, IC1, IC4 or IC3, respectively. */
bogdanm	73:1efda918f0ba	573	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
bogdanm	73:1efda918f0ba	574	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
bogdanm	73:1efda918f0ba	575	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
bogdanm	73:1efda918f0ba	576	((SELECTION) == TIM_ICSelection_TRC))
bogdanm	73:1efda918f0ba	577	/**
bogdanm	73:1efda918f0ba	578	* @}
bogdanm	73:1efda918f0ba	579	*/
bogdanm	73:1efda918f0ba	580
bogdanm	73:1efda918f0ba	581	/** @defgroup TIM_Input_Capture_Prescaler
bogdanm	73:1efda918f0ba	582	* @{
bogdanm	73:1efda918f0ba	583	*/
bogdanm	73:1efda918f0ba	584
bogdanm	73:1efda918f0ba	585	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
bogdanm	73:1efda918f0ba	586	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
bogdanm	73:1efda918f0ba	587	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
bogdanm	73:1efda918f0ba	588	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
bogdanm	73:1efda918f0ba	589	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	73:1efda918f0ba	590	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	73:1efda918f0ba	591	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	73:1efda918f0ba	592	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	73:1efda918f0ba	593	/**
bogdanm	73:1efda918f0ba	594	* @}
bogdanm	73:1efda918f0ba	595	*/
bogdanm	73:1efda918f0ba	596
bogdanm	73:1efda918f0ba	597	/** @defgroup TIM_interrupt_sources
bogdanm	73:1efda918f0ba	598	* @{
bogdanm	73:1efda918f0ba	599	*/
bogdanm	73:1efda918f0ba	600
bogdanm	73:1efda918f0ba	601	#define TIM_IT_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	602	#define TIM_IT_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	603	#define TIM_IT_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	604	#define TIM_IT_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	605	#define TIM_IT_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	606	#define TIM_IT_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	607	#define TIM_IT_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	608	#define TIM_IT_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	609	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
bogdanm	73:1efda918f0ba	610
bogdanm	73:1efda918f0ba	611	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
bogdanm	73:1efda918f0ba	612	((IT) == TIM_IT_CC1) \|\| \
bogdanm	73:1efda918f0ba	613	((IT) == TIM_IT_CC2) \|\| \
bogdanm	73:1efda918f0ba	614	((IT) == TIM_IT_CC3) \|\| \
bogdanm	73:1efda918f0ba	615	((IT) == TIM_IT_CC4) \|\| \
bogdanm	73:1efda918f0ba	616	((IT) == TIM_IT_COM) \|\| \
bogdanm	73:1efda918f0ba	617	((IT) == TIM_IT_Trigger) \|\| \
bogdanm	73:1efda918f0ba	618	((IT) == TIM_IT_Break))
bogdanm	73:1efda918f0ba	619	/**
bogdanm	73:1efda918f0ba	620	* @}
bogdanm	73:1efda918f0ba	621	*/
bogdanm	73:1efda918f0ba	622
bogdanm	73:1efda918f0ba	623	/** @defgroup TIM_DMA_Base_address
bogdanm	73:1efda918f0ba	624	* @{
bogdanm	73:1efda918f0ba	625	*/
bogdanm	73:1efda918f0ba	626
bogdanm	73:1efda918f0ba	627	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	628	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	629	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	630	#define TIM_DMABase_DIER ((uint16_t)0x0003)
bogdanm	73:1efda918f0ba	631	#define TIM_DMABase_SR ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	632	#define TIM_DMABase_EGR ((uint16_t)0x0005)
bogdanm	73:1efda918f0ba	633	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
bogdanm	73:1efda918f0ba	634	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
bogdanm	73:1efda918f0ba	635	#define TIM_DMABase_CCER ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	636	#define TIM_DMABase_CNT ((uint16_t)0x0009)
bogdanm	73:1efda918f0ba	637	#define TIM_DMABase_PSC ((uint16_t)0x000A)
bogdanm	73:1efda918f0ba	638	#define TIM_DMABase_ARR ((uint16_t)0x000B)
bogdanm	73:1efda918f0ba	639	#define TIM_DMABase_RCR ((uint16_t)0x000C)
bogdanm	73:1efda918f0ba	640	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
bogdanm	73:1efda918f0ba	641	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
bogdanm	73:1efda918f0ba	642	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
bogdanm	73:1efda918f0ba	643	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	644	#define TIM_DMABase_BDTR ((uint16_t)0x0011)
bogdanm	73:1efda918f0ba	645	#define TIM_DMABase_DCR ((uint16_t)0x0012)
bogdanm	73:1efda918f0ba	646	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	73:1efda918f0ba	647	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	73:1efda918f0ba	648	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	73:1efda918f0ba	649	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	73:1efda918f0ba	650	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	73:1efda918f0ba	651	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	73:1efda918f0ba	652	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	73:1efda918f0ba	653	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	73:1efda918f0ba	654	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	73:1efda918f0ba	655	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	73:1efda918f0ba	656	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	73:1efda918f0ba	657	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	73:1efda918f0ba	658	((BASE) == TIM_DMABase_RCR) \|\| \
bogdanm	73:1efda918f0ba	659	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	73:1efda918f0ba	660	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	73:1efda918f0ba	661	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	73:1efda918f0ba	662	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	73:1efda918f0ba	663	((BASE) == TIM_DMABase_BDTR) \|\| \
bogdanm	73:1efda918f0ba	664	((BASE) == TIM_DMABase_DCR))
bogdanm	73:1efda918f0ba	665	/**
bogdanm	73:1efda918f0ba	666	* @}
bogdanm	73:1efda918f0ba	667	*/
bogdanm	73:1efda918f0ba	668
bogdanm	73:1efda918f0ba	669	/** @defgroup TIM_DMA_Burst_Length
bogdanm	73:1efda918f0ba	670	* @{
bogdanm	73:1efda918f0ba	671	*/
bogdanm	73:1efda918f0ba	672
bogdanm	73:1efda918f0ba	673	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	674	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	675	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	676	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
bogdanm	73:1efda918f0ba	677	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	678	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
bogdanm	73:1efda918f0ba	679	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
bogdanm	73:1efda918f0ba	680	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
bogdanm	73:1efda918f0ba	681	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	682	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
bogdanm	73:1efda918f0ba	683	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
bogdanm	73:1efda918f0ba	684	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
bogdanm	73:1efda918f0ba	685	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
bogdanm	73:1efda918f0ba	686	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
bogdanm	73:1efda918f0ba	687	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
bogdanm	73:1efda918f0ba	688	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
bogdanm	73:1efda918f0ba	689	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	690	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
bogdanm	73:1efda918f0ba	691	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	73:1efda918f0ba	692	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	73:1efda918f0ba	693	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	73:1efda918f0ba	694	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	73:1efda918f0ba	695	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	73:1efda918f0ba	696	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	73:1efda918f0ba	697	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	73:1efda918f0ba	698	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	73:1efda918f0ba	699	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	73:1efda918f0ba	700	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	73:1efda918f0ba	701	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	73:1efda918f0ba	702	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	73:1efda918f0ba	703	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	73:1efda918f0ba	704	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	73:1efda918f0ba	705	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	73:1efda918f0ba	706	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	73:1efda918f0ba	707	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	73:1efda918f0ba	708	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	73:1efda918f0ba	709	/**
bogdanm	73:1efda918f0ba	710	* @}
bogdanm	73:1efda918f0ba	711	*/
bogdanm	73:1efda918f0ba	712
bogdanm	73:1efda918f0ba	713	/** @defgroup TIM_DMA_sources
bogdanm	73:1efda918f0ba	714	* @{
bogdanm	73:1efda918f0ba	715	*/
bogdanm	73:1efda918f0ba	716
bogdanm	73:1efda918f0ba	717	#define TIM_DMA_Update ((uint16_t)0x0100)
bogdanm	73:1efda918f0ba	718	#define TIM_DMA_CC1 ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	719	#define TIM_DMA_CC2 ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	720	#define TIM_DMA_CC3 ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	721	#define TIM_DMA_CC4 ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	722	#define TIM_DMA_COM ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	723	#define TIM_DMA_Trigger ((uint16_t)0x4000)
bogdanm	73:1efda918f0ba	724	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm	73:1efda918f0ba	725
bogdanm	73:1efda918f0ba	726	/**
bogdanm	73:1efda918f0ba	727	* @}
bogdanm	73:1efda918f0ba	728	*/
bogdanm	73:1efda918f0ba	729
bogdanm	73:1efda918f0ba	730	/** @defgroup TIM_External_Trigger_Prescaler
bogdanm	73:1efda918f0ba	731	* @{
bogdanm	73:1efda918f0ba	732	*/
bogdanm	73:1efda918f0ba	733
bogdanm	73:1efda918f0ba	734	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	735	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	736	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
bogdanm	73:1efda918f0ba	737	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
bogdanm	73:1efda918f0ba	738	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
bogdanm	73:1efda918f0ba	739	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
bogdanm	73:1efda918f0ba	740	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
bogdanm	73:1efda918f0ba	741	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
bogdanm	73:1efda918f0ba	742	/**
bogdanm	73:1efda918f0ba	743	* @}
bogdanm	73:1efda918f0ba	744	*/
bogdanm	73:1efda918f0ba	745
bogdanm	73:1efda918f0ba	746	/** @defgroup TIM_Internal_Trigger_Selection
bogdanm	73:1efda918f0ba	747	* @{
bogdanm	73:1efda918f0ba	748	*/
bogdanm	73:1efda918f0ba	749
bogdanm	73:1efda918f0ba	750	#define TIM_TS_ITR0 ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	751	#define TIM_TS_ITR1 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	752	#define TIM_TS_ITR2 ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	753	#define TIM_TS_ITR3 ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	754	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	755	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	756	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	757	#define TIM_TS_ETRF ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	758	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	73:1efda918f0ba	759	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	73:1efda918f0ba	760	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	73:1efda918f0ba	761	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	73:1efda918f0ba	762	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	73:1efda918f0ba	763	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	73:1efda918f0ba	764	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	73:1efda918f0ba	765	((SELECTION) == TIM_TS_ETRF))
bogdanm	73:1efda918f0ba	766	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	73:1efda918f0ba	767	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	73:1efda918f0ba	768	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	73:1efda918f0ba	769	((SELECTION) == TIM_TS_ITR3))
bogdanm	73:1efda918f0ba	770	/**
bogdanm	73:1efda918f0ba	771	* @}
bogdanm	73:1efda918f0ba	772	*/
bogdanm	73:1efda918f0ba	773
bogdanm	73:1efda918f0ba	774	/** @defgroup TIM_TIx_External_Clock_Source
bogdanm	73:1efda918f0ba	775	* @{
bogdanm	73:1efda918f0ba	776	*/
bogdanm	73:1efda918f0ba	777
bogdanm	73:1efda918f0ba	778	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	779	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	780	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	781	#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) \|\| \
bogdanm	73:1efda918f0ba	782	((SOURCE) == TIM_TIxExternalCLK1Source_TI2) \|\| \
bogdanm	73:1efda918f0ba	783	((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
bogdanm	73:1efda918f0ba	784	/**
bogdanm	73:1efda918f0ba	785	* @}
bogdanm	73:1efda918f0ba	786	*/
bogdanm	73:1efda918f0ba	787
bogdanm	73:1efda918f0ba	788	/** @defgroup TIM_External_Trigger_Polarity
bogdanm	73:1efda918f0ba	789	* @{
bogdanm	73:1efda918f0ba	790	*/
bogdanm	73:1efda918f0ba	791	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
bogdanm	73:1efda918f0ba	792	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	793	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
bogdanm	73:1efda918f0ba	794	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
bogdanm	73:1efda918f0ba	795	/**
bogdanm	73:1efda918f0ba	796	* @}
bogdanm	73:1efda918f0ba	797	*/
bogdanm	73:1efda918f0ba	798
bogdanm	73:1efda918f0ba	799	/** @defgroup TIM_Prescaler_Reload_Mode
bogdanm	73:1efda918f0ba	800	* @{
bogdanm	73:1efda918f0ba	801	*/
bogdanm	73:1efda918f0ba	802
bogdanm	73:1efda918f0ba	803	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	804	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	805	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
bogdanm	73:1efda918f0ba	806	((RELOAD) == TIM_PSCReloadMode_Immediate))
bogdanm	73:1efda918f0ba	807	/**
bogdanm	73:1efda918f0ba	808	* @}
bogdanm	73:1efda918f0ba	809	*/
bogdanm	73:1efda918f0ba	810
bogdanm	73:1efda918f0ba	811	/** @defgroup TIM_Forced_Action
bogdanm	73:1efda918f0ba	812	* @{
bogdanm	73:1efda918f0ba	813	*/
bogdanm	73:1efda918f0ba	814
bogdanm	73:1efda918f0ba	815	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	816	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	817	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
bogdanm	73:1efda918f0ba	818	((ACTION) == TIM_ForcedAction_InActive))
bogdanm	73:1efda918f0ba	819	/**
bogdanm	73:1efda918f0ba	820	* @}
bogdanm	73:1efda918f0ba	821	*/
bogdanm	73:1efda918f0ba	822
bogdanm	73:1efda918f0ba	823	/** @defgroup TIM_Encoder_Mode
bogdanm	73:1efda918f0ba	824	* @{
bogdanm	73:1efda918f0ba	825	*/
bogdanm	73:1efda918f0ba	826
bogdanm	73:1efda918f0ba	827	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	828	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	829	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
bogdanm	73:1efda918f0ba	830	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
bogdanm	73:1efda918f0ba	831	((MODE) == TIM_EncoderMode_TI2) \|\| \
bogdanm	73:1efda918f0ba	832	((MODE) == TIM_EncoderMode_TI12))
bogdanm	73:1efda918f0ba	833	/**
bogdanm	73:1efda918f0ba	834	* @}
bogdanm	73:1efda918f0ba	835	*/
bogdanm	73:1efda918f0ba	836
bogdanm	73:1efda918f0ba	837
bogdanm	73:1efda918f0ba	838	/** @defgroup TIM_Event_Source
bogdanm	73:1efda918f0ba	839	* @{
bogdanm	73:1efda918f0ba	840	*/
bogdanm	73:1efda918f0ba	841
bogdanm	73:1efda918f0ba	842	#define TIM_EventSource_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	843	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	844	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	845	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	846	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	847	#define TIM_EventSource_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	848	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	849	#define TIM_EventSource_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	850	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
bogdanm	73:1efda918f0ba	851
bogdanm	73:1efda918f0ba	852	/**
bogdanm	73:1efda918f0ba	853	* @}
bogdanm	73:1efda918f0ba	854	*/
bogdanm	73:1efda918f0ba	855
bogdanm	73:1efda918f0ba	856	/** @defgroup TIM_Update_Source
bogdanm	73:1efda918f0ba	857	* @{
bogdanm	73:1efda918f0ba	858	*/
bogdanm	73:1efda918f0ba	859
bogdanm	73:1efda918f0ba	860	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
bogdanm	73:1efda918f0ba	861	or the setting of UG bit, or an update generation
bogdanm	73:1efda918f0ba	862	through the slave mode controller. */
bogdanm	73:1efda918f0ba	863	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
bogdanm	73:1efda918f0ba	864	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
bogdanm	73:1efda918f0ba	865	((SOURCE) == TIM_UpdateSource_Regular))
bogdanm	73:1efda918f0ba	866	/**
bogdanm	73:1efda918f0ba	867	* @}
bogdanm	73:1efda918f0ba	868	*/
bogdanm	73:1efda918f0ba	869
bogdanm	73:1efda918f0ba	870	/** @defgroup TIM_Output_Compare_Preload_State
bogdanm	73:1efda918f0ba	871	* @{
bogdanm	73:1efda918f0ba	872	*/
bogdanm	73:1efda918f0ba	873
bogdanm	73:1efda918f0ba	874	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	875	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	876	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
bogdanm	73:1efda918f0ba	877	((STATE) == TIM_OCPreload_Disable))
bogdanm	73:1efda918f0ba	878	/**
bogdanm	73:1efda918f0ba	879	* @}
bogdanm	73:1efda918f0ba	880	*/
bogdanm	73:1efda918f0ba	881
bogdanm	73:1efda918f0ba	882	/** @defgroup TIM_Output_Compare_Fast_State
bogdanm	73:1efda918f0ba	883	* @{
bogdanm	73:1efda918f0ba	884	*/
bogdanm	73:1efda918f0ba	885
bogdanm	73:1efda918f0ba	886	#define TIM_OCFast_Enable ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	887	#define TIM_OCFast_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	888	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
bogdanm	73:1efda918f0ba	889	((STATE) == TIM_OCFast_Disable))
bogdanm	73:1efda918f0ba	890
bogdanm	73:1efda918f0ba	891	/**
bogdanm	73:1efda918f0ba	892	* @}
bogdanm	73:1efda918f0ba	893	*/
bogdanm	73:1efda918f0ba	894
bogdanm	73:1efda918f0ba	895	/** @defgroup TIM_Output_Compare_Clear_State
bogdanm	73:1efda918f0ba	896	* @{
bogdanm	73:1efda918f0ba	897	*/
bogdanm	73:1efda918f0ba	898
bogdanm	73:1efda918f0ba	899	#define TIM_OCClear_Enable ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	900	#define TIM_OCClear_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	901	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
bogdanm	73:1efda918f0ba	902	((STATE) == TIM_OCClear_Disable))
bogdanm	73:1efda918f0ba	903	/**
bogdanm	73:1efda918f0ba	904	* @}
bogdanm	73:1efda918f0ba	905	*/
bogdanm	73:1efda918f0ba	906
bogdanm	73:1efda918f0ba	907	/** @defgroup TIM_Trigger_Output_Source
bogdanm	73:1efda918f0ba	908	* @{
bogdanm	73:1efda918f0ba	909	*/
bogdanm	73:1efda918f0ba	910
bogdanm	73:1efda918f0ba	911	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	912	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	913	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	914	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
bogdanm	73:1efda918f0ba	915	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	916	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
bogdanm	73:1efda918f0ba	917	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
bogdanm	73:1efda918f0ba	918	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
bogdanm	73:1efda918f0ba	919	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
bogdanm	73:1efda918f0ba	920	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
bogdanm	73:1efda918f0ba	921	((SOURCE) == TIM_TRGOSource_Update) \|\| \
bogdanm	73:1efda918f0ba	922	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
bogdanm	73:1efda918f0ba	923	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
bogdanm	73:1efda918f0ba	924	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
bogdanm	73:1efda918f0ba	925	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
bogdanm	73:1efda918f0ba	926	((SOURCE) == TIM_TRGOSource_OC4Ref))
bogdanm	73:1efda918f0ba	927	/**
bogdanm	73:1efda918f0ba	928	* @}
bogdanm	73:1efda918f0ba	929	*/
bogdanm	73:1efda918f0ba	930
bogdanm	73:1efda918f0ba	931	/** @defgroup TIM_Slave_Mode
bogdanm	73:1efda918f0ba	932	* @{
bogdanm	73:1efda918f0ba	933	*/
bogdanm	73:1efda918f0ba	934
bogdanm	73:1efda918f0ba	935	#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	936	#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
bogdanm	73:1efda918f0ba	937	#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
bogdanm	73:1efda918f0ba	938	#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
bogdanm	73:1efda918f0ba	939	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
bogdanm	73:1efda918f0ba	940	((MODE) == TIM_SlaveMode_Gated) \|\| \
bogdanm	73:1efda918f0ba	941	((MODE) == TIM_SlaveMode_Trigger) \|\| \
bogdanm	73:1efda918f0ba	942	((MODE) == TIM_SlaveMode_External1))
bogdanm	73:1efda918f0ba	943	/**
bogdanm	73:1efda918f0ba	944	* @}
bogdanm	73:1efda918f0ba	945	*/
bogdanm	73:1efda918f0ba	946
bogdanm	73:1efda918f0ba	947	/** @defgroup TIM_Master_Slave_Mode
bogdanm	73:1efda918f0ba	948	* @{
bogdanm	73:1efda918f0ba	949	*/
bogdanm	73:1efda918f0ba	950
bogdanm	73:1efda918f0ba	951	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	952	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
bogdanm	73:1efda918f0ba	953	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
bogdanm	73:1efda918f0ba	954	((STATE) == TIM_MasterSlaveMode_Disable))
bogdanm	73:1efda918f0ba	955	/**
bogdanm	73:1efda918f0ba	956	* @}
bogdanm	73:1efda918f0ba	957	*/
bogdanm	73:1efda918f0ba	958
bogdanm	73:1efda918f0ba	959	/** @defgroup TIM_Flags
bogdanm	73:1efda918f0ba	960	* @{
bogdanm	73:1efda918f0ba	961	*/
bogdanm	73:1efda918f0ba	962
bogdanm	73:1efda918f0ba	963	#define TIM_FLAG_Update ((uint16_t)0x0001)
bogdanm	73:1efda918f0ba	964	#define TIM_FLAG_CC1 ((uint16_t)0x0002)
bogdanm	73:1efda918f0ba	965	#define TIM_FLAG_CC2 ((uint16_t)0x0004)
bogdanm	73:1efda918f0ba	966	#define TIM_FLAG_CC3 ((uint16_t)0x0008)
bogdanm	73:1efda918f0ba	967	#define TIM_FLAG_CC4 ((uint16_t)0x0010)
bogdanm	73:1efda918f0ba	968	#define TIM_FLAG_COM ((uint16_t)0x0020)
bogdanm	73:1efda918f0ba	969	#define TIM_FLAG_Trigger ((uint16_t)0x0040)
bogdanm	73:1efda918f0ba	970	#define TIM_FLAG_Break ((uint16_t)0x0080)
bogdanm	73:1efda918f0ba	971	#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
bogdanm	73:1efda918f0ba	972	#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
bogdanm	73:1efda918f0ba	973	#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
bogdanm	73:1efda918f0ba	974	#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
bogdanm	73:1efda918f0ba	975	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
bogdanm	73:1efda918f0ba	976	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	73:1efda918f0ba	977	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	73:1efda918f0ba	978	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	73:1efda918f0ba	979	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	73:1efda918f0ba	980	((FLAG) == TIM_FLAG_COM) \|\| \
bogdanm	73:1efda918f0ba	981	((FLAG) == TIM_FLAG_Trigger) \|\| \
bogdanm	73:1efda918f0ba	982	((FLAG) == TIM_FLAG_Break) \|\| \
bogdanm	73:1efda918f0ba	983	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	73:1efda918f0ba	984	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	73:1efda918f0ba	985	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	73:1efda918f0ba	986	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	73:1efda918f0ba	987
bogdanm	73:1efda918f0ba	988
bogdanm	73:1efda918f0ba	989	#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
bogdanm	73:1efda918f0ba	990	/**
bogdanm	73:1efda918f0ba	991	* @}
bogdanm	73:1efda918f0ba	992	*/
bogdanm	73:1efda918f0ba	993
bogdanm	73:1efda918f0ba	994	/** @defgroup TIM_Input_Capture_Filer_Value
bogdanm	73:1efda918f0ba	995	* @{
bogdanm	73:1efda918f0ba	996	*/
bogdanm	73:1efda918f0ba	997
bogdanm	73:1efda918f0ba	998	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	73:1efda918f0ba	999	/**
bogdanm	73:1efda918f0ba	1000	* @}
bogdanm	73:1efda918f0ba	1001	*/
bogdanm	73:1efda918f0ba	1002
bogdanm	73:1efda918f0ba	1003	/** @defgroup TIM_External_Trigger_Filter
bogdanm	73:1efda918f0ba	1004	* @{
bogdanm	73:1efda918f0ba	1005	*/
bogdanm	73:1efda918f0ba	1006
bogdanm	73:1efda918f0ba	1007	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
bogdanm	73:1efda918f0ba	1008	/**
bogdanm	73:1efda918f0ba	1009	* @}
bogdanm	73:1efda918f0ba	1010	*/
bogdanm	73:1efda918f0ba	1011
bogdanm	73:1efda918f0ba	1012	/** @defgroup TIM_Legacy
bogdanm	73:1efda918f0ba	1013	* @{
bogdanm	73:1efda918f0ba	1014	*/
bogdanm	73:1efda918f0ba	1015
bogdanm	73:1efda918f0ba	1016	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
bogdanm	73:1efda918f0ba	1017	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
bogdanm	73:1efda918f0ba	1018	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
bogdanm	73:1efda918f0ba	1019	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
bogdanm	73:1efda918f0ba	1020	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
bogdanm	73:1efda918f0ba	1021	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
bogdanm	73:1efda918f0ba	1022	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
bogdanm	73:1efda918f0ba	1023	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
bogdanm	73:1efda918f0ba	1024	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
bogdanm	73:1efda918f0ba	1025	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
bogdanm	73:1efda918f0ba	1026	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
bogdanm	73:1efda918f0ba	1027	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
bogdanm	73:1efda918f0ba	1028	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
bogdanm	73:1efda918f0ba	1029	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
bogdanm	73:1efda918f0ba	1030	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
bogdanm	73:1efda918f0ba	1031	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
bogdanm	73:1efda918f0ba	1032	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
bogdanm	73:1efda918f0ba	1033	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
bogdanm	73:1efda918f0ba	1034	/**
bogdanm	73:1efda918f0ba	1035	* @}
bogdanm	73:1efda918f0ba	1036	*/
bogdanm	73:1efda918f0ba	1037
bogdanm	73:1efda918f0ba	1038	/**
bogdanm	73:1efda918f0ba	1039	* @}
bogdanm	73:1efda918f0ba	1040	*/
bogdanm	73:1efda918f0ba	1041
bogdanm	73:1efda918f0ba	1042	/** @defgroup TIM_Exported_Macros
bogdanm	73:1efda918f0ba	1043	* @{
bogdanm	73:1efda918f0ba	1044	*/
bogdanm	73:1efda918f0ba	1045
bogdanm	73:1efda918f0ba	1046	/**
bogdanm	73:1efda918f0ba	1047	* @}
bogdanm	73:1efda918f0ba	1048	*/
bogdanm	73:1efda918f0ba	1049
bogdanm	73:1efda918f0ba	1050	/** @defgroup TIM_Exported_Functions
bogdanm	73:1efda918f0ba	1051	* @{
bogdanm	73:1efda918f0ba	1052	*/
bogdanm	73:1efda918f0ba	1053
bogdanm	73:1efda918f0ba	1054	void TIM_DeInit(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1055	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm	73:1efda918f0ba	1056	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1057	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1058	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1059	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1060	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1061	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1062	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
bogdanm	73:1efda918f0ba	1063	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
bogdanm	73:1efda918f0ba	1064	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
bogdanm	73:1efda918f0ba	1065	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
bogdanm	73:1efda918f0ba	1066	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
bogdanm	73:1efda918f0ba	1067	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1068	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1069	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1070	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
bogdanm	73:1efda918f0ba	1071	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
bogdanm	73:1efda918f0ba	1072	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1073	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1074	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm	73:1efda918f0ba	1075	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
bogdanm	73:1efda918f0ba	1076	uint16_t TIM_ICPolarity, uint16_t ICFilter);
bogdanm	73:1efda918f0ba	1077	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm	73:1efda918f0ba	1078	uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1079	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
bogdanm	73:1efda918f0ba	1080	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1081	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
bogdanm	73:1efda918f0ba	1082	uint16_t ExtTRGFilter);
bogdanm	73:1efda918f0ba	1083	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
bogdanm	73:1efda918f0ba	1084	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
bogdanm	73:1efda918f0ba	1085	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
bogdanm	73:1efda918f0ba	1086	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
bogdanm	73:1efda918f0ba	1087	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
bogdanm	73:1efda918f0ba	1088	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1089	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1090	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1091	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
bogdanm	73:1efda918f0ba	1092	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1093	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1094	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1095	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1096	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1097	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1098	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1099	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
bogdanm	73:1efda918f0ba	1100	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1101	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1102	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1103	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
bogdanm	73:1efda918f0ba	1104	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1105	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1106	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1107	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
bogdanm	73:1efda918f0ba	1108	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1109	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1110	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1111	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1112	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1113	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
bogdanm	73:1efda918f0ba	1114	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
bogdanm	73:1efda918f0ba	1115	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
bogdanm	73:1efda918f0ba	1116	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
bogdanm	73:1efda918f0ba	1117	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
bogdanm	73:1efda918f0ba	1118	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1119	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
bogdanm	73:1efda918f0ba	1120	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
bogdanm	73:1efda918f0ba	1121	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
bogdanm	73:1efda918f0ba	1122	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
bogdanm	73:1efda918f0ba	1123	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
bogdanm	73:1efda918f0ba	1124	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
bogdanm	73:1efda918f0ba	1125	void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
bogdanm	73:1efda918f0ba	1126	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
bogdanm	73:1efda918f0ba	1127	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
bogdanm	73:1efda918f0ba	1128	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
bogdanm	73:1efda918f0ba	1129	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
bogdanm	73:1efda918f0ba	1130	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
bogdanm	73:1efda918f0ba	1131	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1132	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1133	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1134	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
bogdanm	73:1efda918f0ba	1135	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
bogdanm	73:1efda918f0ba	1136	uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1137	uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1138	uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1139	uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1140	uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1141	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
bogdanm	73:1efda918f0ba	1142	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
bogdanm	73:1efda918f0ba	1143	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
bogdanm	73:1efda918f0ba	1144	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm	73:1efda918f0ba	1145	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
bogdanm	73:1efda918f0ba	1146
bogdanm	73:1efda918f0ba	1147	#ifdef __cplusplus
bogdanm	73:1efda918f0ba	1148	}
bogdanm	73:1efda918f0ba	1149	#endif
bogdanm	73:1efda918f0ba	1150
bogdanm	73:1efda918f0ba	1151	#endif /__STM32F10x_TIM_H /
bogdanm	73:1efda918f0ba	1152	/**
bogdanm	73:1efda918f0ba	1153	* @}
bogdanm	73:1efda918f0ba	1154	*/
bogdanm	73:1efda918f0ba	1155
bogdanm	73:1efda918f0ba	1156	/**
bogdanm	73:1efda918f0ba	1157	* @}
bogdanm	73:1efda918f0ba	1158	*/
bogdanm	73:1efda918f0ba	1159
bogdanm	73:1efda918f0ba	1160	/**
bogdanm	73:1efda918f0ba	1161	* @}
bogdanm	73:1efda918f0ba	1162	*/
bogdanm	73:1efda918f0ba	1163
bogdanm	73:1efda918f0ba	1164	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	25 Jun 2015
Imports:	24
Forks:	0
Commits:	103
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TARGET_NUCLEO_F103RB/stm32f10x_tim.h@73:1efda918f0ba, 2013-12-09 (annotated)

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