Johannes Stratmann / mbed-dev

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targets/cmsis/TARGET_WIZNET/TARGET_W7500x/system_W7500x.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file system_CMSDK_CM0.c
<> 144:ef7eb2e8f9f7 3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
<> 144:ef7eb2e8f9f7 4 * Device CMSDK
<> 144:ef7eb2e8f9f7 5 * @version V3.01
<> 144:ef7eb2e8f9f7 6 * @date 06. March 2012
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @note
<> 144:ef7eb2e8f9f7 9 * Copyright (C) 2010-2012 ARM Limited. All rights reserved.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @par
<> 144:ef7eb2e8f9f7 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 144:ef7eb2e8f9f7 13 * processor based microcontrollers. This file can be freely distributed
<> 144:ef7eb2e8f9f7 14 * within development tools that are supporting such ARM based processors.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * @par
<> 144:ef7eb2e8f9f7 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 144:ef7eb2e8f9f7 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 ******************************************************************************/
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #include "system_W7500x.h"
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 DEFINES
<> 144:ef7eb2e8f9f7 31 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 32 //#define SYSCLK_EXTERN_OSC
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 37 Clock Variable definitions
<> 144:ef7eb2e8f9f7 38 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 39 uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */
<> 144:ef7eb2e8f9f7 40 uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /*----------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 44 Clock functions
<> 144:ef7eb2e8f9f7 45 *----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 46 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
<> 144:ef7eb2e8f9f7 47 {
<> 144:ef7eb2e8f9f7 48 uint8_t M,N,OD;
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 #ifdef SYSCLK_EXTERN_OSC
<> 144:ef7eb2e8f9f7 51 CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
<> 144:ef7eb2e8f9f7 52 #else
<> 144:ef7eb2e8f9f7 53 CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55 OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
<> 144:ef7eb2e8f9f7 56 N = (CRG->PLL_FCR >> 8 ) & 0x3F;
<> 144:ef7eb2e8f9f7 57 M = (CRG->PLL_FCR >> 16) & 0x3F;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #ifdef SYSCLK_EXTERN_OSC
<> 144:ef7eb2e8f9f7 60 SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
<> 144:ef7eb2e8f9f7 61 #else
<> 144:ef7eb2e8f9f7 62 SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
<> 144:ef7eb2e8f9f7 63 #endif
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 uint32_t GetSystemClock()
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /**
<> 144:ef7eb2e8f9f7 73 * Initialize the system
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * @param none
<> 144:ef7eb2e8f9f7 76 * @return none
<> 144:ef7eb2e8f9f7 77 *
<> 144:ef7eb2e8f9f7 78 * @brief Setup the microcontroller system.
<> 144:ef7eb2e8f9f7 79 * Initialize the System.
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81 void SystemInit (void)
<> 144:ef7eb2e8f9f7 82 {
<> 144:ef7eb2e8f9f7 83 uint8_t M,N,OD;
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
<> 144:ef7eb2e8f9f7 86 (*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // Set PLL input frequency
<> 144:ef7eb2e8f9f7 90 #ifdef SYSCLK_EXTERN_OSC
<> 144:ef7eb2e8f9f7 91 CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
<> 144:ef7eb2e8f9f7 92 #else
<> 144:ef7eb2e8f9f7 93 CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
<> 144:ef7eb2e8f9f7 94 #endif
<> 144:ef7eb2e8f9f7 95 OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
<> 144:ef7eb2e8f9f7 96 N = (CRG->PLL_FCR >> 8 ) & 0x3F;
<> 144:ef7eb2e8f9f7 97 M = (CRG->PLL_FCR >> 16) & 0x3F;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 #ifdef SYSCLK_EXTERN_OSC
<> 144:ef7eb2e8f9f7 100 SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
<> 144:ef7eb2e8f9f7 101 #else
<> 144:ef7eb2e8f9f7 102 SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
<> 144:ef7eb2e8f9f7 103 #endif
<> 144:ef7eb2e8f9f7 104 }