Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file uart_16c550_map.h
<> 144:ef7eb2e8f9f7 4 * @brief UART module hardware register map.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor.
<> 144:ef7eb2e8f9f7 7 * $Rev: 2615 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup uart_16c550
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 25 * <p>
<> 144:ef7eb2e8f9f7 26 * <a href="../pdf/IPC7202_UART_APB_DS_v1P4.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 27 * IPC7202 APB UART Design Specification v1.4 </a>
<> 144:ef7eb2e8f9f7 28 * </p>
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifndef UART_16C550_MAP_H_
<> 144:ef7eb2e8f9f7 32 #define UART_16C550_MAP_H_
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "architecture.h"
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 37 #pragma anon_unions
<> 144:ef7eb2e8f9f7 38 #endif
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #define DCTS (uint8_t)0x01
<> 144:ef7eb2e8f9f7 41 #define DDSR (uint8_t)0x02
<> 144:ef7eb2e8f9f7 42 #define TERI (uint8_t)0x04
<> 144:ef7eb2e8f9f7 43 #define DDCD (uint8_t)0x08
<> 144:ef7eb2e8f9f7 44 //#define CTS (uint8_t)0x10
<> 144:ef7eb2e8f9f7 45 #define DSR (uint8_t)0x20
<> 144:ef7eb2e8f9f7 46 #define RI (uint8_t)0x40
<> 144:ef7eb2e8f9f7 47 #define DCD (uint8_t)0x80
<> 144:ef7eb2e8f9f7 48 #define IER_PWRDNENACTIVE ((uint8_t)(1<<5))
<> 144:ef7eb2e8f9f7 49 #define IER_MSI ((uint8_t)(1<<3))
<> 144:ef7eb2e8f9f7 50 #define IER_RLSI ((uint8_t)(1<<2))
<> 144:ef7eb2e8f9f7 51 #define IER_THRI ((uint8_t)(1<<1))
<> 144:ef7eb2e8f9f7 52 #define IER_RDAI ((uint8_t)(1<<0))
<> 144:ef7eb2e8f9f7 53 #define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00))
<> 144:ef7eb2e8f9f7 54 #define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40))
<> 144:ef7eb2e8f9f7 55 #define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80))
<> 144:ef7eb2e8f9f7 56 #define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0))
<> 144:ef7eb2e8f9f7 57 #define FCR_DMA_MODE_0 ((uint8_t)(0<<3))
<> 144:ef7eb2e8f9f7 58 #define FCR_DMA_MODE_1 ((uint8_t)(1<<3))
<> 144:ef7eb2e8f9f7 59 #define FCR_TXFIFO_RESET ((uint8_t)(1<<2))
<> 144:ef7eb2e8f9f7 60 #define FCR_RXFIFO_RESET ((uint8_t)(1<<1))
<> 144:ef7eb2e8f9f7 61 #define FCR_FIFO_ENABLE ((uint8_t)(1<<0))
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** UART HW Structure Overlay */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 /** Base address + 0x0: Receive, transmit and divisor_LSB offset */
<> 144:ef7eb2e8f9f7 66 union {
<> 144:ef7eb2e8f9f7 67 __I uint32_t RBR; /**< Received data (8 bits wide) / read only */
<> 144:ef7eb2e8f9f7 68 __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
<> 144:ef7eb2e8f9f7 69 __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
<> 144:ef7eb2e8f9f7 70 };
<> 144:ef7eb2e8f9f7 71 /** Base address + 0x4: Interrupt enable and divisor_MSB offset */
<> 144:ef7eb2e8f9f7 72 union {
<> 144:ef7eb2e8f9f7 73 union {
<> 144:ef7eb2e8f9f7 74 struct {
<> 144:ef7eb2e8f9f7 75 __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
<> 144:ef7eb2e8f9f7 79 __IO uint32_t PAD0 :1;
<> 144:ef7eb2e8f9f7 80 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t PAD1 :2;
<> 144:ef7eb2e8f9f7 82 } BITS;
<> 144:ef7eb2e8f9f7 83 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 84 } IER; /** Interrupt enable offset 0x04 */
<> 144:ef7eb2e8f9f7 85 __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
<> 144:ef7eb2e8f9f7 86 };
<> 144:ef7eb2e8f9f7 87 /** Base address + 0x8: Interrupt status and fifo control offset*/
<> 144:ef7eb2e8f9f7 88 union {
<> 144:ef7eb2e8f9f7 89 union {
<> 144:ef7eb2e8f9f7 90 struct {
<> 144:ef7eb2e8f9f7 91 __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
<> 144:ef7eb2e8f9f7 92 __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
<> 144:ef7eb2e8f9f7 93 __I uint32_t PAD0 :2;
<> 144:ef7eb2e8f9f7 94 __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
<> 144:ef7eb2e8f9f7 95 } BITS;
<> 144:ef7eb2e8f9f7 96 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 97 } IIR; /** Interrupt status and fifo status offset 0x08 */
<> 144:ef7eb2e8f9f7 98 union {
<> 144:ef7eb2e8f9f7 99 struct {
<> 144:ef7eb2e8f9f7 100 __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
<> 144:ef7eb2e8f9f7 101 __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
<> 144:ef7eb2e8f9f7 102 __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
<> 144:ef7eb2e8f9f7 103 __O uint32_t DMA_SEL :1; /**< DMA mode select */
<> 144:ef7eb2e8f9f7 104 __O uint32_t PAD0 :2;
<> 144:ef7eb2e8f9f7 105 __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
<> 144:ef7eb2e8f9f7 106 } BITS;
<> 144:ef7eb2e8f9f7 107 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 108 } FCR; /** Fifo control offset 0x08 */
<> 144:ef7eb2e8f9f7 109 };
<> 144:ef7eb2e8f9f7 110 /** Base address + 0xC: Line control offset */
<> 144:ef7eb2e8f9f7 111 union {
<> 144:ef7eb2e8f9f7 112 struct {
<> 144:ef7eb2e8f9f7 113 __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
<> 144:ef7eb2e8f9f7 114 __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
<> 144:ef7eb2e8f9f7 115 __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
<> 144:ef7eb2e8f9f7 116 __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
<> 144:ef7eb2e8f9f7 117 __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
<> 144:ef7eb2e8f9f7 118 } BITS;
<> 144:ef7eb2e8f9f7 119 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 120 } LCR; /** Line control offset 0x0C */
<> 144:ef7eb2e8f9f7 121 /** Base address + 0x10: Modem control offset */
<> 144:ef7eb2e8f9f7 122 union {
<> 144:ef7eb2e8f9f7 123 struct {
<> 144:ef7eb2e8f9f7 124 __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
<> 144:ef7eb2e8f9f7 125 __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
<> 144:ef7eb2e8f9f7 126 __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
<> 144:ef7eb2e8f9f7 127 __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
<> 144:ef7eb2e8f9f7 128 __IO uint32_t PAD0 :3;
<> 144:ef7eb2e8f9f7 129 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
<> 144:ef7eb2e8f9f7 130 } BITS;
<> 144:ef7eb2e8f9f7 131 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 132 } MCR; /**< Modem control offset 0x10 */
<> 144:ef7eb2e8f9f7 133 /** Base address + 0x14: Line status offset */
<> 144:ef7eb2e8f9f7 134 union {
<> 144:ef7eb2e8f9f7 135 struct {
<> 144:ef7eb2e8f9f7 136 __O uint32_t READY :1; /**< Rx data available */
<> 144:ef7eb2e8f9f7 137 __O uint32_t OVERRUN_ERR :1; /**< Overrun error */
<> 144:ef7eb2e8f9f7 138 __O uint32_t PARITY_ERR :1; /**< Parity error */
<> 144:ef7eb2e8f9f7 139 __O uint32_t FRAME_ERR :1; /**< Framing error */
<> 144:ef7eb2e8f9f7 140 __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
<> 144:ef7eb2e8f9f7 141 __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
<> 144:ef7eb2e8f9f7 142 __O uint32_t TX_EMPTY :1; /**< Transmitter empty */
<> 144:ef7eb2e8f9f7 143 __O uint32_t FIFO_ERR :1; /**< Receive fifo error */
<> 144:ef7eb2e8f9f7 144 } BITS;
<> 144:ef7eb2e8f9f7 145 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 146 } LSR; /**< Line status offset 0x14 */
<> 144:ef7eb2e8f9f7 147 /** Base address + 0x18: Modem status offset */
<> 144:ef7eb2e8f9f7 148 union {
<> 144:ef7eb2e8f9f7 149 struct {
<> 144:ef7eb2e8f9f7 150 __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
<> 144:ef7eb2e8f9f7 151 __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
<> 144:ef7eb2e8f9f7 152 __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
<> 144:ef7eb2e8f9f7 153 __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
<> 144:ef7eb2e8f9f7 154 __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
<> 144:ef7eb2e8f9f7 155 __O uint32_t CURR_DSRN :1; /**< DSR current state */
<> 144:ef7eb2e8f9f7 156 __O uint32_t CURR_RIN :1; /**< RI current state */
<> 144:ef7eb2e8f9f7 157 __O uint32_t CURR_DCDN :1; /**< DCD current state */
<> 144:ef7eb2e8f9f7 158 } BITS;
<> 144:ef7eb2e8f9f7 159 __O uint32_t WORD;
<> 144:ef7eb2e8f9f7 160 } MSR; /**< Modem status offset 0x18 */
<> 144:ef7eb2e8f9f7 161 /** Base address + 0x1C: Scratch offset*/
<> 144:ef7eb2e8f9f7 162 __IO uint32_t SCR; /**< Scratch pad register */
<> 144:ef7eb2e8f9f7 163 } Uart16C550Reg_t, *Uart16C550Reg_pt;
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 #endif /* UART_16C550_MAP_H_ */