Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file spi_ipc7207_map.h
<> 144:ef7eb2e8f9f7 4 * @brief SPI IPC 7207 HW register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 2110 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup spi_ipc7207
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * <p>
<> 144:ef7eb2e8f9f7 25 * SPI HW register map description
<> 144:ef7eb2e8f9f7 26 * </p>
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 29 * <p>
<> 144:ef7eb2e8f9f7 30 * <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank">
<> 144:ef7eb2e8f9f7 31 * IPC7207 APB SPI Design Specification v1.2 </a>
<> 144:ef7eb2e8f9f7 32 * </p>
<> 144:ef7eb2e8f9f7 33 */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #ifndef SPI_IPC7207_MAP_H_
<> 144:ef7eb2e8f9f7 36 #define SPI_IPC7207_MAP_H_
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 #include "architecture.h"
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /** SPI HW Structure Overlay */
<> 144:ef7eb2e8f9f7 41 typedef struct {
<> 144:ef7eb2e8f9f7 42 __O uint32_t TX_DATA;
<> 144:ef7eb2e8f9f7 43 __I uint32_t RX_DATA;
<> 144:ef7eb2e8f9f7 44 __IO uint32_t FDIV;
<> 144:ef7eb2e8f9f7 45 union {
<> 144:ef7eb2e8f9f7 46 struct {
<> 144:ef7eb2e8f9f7 47 __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */
<> 144:ef7eb2e8f9f7 54 } BITS;
<> 144:ef7eb2e8f9f7 55 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 56 } CONTROL;
<> 144:ef7eb2e8f9f7 57 union {
<> 144:ef7eb2e8f9f7 58 struct {
<> 144:ef7eb2e8f9f7 59 __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */
<> 144:ef7eb2e8f9f7 60 __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */
<> 144:ef7eb2e8f9f7 61 __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */
<> 144:ef7eb2e8f9f7 62 __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
<> 144:ef7eb2e8f9f7 63 __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */
<> 144:ef7eb2e8f9f7 64 __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */
<> 144:ef7eb2e8f9f7 65 __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */
<> 144:ef7eb2e8f9f7 66 __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */
<> 144:ef7eb2e8f9f7 67 } BITS;
<> 144:ef7eb2e8f9f7 68 __I uint32_t WORD;
<> 144:ef7eb2e8f9f7 69 } STATUS;
<> 144:ef7eb2e8f9f7 70 union {
<> 144:ef7eb2e8f9f7 71 struct {
<> 144:ef7eb2e8f9f7 72 __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */
<> 144:ef7eb2e8f9f7 73 __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */
<> 144:ef7eb2e8f9f7 74 } BITS;
<> 144:ef7eb2e8f9f7 75 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 76 } SLAVE_SELECT;
<> 144:ef7eb2e8f9f7 77 __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */
<> 144:ef7eb2e8f9f7 79 __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */
<> 144:ef7eb2e8f9f7 80 __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */
<> 144:ef7eb2e8f9f7 81 __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */
<> 144:ef7eb2e8f9f7 82 __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */
<> 144:ef7eb2e8f9f7 83 __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */
<> 144:ef7eb2e8f9f7 84 __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */
<> 144:ef7eb2e8f9f7 85 } SpiIpc7207Reg_t, *SpiIpc7207Reg_pt;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #endif /* SPI_IPC7207_MAP_H_ */