Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rtc.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of a Rtc driver
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3525 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup rtc
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
<> 144:ef7eb2e8f9f7 25 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
<> 144:ef7eb2e8f9f7 26 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
<> 144:ef7eb2e8f9f7 27 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
<> 144:ef7eb2e8f9f7 28 * Use the Reset bit in the Control Register to reset the counters to their default values.
<> 144:ef7eb2e8f9f7 29 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
<> 144:ef7eb2e8f9f7 30 * internally to time the incrementing of the Seconds Counter.
<> 144:ef7eb2e8f9f7 31 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
<> 144:ef7eb2e8f9f7 32 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
<> 144:ef7eb2e8f9f7 33 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
<> 144:ef7eb2e8f9f7 34 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
<> 144:ef7eb2e8f9f7 35 * if the alarm occurs upon a Counter increment condition.
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38 #include "rtc.h"
<> 144:ef7eb2e8f9f7 39 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 static uint16_t SubSecond;
<> 144:ef7eb2e8f9f7 42 static uint64_t LastRtcTimeus;
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 45 void fRtcInit(void)
<> 144:ef7eb2e8f9f7 46 {
<> 144:ef7eb2e8f9f7 47 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
<> 144:ef7eb2e8f9f7 48 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Reset RTC control register */
<> 144:ef7eb2e8f9f7 51 RTCREG->CONTROL.WORD = False;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /* Initialize all counters */
<> 144:ef7eb2e8f9f7 54 RTCREG->SECOND_COUNTER = False;
<> 144:ef7eb2e8f9f7 55 RTCREG->SUB_SECOND_COUNTER = False;
<> 144:ef7eb2e8f9f7 56 RTCREG->SECOND_ALARM = False;
<> 144:ef7eb2e8f9f7 57 RTCREG->SUB_SECOND_ALARM = False;
<> 144:ef7eb2e8f9f7 58 LastRtcTimeus = 0;
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /* Reset RTC Status register */
<> 144:ef7eb2e8f9f7 61 RTCREG->STATUS.WORD = False;
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Clear interrupt status */
<> 144:ef7eb2e8f9f7 64 RTCREG->INT_CLEAR.WORD = False;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Start sec & sub_sec counter */
<> 144:ef7eb2e8f9f7 67 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
<> 144:ef7eb2e8f9f7 68 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 69 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* enable interruption associated with the rtc at NVIC level */
<> 144:ef7eb2e8f9f7 72 NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
<> 144:ef7eb2e8f9f7 73 NVIC_ClearPendingIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 74 NVIC_EnableIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 return;
<> 144:ef7eb2e8f9f7 79 }
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 82 void fRtcFree(void)
<> 144:ef7eb2e8f9f7 83 {
<> 144:ef7eb2e8f9f7 84 /* Reset RTC control register */
<> 144:ef7eb2e8f9f7 85 RTCREG->CONTROL.WORD = False;
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /* disable interruption associated with the rtc */
<> 144:ef7eb2e8f9f7 88 NVIC_DisableIRQ(Rtc_IRQn);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 94 void fRtcSetInterrupt(uint32_t timestamp)
<> 144:ef7eb2e8f9f7 95 {
<> 144:ef7eb2e8f9f7 96 SubSecond = False;
<> 144:ef7eb2e8f9f7 97 uint32_t Second = False;
<> 144:ef7eb2e8f9f7 98 uint8_t DividerAdjust = 1;
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 if(timestamp) {
<> 144:ef7eb2e8f9f7 101 if(timestamp >= RTC_SEC_TO_US) {
<> 144:ef7eb2e8f9f7 102 /* TimeStamp is big enough to set second alarm */
<> 144:ef7eb2e8f9f7 103 Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
<> 144:ef7eb2e8f9f7 104 RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /* Enable second interrupt */
<> 144:ef7eb2e8f9f7 107 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 108 }
<> 144:ef7eb2e8f9f7 109 timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
<> 144:ef7eb2e8f9f7 110 if(timestamp > False) {
<> 144:ef7eb2e8f9f7 111 /* We have some thing for sub second */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Convert micro second to sub_seconds(each count = 30.5 us) */
<> 144:ef7eb2e8f9f7 114 if(timestamp > 131000) {
<> 144:ef7eb2e8f9f7 115 DividerAdjust = 100;
<> 144:ef7eb2e8f9f7 116 }
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
<> 144:ef7eb2e8f9f7 119 timestamp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
<> 144:ef7eb2e8f9f7 120 SubSecond = Temp & RTC_SUB_SEC_MASK;
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 if(SubSecond <= 5) {
<> 144:ef7eb2e8f9f7 123 SubSecond = 0;
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 if(SubSecond > False) {
<> 144:ef7eb2e8f9f7 128 /* Second interrupt not enabled */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Set SUB SEC_ALARM */
<> 144:ef7eb2e8f9f7 131 RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Enable sub second interrupt */
<> 144:ef7eb2e8f9f7 134 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136 }
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140 return;
<> 144:ef7eb2e8f9f7 141 }
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 144 void fRtcDisableInterrupt(void)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 147 RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 148 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 149 }
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 152 void fRtcEnableInterrupt(void)
<> 144:ef7eb2e8f9f7 153 {
<> 144:ef7eb2e8f9f7 154 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 155 RTCREG->CONTROL.WORD |= ((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 156 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 157 }
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 160 void fRtcClearInterrupt(void)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 /* Disable subsec/sec interrupt */
<> 144:ef7eb2e8f9f7 163 /* Clear sec & sub_sec interrupts */
<> 144:ef7eb2e8f9f7 164 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 144:ef7eb2e8f9f7 165 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 144:ef7eb2e8f9f7 166 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 170 uint64_t fRtcRead(void)
<> 144:ef7eb2e8f9f7 171 {
<> 144:ef7eb2e8f9f7 172 uint32_t Second;
<> 144:ef7eb2e8f9f7 173 uint16_t SubSecond;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
<> 144:ef7eb2e8f9f7 176 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
<> 144:ef7eb2e8f9f7 177 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
<> 144:ef7eb2e8f9f7 178 * If you read a zero in the sub-second counter then increment the second counter by 1.
<> 144:ef7eb2e8f9f7 179 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
<> 144:ef7eb2e8f9f7 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Read the Second and Sub-second counters, then read the Second counter again.
<> 144:ef7eb2e8f9f7 183 * If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 do {
<> 144:ef7eb2e8f9f7 187 Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
<> 144:ef7eb2e8f9f7 188 SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & 0x7FFF; /* Get SUB_SEC_COUNTER reg value */
<> 144:ef7eb2e8f9f7 189 } while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 //note: casting to float removed to avoid reduction in resolution
<> 144:ef7eb2e8f9f7 192 uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /*check that the time did not go backwards */
<> 144:ef7eb2e8f9f7 195 MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
<> 144:ef7eb2e8f9f7 196 LastRtcTimeus = RtcTimeus;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 return RtcTimeus;
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 202 void fRtcWrite(uint64_t RtcTimeus)
<> 144:ef7eb2e8f9f7 203 {
<> 144:ef7eb2e8f9f7 204 uint32_t Second = 0;
<> 144:ef7eb2e8f9f7 205 uint16_t SubSecond = 0;
<> 144:ef7eb2e8f9f7 206 /* Stop RTC */
<> 144:ef7eb2e8f9f7 207 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 208 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 if(RtcTimeus > RTC_SEC_TO_US) {
<> 144:ef7eb2e8f9f7 211 /* TimeStamp is big enough to set second counter */
<> 144:ef7eb2e8f9f7 212 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
<> 144:ef7eb2e8f9f7 213 }
<> 144:ef7eb2e8f9f7 214 RTCREG->SECOND_COUNTER = Second;
<> 144:ef7eb2e8f9f7 215 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
<> 144:ef7eb2e8f9f7 216 if(RtcTimeus > False) {
<> 144:ef7eb2e8f9f7 217 /* Convert TimeStamp to sub_seconds */
<> 144:ef7eb2e8f9f7 218 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220 /* Set SUB_SEC_ALARM */
<> 144:ef7eb2e8f9f7 221 RTCREG->SUB_SECOND_COUNTER = SubSecond;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 224 /* Start RTC */
<> 144:ef7eb2e8f9f7 225 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 144:ef7eb2e8f9f7 226 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 229 }
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /* See rtc.h for details */
<> 144:ef7eb2e8f9f7 232 void fRtcHandler(void)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* SUB_SECOND/SECOND interrupt occured */
<> 144:ef7eb2e8f9f7 235 volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /* disable all interrupts */
<> 144:ef7eb2e8f9f7 238 RTCREG->CONTROL.WORD &= ~((RTC_ALL_INTERRUPT_BIT_VAL) << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Clear sec & sub_sec interrupts */
<> 144:ef7eb2e8f9f7 241 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 144:ef7eb2e8f9f7 242 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be solved in REV G */
<> 144:ef7eb2e8f9f7 245 if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
<> 144:ef7eb2e8f9f7 246 /* Second interrupt occured */
<> 144:ef7eb2e8f9f7 247 if(SubSecond > False) {
<> 144:ef7eb2e8f9f7 248 /* Set SUB SEC_ALARM */
<> 144:ef7eb2e8f9f7 249 RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
<> 144:ef7eb2e8f9f7 250 /* Enable sub second interrupt */
<> 144:ef7eb2e8f9f7 251 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 252 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 253 } else {
<> 144:ef7eb2e8f9f7 254 /* We reach here after second interrupt is occured */
<> 144:ef7eb2e8f9f7 255 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 256 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 144:ef7eb2e8f9f7 257 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259 } else {
<> 144:ef7eb2e8f9f7 260 /* We reach here after sub_second or (Sub second + second) interrupt occured */
<> 144:ef7eb2e8f9f7 261 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);
<> 144:ef7eb2e8f9f7 262 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 144:ef7eb2e8f9f7 263 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 boolean fIsRtcEnabled(void)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
<> 144:ef7eb2e8f9f7 272 return True;
<> 144:ef7eb2e8f9f7 273 } else {
<> 144:ef7eb2e8f9f7 274 return False;
<> 144:ef7eb2e8f9f7 275 }
<> 144:ef7eb2e8f9f7 276 }