Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/pmu_map.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file pmu_map.h
<> 144:ef7eb2e8f9f7 4 * @brief PMU hw module register map
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3372 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-04-22 12:18:18 +0530 (Wed, 22 Apr 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup pmu
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * @details
<> 144:ef7eb2e8f9f7 24 */
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 #ifndef PMU_MAP_H_
<> 144:ef7eb2e8f9f7 27 #define PMU_MAP_H_
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 30 * *
<> 144:ef7eb2e8f9f7 31 * Header files *
<> 144:ef7eb2e8f9f7 32 * *
<> 144:ef7eb2e8f9f7 33 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #include "architecture.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 /**************************************************************************************************
<> 144:ef7eb2e8f9f7 38 * *
<> 144:ef7eb2e8f9f7 39 * Type definitions *
<> 144:ef7eb2e8f9f7 40 * *
<> 144:ef7eb2e8f9f7 41 **************************************************************************************************/
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /** PMU control
<> 144:ef7eb2e8f9f7 44 * The Power Management Unit (PMU) is used to control the differing power modes.
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 typedef struct {
<> 144:ef7eb2e8f9f7 47 union {
<> 144:ef7eb2e8f9f7 48 struct {
<> 144:ef7eb2e8f9f7 49 __IO uint32_t ENCOMA :1; /**< 0- Sleep or SleepDeep depending on System Control Register (see WFI and WFE instructions), 1 – Coma */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t SRAMA :1; /**< SRAMA Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
<> 144:ef7eb2e8f9f7 51 __IO uint32_t SRAMB :1; /**< SRAMB Powered in Coma Modes: 0 – SRAM Powered, 1 – SRAM Un-Powered */
<> 144:ef7eb2e8f9f7 52 __IO uint32_t EXT32K :1; /**< External 32.768kHz Enable: 0 – Disabled (off), 1 – Enabled (on), Hardware guarantees that this oscillator cannot be powered if the internal 32kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
<> 144:ef7eb2e8f9f7 53 __IO uint32_t INT32K :1; /**< Internal 32kHz Enable: 0 – Enabled (on), 1 – Disabled (Off), Hardware guarantees that this oscillator cannot be powered down if the external 32.768kHz oscillator is already powered down. Hardware insures that one of the 32kHz oscillators is running. */
<> 144:ef7eb2e8f9f7 54 __IO uint32_t INT32M :1; /**< Internal 32MHz Enable: 0 – Enabled (on), 1 – Disabled (off), This bit will automatically get cleared when exiting Coma, or SleepDeep modes of operation. This bit should be set by software after switching over to the external 32MHz oscillator using the Oscillator Select bit in the Clock Control register */
<> 144:ef7eb2e8f9f7 55 __IO uint32_t C1V1:1; /**< Coma mode 1V1 regulator setting: 0 - Linear regulator, 1 - switching regulator */
<> 144:ef7eb2e8f9f7 56 __IO uint32_t N1V1:1; /**< Regular mode (Run sleep and deepsleep) 1V1 regulator mode: 0 - Linear regulator, 1 - switching regulator */
<> 144:ef7eb2e8f9f7 57 __IO uint32_t DBGPOW :1; /**< Debugger Power Behavior: 0 – Normal power behavior when the debugger is present, 1 – When debugger is present the ASIC can only enter SleepDeep mode and FVDDH and FVDDL always remain powered. The 32MHz oscillators can never be powered down in this mode either. */
<> 144:ef7eb2e8f9f7 58 __IO uint32_t UVIC:1; /**< Under voltage indicator control: 0 - disabled, 1 - enabled */
<> 144:ef7eb2e8f9f7 59 __IO uint32_t UVII:1; /**< Under voltage indicator input: 0 - 1V1 regulator, 1 - FVDDH regulator */
<> 144:ef7eb2e8f9f7 60 __IO uint32_t UVIR:1; /**< Under voltage indicator reset: 0 - do not reset, 1 - reset */
<> 144:ef7eb2e8f9f7 61 } BITS;
<> 144:ef7eb2e8f9f7 62 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 63 } CONTROL; /* 0x4001D000 */
<> 144:ef7eb2e8f9f7 64 union {
<> 144:ef7eb2e8f9f7 65 struct {
<> 144:ef7eb2e8f9f7 66 __I uint32_t BATTDET:1; /**< Detected battery: 0 - 1V, 1 - 3V */
<> 144:ef7eb2e8f9f7 67 __I uint32_t UVIC:1; /**< Under voltage status: 0 - normal, 1 - low */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 } BITS;
<> 144:ef7eb2e8f9f7 70 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 71 } STATUS; /* 0x4001D004 */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #ifdef REVB
<> 144:ef7eb2e8f9f7 74 __IO uint32_t RAMBIAS;
<> 144:ef7eb2e8f9f7 75 __IO uint32_t RETAINA_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
<> 144:ef7eb2e8f9f7 76 __IO uint32_t RETAINB_T; /**< RAM retain make/break time. This is clocked using FCLK, so it’s range & resolution are determined by the FCLK divider register in the Clock Control Section. */
<> 144:ef7eb2e8f9f7 77 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */
<> 144:ef7eb2e8f9f7 78 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */
<> 144:ef7eb2e8f9f7 79 union {
<> 144:ef7eb2e8f9f7 80 struct {
<> 144:ef7eb2e8f9f7 81 __IO uint32_t TH:6; /**< Threshold */
<> 144:ef7eb2e8f9f7 82 __I uint32_t PAD:2;
<> 144:ef7eb2e8f9f7 83 __I uint32_t UVIVAL; /**< UVI value */
<> 144:ef7eb2e8f9f7 84 } BITS;
<> 144:ef7eb2e8f9f7 85 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 86 } UVI_TBASE;
<> 144:ef7eb2e8f9f7 87 __IO uint32_t UVI_LIM;
<> 144:ef7eb2e8f9f7 88 #endif /* REVB */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #ifdef REVD
<> 144:ef7eb2e8f9f7 91 __IO uint32_t PLACEHOLDER; /* 0x4001D008 */
<> 144:ef7eb2e8f9f7 92 __IO uint32_t FVDD_TSTARTUP; /**< Regulator start time. */ /* 0x4001D00C */
<> 144:ef7eb2e8f9f7 93 __IO uint32_t PLACEHOLDER1; /* 0x4001D010 */
<> 144:ef7eb2e8f9f7 94 __IO uint32_t FVDD_TSETTLE; /**< Regulator settle time. */ /* 0x4001D014 */
<> 144:ef7eb2e8f9f7 95 union {
<> 144:ef7eb2e8f9f7 96 struct {
<> 144:ef7eb2e8f9f7 97 __IO uint32_t TH:6; /**< Threshold */
<> 144:ef7eb2e8f9f7 98 __I uint32_t PAD:2;
<> 144:ef7eb2e8f9f7 99 __I uint32_t UVIVAL:6; /**< UVI value */
<> 144:ef7eb2e8f9f7 100 } BITS;
<> 144:ef7eb2e8f9f7 101 __IO uint32_t WORD;
<> 144:ef7eb2e8f9f7 102 } UVI_TBASE; /* 0x4001D018 */
<> 144:ef7eb2e8f9f7 103 __IO uint32_t SRAM_TRIM; /* 0x4001D01C */
<> 144:ef7eb2e8f9f7 104 #endif /* REVD */
<> 144:ef7eb2e8f9f7 105 } PmuReg_t, *PmuReg_pt;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #endif /* PMU_MAP_H_ */