Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/hal/TARGET_ONSEMI/TARGET_NCS36510/memory_map.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file memory_map.h
<> 144:ef7eb2e8f9f7 4 * @brief Defines the silicon memory map. All peripheral devices shall be mapped in structures.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3525 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 144:ef7eb2e8f9f7 10 * @copyright (c) 2012 ON Semiconductor. All rights reserved.
<> 144:ef7eb2e8f9f7 11 * ON Semiconductor is supplying this software for use with ON Semiconductor
<> 144:ef7eb2e8f9f7 12 * processor based microcontrollers only.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 17 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 18 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 19 * @endinternal
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * @ingroup bsp
<> 144:ef7eb2e8f9f7 22 @verbatim
<> 144:ef7eb2e8f9f7 23 +-----------------+
<> 144:ef7eb2e8f9f7 24 | | ,_________________________
<> 144:ef7eb2e8f9f7 25 | Private Per. | |PMUREG 0x4001D000|
<> 144:ef7eb2e8f9f7 26 0xE0000000 +-----------------+ |PADREG 0x4001C000|
<> 144:ef7eb2e8f9f7 27 | |_____________|CLOCKREG 0x4001B000|
<> 144:ef7eb2e8f9f7 28 | PERIPHERALS | |RFANAREG 0x40019000|
<> 144:ef7eb2e8f9f7 29 +-----------------+ |RESETREG 0x40018000|
<> 144:ef7eb2e8f9f7 30 | | |FLASHREG 0x40017000|
<> 144:ef7eb2e8f9f7 31 0x3FFF8000 |SRAM A 32K | |AESREG 0x40016000|
<> 144:ef7eb2e8f9f7 32 +-----------------+ |ADCREG 0x40015000|
<> 144:ef7eb2e8f9f7 33 | | |MACHWREG 0x40014000|
<> 144:ef7eb2e8f9f7 34 |SRAM B 16K | |RANDREG 0x40011000|
<> 144:ef7eb2e8f9f7 35 0x3FFF4000 +-----------------+ |CROSSBREG 0x40010000|
<> 144:ef7eb2e8f9f7 36 | | |RTCREG 0x4000F000|
<> 144:ef7eb2e8f9f7 37 0x24000100 |SRAM DMA 7B | |GPIOREG 0x4000C000|
<> 144:ef7eb2e8f9f7 38 +-----------------+ |PWMREG 0x4000B000|
<> 144:ef7eb2e8f9f7 39 0x24000000 |SRAM MAC 256B | |WDTREG 0x4000A000|
<> 144:ef7eb2e8f9f7 40 +-----------------+ |UARTREG 0x40008000|
<> 144:ef7eb2e8f9f7 41 | 320K | |I2CREG 0x40007000|
<> 144:ef7eb2e8f9f7 42 0x00102000 |FLASHB | |SPIREG 0x40006000|
<> 144:ef7eb2e8f9f7 43 0x00100000 |FLASHB Inf Block | |UARTREG 0x40005000|
<> 144:ef7eb2e8f9f7 44 +-----------------+ |TIM2REG 0x40002000|
<> 144:ef7eb2e8f9f7 45 | 320K | |TIM1REG 0x40001000|
<> 144:ef7eb2e8f9f7 46 0x00002000 |FLASHA | |TIM0REG 0x40000000|
<> 144:ef7eb2e8f9f7 47 0x00000000 |FLASHA Inf Block | '`''''''''''''''''''''''''
<> 144:ef7eb2e8f9f7 48 '`'''''''''''''''''
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 @endverbatim
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #ifndef _MEMORY_MAP_H_
<> 144:ef7eb2e8f9f7 54 #define _MEMORY_MAP_H_
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 57 * *
<> 144:ef7eb2e8f9f7 58 * Header files *
<> 144:ef7eb2e8f9f7 59 * *
<> 144:ef7eb2e8f9f7 60 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #include <stdint.h>
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 #include "architecture.h"
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 // Register maps of HW modules controlled with device drivers
<> 144:ef7eb2e8f9f7 67 #include "adc_sar_map.h"
<> 144:ef7eb2e8f9f7 68 #include "aes_map.h"
<> 144:ef7eb2e8f9f7 69 #include "flash_map.h"
<> 144:ef7eb2e8f9f7 70 #include "gpio_map.h"
<> 144:ef7eb2e8f9f7 71 #include "i2c_ipc7208_map.h"
<> 144:ef7eb2e8f9f7 72 #include "pwm_map.h"
<> 144:ef7eb2e8f9f7 73 #include "rtc_map.h"
<> 144:ef7eb2e8f9f7 74 #include "spi_ipc7207_map.h"
<> 144:ef7eb2e8f9f7 75 #include "timer_map.h"
<> 144:ef7eb2e8f9f7 76 #include "uart_16c550_map.h"
<> 144:ef7eb2e8f9f7 77 #include "wdt_map.h"
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 // Register maps of HW modules controlled with specific functions
<> 144:ef7eb2e8f9f7 80 #include "clock_map.h"
<> 144:ef7eb2e8f9f7 81 #include "crossbar_map.h"
<> 144:ef7eb2e8f9f7 82 #include "dma_map.h"
<> 144:ef7eb2e8f9f7 83 #include "macHw_map.h"
<> 144:ef7eb2e8f9f7 84 #include "pad_map.h"
<> 144:ef7eb2e8f9f7 85 #include "pmu_map.h"
<> 144:ef7eb2e8f9f7 86 #include "random_map.h"
<> 144:ef7eb2e8f9f7 87 #include "reset_map.h"
<> 144:ef7eb2e8f9f7 88 #include "rfAna_map.h"
<> 144:ef7eb2e8f9f7 89 #include "test_map.h"
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 // Trim structure map
<> 144:ef7eb2e8f9f7 92 #include "trim_map.h"
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 95 * *
<> 144:ef7eb2e8f9f7 96 * Symbolic Constants *
<> 144:ef7eb2e8f9f7 97 * *
<> 144:ef7eb2e8f9f7 98 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /** Trim structure mapping
<> 144:ef7eb2e8f9f7 101 *
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103 #define TRIMREG_BASE ((uint32_t)0x1FA0)
<> 144:ef7eb2e8f9f7 104 #define TRIMREG ((TrimReg_t *)TRIMREG_BASE)
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** DMA HW Registers Offset */
<> 144:ef7eb2e8f9f7 107 #define DMAREG_BASE ((uint32_t)0x24000400)
<> 144:ef7eb2e8f9f7 108 /** DMA HW Structure Overlay */
<> 144:ef7eb2e8f9f7 109 #define DMAREG ((DmaReg_pt)DMAREG_BASE)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** MAC MATCH HW Registers Offset */
<> 144:ef7eb2e8f9f7 112 #define MACMATCHREG_BASE ((uint32_t)0x24000100)
<> 144:ef7eb2e8f9f7 113 /** MAC MATCH HW Structure Overlay */
<> 144:ef7eb2e8f9f7 114 #define MACMATCHREG ((volatile uint8_t *)MACMATCHREG_BASE)
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /** MAC RX HW Registers Offset */
<> 144:ef7eb2e8f9f7 117 #define MACRXREG_BASE ((uint32_t)0x24000080)
<> 144:ef7eb2e8f9f7 118 /** MAC RX HW Structure Overlay */
<> 144:ef7eb2e8f9f7 119 #define MACRXREG ((volatile uint8_t *)MACRXREG_BASE)
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** MAC TX HW Registers Offset */
<> 144:ef7eb2e8f9f7 122 #define MACTXREG_BASE ((uint32_t)0x24000000)
<> 144:ef7eb2e8f9f7 123 /** MAC TX HW Structure Overlay */
<> 144:ef7eb2e8f9f7 124 #define MACTXREG ((volatile uint8_t *)MACTXREG_BASE)
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** TEST Interface for flash HW Registers Offset */
<> 144:ef7eb2e8f9f7 127 #define TESTNVMREG_BASE ((uint32_t)0x4001F140)
<> 144:ef7eb2e8f9f7 128 /** TEST Interface for flash HW Structure Overlay */
<> 144:ef7eb2e8f9f7 129 #define TESTNVMREG ((TestNvmReg_pt)TESTNVMREG_BASE)
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** Test Interface for digital HW Registers Offset */
<> 144:ef7eb2e8f9f7 132 #define TESTDIGREG_BASE ((uint32_t)0x4001F100)
<> 144:ef7eb2e8f9f7 133 /** Test Interface for digital HW Structure Overlay */
<> 144:ef7eb2e8f9f7 134 #define TESTDIGREG ((TestDigReg_pt)TESTDIGREG_BASE)
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /** Test Interface HW Registers Offset */
<> 144:ef7eb2e8f9f7 137 #define TESTREG_BASE ((uint32_t)0x4001F000)
<> 144:ef7eb2e8f9f7 138 /** Test Interface HW Structure Overlay */
<> 144:ef7eb2e8f9f7 139 #define TESTREG ((TestReg_pt)TESTREG_BASE)
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /** Device option HW Registers Offset */
<> 144:ef7eb2e8f9f7 142 #define DEVOPTREG_BASE ((uint32_t)0x4001E000)
<> 144:ef7eb2e8f9f7 143 /** MAC TX HW Structure Overlay */
<> 144:ef7eb2e8f9f7 144 #define DEVOPTREG ((volatile uint32_t *)DEVOPTREG_BASE)
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /** PMU HW Registers Offset */
<> 144:ef7eb2e8f9f7 147 #define PMUREG_BASE ((uint32_t)0x4001D000)
<> 144:ef7eb2e8f9f7 148 /** PMU HW Structure Overlay */
<> 144:ef7eb2e8f9f7 149 #define PMUREG ((PmuReg_pt)PMUREG_BASE)
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /** PAD Control HW Registers Offset */
<> 144:ef7eb2e8f9f7 152 #define PADREG_BASE ((uint32_t)0x4001C000)
<> 144:ef7eb2e8f9f7 153 /** PAD Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 154 #define PADREG ((PadReg_pt)PADREG_BASE)
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /** Clock Control HW Registers Offset */
<> 144:ef7eb2e8f9f7 157 #define CLOCKREG_BASE ((uint32_t)0x4001B000)
<> 144:ef7eb2e8f9f7 158 /** Clock Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 159 #define CLOCKREG ((ClockReg_pt)CLOCKREG_BASE)
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** Analogue Trim HW Registers Offset */
<> 144:ef7eb2e8f9f7 162 #define RFANATRIMREG_BASE ((uint32_t)0x40019080)
<> 144:ef7eb2e8f9f7 163 /** Analogue Trim HW Structure Overlay */
<> 144:ef7eb2e8f9f7 164 #define RFANATRIMREG ((RfAnaTrimReg_pt)RFANATRIMREG_BASE)
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /** Analogue RF HW Registers Offset */
<> 144:ef7eb2e8f9f7 167 #define RFANAREG_BASE ((uint32_t)0x40019000)
<> 144:ef7eb2e8f9f7 168 /** Analogue RF HW Structure Overlay */
<> 144:ef7eb2e8f9f7 169 #define RFANAREG ((RfAnaReg_pt)RFANAREG_BASE)
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** Reset Cause HW Registers Offset */
<> 144:ef7eb2e8f9f7 172 #define RESETREG_BASE ((uint32_t)0x40018000)
<> 144:ef7eb2e8f9f7 173 /** Reset Cause HW Structure Overlay */
<> 144:ef7eb2e8f9f7 174 #define RESETREG ((ResetReg_pt)RESETREG_BASE)
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** FLASH Control HW Registers Offset */
<> 144:ef7eb2e8f9f7 177 #define FLASHREG_BASE ((uint32_t)0x40017000)
<> 144:ef7eb2e8f9f7 178 /** FLASH Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 179 #define FLASHREG ((FlashReg_pt)FLASHREG_BASE)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** AES Encryption HW Registers Offset */
<> 144:ef7eb2e8f9f7 182 #define AESREG_BASE ((uint32_t)0x40016000)
<> 144:ef7eb2e8f9f7 183 /** AES Encryption HW Structure Overlay */
<> 144:ef7eb2e8f9f7 184 #define AESREG ((AesReg_pt)AESREG_BASE)
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /** SAR ADC HW Registers Offset */
<> 144:ef7eb2e8f9f7 187 #define ADCREG_BASE ((uint32_t)0x40015000)
<> 144:ef7eb2e8f9f7 188 /** SAR ADC HW Structure Overlay */
<> 144:ef7eb2e8f9f7 189 #define ADCREG ((AdcReg_pt)ADCREG_BASE)
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /** Demodulator HW Registers Offset */
<> 144:ef7eb2e8f9f7 192 #define DMDREG_BASE ((uint32_t)0x40014100)
<> 144:ef7eb2e8f9f7 193 /** Demodulator HW Structure Overlay */
<> 144:ef7eb2e8f9f7 194 #define DMDREG ((DmdReg_pt)DMDREG_BASE)
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /** MAC Control HW Registers Offset */
<> 144:ef7eb2e8f9f7 197 #define MACHWREG_BASE ((uint32_t)0x40014000)
<> 144:ef7eb2e8f9f7 198 /** MAC Control HW Structure Overlay */
<> 144:ef7eb2e8f9f7 199 #define MACHWREG ((MacHwReg_pt)MACHWREG_BASE)
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** Random Generator HW Registers Offset */
<> 144:ef7eb2e8f9f7 202 #define RANDREG_BASE ((uint32_t)0x40011000)
<> 144:ef7eb2e8f9f7 203 /** Random Generator HW Structure Overlay */
<> 144:ef7eb2e8f9f7 204 #define RANDREG ((RandReg_pt)RANDREG_BASE)
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** Cross Bar HW Registers Offset */
<> 144:ef7eb2e8f9f7 207 #define CROSSBREG_BASE ((uint32_t)0x40010000)
<> 144:ef7eb2e8f9f7 208 /** Cross Bar HW Structure Overlay */
<> 144:ef7eb2e8f9f7 209 #define CROSSBREG ((CrossbReg_pt)CROSSBREG_BASE)
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** Real Time Clock HW Registers Offset */
<> 144:ef7eb2e8f9f7 212 #define RTCREG_BASE ((uint32_t)0x4000F000)
<> 144:ef7eb2e8f9f7 213 /** Real Time Clock HW Structure Overlay */
<> 144:ef7eb2e8f9f7 214 #define RTCREG ((RtcReg_pt)RTCREG_BASE)
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** GPIO HW Registers Offset */
<> 144:ef7eb2e8f9f7 217 #define GPIOREG_BASE ((uint32_t)0x4000C000)
<> 144:ef7eb2e8f9f7 218 /** GPIO HW Structure Overlay */
<> 144:ef7eb2e8f9f7 219 #define GPIOREG ((GpioReg_pt)GPIOREG_BASE)
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** PWM HW Registers Offset */
<> 144:ef7eb2e8f9f7 222 #define PWMREG_BASE ((uint32_t)0x4000B000)
<> 144:ef7eb2e8f9f7 223 /** PWM HW Structure Overlay */
<> 144:ef7eb2e8f9f7 224 #define PWMREG ((PwmReg_pt)PWMREG_BASE)
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /** Watchdog Timer HW Registers Offset */
<> 144:ef7eb2e8f9f7 227 #define WDTREG_BASE ((uint32_t)0x4000A000)
<> 144:ef7eb2e8f9f7 228 /** Watchdog Timer HW Structure Overlay */
<> 144:ef7eb2e8f9f7 229 #define WDTREG ((WdtReg_pt)WDTREG_BASE)
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** UART 2 HW Registers Offset */
<> 144:ef7eb2e8f9f7 232 #define UART2REG_BASE ((uint32_t)0x40008000)
<> 144:ef7eb2e8f9f7 233 /** UART 2 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 234 #define UART2REG ((Uart16C550Reg_pt)UART2REG_BASE)
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /** I2C HW Registers Offset */
<> 144:ef7eb2e8f9f7 237 #define I2C1REG_BASE ((uint32_t)0x40007000)
<> 144:ef7eb2e8f9f7 238 /** I2C HW Structure Overlay */
<> 144:ef7eb2e8f9f7 239 #define I2C1REG ((I2cIpc7208Reg_pt)I2C1REG_BASE)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** SPI HW Registers Offset */
<> 144:ef7eb2e8f9f7 242 #define SPI1REG_BASE ((uint32_t)0x40006000)
<> 144:ef7eb2e8f9f7 243 /** SPI HW Structure Overlay */
<> 144:ef7eb2e8f9f7 244 #define SPI1REG ((SpiIpc7207Reg_pt)SPI1REG_BASE)
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** UART1 HW Registers Offset */
<> 144:ef7eb2e8f9f7 247 #define UART1REG_BASE ((uint32_t)0x40005000)
<> 144:ef7eb2e8f9f7 248 /** UART1 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 249 #define UART1REG ((Uart16C550Reg_pt)UART1REG_BASE)
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #define UARTREG_BASES { UART1REG_BASE, UART2REG_BASE}
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** Timer 2 HW Registers Offset */
<> 144:ef7eb2e8f9f7 254 #define TIM2REG_BASE ((uint32_t)0x40002000)
<> 144:ef7eb2e8f9f7 255 /** Timer 2 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 256 #define TIM2REG ((TimerReg_pt)TIM2REG_BASE)
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** Timer 1 HW Registers Offset */
<> 144:ef7eb2e8f9f7 259 #define TIM1REG_BASE ((uint32_t)0x40001000)
<> 144:ef7eb2e8f9f7 260 /** Timer 1 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 261 #define TIM1REG ((TimerReg_pt)TIM1REG_BASE)
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /** Timer 0 HW Registers Offset */
<> 144:ef7eb2e8f9f7 264 #define TIM0REG_BASE ((uint32_t)0x40000000)
<> 144:ef7eb2e8f9f7 265 /** Timer 0 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 266 #define TIM0REG ((TimerReg_pt)TIM0REG_BASE)
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** I2C2 HW Registers Offset */
<> 144:ef7eb2e8f9f7 269 #define I2C2REG_BASE ((uint32_t)0x4000D000)
<> 144:ef7eb2e8f9f7 270 /** I2C2 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 271 #define I2C2REG ((I2cIpc7208Reg_pt)I2C2REG_BASE)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** SPI2 HW Registers Offset */
<> 144:ef7eb2e8f9f7 274 #define SPI2REG_BASE ((uint32_t)0x40009000)
<> 144:ef7eb2e8f9f7 275 /** SPI2 HW Structure Overlay */
<> 144:ef7eb2e8f9f7 276 #define SPI2REG ((SpiIpc7207Reg_pt)SPI2REG_BASE)
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #endif /*_MEMORY_MAP_H_*/