Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_sdmmc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_ll_sdmmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief SDMMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the SDMMC peripheral:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + I/O operation functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### SDMMC peripheral features #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
<> 144:ef7eb2e8f9f7 21 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
<> 144:ef7eb2e8f9f7 22 devices.
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 [..] The SDMMC features include the following:
<> 144:ef7eb2e8f9f7 25 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
<> 144:ef7eb2e8f9f7 26 for three different databus modes: 1-bit (default), 4-bit and 8-bit
<> 144:ef7eb2e8f9f7 27 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
<> 144:ef7eb2e8f9f7 28 (+) Full compliance with SD Memory Card Specifications Version 2.0
<> 144:ef7eb2e8f9f7 29 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
<> 144:ef7eb2e8f9f7 30 different data bus modes: 1-bit (default) and 4-bit
<> 144:ef7eb2e8f9f7 31 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
<> 144:ef7eb2e8f9f7 32 Rev1.1)
<> 144:ef7eb2e8f9f7 33 (+) Data transfer up to 48 MHz for the 8 bit mode
<> 144:ef7eb2e8f9f7 34 (+) Data and command output enable signals to control external bidirectional drivers.
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 38 ==============================================================================
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 This driver is a considered as a driver of service for external devices drivers
<> 144:ef7eb2e8f9f7 41 that interfaces with the SDMMC peripheral.
<> 144:ef7eb2e8f9f7 42 According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
<> 144:ef7eb2e8f9f7 43 is used in the device's driver to perform SDMMC operations and functionalities.
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 This driver is almost transparent for the final user, it is only used to implement other
<> 144:ef7eb2e8f9f7 46 functionalities of the external device.
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 [..]
<> 144:ef7eb2e8f9f7 49 (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output of PLL
<> 144:ef7eb2e8f9f7 50 (PLL48CLK). Before start working with SDMMC peripheral make sure that the
<> 144:ef7eb2e8f9f7 51 PLL is well configured.
<> 144:ef7eb2e8f9f7 52 The SDMMC peripheral uses two clock signals:
<> 144:ef7eb2e8f9f7 53 (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
<> 144:ef7eb2e8f9f7 54 (++) APB2 bus clock (PCLK2)
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
<> 144:ef7eb2e8f9f7 57 Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
<> 144:ef7eb2e8f9f7 60 peripheral.
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
<> 144:ef7eb2e8f9f7 63 function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
<> 144:ef7eb2e8f9f7 68 and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 (+) When using the DMA mode
<> 144:ef7eb2e8f9f7 71 (++) Configure the DMA in the MSP layer of the external device
<> 144:ef7eb2e8f9f7 72 (++) Active the needed channel Request
<> 144:ef7eb2e8f9f7 73 (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
<> 144:ef7eb2e8f9f7 74 __SDMMC_DMA_DISABLE().
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 (+) To control the CPSM (Command Path State Machine) and send
<> 144:ef7eb2e8f9f7 77 commands to the card use the SDMMC_SendCommand(SDMMCx),
<> 144:ef7eb2e8f9f7 78 SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
<> 144:ef7eb2e8f9f7 79 to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
<> 144:ef7eb2e8f9f7 80 to the selected command to be sent.
<> 144:ef7eb2e8f9f7 81 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 82 (++) Command Argument
<> 144:ef7eb2e8f9f7 83 (++) Command Index
<> 144:ef7eb2e8f9f7 84 (++) Command Response type
<> 144:ef7eb2e8f9f7 85 (++) Command Wait
<> 144:ef7eb2e8f9f7 86 (++) CPSM Status (Enable or Disable).
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 -@@- To check if the command is well received, read the SDMMC_CMDRESP
<> 144:ef7eb2e8f9f7 89 register using the SDMMC_GetCommandResponse().
<> 144:ef7eb2e8f9f7 90 The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
<> 144:ef7eb2e8f9f7 91 SDMMC_GetResponse() function.
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (+) To control the DPSM (Data Path State Machine) and send/receive
<> 144:ef7eb2e8f9f7 94 data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
<> 144:ef7eb2e8f9f7 95 SDMMC_ReadFIFO(), DIO_WriteFIFO() and SDMMC_GetFIFOCount() functions.
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 *** Read Operations ***
<> 144:ef7eb2e8f9f7 98 =======================
<> 144:ef7eb2e8f9f7 99 [..]
<> 144:ef7eb2e8f9f7 100 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 101 SDMMC_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 102 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 103 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 104 (++) Data Length
<> 144:ef7eb2e8f9f7 105 (++) Data Block size
<> 144:ef7eb2e8f9f7 106 (++) Data Transfer direction: should be from card (To SDMMC)
<> 144:ef7eb2e8f9f7 107 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 108 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (#) Configure the SDMMC resources to receive the data from the card
<> 144:ef7eb2e8f9f7 111 according to selected transfer mode (Refer to Step 8, 9 and 10).
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 (#) Send the selected Read command (refer to step 11).
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 (#) Use the SDMMC flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 *** Write Operations ***
<> 144:ef7eb2e8f9f7 118 ========================
<> 144:ef7eb2e8f9f7 119 [..]
<> 144:ef7eb2e8f9f7 120 (#) First, user has to fill the data structure (pointer to
<> 144:ef7eb2e8f9f7 121 SDMMC_DataInitTypeDef) according to the selected data type to be received.
<> 144:ef7eb2e8f9f7 122 The parameters that should be filled are:
<> 144:ef7eb2e8f9f7 123 (++) Data TimeOut
<> 144:ef7eb2e8f9f7 124 (++) Data Length
<> 144:ef7eb2e8f9f7 125 (++) Data Block size
<> 144:ef7eb2e8f9f7 126 (++) Data Transfer direction: should be to card (To CARD)
<> 144:ef7eb2e8f9f7 127 (++) Data Transfer mode
<> 144:ef7eb2e8f9f7 128 (++) DPSM Status (Enable or Disable)
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 (#) Configure the SDMMC resources to send the data to the card according to
<> 144:ef7eb2e8f9f7 131 selected transfer mode.
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 (#) Send the selected Write command.
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 (#) Use the SDMMC flags/interrupts to check the transfer status.
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 @endverbatim
<> 144:ef7eb2e8f9f7 138 ******************************************************************************
<> 144:ef7eb2e8f9f7 139 * @attention
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 142 *
<> 144:ef7eb2e8f9f7 143 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 144 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 145 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 146 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 147 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 148 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 149 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 150 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 151 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 152 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 153 *
<> 144:ef7eb2e8f9f7 154 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 155 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 156 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 157 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 158 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 159 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 160 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 161 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 162 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 163 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 164 *
<> 144:ef7eb2e8f9f7 165 ******************************************************************************
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 172 * @{
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup SDMMC_LL SDMMC Low Layer
<> 144:ef7eb2e8f9f7 176 * @brief Low layer module for SD
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 183 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 184 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 185 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 186 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 187 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
<> 144:ef7eb2e8f9f7 190 * @{
<> 144:ef7eb2e8f9f7 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
<> 144:ef7eb2e8f9f7 194 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 195 *
<> 144:ef7eb2e8f9f7 196 @verbatim
<> 144:ef7eb2e8f9f7 197 ===============================================================================
<> 144:ef7eb2e8f9f7 198 ##### Initialization/de-initialization functions #####
<> 144:ef7eb2e8f9f7 199 ===============================================================================
<> 144:ef7eb2e8f9f7 200 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 @endverbatim
<> 144:ef7eb2e8f9f7 203 * @{
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /**
<> 144:ef7eb2e8f9f7 207 * @brief Initializes the SDMMC according to the specified
<> 144:ef7eb2e8f9f7 208 * parameters in the SDMMC_InitTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 209 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 210 * @param Init: SDMMC initialization structure
<> 144:ef7eb2e8f9f7 211 * @retval HAL status
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
<> 144:ef7eb2e8f9f7 214 {
<> 144:ef7eb2e8f9f7 215 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Check the parameters */
<> 144:ef7eb2e8f9f7 218 assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
<> 144:ef7eb2e8f9f7 219 assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
<> 144:ef7eb2e8f9f7 220 assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
<> 144:ef7eb2e8f9f7 221 assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
<> 144:ef7eb2e8f9f7 222 assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
<> 144:ef7eb2e8f9f7 223 assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
<> 144:ef7eb2e8f9f7 224 assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Set SDMMC configuration parameters */
<> 144:ef7eb2e8f9f7 227 tmpreg |= (Init.ClockEdge |\
<> 144:ef7eb2e8f9f7 228 Init.ClockBypass |\
<> 144:ef7eb2e8f9f7 229 Init.ClockPowerSave |\
<> 144:ef7eb2e8f9f7 230 Init.BusWide |\
<> 144:ef7eb2e8f9f7 231 Init.HardwareFlowControl |\
<> 144:ef7eb2e8f9f7 232 Init.ClockDiv
<> 144:ef7eb2e8f9f7 233 );
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Write to SDMMC CLKCR */
<> 144:ef7eb2e8f9f7 236 MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 return HAL_OK;
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /**
<> 144:ef7eb2e8f9f7 243 * @}
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 247 * @brief Data transfers functions
<> 144:ef7eb2e8f9f7 248 *
<> 144:ef7eb2e8f9f7 249 @verbatim
<> 144:ef7eb2e8f9f7 250 ===============================================================================
<> 144:ef7eb2e8f9f7 251 ##### I/O operation functions #####
<> 144:ef7eb2e8f9f7 252 ===============================================================================
<> 144:ef7eb2e8f9f7 253 [..]
<> 144:ef7eb2e8f9f7 254 This subsection provides a set of functions allowing to manage the SDMMC data
<> 144:ef7eb2e8f9f7 255 transfers.
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 @endverbatim
<> 144:ef7eb2e8f9f7 258 * @{
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 263 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 264 * @retval HAL status
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /* Read data from Rx FIFO */
<> 144:ef7eb2e8f9f7 269 return (SDMMCx->FIFO);
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
<> 144:ef7eb2e8f9f7 274 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 275 * @param pWriteData: pointer to data to write
<> 144:ef7eb2e8f9f7 276 * @retval HAL status
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* Write data to FIFO */
<> 144:ef7eb2e8f9f7 281 SDMMCx->FIFO = *pWriteData;
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 return HAL_OK;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 291 * @brief management functions
<> 144:ef7eb2e8f9f7 292 *
<> 144:ef7eb2e8f9f7 293 @verbatim
<> 144:ef7eb2e8f9f7 294 ===============================================================================
<> 144:ef7eb2e8f9f7 295 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 296 ===============================================================================
<> 144:ef7eb2e8f9f7 297 [..]
<> 144:ef7eb2e8f9f7 298 This subsection provides a set of functions allowing to control the SDMMC data
<> 144:ef7eb2e8f9f7 299 transfers.
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 @endverbatim
<> 144:ef7eb2e8f9f7 302 * @{
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief Set SDMMC Power state to ON.
<> 144:ef7eb2e8f9f7 307 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 308 * @retval HAL status
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 311 {
<> 144:ef7eb2e8f9f7 312 /* Set power state to ON */
<> 144:ef7eb2e8f9f7 313 SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 return HAL_OK;
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @brief Set SDMMC Power state to OFF.
<> 144:ef7eb2e8f9f7 320 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 321 * @retval HAL status
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 /* Set power state to OFF */
<> 144:ef7eb2e8f9f7 326 SDMMCx->POWER = (uint32_t)0x00000000;
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 return HAL_OK;
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /**
<> 144:ef7eb2e8f9f7 332 * @brief Get SDMMC Power state.
<> 144:ef7eb2e8f9f7 333 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 334 * @retval Power status of the controller. The returned value can be one of the
<> 144:ef7eb2e8f9f7 335 * following values:
<> 144:ef7eb2e8f9f7 336 * - 0x00: Power OFF
<> 144:ef7eb2e8f9f7 337 * - 0x02: Power UP
<> 144:ef7eb2e8f9f7 338 * - 0x03: Power ON
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @brief Configure the SDMMC command path according to the specified parameters in
<> 144:ef7eb2e8f9f7 347 * SDMMC_CmdInitTypeDef structure and send the command
<> 144:ef7eb2e8f9f7 348 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 349 * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 350 * the configuration information for the SDMMC command
<> 144:ef7eb2e8f9f7 351 * @retval HAL status
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Check the parameters */
<> 144:ef7eb2e8f9f7 358 assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
<> 144:ef7eb2e8f9f7 359 assert_param(IS_SDMMC_RESPONSE(Command->Response));
<> 144:ef7eb2e8f9f7 360 assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
<> 144:ef7eb2e8f9f7 361 assert_param(IS_SDMMC_CPSM(Command->CPSM));
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /* Set the SDMMC Argument value */
<> 144:ef7eb2e8f9f7 364 SDMMCx->ARG = Command->Argument;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /* Set SDMMC command parameters */
<> 144:ef7eb2e8f9f7 367 tmpreg |= (uint32_t)(Command->CmdIndex |\
<> 144:ef7eb2e8f9f7 368 Command->Response |\
<> 144:ef7eb2e8f9f7 369 Command->WaitForInterrupt |\
<> 144:ef7eb2e8f9f7 370 Command->CPSM);
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /* Write to SDMMC CMD register */
<> 144:ef7eb2e8f9f7 373 MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 return HAL_OK;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Return the command index of last command for which response received
<> 144:ef7eb2e8f9f7 380 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 381 * @retval Command index of the last command response received
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 return (uint8_t)(SDMMCx->RESPCMD);
<> 144:ef7eb2e8f9f7 386 }
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /**
<> 144:ef7eb2e8f9f7 390 * @brief Return the response received from the card for the last command
<> 144:ef7eb2e8f9f7 391 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 392 * @param Response: Specifies the SDMMC response register.
<> 144:ef7eb2e8f9f7 393 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 394 * @arg SDMMC_RESP1: Response Register 1
<> 144:ef7eb2e8f9f7 395 * @arg SDMMC_RESP2: Response Register 2
<> 144:ef7eb2e8f9f7 396 * @arg SDMMC_RESP3: Response Register 3
<> 144:ef7eb2e8f9f7 397 * @arg SDMMC_RESP4: Response Register 4
<> 144:ef7eb2e8f9f7 398 * @retval The Corresponding response register value
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 __IO uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Check the parameters */
<> 144:ef7eb2e8f9f7 405 assert_param(IS_SDMMC_RESP(Response));
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Get the response */
<> 144:ef7eb2e8f9f7 408 tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 return (*(__IO uint32_t *) tmp);
<> 144:ef7eb2e8f9f7 411 }
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /**
<> 144:ef7eb2e8f9f7 414 * @brief Configure the SDMMC data path according to the specified
<> 144:ef7eb2e8f9f7 415 * parameters in the SDMMC_DataInitTypeDef.
<> 144:ef7eb2e8f9f7 416 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 417 * @param Data : pointer to a SDMMC_DataInitTypeDef structure
<> 144:ef7eb2e8f9f7 418 * that contains the configuration information for the SDMMC data.
<> 144:ef7eb2e8f9f7 419 * @retval HAL status
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
<> 144:ef7eb2e8f9f7 422 {
<> 144:ef7eb2e8f9f7 423 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Check the parameters */
<> 144:ef7eb2e8f9f7 426 assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
<> 144:ef7eb2e8f9f7 427 assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
<> 144:ef7eb2e8f9f7 428 assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
<> 144:ef7eb2e8f9f7 429 assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
<> 144:ef7eb2e8f9f7 430 assert_param(IS_SDMMC_DPSM(Data->DPSM));
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Set the SDMMC Data TimeOut value */
<> 144:ef7eb2e8f9f7 433 SDMMCx->DTIMER = Data->DataTimeOut;
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /* Set the SDMMC DataLength value */
<> 144:ef7eb2e8f9f7 436 SDMMCx->DLEN = Data->DataLength;
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /* Set the SDMMC data configuration parameters */
<> 144:ef7eb2e8f9f7 439 tmpreg |= (uint32_t)(Data->DataBlockSize |\
<> 144:ef7eb2e8f9f7 440 Data->TransferDir |\
<> 144:ef7eb2e8f9f7 441 Data->TransferMode |\
<> 144:ef7eb2e8f9f7 442 Data->DPSM);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Write to SDMMC DCTRL */
<> 144:ef7eb2e8f9f7 445 MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 return HAL_OK;
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 }
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @brief Returns number of remaining data bytes to be transferred.
<> 144:ef7eb2e8f9f7 453 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 454 * @retval Number of remaining data bytes to be transferred
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 return (SDMMCx->DCOUNT);
<> 144:ef7eb2e8f9f7 459 }
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /**
<> 144:ef7eb2e8f9f7 462 * @brief Get the FIFO data
<> 144:ef7eb2e8f9f7 463 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 464 * @retval Data received
<> 144:ef7eb2e8f9f7 465 */
<> 144:ef7eb2e8f9f7 466 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 return (SDMMCx->FIFO);
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /**
<> 144:ef7eb2e8f9f7 473 * @brief Sets one of the two options of inserting read wait interval.
<> 144:ef7eb2e8f9f7 474 * @param SDMMCx: Pointer to SDMMC register base
<> 144:ef7eb2e8f9f7 475 * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
<> 144:ef7eb2e8f9f7 476 * This parameter can be:
<> 144:ef7eb2e8f9f7 477 * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
<> 144:ef7eb2e8f9f7 478 * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
<> 144:ef7eb2e8f9f7 479 * @retval None
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 /* Check the parameters */
<> 144:ef7eb2e8f9f7 484 assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Set SDMMC read wait mode */
<> 144:ef7eb2e8f9f7 487 MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 return HAL_OK;
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @}
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
<> 144:ef7eb2e8f9f7 501 /**
<> 144:ef7eb2e8f9f7 502 * @}
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /**
<> 144:ef7eb2e8f9f7 506 * @}
<> 144:ef7eb2e8f9f7 507 */
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/