mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 83:a036322b8637

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_uart.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.0
<>	144:ef7eb2e8f9f7	6	* @date 22-April-2016
<>	144:ef7eb2e8f9f7	7	* @brief UART HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	144:ef7eb2e8f9f7	12	* + Peripheral Control functions
<>	144:ef7eb2e8f9f7	13	* + Peripheral State and Errors functions
<>	144:ef7eb2e8f9f7	14	*
<>	144:ef7eb2e8f9f7	15	@verbatim
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	[..]
<>	144:ef7eb2e8f9f7	20	The UART HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	21
<>	144:ef7eb2e8f9f7	22	(#) Declare a UART_HandleTypeDef handle structure.
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the USARTx interface clock.
<>	144:ef7eb2e8f9f7	26	(##) UART pins configuration:
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the UART GPIOs.
<>	144:ef7eb2e8f9f7	28	(+++) Configure these UART pins as alternate function pull-up.
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	30	and HAL_UART_Receive_IT() APIs):
<>	144:ef7eb2e8f9f7	31	(+++) Configure the USARTx interrupt priority.
<>	144:ef7eb2e8f9f7	32	(+++) Enable the NVIC USART IRQ handle.
<>	144:ef7eb2e8f9f7	33	(##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	34	and HAL_UART_Receive_DMA() APIs):
<>	144:ef7eb2e8f9f7	35	(+++) Declare a DMA handle structure for the Tx/Rx stream.
<>	144:ef7eb2e8f9f7	36	(+++) Enable the DMAx interface clock.
<>	144:ef7eb2e8f9f7	37	(+++) Configure the declared DMA handle structure with the required
<>	144:ef7eb2e8f9f7	38	Tx/Rx parameters.
<>	144:ef7eb2e8f9f7	39	(+++) Configure the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	40	(+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
<>	144:ef7eb2e8f9f7	41	(+++) Configure the priority and enable the NVIC for the transfer complete
<>	144:ef7eb2e8f9f7	42	interrupt on the DMA Tx/Rx Stream.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
<>	144:ef7eb2e8f9f7	45	flow control and Mode(Receiver/Transmitter) in the Init structure.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) For the UART asynchronous mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	48	the HAL_UART_Init() API.
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) For the UART Half duplex mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	51	the HAL_HalfDuplex_Init() API.
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	(#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	(#) For the Multi-Processor mode, initialize the UART registers by calling
<>	144:ef7eb2e8f9f7	56	the HAL_MultiProcessor_Init() API.
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	[..]
<>	144:ef7eb2e8f9f7	59	(@) The specific UART interrupts (Transmission complete interrupt,
<>	144:ef7eb2e8f9f7	60	RXNE interrupt and Error Interrupts) will be managed using the macros
<>	144:ef7eb2e8f9f7	61	__HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
<>	144:ef7eb2e8f9f7	62	and receive process.
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	[..]
<>	144:ef7eb2e8f9f7	65	(@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
<>	144:ef7eb2e8f9f7	66	low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
<>	144:ef7eb2e8f9f7	67	HAL_UART_MspInit() API.
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	[..]
<>	144:ef7eb2e8f9f7	70	Three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	73	=================================
<>	144:ef7eb2e8f9f7	74	[..]
<>	144:ef7eb2e8f9f7	75	(+) Send an amount of data in blocking mode using HAL_UART_Transmit()
<>	144:ef7eb2e8f9f7	76	(+) Receive an amount of data in blocking mode using HAL_UART_Receive()
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	79	===================================
<>	144:ef7eb2e8f9f7	80	[..]
<>	144:ef7eb2e8f9f7	81	(+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	82	(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	83	add his own code by customization of function pointer HAL_UART_TxCpltCallback
<>	144:ef7eb2e8f9f7	84	(+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
<>	144:ef7eb2e8f9f7	85	(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	86	add his own code by customization of function pointer HAL_UART_RxCpltCallback
<>	144:ef7eb2e8f9f7	87	(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	88	add his own code by customization of function pointer HAL_UART_ErrorCallback
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	91	==============================
<>	144:ef7eb2e8f9f7	92	[..]
<>	144:ef7eb2e8f9f7	93	(+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	94	(+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	95	add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
<>	144:ef7eb2e8f9f7	96	(+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	97	add his own code by customization of function pointer HAL_UART_TxCpltCallback
<>	144:ef7eb2e8f9f7	98	(+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
<>	144:ef7eb2e8f9f7	99	(+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	100	add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
<>	144:ef7eb2e8f9f7	101	(+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
<>	144:ef7eb2e8f9f7	102	add his own code by customization of function pointer HAL_UART_RxCpltCallback
<>	144:ef7eb2e8f9f7	103	(+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	104	add his own code by customization of function pointer HAL_UART_ErrorCallback
<>	144:ef7eb2e8f9f7	105	(+) Pause the DMA Transfer using HAL_UART_DMAPause()
<>	144:ef7eb2e8f9f7	106	(+) Resume the DMA Transfer using HAL_UART_DMAResume()
<>	144:ef7eb2e8f9f7	107	(+) Stop the DMA Transfer using HAL_UART_DMAStop()
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	* UART HAL driver macros list *
<>	144:ef7eb2e8f9f7	110	=============================================
<>	144:ef7eb2e8f9f7	111	[..]
<>	144:ef7eb2e8f9f7	112	Below the list of most used macros in UART HAL driver.
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	(+) __HAL_UART_ENABLE: Enable the UART peripheral
<>	144:ef7eb2e8f9f7	115	(+) __HAL_UART_DISABLE: Disable the UART peripheral
<>	144:ef7eb2e8f9f7	116	(+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
<>	144:ef7eb2e8f9f7	117	(+) __HAL_UART_CLEAR_IT : Clears the specified UART ISR flag
<>	144:ef7eb2e8f9f7	118	(+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
<>	144:ef7eb2e8f9f7	119	(+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
<>	144:ef7eb2e8f9f7	120	(+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122	[..]
<>	144:ef7eb2e8f9f7	123	(@) You can refer to the UART HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	@endverbatim
<>	144:ef7eb2e8f9f7	126	******************************************************************************
<>	144:ef7eb2e8f9f7	127	* @attention
<>	144:ef7eb2e8f9f7	128	*
<>	144:ef7eb2e8f9f7	129	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	130	*
<>	144:ef7eb2e8f9f7	131	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	132	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	133	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	134	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	135	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	136	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	137	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	138	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	139	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	140	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	141	*
<>	144:ef7eb2e8f9f7	142	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	143	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	144	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	145	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	146	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	147	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	148	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	149	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	150	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	151	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	152	*
<>	144:ef7eb2e8f9f7	153	******************************************************************************
<>	144:ef7eb2e8f9f7	154	*/
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	157	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	158
<>	144:ef7eb2e8f9f7	159	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	160	* @{
<>	144:ef7eb2e8f9f7	161	*/
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	/** @defgroup UART UART
<>	144:ef7eb2e8f9f7	164	* @brief HAL UART module driver
<>	144:ef7eb2e8f9f7	165	* @{
<>	144:ef7eb2e8f9f7	166	*/
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	#ifdef HAL_UART_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	169
<>	144:ef7eb2e8f9f7	170	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	171	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	172	/** @defgroup UART_Private_Constants UART Private Constants
<>	144:ef7eb2e8f9f7	173	* @{
<>	144:ef7eb2e8f9f7	174	*/
<>	144:ef7eb2e8f9f7	175	#define UART_CR1_FIELDS ((uint32_t)(USART_CR1_M \| USART_CR1_PCE \| USART_CR1_PS \| \
<>	144:ef7eb2e8f9f7	176	USART_CR1_TE \| USART_CR1_RE \| USART_CR1_OVER8))
<>	144:ef7eb2e8f9f7	177	/**
<>	144:ef7eb2e8f9f7	178	* @}
<>	144:ef7eb2e8f9f7	179	*/
<>	144:ef7eb2e8f9f7	180	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	181	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	182	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	183	/** @addtogroup UART_Private_Functions
<>	144:ef7eb2e8f9f7	184	* @{
<>	144:ef7eb2e8f9f7	185	*/
<>	144:ef7eb2e8f9f7	186	static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	187	static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	188	static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	189	static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	190	static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	191	static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	192	static void UART_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	193	static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	194	static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	195	static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	196	static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	197	/**
<>	144:ef7eb2e8f9f7	198	* @}
<>	144:ef7eb2e8f9f7	199	*/
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	/** @defgroup UART_Exported_Functions UART Exported Functions
<>	144:ef7eb2e8f9f7	204	* @{
<>	144:ef7eb2e8f9f7	205	*/
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	208	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	209	*
<>	144:ef7eb2e8f9f7	210	@verbatim
<>	144:ef7eb2e8f9f7	211	===============================================================================
<>	144:ef7eb2e8f9f7	212	##### Initialization and Configuration functions #####
<>	144:ef7eb2e8f9f7	213	===============================================================================
<>	144:ef7eb2e8f9f7	214	[..]
<>	144:ef7eb2e8f9f7	215	This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
<>	144:ef7eb2e8f9f7	216	in asynchronous mode.
<>	144:ef7eb2e8f9f7	217	(+) For the asynchronous mode only these parameters can be configured:
<>	144:ef7eb2e8f9f7	218	(++) Baud Rate
<>	144:ef7eb2e8f9f7	219	(++) Word Length
<>	144:ef7eb2e8f9f7	220	(++) Stop Bit
<>	144:ef7eb2e8f9f7	221	(++) Parity: If the parity is enabled, then the MSB bit of the data written
<>	144:ef7eb2e8f9f7	222	in the data register is transmitted but is changed by the parity bit.
<>	144:ef7eb2e8f9f7	223	Depending on the frame length defined by the M bit (8-bits or 9-bits),
<>	144:ef7eb2e8f9f7	224	please refer to Reference manual for possible UART frame formats.
<>	144:ef7eb2e8f9f7	225	(++) Hardware flow control
<>	144:ef7eb2e8f9f7	226	(++) Receiver/transmitter modes
<>	144:ef7eb2e8f9f7	227	(++) Over Sampling Method
<>	144:ef7eb2e8f9f7	228	[..]
<>	144:ef7eb2e8f9f7	229	The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
<>	144:ef7eb2e8f9f7	230	follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
<>	144:ef7eb2e8f9f7	231	configuration procedures (details for the procedures are available in reference manual (RM0329)).
<>	144:ef7eb2e8f9f7	232
<>	144:ef7eb2e8f9f7	233	@endverbatim
<>	144:ef7eb2e8f9f7	234	* @{
<>	144:ef7eb2e8f9f7	235	*/
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/**
<>	144:ef7eb2e8f9f7	238	* @brief Initializes the UART mode according to the specified
<>	144:ef7eb2e8f9f7	239	* parameters in the UART_InitTypeDef and creates the associated handle .
<>	144:ef7eb2e8f9f7	240	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	241	* @retval HAL status
<>	144:ef7eb2e8f9f7	242	*/
<>	144:ef7eb2e8f9f7	243	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	244	{
<>	144:ef7eb2e8f9f7	245	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	246	if(huart == NULL)
<>	144:ef7eb2e8f9f7	247	{
<>	144:ef7eb2e8f9f7	248	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	249	}
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
<>	144:ef7eb2e8f9f7	252	{
<>	144:ef7eb2e8f9f7	253	/* Check the parameters */
<>	144:ef7eb2e8f9f7	254	assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	255	}
<>	144:ef7eb2e8f9f7	256	else
<>	144:ef7eb2e8f9f7	257	{
<>	144:ef7eb2e8f9f7	258	/* Check the parameters */
<>	144:ef7eb2e8f9f7	259	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	260	}
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	263	{
<>	144:ef7eb2e8f9f7	264	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	265	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	268	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	269	}
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	274	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	275
<>	144:ef7eb2e8f9f7	276	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	277	if (UART_SetConfig(huart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	278	{
<>	144:ef7eb2e8f9f7	279	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	280	}
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<>	144:ef7eb2e8f9f7	283	{
<>	144:ef7eb2e8f9f7	284	UART_AdvFeatureConfig(huart);
<>	144:ef7eb2e8f9f7	285	}
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287	/* In asynchronous mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	288	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	289	- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	290	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	291	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	294	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	297	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	298	}
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @brief Initializes the half-duplex mode according to the specified
<>	144:ef7eb2e8f9f7	302	* parameters in the UART_InitTypeDef and creates the associated handle .
<>	144:ef7eb2e8f9f7	303	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	304	* @retval HAL status
<>	144:ef7eb2e8f9f7	305	*/
<>	144:ef7eb2e8f9f7	306	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	307	{
<>	144:ef7eb2e8f9f7	308	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	309	if(huart == NULL)
<>	144:ef7eb2e8f9f7	310	{
<>	144:ef7eb2e8f9f7	311	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	312	}
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	315	{
<>	144:ef7eb2e8f9f7	316	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	317	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	320	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	321	}
<>	144:ef7eb2e8f9f7	322
<>	144:ef7eb2e8f9f7	323	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	326	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	329	if (UART_SetConfig(huart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	330	{
<>	144:ef7eb2e8f9f7	331	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	332	}
<>	144:ef7eb2e8f9f7	333
<>	144:ef7eb2e8f9f7	334	if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<>	144:ef7eb2e8f9f7	335	{
<>	144:ef7eb2e8f9f7	336	UART_AdvFeatureConfig(huart);
<>	144:ef7eb2e8f9f7	337	}
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/* In half-duplex mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	340	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	341	- SCEN and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	342	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	343	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN \| USART_CR3_SCEN));
<>	144:ef7eb2e8f9f7	344
<>	144:ef7eb2e8f9f7	345	/* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
<>	144:ef7eb2e8f9f7	346	SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	349	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	352	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	353	}
<>	144:ef7eb2e8f9f7	354
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/**
<>	144:ef7eb2e8f9f7	357	* @brief Initialize the LIN mode according to the specified
<>	144:ef7eb2e8f9f7	358	* parameters in the UART_InitTypeDef and creates the associated handle .
<>	144:ef7eb2e8f9f7	359	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	360	* @param BreakDetectLength: specifies the LIN break detection length.
<>	144:ef7eb2e8f9f7	361	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	362	* @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
<>	144:ef7eb2e8f9f7	363	* @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
<>	144:ef7eb2e8f9f7	364	* @retval HAL status
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
<>	144:ef7eb2e8f9f7	367	{
<>	144:ef7eb2e8f9f7	368	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	369	if(huart == NULL)
<>	144:ef7eb2e8f9f7	370	{
<>	144:ef7eb2e8f9f7	371	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	372	}
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	/* Check the parameters */
<>	144:ef7eb2e8f9f7	375	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	376	assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
<>	144:ef7eb2e8f9f7	377	assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	380	{
<>	144:ef7eb2e8f9f7	381	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	382	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	385	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	386	}
<>	144:ef7eb2e8f9f7	387
<>	144:ef7eb2e8f9f7	388	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	391	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	394	if (UART_SetConfig(huart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	395	{
<>	144:ef7eb2e8f9f7	396	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	397	}
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399	if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<>	144:ef7eb2e8f9f7	400	{
<>	144:ef7eb2e8f9f7	401	UART_AdvFeatureConfig(huart);
<>	144:ef7eb2e8f9f7	402	}
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/* In LIN mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	405	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	406	- SCEN and IREN bits in the USART_CR3 register.*/
<>	144:ef7eb2e8f9f7	407	CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
<>	144:ef7eb2e8f9f7	408	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL \| USART_CR3_IREN \| USART_CR3_SCEN));
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410	/* Enable the LIN mode by setting the LINEN bit in the CR2 register */
<>	144:ef7eb2e8f9f7	411	SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
<>	144:ef7eb2e8f9f7	412
<>	144:ef7eb2e8f9f7	413	/* Set the USART LIN Break detection length. */
<>	144:ef7eb2e8f9f7	414	MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	417	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	420	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	421	}
<>	144:ef7eb2e8f9f7	422
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/**
<>	144:ef7eb2e8f9f7	425	* @brief Initialize the multiprocessor mode according to the specified
<>	144:ef7eb2e8f9f7	426	* parameters in the UART_InitTypeDef and initialize the associated handle.
<>	144:ef7eb2e8f9f7	427	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	428	* @param Address: UART node address (4-, 6-, 7- or 8-bit long).
<>	144:ef7eb2e8f9f7	429	* @param WakeUpMethod: specifies the UART wakeup method.
<>	144:ef7eb2e8f9f7	430	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	431	* @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
<>	144:ef7eb2e8f9f7	432	* @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
<>	144:ef7eb2e8f9f7	433	* @note If the user resorts to idle line detection wake up, the Address parameter
<>	144:ef7eb2e8f9f7	434	* is useless and ignored by the initialization function.
<>	144:ef7eb2e8f9f7	435	* @note If the user resorts to address mark wake up, the address length detection
<>	144:ef7eb2e8f9f7	436	* is configured by default to 4 bits only. For the UART to be able to
<>	144:ef7eb2e8f9f7	437	* manage 6-, 7- or 8-bit long addresses detection
<>	144:ef7eb2e8f9f7	438	* @retval HAL status
<>	144:ef7eb2e8f9f7	439	*/
<>	144:ef7eb2e8f9f7	440	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
<>	144:ef7eb2e8f9f7	441	{
<>	144:ef7eb2e8f9f7	442	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	443	if(huart == NULL)
<>	144:ef7eb2e8f9f7	444	{
<>	144:ef7eb2e8f9f7	445	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	446	}
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/* Check the wake up method parameter */
<>	144:ef7eb2e8f9f7	449	assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	452	{
<>	144:ef7eb2e8f9f7	453	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	454	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	455
<>	144:ef7eb2e8f9f7	456	/* Init the low level hardware : GPIO, CLOCK */
<>	144:ef7eb2e8f9f7	457	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	458	}
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	463	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	464
<>	144:ef7eb2e8f9f7	465	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	466	if (UART_SetConfig(huart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	467	{
<>	144:ef7eb2e8f9f7	468	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	469	}
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<>	144:ef7eb2e8f9f7	472	{
<>	144:ef7eb2e8f9f7	473	UART_AdvFeatureConfig(huart);
<>	144:ef7eb2e8f9f7	474	}
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/* In multiprocessor mode, the following bits must be kept cleared:
<>	144:ef7eb2e8f9f7	477	- LINEN and CLKEN bits in the USART_CR2 register,
<>	144:ef7eb2e8f9f7	478	- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
<>	144:ef7eb2e8f9f7	479	CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN \| USART_CR2_CLKEN));
<>	144:ef7eb2e8f9f7	480	CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN \| USART_CR3_HDSEL \| USART_CR3_IREN));
<>	144:ef7eb2e8f9f7	481
<>	144:ef7eb2e8f9f7	482	if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
<>	144:ef7eb2e8f9f7	483	{
<>	144:ef7eb2e8f9f7	484	/* If address mark wake up method is chosen, set the USART address node */
<>	144:ef7eb2e8f9f7	485	MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
<>	144:ef7eb2e8f9f7	486	}
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	/* Set the wake up method by setting the WAKE bit in the CR1 register */
<>	144:ef7eb2e8f9f7	489	MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
<>	144:ef7eb2e8f9f7	490
<>	144:ef7eb2e8f9f7	491	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	492	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	493
<>	144:ef7eb2e8f9f7	494	/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	495	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	496	}
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/**
<>	144:ef7eb2e8f9f7	500	* @brief Initialize the RS485 Driver enable feature according to the specified
<>	144:ef7eb2e8f9f7	501	* parameters in the UART_InitTypeDef and creates the associated handle.
<>	144:ef7eb2e8f9f7	502	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	503	* @param Polarity: select the driver enable polarity.
<>	144:ef7eb2e8f9f7	504	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	505	* @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
<>	144:ef7eb2e8f9f7	506	* @arg @ref UART_DE_POLARITY_LOW DE signal is active low
<>	144:ef7eb2e8f9f7	507	* @param AssertionTime: Driver Enable assertion time:
<>	144:ef7eb2e8f9f7	508	* 5-bit value defining the time between the activation of the DE (Driver Enable)
<>	144:ef7eb2e8f9f7	509	* signal and the beginning of the start bit. It is expressed in sample time
<>	144:ef7eb2e8f9f7	510	* units (1/8 or 1/16 bit time, depending on the oversampling rate)
<>	144:ef7eb2e8f9f7	511	* @param DeassertionTime: Driver Enable deassertion time:
<>	144:ef7eb2e8f9f7	512	* 5-bit value defining the time between the end of the last stop bit, in a
<>	144:ef7eb2e8f9f7	513	* transmitted message, and the de-activation of the DE (Driver Enable) signal.
<>	144:ef7eb2e8f9f7	514	* It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
<>	144:ef7eb2e8f9f7	515	* oversampling rate).
<>	144:ef7eb2e8f9f7	516	* @retval HAL status
<>	144:ef7eb2e8f9f7	517	*/
<>	144:ef7eb2e8f9f7	518	HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
<>	144:ef7eb2e8f9f7	519	{
<>	144:ef7eb2e8f9f7	520	uint32_t temp = 0x0;
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	523	if(huart == NULL)
<>	144:ef7eb2e8f9f7	524	{
<>	144:ef7eb2e8f9f7	525	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	526	}
<>	144:ef7eb2e8f9f7	527	/* Check the Driver Enable UART instance */
<>	144:ef7eb2e8f9f7	528	assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* Check the Driver Enable polarity */
<>	144:ef7eb2e8f9f7	531	assert_param(IS_UART_DE_POLARITY(Polarity));
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/* Check the Driver Enable assertion time */
<>	144:ef7eb2e8f9f7	534	assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/* Check the Driver Enable deassertion time */
<>	144:ef7eb2e8f9f7	537	assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	if(huart->gState == HAL_UART_STATE_RESET)
<>	144:ef7eb2e8f9f7	540	{
<>	144:ef7eb2e8f9f7	541	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	542	huart->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/* Init the low level hardware : GPIO, CLOCK, CORTEX */
<>	144:ef7eb2e8f9f7	545	HAL_UART_MspInit(huart);
<>	144:ef7eb2e8f9f7	546	}
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	551	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	552
<>	144:ef7eb2e8f9f7	553	/* Set the UART Communication parameters */
<>	144:ef7eb2e8f9f7	554	if (UART_SetConfig(huart) == HAL_ERROR)
<>	144:ef7eb2e8f9f7	555	{
<>	144:ef7eb2e8f9f7	556	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	557	}
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
<>	144:ef7eb2e8f9f7	560	{
<>	144:ef7eb2e8f9f7	561	UART_AdvFeatureConfig(huart);
<>	144:ef7eb2e8f9f7	562	}
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
<>	144:ef7eb2e8f9f7	565	SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/* Set the Driver Enable polarity */
<>	144:ef7eb2e8f9f7	568	MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/* Set the Driver Enable assertion and deassertion times */
<>	144:ef7eb2e8f9f7	571	temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
<>	144:ef7eb2e8f9f7	572	temp \|= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
<>	144:ef7eb2e8f9f7	573	MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT\|USART_CR1_DEAT), temp);
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	576	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	577
<>	144:ef7eb2e8f9f7	578	/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	579	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	580	}
<>	144:ef7eb2e8f9f7	581
<>	144:ef7eb2e8f9f7	582	/**
<>	144:ef7eb2e8f9f7	583	* @brief DeInitializes the UART peripheral
<>	144:ef7eb2e8f9f7	584	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	585	* @retval HAL status
<>	144:ef7eb2e8f9f7	586	*/
<>	144:ef7eb2e8f9f7	587	HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	588	{
<>	144:ef7eb2e8f9f7	589	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	590	if(huart == NULL)
<>	144:ef7eb2e8f9f7	591	{
<>	144:ef7eb2e8f9f7	592	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	593	}
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/* Check the parameters */
<>	144:ef7eb2e8f9f7	596	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	601	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	huart->Instance->CR1 = 0x0U;
<>	144:ef7eb2e8f9f7	604	huart->Instance->CR2 = 0x0U;
<>	144:ef7eb2e8f9f7	605	huart->Instance->CR3 = 0x0U;
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	/* DeInit the low level hardware */
<>	144:ef7eb2e8f9f7	608	HAL_UART_MspDeInit(huart);
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	611	huart->gState = HAL_UART_STATE_RESET;
<>	144:ef7eb2e8f9f7	612	huart->RxState = HAL_UART_STATE_RESET;
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	/* Process Unlock */
<>	144:ef7eb2e8f9f7	615	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	616
<>	144:ef7eb2e8f9f7	617	return HAL_OK;
<>	144:ef7eb2e8f9f7	618	}
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/**
<>	144:ef7eb2e8f9f7	621	* @brief UART MSP Init
<>	144:ef7eb2e8f9f7	622	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	623	* @retval None
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625	__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	626	{
<>	144:ef7eb2e8f9f7	627	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	628	UNUSED(huart);
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	631	the HAL_UART_MspInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	632	*/
<>	144:ef7eb2e8f9f7	633	}
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/**
<>	144:ef7eb2e8f9f7	636	* @brief UART MSP DeInit
<>	144:ef7eb2e8f9f7	637	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	638	* @retval None
<>	144:ef7eb2e8f9f7	639	*/
<>	144:ef7eb2e8f9f7	640	__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	641	{
<>	144:ef7eb2e8f9f7	642	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	643	UNUSED(huart);
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	646	the HAL_UART_MspDeInit can be implemented in the user file
<>	144:ef7eb2e8f9f7	647	*/
<>	144:ef7eb2e8f9f7	648	}
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	/**
<>	144:ef7eb2e8f9f7	651	* @}
<>	144:ef7eb2e8f9f7	652	*/
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	/** @defgroup UART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	655	* @brief UART Transmit/Receive functions
<>	144:ef7eb2e8f9f7	656	*
<>	144:ef7eb2e8f9f7	657	@verbatim
<>	144:ef7eb2e8f9f7	658	===============================================================================
<>	144:ef7eb2e8f9f7	659	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	660	===============================================================================
<>	144:ef7eb2e8f9f7	661	This subsection provides a set of functions allowing to manage the UART asynchronous
<>	144:ef7eb2e8f9f7	662	and Half duplex data transfers.
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	(#) There are two mode of transfer:
<>	144:ef7eb2e8f9f7	665	(+) Blocking mode: The communication is performed in polling mode.
<>	144:ef7eb2e8f9f7	666	The HAL status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	667	after finishing transfer.
<>	144:ef7eb2e8f9f7	668	(+) Non-Blocking mode: The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	669	or DMA, These API's return the HAL status.
<>	144:ef7eb2e8f9f7	670	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	671	dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	672	using DMA mode.
<>	144:ef7eb2e8f9f7	673	The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
<>	144:ef7eb2e8f9f7	674	will be executed respectively at the end of the transmit or Receive process
<>	144:ef7eb2e8f9f7	675	The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	(#) Blocking mode API's are :
<>	144:ef7eb2e8f9f7	678	(+) HAL_UART_Transmit()
<>	144:ef7eb2e8f9f7	679	(+) HAL_UART_Receive()
<>	144:ef7eb2e8f9f7	680
<>	144:ef7eb2e8f9f7	681	(#) Non-Blocking mode API's with Interrupt are :
<>	144:ef7eb2e8f9f7	682	(+) HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	683	(+) HAL_UART_Receive_IT()
<>	144:ef7eb2e8f9f7	684	(+) HAL_UART_IRQHandler()
<>	144:ef7eb2e8f9f7	685	(+) UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	686	(+) UART_Receive_IT()
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	(#) Non-Blocking mode API's with DMA are :
<>	144:ef7eb2e8f9f7	689	(+) HAL_UART_Transmit_DMA()
<>	144:ef7eb2e8f9f7	690	(+) HAL_UART_Receive_DMA()
<>	144:ef7eb2e8f9f7	691	(+) HAL_UART_DMAPause()
<>	144:ef7eb2e8f9f7	692	(+) HAL_UART_DMAResume()
<>	144:ef7eb2e8f9f7	693	(+) HAL_UART_DMAStop()
<>	144:ef7eb2e8f9f7	694
<>	144:ef7eb2e8f9f7	695	(#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
<>	144:ef7eb2e8f9f7	696	(+) HAL_UART_TxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	697	(+) HAL_UART_TxCpltCallback()
<>	144:ef7eb2e8f9f7	698	(+) HAL_UART_RxHalfCpltCallback()
<>	144:ef7eb2e8f9f7	699	(+) HAL_UART_RxCpltCallback()
<>	144:ef7eb2e8f9f7	700	(+) HAL_UART_ErrorCallback()
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	-@- In the Half duplex communication, it is forbidden to run the transmit
<>	144:ef7eb2e8f9f7	704	and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706	@endverbatim
<>	144:ef7eb2e8f9f7	707	* @{
<>	144:ef7eb2e8f9f7	708	*/
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	/**
<>	144:ef7eb2e8f9f7	711	* @brief Send an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	712	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	713	* @param pData: Pointer to data buffer.
<>	144:ef7eb2e8f9f7	714	* @param Size: Amount of data to be sent.
<>	144:ef7eb2e8f9f7	715	* @param Timeout: Timeout duration.
<>	144:ef7eb2e8f9f7	716	* @retval HAL status
<>	144:ef7eb2e8f9f7	717	*/
<>	144:ef7eb2e8f9f7	718	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	719	{
<>	144:ef7eb2e8f9f7	720	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	721	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	724	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	725	{
<>	144:ef7eb2e8f9f7	726	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	729	}
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Process Locked */
<>	144:ef7eb2e8f9f7	732	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	735	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Init tickstart for timeout managment*/
<>	144:ef7eb2e8f9f7	738	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	739
<>	144:ef7eb2e8f9f7	740	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	741	huart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	742	while(huart->TxXferCount > 0U)
<>	144:ef7eb2e8f9f7	743	{
<>	144:ef7eb2e8f9f7	744	huart->TxXferCount--;
<>	144:ef7eb2e8f9f7	745	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	746	{
<>	144:ef7eb2e8f9f7	747	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	748	}
<>	144:ef7eb2e8f9f7	749	if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	750	{
<>	144:ef7eb2e8f9f7	751	tmp = (uint16_t*) pData;
<>	144:ef7eb2e8f9f7	752	huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<>	144:ef7eb2e8f9f7	753	pData += 2;
<>	144:ef7eb2e8f9f7	754	}
<>	144:ef7eb2e8f9f7	755	else
<>	144:ef7eb2e8f9f7	756	{
<>	144:ef7eb2e8f9f7	757	huart->Instance->TDR = (*pData++ & (uint8_t)0xFFU);
<>	144:ef7eb2e8f9f7	758	}
<>	144:ef7eb2e8f9f7	759	}
<>	144:ef7eb2e8f9f7	760	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	761	{
<>	144:ef7eb2e8f9f7	762	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	763	}
<>	144:ef7eb2e8f9f7	764
<>	144:ef7eb2e8f9f7	765	/* At end of Tx process, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	766	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	769	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771	return HAL_OK;
<>	144:ef7eb2e8f9f7	772	}
<>	144:ef7eb2e8f9f7	773	else
<>	144:ef7eb2e8f9f7	774	{
<>	144:ef7eb2e8f9f7	775	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/**
<>	144:ef7eb2e8f9f7	780	* @brief Receive an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	781	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	782	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	783	* @param Size: amount of data to be received.
<>	144:ef7eb2e8f9f7	784	* @param Timeout: Timeout duration.
<>	144:ef7eb2e8f9f7	785	* @retval HAL status
<>	144:ef7eb2e8f9f7	786	*/
<>	144:ef7eb2e8f9f7	787	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	788	{
<>	144:ef7eb2e8f9f7	789	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	790	uint16_t uhMask;
<>	144:ef7eb2e8f9f7	791	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	792
<>	144:ef7eb2e8f9f7	793	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	794	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	795	{
<>	144:ef7eb2e8f9f7	796	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	797	{
<>	144:ef7eb2e8f9f7	798	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	799	}
<>	144:ef7eb2e8f9f7	800
<>	144:ef7eb2e8f9f7	801	/* Process Locked */
<>	144:ef7eb2e8f9f7	802	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	803
<>	144:ef7eb2e8f9f7	804	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	805	huart->RxState = HAL_UART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	/* Init tickstart for timeout managment*/
<>	144:ef7eb2e8f9f7	808	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	811	huart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	812
<>	144:ef7eb2e8f9f7	813	/* Computation of UART mask to apply to RDR register */
<>	144:ef7eb2e8f9f7	814	UART_MASK_COMPUTATION(huart);
<>	144:ef7eb2e8f9f7	815	uhMask = huart->Mask;
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	/* as long as data have to be received */
<>	144:ef7eb2e8f9f7	818	while(huart->RxXferCount > 0U)
<>	144:ef7eb2e8f9f7	819	{
<>	144:ef7eb2e8f9f7	820	huart->RxXferCount--;
<>	144:ef7eb2e8f9f7	821	if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
<>	144:ef7eb2e8f9f7	822	{
<>	144:ef7eb2e8f9f7	823	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	824	}
<>	144:ef7eb2e8f9f7	825	if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	826	{
<>	144:ef7eb2e8f9f7	827	tmp = (uint16_t*) pData ;
<>	144:ef7eb2e8f9f7	828	*tmp = (uint16_t)(huart->Instance->RDR & uhMask);
<>	144:ef7eb2e8f9f7	829	pData +=2U;
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831	else
<>	144:ef7eb2e8f9f7	832	{
<>	144:ef7eb2e8f9f7	833	*pData++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	834	}
<>	144:ef7eb2e8f9f7	835	}
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	838	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	841	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	return HAL_OK;
<>	144:ef7eb2e8f9f7	844	}
<>	144:ef7eb2e8f9f7	845	else
<>	144:ef7eb2e8f9f7	846	{
<>	144:ef7eb2e8f9f7	847	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	848	}
<>	144:ef7eb2e8f9f7	849	}
<>	144:ef7eb2e8f9f7	850
<>	144:ef7eb2e8f9f7	851	/**
<>	144:ef7eb2e8f9f7	852	* @brief Send an amount of data in interrupt mode.
<>	144:ef7eb2e8f9f7	853	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	854	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	855	* @param Size: amount of data to be sent.
<>	144:ef7eb2e8f9f7	856	* @retval HAL status
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	859	{
<>	144:ef7eb2e8f9f7	860	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	861	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	864	{
<>	144:ef7eb2e8f9f7	865	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	866	}
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/* Process Locked */
<>	144:ef7eb2e8f9f7	869	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	huart->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	872	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	873	huart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	876	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	879	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Enable the UART Transmit Data Register Empty Interrupt */
<>	144:ef7eb2e8f9f7	882	SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	return HAL_OK;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886	else
<>	144:ef7eb2e8f9f7	887	{
<>	144:ef7eb2e8f9f7	888	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	889	}
<>	144:ef7eb2e8f9f7	890	}
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/**
<>	144:ef7eb2e8f9f7	893	* @brief Receive an amount of data in interrupt mode.
<>	144:ef7eb2e8f9f7	894	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	895	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	896	* @param Size: amount of data to be received.
<>	144:ef7eb2e8f9f7	897	* @retval HAL status
<>	144:ef7eb2e8f9f7	898	*/
<>	144:ef7eb2e8f9f7	899	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	900	{
<>	144:ef7eb2e8f9f7	901	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	902	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	903	{
<>	144:ef7eb2e8f9f7	904	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	905	{
<>	144:ef7eb2e8f9f7	906	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	907	}
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/* Process Locked */
<>	144:ef7eb2e8f9f7	910	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	911
<>	144:ef7eb2e8f9f7	912	huart->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	913	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	914	huart->RxXferCount = Size;
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/* Computation of UART mask to apply to RDR register */
<>	144:ef7eb2e8f9f7	917	UART_MASK_COMPUTATION(huart);
<>	144:ef7eb2e8f9f7	918
<>	144:ef7eb2e8f9f7	919	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	920	huart->RxState = HAL_UART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	921
<>	144:ef7eb2e8f9f7	922	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	923	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/* Enable the UART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	926	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	929	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/* Enable the UART Data Register not empty Interrupt */
<>	144:ef7eb2e8f9f7	932	SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
<>	144:ef7eb2e8f9f7	933
<>	144:ef7eb2e8f9f7	934	return HAL_OK;
<>	144:ef7eb2e8f9f7	935	}
<>	144:ef7eb2e8f9f7	936	else
<>	144:ef7eb2e8f9f7	937	{
<>	144:ef7eb2e8f9f7	938	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	939	}
<>	144:ef7eb2e8f9f7	940	}
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	/**
<>	144:ef7eb2e8f9f7	943	* @brief Send an amount of data in DMA mode.
<>	144:ef7eb2e8f9f7	944	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	945	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	946	* @param Size: amount of data to be sent.
<>	144:ef7eb2e8f9f7	947	* @retval HAL status
<>	144:ef7eb2e8f9f7	948	*/
<>	144:ef7eb2e8f9f7	949	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	950	{
<>	144:ef7eb2e8f9f7	951	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* Check that a Tx process is not already ongoing */
<>	144:ef7eb2e8f9f7	954	if(huart->gState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	955	{
<>	144:ef7eb2e8f9f7	956	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	957	{
<>	144:ef7eb2e8f9f7	958	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	959	}
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	/* Process Locked */
<>	144:ef7eb2e8f9f7	962	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	huart->pTxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	965	huart->TxXferSize = Size;
<>	144:ef7eb2e8f9f7	966	huart->TxXferCount = Size;
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	969	huart->gState = HAL_UART_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	/* Set the UART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	972	huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/* Set the UART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	975	huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	978	huart->hdmatx->XferErrorCallback = UART_DMAError;
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	981	huart->hdmatx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/* Enable the UART transmit DMA channel */
<>	144:ef7eb2e8f9f7	984	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	985	HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)tmp, (uint32_t)&huart->Instance->TDR, Size);
<>	144:ef7eb2e8f9f7	986
<>	144:ef7eb2e8f9f7	987	/* Clear the TC flag in the SR register by writing 0 to it */
<>	144:ef7eb2e8f9f7	988	__HAL_UART_CLEAR_IT(huart, UART_FLAG_TC);
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	991	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	992
<>	144:ef7eb2e8f9f7	993	/* Enable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	994	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	995	SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	return HAL_OK;
<>	144:ef7eb2e8f9f7	998	}
<>	144:ef7eb2e8f9f7	999	else
<>	144:ef7eb2e8f9f7	1000	{
<>	144:ef7eb2e8f9f7	1001	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1002	}
<>	144:ef7eb2e8f9f7	1003	}
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	/**
<>	144:ef7eb2e8f9f7	1006	* @brief Receive an amount of data in DMA mode.
<>	144:ef7eb2e8f9f7	1007	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1008	* @param pData: pointer to data buffer.
<>	144:ef7eb2e8f9f7	1009	* @param Size: amount of data to be received.
<>	144:ef7eb2e8f9f7	1010	* @note When the UART parity is enabled (PCE = 1), the received data contain
<>	144:ef7eb2e8f9f7	1011	* the parity bit (MSB position).
<>	144:ef7eb2e8f9f7	1012	* @retval HAL status
<>	144:ef7eb2e8f9f7	1013	*/
<>	144:ef7eb2e8f9f7	1014	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	uint32_t *tmp;
<>	144:ef7eb2e8f9f7	1017
<>	144:ef7eb2e8f9f7	1018	/* Check that a Rx process is not already ongoing */
<>	144:ef7eb2e8f9f7	1019	if(huart->RxState == HAL_UART_STATE_READY)
<>	144:ef7eb2e8f9f7	1020	{
<>	144:ef7eb2e8f9f7	1021	if((pData == NULL ) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1022	{
<>	144:ef7eb2e8f9f7	1023	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1024	}
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Process Locked */
<>	144:ef7eb2e8f9f7	1027	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	huart->pRxBuffPtr = pData;
<>	144:ef7eb2e8f9f7	1030	huart->RxXferSize = Size;
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1033	huart->RxState = HAL_UART_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/* Set the UART DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1036	huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	/* Set the UART DMA Half transfer complete callback */
<>	144:ef7eb2e8f9f7	1039	huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1042	huart->hdmarx->XferErrorCallback = UART_DMAError;
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	/* Set the DMA abort callback */
<>	144:ef7eb2e8f9f7	1045	huart->hdmarx->XferAbortCallback = NULL;
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1048	tmp = (uint32_t*)&pData;
<>	144:ef7eb2e8f9f7	1049	HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)tmp, Size);
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1052	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	/* Enable the UART Parity Error Interrupt */
<>	144:ef7eb2e8f9f7	1055	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	1058	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/* Enable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	1061	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	1062	SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1063
<>	144:ef7eb2e8f9f7	1064	return HAL_OK;
<>	144:ef7eb2e8f9f7	1065	}
<>	144:ef7eb2e8f9f7	1066	else
<>	144:ef7eb2e8f9f7	1067	{
<>	144:ef7eb2e8f9f7	1068	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1069	}
<>	144:ef7eb2e8f9f7	1070	}
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/**
<>	144:ef7eb2e8f9f7	1073	* @brief Pause the DMA Transfer.
<>	144:ef7eb2e8f9f7	1074	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1075	* @retval HAL status
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1078	{
<>	144:ef7eb2e8f9f7	1079	/* Process Locked */
<>	144:ef7eb2e8f9f7	1080	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<>	144:ef7eb2e8f9f7	1083	(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<>	144:ef7eb2e8f9f7	1084	{
<>	144:ef7eb2e8f9f7	1085	/* Disable the UART DMA Tx request */
<>	144:ef7eb2e8f9f7	1086	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1087	}
<>	144:ef7eb2e8f9f7	1088	if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<>	144:ef7eb2e8f9f7	1089	(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<>	144:ef7eb2e8f9f7	1090	{
<>	144:ef7eb2e8f9f7	1091	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1092	CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1093	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	/* Disable the UART DMA Rx request */
<>	144:ef7eb2e8f9f7	1096	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1097	}
<>	144:ef7eb2e8f9f7	1098
<>	144:ef7eb2e8f9f7	1099	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1100	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1101
<>	144:ef7eb2e8f9f7	1102	return HAL_OK;
<>	144:ef7eb2e8f9f7	1103	}
<>	144:ef7eb2e8f9f7	1104
<>	144:ef7eb2e8f9f7	1105	/**
<>	144:ef7eb2e8f9f7	1106	* @brief Resume the DMA Transfer.
<>	144:ef7eb2e8f9f7	1107	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1108	* @retval HAL status
<>	144:ef7eb2e8f9f7	1109	*/
<>	144:ef7eb2e8f9f7	1110	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1111	{
<>	144:ef7eb2e8f9f7	1112	/* Process Locked */
<>	144:ef7eb2e8f9f7	1113	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1114
<>	144:ef7eb2e8f9f7	1115	if(huart->gState == HAL_UART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1116	{
<>	144:ef7eb2e8f9f7	1117	/* Enable the UART DMA Tx request */
<>	144:ef7eb2e8f9f7	1118	SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1119	}
<>	144:ef7eb2e8f9f7	1120	if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1121	{
<>	144:ef7eb2e8f9f7	1122	/* Clear the Overrun flag before resuming the Rx transfer*/
<>	144:ef7eb2e8f9f7	1123	__HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1126	SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1127	SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1128
<>	144:ef7eb2e8f9f7	1129	/* Enable the UART DMA Rx request */
<>	144:ef7eb2e8f9f7	1130	SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1131	}
<>	144:ef7eb2e8f9f7	1132
<>	144:ef7eb2e8f9f7	1133	/* If the UART peripheral is still not enabled, enable it */
<>	144:ef7eb2e8f9f7	1134	if ((huart->Instance->CR1 & USART_CR1_UE) == 0U)
<>	144:ef7eb2e8f9f7	1135	{
<>	144:ef7eb2e8f9f7	1136	/* Enable UART peripheral */
<>	144:ef7eb2e8f9f7	1137	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	1138	}
<>	144:ef7eb2e8f9f7	1139
<>	144:ef7eb2e8f9f7	1140	return HAL_OK;
<>	144:ef7eb2e8f9f7	1141	}
<>	144:ef7eb2e8f9f7	1142
<>	144:ef7eb2e8f9f7	1143	/**
<>	144:ef7eb2e8f9f7	1144	* @brief Stop the DMA Transfer.
<>	144:ef7eb2e8f9f7	1145	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1146	* @retval HAL status
<>	144:ef7eb2e8f9f7	1147	*/
<>	144:ef7eb2e8f9f7	1148	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1149	{
<>	144:ef7eb2e8f9f7	1150	/* The Lock is not implemented on this API to allow the user application
<>	144:ef7eb2e8f9f7	1151	to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
<>	144:ef7eb2e8f9f7	1152	HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
<>	144:ef7eb2e8f9f7	1153	indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
<>	144:ef7eb2e8f9f7	1154	interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
<>	144:ef7eb2e8f9f7	1155	the stream and the corresponding call back is executed. */
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/* Stop UART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	1158	if ((huart->gState == HAL_UART_STATE_BUSY_TX) &&
<>	144:ef7eb2e8f9f7	1159	(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)))
<>	144:ef7eb2e8f9f7	1160	{
<>	144:ef7eb2e8f9f7	1161	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Abort the UART DMA Tx channel */
<>	144:ef7eb2e8f9f7	1164	if(huart->hdmatx != NULL)
<>	144:ef7eb2e8f9f7	1165	{
<>	144:ef7eb2e8f9f7	1166	HAL_DMA_Abort(huart->hdmatx);
<>	144:ef7eb2e8f9f7	1167	}
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	UART_EndTxTransfer(huart);
<>	144:ef7eb2e8f9f7	1170	}
<>	144:ef7eb2e8f9f7	1171
<>	144:ef7eb2e8f9f7	1172	/* Stop UART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	1173	if ((huart->RxState == HAL_UART_STATE_BUSY_RX) &&
<>	144:ef7eb2e8f9f7	1174	(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<>	144:ef7eb2e8f9f7	1175	{
<>	144:ef7eb2e8f9f7	1176	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/* Abort the UART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1179	if(huart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1180	{
<>	144:ef7eb2e8f9f7	1181	HAL_DMA_Abort(huart->hdmarx);
<>	144:ef7eb2e8f9f7	1182	}
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	1185	}
<>	144:ef7eb2e8f9f7	1186
<>	144:ef7eb2e8f9f7	1187	return HAL_OK;
<>	144:ef7eb2e8f9f7	1188	}
<>	144:ef7eb2e8f9f7	1189
<>	144:ef7eb2e8f9f7	1190	/**
<>	144:ef7eb2e8f9f7	1191	* @brief This function handles UART interrupt request.
<>	144:ef7eb2e8f9f7	1192	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1193	* @retval None
<>	144:ef7eb2e8f9f7	1194	*/
<>	144:ef7eb2e8f9f7	1195	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1196	{
<>	144:ef7eb2e8f9f7	1197	uint32_t isrflags = READ_REG(huart->Instance->ISR);
<>	144:ef7eb2e8f9f7	1198	uint32_t cr1its = READ_REG(huart->Instance->CR1);
<>	144:ef7eb2e8f9f7	1199	uint32_t cr3its = READ_REG(huart->Instance->CR3);
<>	144:ef7eb2e8f9f7	1200	uint32_t errorflags;
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/* If no error occurs */
<>	144:ef7eb2e8f9f7	1203	errorflags = (isrflags & (uint32_t)(USART_ISR_PE \| USART_ISR_FE \| USART_ISR_ORE \| USART_ISR_NE));
<>	144:ef7eb2e8f9f7	1204	if (errorflags == RESET)
<>	144:ef7eb2e8f9f7	1205	{
<>	144:ef7eb2e8f9f7	1206	/* UART in mode Receiver ---------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1207	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1208	{
<>	144:ef7eb2e8f9f7	1209	UART_Receive_IT(huart);
<>	144:ef7eb2e8f9f7	1210	return;
<>	144:ef7eb2e8f9f7	1211	}
<>	144:ef7eb2e8f9f7	1212	}
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/* If some errors occur */
<>	144:ef7eb2e8f9f7	1215	if((errorflags != RESET) && ((cr3its & (USART_CR3_EIE \| USART_CR1_PEIE)) != RESET))
<>	144:ef7eb2e8f9f7	1216	{
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* UART parity error interrupt occurred -------------------------------------*/
<>	144:ef7eb2e8f9f7	1219	if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
<>	144:ef7eb2e8f9f7	1220	{
<>	144:ef7eb2e8f9f7	1221	__HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF);
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	huart->ErrorCode \|= HAL_UART_ERROR_PE;
<>	144:ef7eb2e8f9f7	1224	}
<>	144:ef7eb2e8f9f7	1225
<>	144:ef7eb2e8f9f7	1226	/* UART frame error interrupt occurred --------------------------------------*/
<>	144:ef7eb2e8f9f7	1227	if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1228	{
<>	144:ef7eb2e8f9f7	1229	__HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF);
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	huart->ErrorCode \|= HAL_UART_ERROR_FE;
<>	144:ef7eb2e8f9f7	1232	}
<>	144:ef7eb2e8f9f7	1233
<>	144:ef7eb2e8f9f7	1234	/* UART noise error interrupt occurred --------------------------------------*/
<>	144:ef7eb2e8f9f7	1235	if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
<>	144:ef7eb2e8f9f7	1236	{
<>	144:ef7eb2e8f9f7	1237	__HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF);
<>	144:ef7eb2e8f9f7	1238
<>	144:ef7eb2e8f9f7	1239	huart->ErrorCode \|= HAL_UART_ERROR_NE;
<>	144:ef7eb2e8f9f7	1240	}
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	/* UART Over-Run interrupt occurred -----------------------------------------*/
<>	144:ef7eb2e8f9f7	1243	if(((isrflags & USART_ISR_ORE) != RESET) &&
<>	144:ef7eb2e8f9f7	1244	(((cr1its & USART_CR1_RXNEIE) != RESET) \|\| ((cr3its & USART_CR3_EIE) != RESET)))
<>	144:ef7eb2e8f9f7	1245	{
<>	144:ef7eb2e8f9f7	1246	__HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF);
<>	144:ef7eb2e8f9f7	1247
<>	144:ef7eb2e8f9f7	1248	huart->ErrorCode \|= HAL_UART_ERROR_ORE;
<>	144:ef7eb2e8f9f7	1249	}
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/* Call UART Error Call back function if need be --------------------------*/
<>	144:ef7eb2e8f9f7	1252	if(huart->ErrorCode != HAL_UART_ERROR_NONE)
<>	144:ef7eb2e8f9f7	1253	{
<>	144:ef7eb2e8f9f7	1254	/* UART in mode Receiver ---------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1255	if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
<>	144:ef7eb2e8f9f7	1256	{
<>	144:ef7eb2e8f9f7	1257	UART_Receive_IT(huart);
<>	144:ef7eb2e8f9f7	1258	}
<>	144:ef7eb2e8f9f7	1259
<>	144:ef7eb2e8f9f7	1260	/* If Overrun error occurs, or if any error occurs in DMA mode reception,
<>	144:ef7eb2e8f9f7	1261	consider error as blocking */
<>	144:ef7eb2e8f9f7	1262	if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) \|\|
<>	144:ef7eb2e8f9f7	1263	(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)))
<>	144:ef7eb2e8f9f7	1264	{
<>	144:ef7eb2e8f9f7	1265	/* Blocking error : transfer is aborted
<>	144:ef7eb2e8f9f7	1266	Set the UART state ready to be able to start again the process,
<>	144:ef7eb2e8f9f7	1267	Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
<>	144:ef7eb2e8f9f7	1268	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	1269
<>	144:ef7eb2e8f9f7	1270	/* Disable the UART DMA Rx request if enabled */
<>	144:ef7eb2e8f9f7	1271	if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
<>	144:ef7eb2e8f9f7	1272	{
<>	144:ef7eb2e8f9f7	1273	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1274
<>	144:ef7eb2e8f9f7	1275	/* Abort the UART DMA Rx channel */
<>	144:ef7eb2e8f9f7	1276	if(huart->hdmarx != NULL)
<>	144:ef7eb2e8f9f7	1277	{
<>	144:ef7eb2e8f9f7	1278	/* Set the UART DMA Abort callback :
<>	144:ef7eb2e8f9f7	1279	will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
<>	144:ef7eb2e8f9f7	1280	huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
<>	144:ef7eb2e8f9f7	1281
<>	144:ef7eb2e8f9f7	1282	/* Abort DMA RX */
<>	144:ef7eb2e8f9f7	1283	if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
<>	144:ef7eb2e8f9f7	1284	{
<>	144:ef7eb2e8f9f7	1285	/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
<>	144:ef7eb2e8f9f7	1286	huart->hdmarx->XferAbortCallback(huart->hdmarx);
<>	144:ef7eb2e8f9f7	1287	}
<>	144:ef7eb2e8f9f7	1288	}
<>	144:ef7eb2e8f9f7	1289	else
<>	144:ef7eb2e8f9f7	1290	{
<>	144:ef7eb2e8f9f7	1291	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1292	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1293	}
<>	144:ef7eb2e8f9f7	1294	}
<>	144:ef7eb2e8f9f7	1295	else
<>	144:ef7eb2e8f9f7	1296	{
<>	144:ef7eb2e8f9f7	1297	/* Call user error callback */
<>	144:ef7eb2e8f9f7	1298	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1299	}
<>	144:ef7eb2e8f9f7	1300	}
<>	144:ef7eb2e8f9f7	1301	else
<>	144:ef7eb2e8f9f7	1302	{
<>	144:ef7eb2e8f9f7	1303	/* Non Blocking error : transfer could go on.
<>	144:ef7eb2e8f9f7	1304	Error is notified to user through user error callback */
<>	144:ef7eb2e8f9f7	1305	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1306	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1307	}
<>	144:ef7eb2e8f9f7	1308	}
<>	144:ef7eb2e8f9f7	1309	return;
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	} /* End if some error occurs */
<>	144:ef7eb2e8f9f7	1312
<>	144:ef7eb2e8f9f7	1313	/* UART in mode Transmitter ------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1314	if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
<>	144:ef7eb2e8f9f7	1315	{
<>	144:ef7eb2e8f9f7	1316	UART_Transmit_IT(huart);
<>	144:ef7eb2e8f9f7	1317	return;
<>	144:ef7eb2e8f9f7	1318	}
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	/* UART in mode Transmitter (transmission end) -----------------------------*/
<>	144:ef7eb2e8f9f7	1321	if(((isrflags & USART_ISR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
<>	144:ef7eb2e8f9f7	1322	{
<>	144:ef7eb2e8f9f7	1323	UART_EndTransmit_IT(huart);
<>	144:ef7eb2e8f9f7	1324	return;
<>	144:ef7eb2e8f9f7	1325	}
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	}
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/**
<>	144:ef7eb2e8f9f7	1330	* @brief This function handles UART Communication Timeout.
<>	144:ef7eb2e8f9f7	1331	* @param huart UART handle
<>	144:ef7eb2e8f9f7	1332	* @param Flag specifies the UART flag to check.
<>	144:ef7eb2e8f9f7	1333	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	1334	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	1335	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1336	* @retval HAL status
<>	144:ef7eb2e8f9f7	1337	*/
<>	144:ef7eb2e8f9f7	1338	HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1339	{
<>	144:ef7eb2e8f9f7	1340	/* Wait until flag is set */
<>	144:ef7eb2e8f9f7	1341	while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	1342	{
<>	144:ef7eb2e8f9f7	1343	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1344	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1345	{
<>	144:ef7eb2e8f9f7	1346	if((Timeout == 0U)\|\|((HAL_GetTick()-Tickstart) >= Timeout))
<>	144:ef7eb2e8f9f7	1347	{
<>	144:ef7eb2e8f9f7	1348	/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
<>	144:ef7eb2e8f9f7	1349	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE \| USART_CR1_TXEIE));
<>	144:ef7eb2e8f9f7	1350	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1351
<>	144:ef7eb2e8f9f7	1352	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1353	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1354
<>	144:ef7eb2e8f9f7	1355	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1356	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	1357	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1358	}
<>	144:ef7eb2e8f9f7	1359	}
<>	144:ef7eb2e8f9f7	1360	}
<>	144:ef7eb2e8f9f7	1361	return HAL_OK;
<>	144:ef7eb2e8f9f7	1362	}
<>	144:ef7eb2e8f9f7	1363
<>	144:ef7eb2e8f9f7	1364	/**
<>	144:ef7eb2e8f9f7	1365	* @brief DMA UART transmit process complete callback
<>	144:ef7eb2e8f9f7	1366	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1367	* @retval None
<>	144:ef7eb2e8f9f7	1368	*/
<>	144:ef7eb2e8f9f7	1369	static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1370	{
<>	144:ef7eb2e8f9f7	1371	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1372
<>	144:ef7eb2e8f9f7	1373	/* DMA Normal mode*/
<>	144:ef7eb2e8f9f7	1374	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	1375	{
<>	144:ef7eb2e8f9f7	1376	huart->TxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	/* Disable the DMA transfer for transmit request by setting the DMAT bit
<>	144:ef7eb2e8f9f7	1379	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	1380	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/* Enable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	1383	SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385	/* DMA Circular mode */
<>	144:ef7eb2e8f9f7	1386	else
<>	144:ef7eb2e8f9f7	1387	{
<>	144:ef7eb2e8f9f7	1388	HAL_UART_TxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1389	}
<>	144:ef7eb2e8f9f7	1390	}
<>	144:ef7eb2e8f9f7	1391
<>	144:ef7eb2e8f9f7	1392	/**
<>	144:ef7eb2e8f9f7	1393	* @brief DMA UART transmit process half complete callback
<>	144:ef7eb2e8f9f7	1394	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	1395	* @retval None
<>	144:ef7eb2e8f9f7	1396	*/
<>	144:ef7eb2e8f9f7	1397	static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1398	{
<>	144:ef7eb2e8f9f7	1399	UART_HandleTypeDef* huart = (UART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	HAL_UART_TxHalfCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1402	}
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/**
<>	144:ef7eb2e8f9f7	1405	* @brief DMA UART receive process complete callback
<>	144:ef7eb2e8f9f7	1406	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1407	* @retval None
<>	144:ef7eb2e8f9f7	1408	*/
<>	144:ef7eb2e8f9f7	1409	static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1410	{
<>	144:ef7eb2e8f9f7	1411	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/* DMA Normal mode */
<>	144:ef7eb2e8f9f7	1414	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
<>	144:ef7eb2e8f9f7	1415	{
<>	144:ef7eb2e8f9f7	1416	huart->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1417
<>	144:ef7eb2e8f9f7	1418	/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1419	CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
<>	144:ef7eb2e8f9f7	1420	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1421
<>	144:ef7eb2e8f9f7	1422	/* Disable the DMA transfer for the receiver request by setting the DMAR bit
<>	144:ef7eb2e8f9f7	1423	in the UART CR3 register */
<>	144:ef7eb2e8f9f7	1424	CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
<>	144:ef7eb2e8f9f7	1425
<>	144:ef7eb2e8f9f7	1426	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	1427	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1428	}
<>	144:ef7eb2e8f9f7	1429	HAL_UART_RxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1430	}
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	/**
<>	144:ef7eb2e8f9f7	1433	* @brief DMA UART receive process half complete callback
<>	144:ef7eb2e8f9f7	1434	* @param hdma : DMA handle
<>	144:ef7eb2e8f9f7	1435	* @retval None
<>	144:ef7eb2e8f9f7	1436	*/
<>	144:ef7eb2e8f9f7	1437	static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1438	{
<>	144:ef7eb2e8f9f7	1439	UART_HandleTypeDef* huart = (UART_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	HAL_UART_RxHalfCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1442	}
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/**
<>	144:ef7eb2e8f9f7	1445	* @brief DMA UART communication error callback
<>	144:ef7eb2e8f9f7	1446	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	1447	* @retval None
<>	144:ef7eb2e8f9f7	1448	*/
<>	144:ef7eb2e8f9f7	1449	static void UART_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1450	{
<>	144:ef7eb2e8f9f7	1451	UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	1452	huart->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1453	huart->TxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1454	/* Stop UART DMA Tx request if ongoing */
<>	144:ef7eb2e8f9f7	1455	if ( (huart->gState == HAL_UART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1456	&&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) )
<>	144:ef7eb2e8f9f7	1457	{
<>	144:ef7eb2e8f9f7	1458	UART_EndTxTransfer(huart);
<>	144:ef7eb2e8f9f7	1459	}
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	/* Stop UART DMA Rx request if ongoing */
<>	144:ef7eb2e8f9f7	1462	if ( (huart->RxState == HAL_UART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1463	&&(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) )
<>	144:ef7eb2e8f9f7	1464	{
<>	144:ef7eb2e8f9f7	1465	UART_EndRxTransfer(huart);
<>	144:ef7eb2e8f9f7	1466	}
<>	144:ef7eb2e8f9f7	1467	SET_BIT(huart->ErrorCode, HAL_UART_ERROR_DMA);
<>	144:ef7eb2e8f9f7	1468	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1469	}
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/**
<>	144:ef7eb2e8f9f7	1472	* @brief DMA UART communication abort callback, when call by HAL services on Error
<>	144:ef7eb2e8f9f7	1473	* (To be called at end of DMA Abort procedure following error occurrence).
<>	144:ef7eb2e8f9f7	1474	* @param hdma: DMA handle.
<>	144:ef7eb2e8f9f7	1475	* @retval None
<>	144:ef7eb2e8f9f7	1476	*/
<>	144:ef7eb2e8f9f7	1477	static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	1478	{
<>	144:ef7eb2e8f9f7	1479	UART_HandleTypeDef* huart = (UART_HandleTypeDef*)(hdma->Parent);
<>	144:ef7eb2e8f9f7	1480	huart->RxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1481	huart->TxXferCount = 0U;
<>	144:ef7eb2e8f9f7	1482
<>	144:ef7eb2e8f9f7	1483	HAL_UART_ErrorCallback(huart);
<>	144:ef7eb2e8f9f7	1484	}
<>	144:ef7eb2e8f9f7	1485
<>	144:ef7eb2e8f9f7	1486	/**
<>	144:ef7eb2e8f9f7	1487	* @brief Tx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1488	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1489	* @retval None
<>	144:ef7eb2e8f9f7	1490	*/
<>	144:ef7eb2e8f9f7	1491	__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1492	{
<>	144:ef7eb2e8f9f7	1493	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1494	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1497	the HAL_UART_TxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1498	*/
<>	144:ef7eb2e8f9f7	1499	}
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/**
<>	144:ef7eb2e8f9f7	1502	* @brief Tx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1503	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	1504	* @retval None
<>	144:ef7eb2e8f9f7	1505	*/
<>	144:ef7eb2e8f9f7	1506	__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1507	{
<>	144:ef7eb2e8f9f7	1508	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1509	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1510
<>	144:ef7eb2e8f9f7	1511	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1512	the HAL_UART_TxHalfCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1513	*/
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516	/**
<>	144:ef7eb2e8f9f7	1517	* @brief Rx Transfer completed callbacks
<>	144:ef7eb2e8f9f7	1518	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1519	* @retval None
<>	144:ef7eb2e8f9f7	1520	*/
<>	144:ef7eb2e8f9f7	1521	__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1522	{
<>	144:ef7eb2e8f9f7	1523	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1524	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1525
<>	144:ef7eb2e8f9f7	1526	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1527	the HAL_UART_RxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1528	*/
<>	144:ef7eb2e8f9f7	1529	}
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	/**
<>	144:ef7eb2e8f9f7	1532	* @brief Rx Half Transfer completed callbacks.
<>	144:ef7eb2e8f9f7	1533	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	1534	* @retval None
<>	144:ef7eb2e8f9f7	1535	*/
<>	144:ef7eb2e8f9f7	1536	__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1537	{
<>	144:ef7eb2e8f9f7	1538	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1539	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	/* NOTE: This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1542	the HAL_UART_RxHalfCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1543	*/
<>	144:ef7eb2e8f9f7	1544	}
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	/**
<>	144:ef7eb2e8f9f7	1547	* @brief UART error callbacks
<>	144:ef7eb2e8f9f7	1548	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1549	* @retval None
<>	144:ef7eb2e8f9f7	1550	*/
<>	144:ef7eb2e8f9f7	1551	__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1552	{
<>	144:ef7eb2e8f9f7	1553	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	1554	UNUSED(huart);
<>	144:ef7eb2e8f9f7	1555
<>	144:ef7eb2e8f9f7	1556	/* NOTE : This function should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	1557	the HAL_UART_ErrorCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	1558	*/
<>	144:ef7eb2e8f9f7	1559	}
<>	144:ef7eb2e8f9f7	1560
<>	144:ef7eb2e8f9f7	1561	/**
<>	144:ef7eb2e8f9f7	1562	* @brief Send an amount of data in interrupt mode
<>	144:ef7eb2e8f9f7	1563	* Function called under interruption only, once
<>	144:ef7eb2e8f9f7	1564	* interruptions have been enabled by HAL_UART_Transmit_IT()
<>	144:ef7eb2e8f9f7	1565	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	1566	* @retval HAL status
<>	144:ef7eb2e8f9f7	1567	*/
<>	144:ef7eb2e8f9f7	1568	static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1569	{
<>	144:ef7eb2e8f9f7	1570	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/* Check that a Tx process is ongoing */
<>	144:ef7eb2e8f9f7	1573	if (huart->gState == HAL_UART_STATE_BUSY_TX)
<>	144:ef7eb2e8f9f7	1574	{
<>	144:ef7eb2e8f9f7	1575
<>	144:ef7eb2e8f9f7	1576	if(huart->TxXferCount == 0U)
<>	144:ef7eb2e8f9f7	1577	{
<>	144:ef7eb2e8f9f7	1578	/* Disable the UART Transmit Data Register Empty Interrupt */
<>	144:ef7eb2e8f9f7	1579	CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* Enable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	1582	SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	1583
<>	144:ef7eb2e8f9f7	1584	return HAL_OK;
<>	144:ef7eb2e8f9f7	1585	}
<>	144:ef7eb2e8f9f7	1586	else
<>	144:ef7eb2e8f9f7	1587	{
<>	144:ef7eb2e8f9f7	1588	if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	1589	{
<>	144:ef7eb2e8f9f7	1590	tmp = (uint16_t*) huart->pTxBuffPtr;
<>	144:ef7eb2e8f9f7	1591	huart->Instance->TDR = (*tmp & (uint16_t)0x01FFU);
<>	144:ef7eb2e8f9f7	1592	huart->pTxBuffPtr += 2U;
<>	144:ef7eb2e8f9f7	1593	}
<>	144:ef7eb2e8f9f7	1594	else
<>	144:ef7eb2e8f9f7	1595	{
<>	144:ef7eb2e8f9f7	1596	huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0xFFU);
<>	144:ef7eb2e8f9f7	1597	}
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	huart->TxXferCount--;
<>	144:ef7eb2e8f9f7	1600
<>	144:ef7eb2e8f9f7	1601	return HAL_OK;
<>	144:ef7eb2e8f9f7	1602	}
<>	144:ef7eb2e8f9f7	1603	}
<>	144:ef7eb2e8f9f7	1604	else
<>	144:ef7eb2e8f9f7	1605	{
<>	144:ef7eb2e8f9f7	1606	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1607	}
<>	144:ef7eb2e8f9f7	1608	}
<>	144:ef7eb2e8f9f7	1609
<>	144:ef7eb2e8f9f7	1610	/**
<>	144:ef7eb2e8f9f7	1611	* @brief Wrap up transmission in non-blocking mode.
<>	144:ef7eb2e8f9f7	1612	* @param huart: pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1613	* the configuration information for the specified UART module.
<>	144:ef7eb2e8f9f7	1614	* @retval HAL status
<>	144:ef7eb2e8f9f7	1615	*/
<>	144:ef7eb2e8f9f7	1616	static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1617	{
<>	144:ef7eb2e8f9f7	1618	/* Disable the UART Transmit Complete Interrupt */
<>	144:ef7eb2e8f9f7	1619	CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
<>	144:ef7eb2e8f9f7	1620
<>	144:ef7eb2e8f9f7	1621	/* Tx process is ended, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	1622	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1623
<>	144:ef7eb2e8f9f7	1624	HAL_UART_TxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1625
<>	144:ef7eb2e8f9f7	1626	return HAL_OK;
<>	144:ef7eb2e8f9f7	1627	}
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	/**
<>	144:ef7eb2e8f9f7	1630	* @brief Receive an amount of data in interrupt mode
<>	144:ef7eb2e8f9f7	1631	* Function called under interruption only, once
<>	144:ef7eb2e8f9f7	1632	* interruptions have been enabled by HAL_UART_Receive_IT()
<>	144:ef7eb2e8f9f7	1633	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	1634	* @retval HAL status
<>	144:ef7eb2e8f9f7	1635	*/
<>	144:ef7eb2e8f9f7	1636	static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1637	{
<>	144:ef7eb2e8f9f7	1638	uint16_t* tmp;
<>	144:ef7eb2e8f9f7	1639	uint16_t uhMask = huart->Mask;
<>	144:ef7eb2e8f9f7	1640
<>	144:ef7eb2e8f9f7	1641	/* Check that a Rx process is ongoing */
<>	144:ef7eb2e8f9f7	1642	if(huart->RxState == HAL_UART_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	1643	{
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
<>	144:ef7eb2e8f9f7	1646	{
<>	144:ef7eb2e8f9f7	1647	tmp = (uint16_t*) huart->pRxBuffPtr ;
<>	144:ef7eb2e8f9f7	1648	*tmp = (uint16_t)(huart->Instance->RDR & uhMask);
<>	144:ef7eb2e8f9f7	1649	huart->pRxBuffPtr +=2;
<>	144:ef7eb2e8f9f7	1650	}
<>	144:ef7eb2e8f9f7	1651	else
<>	144:ef7eb2e8f9f7	1652	{
<>	144:ef7eb2e8f9f7	1653	*huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
<>	144:ef7eb2e8f9f7	1654	}
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	if(--huart->RxXferCount == 0)
<>	144:ef7eb2e8f9f7	1657	{
<>	144:ef7eb2e8f9f7	1658	/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
<>	144:ef7eb2e8f9f7	1659	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
<>	144:ef7eb2e8f9f7	1662	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	/* Rx process is completed, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	1665	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	HAL_UART_RxCpltCallback(huart);
<>	144:ef7eb2e8f9f7	1668
<>	144:ef7eb2e8f9f7	1669	return HAL_OK;
<>	144:ef7eb2e8f9f7	1670	}
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	return HAL_OK;
<>	144:ef7eb2e8f9f7	1673	}
<>	144:ef7eb2e8f9f7	1674	else
<>	144:ef7eb2e8f9f7	1675	{
<>	144:ef7eb2e8f9f7	1676	/* Clear RXNE interrupt flag */
<>	144:ef7eb2e8f9f7	1677	__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
<>	144:ef7eb2e8f9f7	1678
<>	144:ef7eb2e8f9f7	1679	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1680	}
<>	144:ef7eb2e8f9f7	1681	}
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/**
<>	144:ef7eb2e8f9f7	1684	* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
<>	144:ef7eb2e8f9f7	1685	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1686	* @retval None
<>	144:ef7eb2e8f9f7	1687	*/
<>	144:ef7eb2e8f9f7	1688	static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1689	{
<>	144:ef7eb2e8f9f7	1690	/* Disable TXEIE and TCIE interrupts */
<>	144:ef7eb2e8f9f7	1691	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE \| USART_CR1_TCIE));
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	/* At end of Tx process, restore huart->gState to Ready */
<>	144:ef7eb2e8f9f7	1694	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1695	}
<>	144:ef7eb2e8f9f7	1696
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	/**
<>	144:ef7eb2e8f9f7	1699	* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
<>	144:ef7eb2e8f9f7	1700	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	1701	* @retval None
<>	144:ef7eb2e8f9f7	1702	*/
<>	144:ef7eb2e8f9f7	1703	static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1704	{
<>	144:ef7eb2e8f9f7	1705	/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
<>	144:ef7eb2e8f9f7	1706	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE \| USART_CR1_PEIE));
<>	144:ef7eb2e8f9f7	1707	CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
<>	144:ef7eb2e8f9f7	1708
<>	144:ef7eb2e8f9f7	1709	/* At end of Rx process, restore huart->RxState to Ready */
<>	144:ef7eb2e8f9f7	1710	huart->RxState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1711	}
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/**
<>	144:ef7eb2e8f9f7	1714	* @}
<>	144:ef7eb2e8f9f7	1715	*/
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1718	* @brief UART control functions
<>	144:ef7eb2e8f9f7	1719	*
<>	144:ef7eb2e8f9f7	1720	@verbatim
<>	144:ef7eb2e8f9f7	1721	===============================================================================
<>	144:ef7eb2e8f9f7	1722	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	1723	===============================================================================
<>	144:ef7eb2e8f9f7	1724	[..]
<>	144:ef7eb2e8f9f7	1725	This subsection provides a set of functions allowing to control the UART.
<>	144:ef7eb2e8f9f7	1726	(+) HAL_UART_GetState() API is helpful to check in run-time the state of the UART peripheral.
<>	144:ef7eb2e8f9f7	1727	(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
<>	144:ef7eb2e8f9f7	1728	(+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
<>	144:ef7eb2e8f9f7	1729	(+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
<>	144:ef7eb2e8f9f7	1730	(+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
<>	144:ef7eb2e8f9f7	1731	(+) UART_SetConfig() API configures the UART peripheral
<>	144:ef7eb2e8f9f7	1732	(+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
<>	144:ef7eb2e8f9f7	1733	(+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
<>	144:ef7eb2e8f9f7	1734	(+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
<>	144:ef7eb2e8f9f7	1735	(+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
<>	144:ef7eb2e8f9f7	1736	(+) HAL_LIN_SendBreak() API transmits the break characters
<>	144:ef7eb2e8f9f7	1737	(+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
<>	144:ef7eb2e8f9f7	1738	detection length to more than 4 bits for multiprocessor address mark wake up.
<>	144:ef7eb2e8f9f7	1739	@endverbatim
<>	144:ef7eb2e8f9f7	1740	* @{
<>	144:ef7eb2e8f9f7	1741	*/
<>	144:ef7eb2e8f9f7	1742
<>	144:ef7eb2e8f9f7	1743	/**
<>	144:ef7eb2e8f9f7	1744	* @brief Enable UART in mute mode (doesn't mean UART enters mute mode;
<>	144:ef7eb2e8f9f7	1745	* to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called)
<>	144:ef7eb2e8f9f7	1746	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	1747	* @retval HAL status
<>	144:ef7eb2e8f9f7	1748	*/
<>	144:ef7eb2e8f9f7	1749	HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1750	{
<>	144:ef7eb2e8f9f7	1751	/* Process Locked */
<>	144:ef7eb2e8f9f7	1752	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1753
<>	144:ef7eb2e8f9f7	1754	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1755
<>	144:ef7eb2e8f9f7	1756	/* Enable USART mute mode by setting the MME bit in the CR1 register */
<>	144:ef7eb2e8f9f7	1757	SET_BIT(huart->Instance->CR1, USART_CR1_MME);
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	1762	}
<>	144:ef7eb2e8f9f7	1763
<>	144:ef7eb2e8f9f7	1764	/**
<>	144:ef7eb2e8f9f7	1765	* @brief Disable UART mute mode (doesn't mean it actually wakes up the software,
<>	144:ef7eb2e8f9f7	1766	* as it may not have been in mute mode at this very moment).
<>	144:ef7eb2e8f9f7	1767	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1768	* @retval HAL status
<>	144:ef7eb2e8f9f7	1769	*/
<>	144:ef7eb2e8f9f7	1770	HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1771	{
<>	144:ef7eb2e8f9f7	1772	/* Process Locked */
<>	144:ef7eb2e8f9f7	1773	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/* Disable USART mute mode by clearing the MME bit in the CR1 register */
<>	144:ef7eb2e8f9f7	1778	CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	1781
<>	144:ef7eb2e8f9f7	1782	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	1783	}
<>	144:ef7eb2e8f9f7	1784
<>	144:ef7eb2e8f9f7	1785	/**
<>	144:ef7eb2e8f9f7	1786	* @brief Enter UART mute mode (means UART actually enters mute mode).
<>	144:ef7eb2e8f9f7	1787	* To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
<>	144:ef7eb2e8f9f7	1788	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1789	* @retval HAL status
<>	144:ef7eb2e8f9f7	1790	*/
<>	144:ef7eb2e8f9f7	1791	void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1792	{
<>	144:ef7eb2e8f9f7	1793	__HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
<>	144:ef7eb2e8f9f7	1794	}
<>	144:ef7eb2e8f9f7	1795
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/**
<>	144:ef7eb2e8f9f7	1799	* @brief return the UART state
<>	144:ef7eb2e8f9f7	1800	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1801	* @retval HAL state
<>	144:ef7eb2e8f9f7	1802	*/
<>	144:ef7eb2e8f9f7	1803	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1804	{
<>	144:ef7eb2e8f9f7	1805	uint32_t temp1= 0x00U, temp2 = 0x00U;
<>	144:ef7eb2e8f9f7	1806	temp1 = huart->gState;
<>	144:ef7eb2e8f9f7	1807	temp2 = huart->RxState;
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	return (HAL_UART_StateTypeDef)(temp1 \| temp2);
<>	144:ef7eb2e8f9f7	1810	}
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/**
<>	144:ef7eb2e8f9f7	1813	* @brief Return the UART error code
<>	144:ef7eb2e8f9f7	1814	* @param huart : pointer to a UART_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1815	* the configuration information for the specified UART.
<>	144:ef7eb2e8f9f7	1816	* @retval UART Error Code
<>	144:ef7eb2e8f9f7	1817	*/
<>	144:ef7eb2e8f9f7	1818	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1819	{
<>	144:ef7eb2e8f9f7	1820	return huart->ErrorCode;
<>	144:ef7eb2e8f9f7	1821	}
<>	144:ef7eb2e8f9f7	1822
<>	144:ef7eb2e8f9f7	1823	/**
<>	144:ef7eb2e8f9f7	1824	* @brief Configure the UART peripheral
<>	144:ef7eb2e8f9f7	1825	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1826	* @retval None
<>	144:ef7eb2e8f9f7	1827	*/
<>	144:ef7eb2e8f9f7	1828	HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1829	{
<>	144:ef7eb2e8f9f7	1830	uint32_t tmpreg = 0x00000000U;
<>	144:ef7eb2e8f9f7	1831	UART_ClockSourceTypeDef clocksource = UART_CLOCKSOURCE_UNDEFINED;
<>	144:ef7eb2e8f9f7	1832	uint16_t brrtemp = 0x0000U;
<>	144:ef7eb2e8f9f7	1833	uint16_t usartdiv = 0x0000U;
<>	144:ef7eb2e8f9f7	1834	HAL_StatusTypeDef ret = HAL_OK;
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1837	assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1838	assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
<>	144:ef7eb2e8f9f7	1839	assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
<>	144:ef7eb2e8f9f7	1840	assert_param(IS_UART_PARITY(huart->Init.Parity));
<>	144:ef7eb2e8f9f7	1841	assert_param(IS_UART_MODE(huart->Init.Mode));
<>	144:ef7eb2e8f9f7	1842	assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
<>	144:ef7eb2e8f9f7	1843	assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
<>	144:ef7eb2e8f9f7	1844
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	/-------------------------- USART CR1 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1847	/* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
<>	144:ef7eb2e8f9f7	1848	* the UART Word Length, Parity, Mode and oversampling:
<>	144:ef7eb2e8f9f7	1849	* set the M bits according to huart->Init.WordLength value
<>	144:ef7eb2e8f9f7	1850	* set PCE and PS bits according to huart->Init.Parity value
<>	144:ef7eb2e8f9f7	1851	* set TE and RE bits according to huart->Init.Mode value
<>	144:ef7eb2e8f9f7	1852	* set OVER8 bit according to huart->Init.OverSampling value */
<>	144:ef7eb2e8f9f7	1853	tmpreg = (uint32_t)huart->Init.WordLength \| huart->Init.Parity \| huart->Init.Mode \| huart->Init.OverSampling ;
<>	144:ef7eb2e8f9f7	1854	MODIFY_REG(huart->Instance->CR1, UART_CR1_FIELDS, tmpreg);
<>	144:ef7eb2e8f9f7	1855
<>	144:ef7eb2e8f9f7	1856	/-------------------------- USART CR2 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1857	/* Configure the UART Stop Bits: Set STOP[13:12] bits according
<>	144:ef7eb2e8f9f7	1858	* to huart->Init.StopBits value */
<>	144:ef7eb2e8f9f7	1859	MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
<>	144:ef7eb2e8f9f7	1860
<>	144:ef7eb2e8f9f7	1861	/-------------------------- USART CR3 Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1862	/* Configure
<>	144:ef7eb2e8f9f7	1863	* - UART HardWare Flow Control: set CTSE and RTSE bits according
<>	144:ef7eb2e8f9f7	1864	* to huart->Init.HwFlowCtl value
<>	144:ef7eb2e8f9f7	1865	* - one-bit sampling method versus three samples' majority rule according
<>	144:ef7eb2e8f9f7	1866	* to huart->Init.OneBitSampling */
<>	144:ef7eb2e8f9f7	1867	tmpreg = (uint32_t)huart->Init.HwFlowCtl \| huart->Init.OneBitSampling ;
<>	144:ef7eb2e8f9f7	1868	MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE \| USART_CR3_CTSE \| USART_CR3_ONEBIT), tmpreg);
<>	144:ef7eb2e8f9f7	1869
<>	144:ef7eb2e8f9f7	1870	/-------------------------- USART BRR Configuration -----------------------/
<>	144:ef7eb2e8f9f7	1871	UART_GETCLOCKSOURCE(huart, clocksource);
<>	144:ef7eb2e8f9f7	1872
<>	144:ef7eb2e8f9f7	1873	/* Check UART Over Sampling to set Baud Rate Register */
<>	144:ef7eb2e8f9f7	1874	if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
<>	144:ef7eb2e8f9f7	1875	{
<>	144:ef7eb2e8f9f7	1876	switch (clocksource)
<>	144:ef7eb2e8f9f7	1877	{
<>	144:ef7eb2e8f9f7	1878	case UART_CLOCKSOURCE_PCLK1:
<>	144:ef7eb2e8f9f7	1879	usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1880	break;
<>	144:ef7eb2e8f9f7	1881	case UART_CLOCKSOURCE_PCLK2:
<>	144:ef7eb2e8f9f7	1882	usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1883	break;
<>	144:ef7eb2e8f9f7	1884	case UART_CLOCKSOURCE_HSI:
<>	144:ef7eb2e8f9f7	1885	usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1886	break;
<>	144:ef7eb2e8f9f7	1887	case UART_CLOCKSOURCE_SYSCLK:
<>	144:ef7eb2e8f9f7	1888	usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1889	break;
<>	144:ef7eb2e8f9f7	1890	case UART_CLOCKSOURCE_LSE:
<>	144:ef7eb2e8f9f7	1891	usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1892	break;
<>	144:ef7eb2e8f9f7	1893	case UART_CLOCKSOURCE_UNDEFINED:
<>	144:ef7eb2e8f9f7	1894	default:
<>	144:ef7eb2e8f9f7	1895	ret = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1896	break;
<>	144:ef7eb2e8f9f7	1897	}
<>	144:ef7eb2e8f9f7	1898
<>	144:ef7eb2e8f9f7	1899	brrtemp = usartdiv & 0xFFF0U;
<>	144:ef7eb2e8f9f7	1900	brrtemp \|= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
<>	144:ef7eb2e8f9f7	1901	huart->Instance->BRR = brrtemp;
<>	144:ef7eb2e8f9f7	1902	}
<>	144:ef7eb2e8f9f7	1903	else
<>	144:ef7eb2e8f9f7	1904	{
<>	144:ef7eb2e8f9f7	1905	switch (clocksource)
<>	144:ef7eb2e8f9f7	1906	{
<>	144:ef7eb2e8f9f7	1907	case UART_CLOCKSOURCE_PCLK1:
<>	144:ef7eb2e8f9f7	1908	huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1909	break;
<>	144:ef7eb2e8f9f7	1910	case UART_CLOCKSOURCE_PCLK2:
<>	144:ef7eb2e8f9f7	1911	huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1912	break;
<>	144:ef7eb2e8f9f7	1913	case UART_CLOCKSOURCE_HSI:
<>	144:ef7eb2e8f9f7	1914	huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1915	break;
<>	144:ef7eb2e8f9f7	1916	case UART_CLOCKSOURCE_SYSCLK:
<>	144:ef7eb2e8f9f7	1917	huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1918	break;
<>	144:ef7eb2e8f9f7	1919	case UART_CLOCKSOURCE_LSE:
<>	144:ef7eb2e8f9f7	1920	huart->Instance->BRR = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate));
<>	144:ef7eb2e8f9f7	1921	break;
<>	144:ef7eb2e8f9f7	1922	case UART_CLOCKSOURCE_UNDEFINED:
<>	144:ef7eb2e8f9f7	1923	default:
<>	144:ef7eb2e8f9f7	1924	ret = HAL_ERROR;
<>	144:ef7eb2e8f9f7	1925	break;
<>	144:ef7eb2e8f9f7	1926	}
<>	144:ef7eb2e8f9f7	1927	}
<>	144:ef7eb2e8f9f7	1928
<>	144:ef7eb2e8f9f7	1929	return ret;
<>	144:ef7eb2e8f9f7	1930
<>	144:ef7eb2e8f9f7	1931	}
<>	144:ef7eb2e8f9f7	1932
<>	144:ef7eb2e8f9f7	1933
<>	144:ef7eb2e8f9f7	1934	/**
<>	144:ef7eb2e8f9f7	1935	* @brief Configure the UART peripheral advanced features
<>	144:ef7eb2e8f9f7	1936	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	1937	* @retval None
<>	144:ef7eb2e8f9f7	1938	*/
<>	144:ef7eb2e8f9f7	1939	void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	1940	{
<>	144:ef7eb2e8f9f7	1941	/* Check whether the set of advanced features to configure is properly set */
<>	144:ef7eb2e8f9f7	1942	assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
<>	144:ef7eb2e8f9f7	1943
<>	144:ef7eb2e8f9f7	1944	/* if required, configure TX pin active level inversion */
<>	144:ef7eb2e8f9f7	1945	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
<>	144:ef7eb2e8f9f7	1946	{
<>	144:ef7eb2e8f9f7	1947	assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
<>	144:ef7eb2e8f9f7	1948	MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
<>	144:ef7eb2e8f9f7	1949	}
<>	144:ef7eb2e8f9f7	1950
<>	144:ef7eb2e8f9f7	1951	/* if required, configure RX pin active level inversion */
<>	144:ef7eb2e8f9f7	1952	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
<>	144:ef7eb2e8f9f7	1953	{
<>	144:ef7eb2e8f9f7	1954	assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
<>	144:ef7eb2e8f9f7	1955	MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
<>	144:ef7eb2e8f9f7	1956	}
<>	144:ef7eb2e8f9f7	1957
<>	144:ef7eb2e8f9f7	1958	/* if required, configure data inversion */
<>	144:ef7eb2e8f9f7	1959	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
<>	144:ef7eb2e8f9f7	1960	{
<>	144:ef7eb2e8f9f7	1961	assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
<>	144:ef7eb2e8f9f7	1962	MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
<>	144:ef7eb2e8f9f7	1963	}
<>	144:ef7eb2e8f9f7	1964
<>	144:ef7eb2e8f9f7	1965	/* if required, configure RX/TX pins swap */
<>	144:ef7eb2e8f9f7	1966	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
<>	144:ef7eb2e8f9f7	1967	{
<>	144:ef7eb2e8f9f7	1968	assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
<>	144:ef7eb2e8f9f7	1969	MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
<>	144:ef7eb2e8f9f7	1970	}
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* if required, configure RX overrun detection disabling */
<>	144:ef7eb2e8f9f7	1973	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
<>	144:ef7eb2e8f9f7	1974	{
<>	144:ef7eb2e8f9f7	1975	assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
<>	144:ef7eb2e8f9f7	1976	MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
<>	144:ef7eb2e8f9f7	1977	}
<>	144:ef7eb2e8f9f7	1978
<>	144:ef7eb2e8f9f7	1979	/* if required, configure DMA disabling on reception error */
<>	144:ef7eb2e8f9f7	1980	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
<>	144:ef7eb2e8f9f7	1981	{
<>	144:ef7eb2e8f9f7	1982	assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
<>	144:ef7eb2e8f9f7	1983	MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
<>	144:ef7eb2e8f9f7	1984	}
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	/* if required, configure auto Baud rate detection scheme */
<>	144:ef7eb2e8f9f7	1987	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
<>	144:ef7eb2e8f9f7	1988	{
<>	144:ef7eb2e8f9f7	1989	assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
<>	144:ef7eb2e8f9f7	1990	MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
<>	144:ef7eb2e8f9f7	1991	/* set auto Baudrate detection parameters if detection is enabled */
<>	144:ef7eb2e8f9f7	1992	if(huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
<>	144:ef7eb2e8f9f7	1993	{
<>	144:ef7eb2e8f9f7	1994	assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
<>	144:ef7eb2e8f9f7	1995	MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
<>	144:ef7eb2e8f9f7	1996	}
<>	144:ef7eb2e8f9f7	1997	}
<>	144:ef7eb2e8f9f7	1998
<>	144:ef7eb2e8f9f7	1999	/* if required, configure MSB first on communication line */
<>	144:ef7eb2e8f9f7	2000	if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
<>	144:ef7eb2e8f9f7	2001	{
<>	144:ef7eb2e8f9f7	2002	assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
<>	144:ef7eb2e8f9f7	2003	MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
<>	144:ef7eb2e8f9f7	2004	}
<>	144:ef7eb2e8f9f7	2005	}
<>	144:ef7eb2e8f9f7	2006
<>	144:ef7eb2e8f9f7	2007
<>	144:ef7eb2e8f9f7	2008
<>	144:ef7eb2e8f9f7	2009	/**
<>	144:ef7eb2e8f9f7	2010	* @brief Check the UART Idle State
<>	144:ef7eb2e8f9f7	2011	* @param huart: uart handle
<>	144:ef7eb2e8f9f7	2012	* @retval HAL status
<>	144:ef7eb2e8f9f7	2013	*/
<>	144:ef7eb2e8f9f7	2014	HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2015	{
<>	144:ef7eb2e8f9f7	2016	uint32_t tickstart = 0U;
<>	144:ef7eb2e8f9f7	2017
<>	144:ef7eb2e8f9f7	2018	/* Initialize the UART ErrorCode */
<>	144:ef7eb2e8f9f7	2019	huart->ErrorCode = HAL_UART_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	/* Init tickstart for timeout managment*/
<>	144:ef7eb2e8f9f7	2022	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	/* Check if the Transmitter is enabled */
<>	144:ef7eb2e8f9f7	2025	if((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
<>	144:ef7eb2e8f9f7	2026	{
<>	144:ef7eb2e8f9f7	2027	/* Wait until TEACK flag is set */
<>	144:ef7eb2e8f9f7	2028	if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2029	{
<>	144:ef7eb2e8f9f7	2030	/* Timeout Occurred */
<>	144:ef7eb2e8f9f7	2031	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2032	}
<>	144:ef7eb2e8f9f7	2033	}
<>	144:ef7eb2e8f9f7	2034	/* Check if the Receiver is enabled */
<>	144:ef7eb2e8f9f7	2035	if((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
<>	144:ef7eb2e8f9f7	2036	{
<>	144:ef7eb2e8f9f7	2037	/* Wait until REACK flag is set */
<>	144:ef7eb2e8f9f7	2038	if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
<>	144:ef7eb2e8f9f7	2039	{
<>	144:ef7eb2e8f9f7	2040	/* Timeout Occurred */
<>	144:ef7eb2e8f9f7	2041	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2042	}
<>	144:ef7eb2e8f9f7	2043	}
<>	144:ef7eb2e8f9f7	2044
<>	144:ef7eb2e8f9f7	2045	/* Initialize the UART State */
<>	144:ef7eb2e8f9f7	2046	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2047	huart->RxState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2048
<>	144:ef7eb2e8f9f7	2049	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2050	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	2051
<>	144:ef7eb2e8f9f7	2052	return HAL_OK;
<>	144:ef7eb2e8f9f7	2053	}
<>	144:ef7eb2e8f9f7	2054
<>	144:ef7eb2e8f9f7	2055	/**
<>	144:ef7eb2e8f9f7	2056	* @brief Enables the UART transmitter and disables the UART receiver.
<>	144:ef7eb2e8f9f7	2057	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	2058	* @retval HAL status
<>	144:ef7eb2e8f9f7	2059	* @retval None
<>	144:ef7eb2e8f9f7	2060	*/
<>	144:ef7eb2e8f9f7	2061	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2062	{
<>	144:ef7eb2e8f9f7	2063	/* Process Locked */
<>	144:ef7eb2e8f9f7	2064	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	2065	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2066
<>	144:ef7eb2e8f9f7	2067	/* Clear TE and RE bits */
<>	144:ef7eb2e8f9f7	2068	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE \| USART_CR1_RE));
<>	144:ef7eb2e8f9f7	2069	/* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
<>	144:ef7eb2e8f9f7	2070	SET_BIT(huart->Instance->CR1, USART_CR1_TE);
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	huart->gState= HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2073	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2074	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	2075
<>	144:ef7eb2e8f9f7	2076	return HAL_OK;
<>	144:ef7eb2e8f9f7	2077	}
<>	144:ef7eb2e8f9f7	2078
<>	144:ef7eb2e8f9f7	2079	/**
<>	144:ef7eb2e8f9f7	2080	* @brief Enables the UART receiver and disables the UART transmitter.
<>	144:ef7eb2e8f9f7	2081	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	2082	* @retval HAL status
<>	144:ef7eb2e8f9f7	2083	*/
<>	144:ef7eb2e8f9f7	2084	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2085	{
<>	144:ef7eb2e8f9f7	2086	/* Process Locked */
<>	144:ef7eb2e8f9f7	2087	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	2088	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2089
<>	144:ef7eb2e8f9f7	2090	/* Clear TE and RE bits */
<>	144:ef7eb2e8f9f7	2091	CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE \| USART_CR1_RE));
<>	144:ef7eb2e8f9f7	2092	/* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
<>	144:ef7eb2e8f9f7	2093	SET_BIT(huart->Instance->CR1, USART_CR1_RE);
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2096	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2097	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	2098
<>	144:ef7eb2e8f9f7	2099	return HAL_OK;
<>	144:ef7eb2e8f9f7	2100	}
<>	144:ef7eb2e8f9f7	2101
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	/**
<>	144:ef7eb2e8f9f7	2104	* @brief Transmits break characters.
<>	144:ef7eb2e8f9f7	2105	* @param huart: UART handle
<>	144:ef7eb2e8f9f7	2106	* @retval HAL status
<>	144:ef7eb2e8f9f7	2107	*/
<>	144:ef7eb2e8f9f7	2108	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
<>	144:ef7eb2e8f9f7	2109	{
<>	144:ef7eb2e8f9f7	2110	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2111	assert_param(IS_UART_INSTANCE(huart->Instance));
<>	144:ef7eb2e8f9f7	2112
<>	144:ef7eb2e8f9f7	2113	/* Process Locked */
<>	144:ef7eb2e8f9f7	2114	__HAL_LOCK(huart);
<>	144:ef7eb2e8f9f7	2115
<>	144:ef7eb2e8f9f7	2116	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2117
<>	144:ef7eb2e8f9f7	2118	/* Send break characters */
<>	144:ef7eb2e8f9f7	2119	SET_BIT(huart->Instance->RQR, UART_SENDBREAK_REQUEST);
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	huart->gState = HAL_UART_STATE_READY;
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2124	__HAL_UNLOCK(huart);
<>	144:ef7eb2e8f9f7	2125
<>	144:ef7eb2e8f9f7	2126	return HAL_OK;
<>	144:ef7eb2e8f9f7	2127	}
<>	144:ef7eb2e8f9f7	2128
<>	144:ef7eb2e8f9f7	2129	/**
<>	144:ef7eb2e8f9f7	2130	* @brief By default in multiprocessor mode, when the wake up method is set
<>	144:ef7eb2e8f9f7	2131	* to address mark, the UART handles only 4-bit long addresses detection;
<>	144:ef7eb2e8f9f7	2132	* this API allows to enable longer addresses detection (6-, 7- or 8-bit
<>	144:ef7eb2e8f9f7	2133	* long).
<>	144:ef7eb2e8f9f7	2134	* @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
<>	144:ef7eb2e8f9f7	2135	* 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
<>	144:ef7eb2e8f9f7	2136	* @param huart: UART handle.
<>	144:ef7eb2e8f9f7	2137	* @param AddressLength: this parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2138	* @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
<>	144:ef7eb2e8f9f7	2139	* @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
<>	144:ef7eb2e8f9f7	2140	* @retval HAL status
<>	144:ef7eb2e8f9f7	2141	*/
<>	144:ef7eb2e8f9f7	2142	HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
<>	144:ef7eb2e8f9f7	2143	{
<>	144:ef7eb2e8f9f7	2144	/* Check the UART handle allocation */
<>	144:ef7eb2e8f9f7	2145	if(huart == NULL)
<>	144:ef7eb2e8f9f7	2146	{
<>	144:ef7eb2e8f9f7	2147	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2148	}
<>	144:ef7eb2e8f9f7	2149
<>	144:ef7eb2e8f9f7	2150	/* Check the address length parameter */
<>	144:ef7eb2e8f9f7	2151	assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
<>	144:ef7eb2e8f9f7	2152
<>	144:ef7eb2e8f9f7	2153	huart->gState = HAL_UART_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2154
<>	144:ef7eb2e8f9f7	2155	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	2156	__HAL_UART_DISABLE(huart);
<>	144:ef7eb2e8f9f7	2157
<>	144:ef7eb2e8f9f7	2158	/* Set the address length */
<>	144:ef7eb2e8f9f7	2159	MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
<>	144:ef7eb2e8f9f7	2160
<>	144:ef7eb2e8f9f7	2161	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	2162	__HAL_UART_ENABLE(huart);
<>	144:ef7eb2e8f9f7	2163
<>	144:ef7eb2e8f9f7	2164	/* TEACK and/or REACK to check before moving huart->gState to Ready */
<>	144:ef7eb2e8f9f7	2165	return (UART_CheckIdleState(huart));
<>	144:ef7eb2e8f9f7	2166	}
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	/**
<>	144:ef7eb2e8f9f7	2169	* @}
<>	144:ef7eb2e8f9f7	2170	*/
<>	144:ef7eb2e8f9f7	2171
<>	144:ef7eb2e8f9f7	2172	/**
<>	144:ef7eb2e8f9f7	2173	* @}
<>	144:ef7eb2e8f9f7	2174	*/
<>	144:ef7eb2e8f9f7	2175
<>	144:ef7eb2e8f9f7	2176	#endif /* HAL_UART_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2177	/**
<>	144:ef7eb2e8f9f7	2178	* @}
<>	144:ef7eb2e8f9f7	2179	*/
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/**
<>	144:ef7eb2e8f9f7	2182	* @}
<>	144:ef7eb2e8f9f7	2183	*/
<>	144:ef7eb2e8f9f7	2184
<>	144:ef7eb2e8f9f7	2185	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_uart.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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