Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_tim.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_tim.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer (TIM) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Base Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Base Start
<> 144:ef7eb2e8f9f7 12 * + Time Base Start Interruption
<> 144:ef7eb2e8f9f7 13 * + Time Base Start DMA
<> 144:ef7eb2e8f9f7 14 * + Time Output Compare/PWM Initialization
<> 144:ef7eb2e8f9f7 15 * + Time Output Compare/PWM Channel Configuration
<> 144:ef7eb2e8f9f7 16 * + Time Output Compare/PWM Start
<> 144:ef7eb2e8f9f7 17 * + Time Output Compare/PWM Start Interruption
<> 144:ef7eb2e8f9f7 18 * + Time Output Compare/PWM Start DMA
<> 144:ef7eb2e8f9f7 19 * + Time Input Capture Initialization
<> 144:ef7eb2e8f9f7 20 * + Time Input Capture Channel Configuration
<> 144:ef7eb2e8f9f7 21 * + Time Input Capture Start
<> 144:ef7eb2e8f9f7 22 * + Time Input Capture Start Interruption
<> 144:ef7eb2e8f9f7 23 * + Time Input Capture Start DMA
<> 144:ef7eb2e8f9f7 24 * + Time One Pulse Initialization
<> 144:ef7eb2e8f9f7 25 * + Time One Pulse Channel Configuration
<> 144:ef7eb2e8f9f7 26 * + Time One Pulse Start
<> 144:ef7eb2e8f9f7 27 * + Time Encoder Interface Initialization
<> 144:ef7eb2e8f9f7 28 * + Time Encoder Interface Start
<> 144:ef7eb2e8f9f7 29 * + Time Encoder Interface Start Interruption
<> 144:ef7eb2e8f9f7 30 * + Time Encoder Interface Start DMA
<> 144:ef7eb2e8f9f7 31 * + Commutation Event configuration with Interruption and DMA
<> 144:ef7eb2e8f9f7 32 * + Time OCRef clear configuration
<> 144:ef7eb2e8f9f7 33 * + Time External Clock configuration
<> 144:ef7eb2e8f9f7 34 @verbatim
<> 144:ef7eb2e8f9f7 35 ==============================================================================
<> 144:ef7eb2e8f9f7 36 ##### TIMER Generic features #####
<> 144:ef7eb2e8f9f7 37 ==============================================================================
<> 144:ef7eb2e8f9f7 38 [..] The Timer features include:
<> 144:ef7eb2e8f9f7 39 (#) 16-bit up, down, up/down auto-reload counter.
<> 144:ef7eb2e8f9f7 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
<> 144:ef7eb2e8f9f7 41 counter clock frequency either by any factor between 1 and 65536.
<> 144:ef7eb2e8f9f7 42 (#) Up to 4 independent channels for:
<> 144:ef7eb2e8f9f7 43 (++) Input Capture
<> 144:ef7eb2e8f9f7 44 (++) Output Compare
<> 144:ef7eb2e8f9f7 45 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 46 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 49 ==============================================================================
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 52 depending from feature used :
<> 144:ef7eb2e8f9f7 53 (++) Time Base : HAL_TIM_Base_MspInit()
<> 144:ef7eb2e8f9f7 54 (++) Input Capture : HAL_TIM_IC_MspInit()
<> 144:ef7eb2e8f9f7 55 (++) Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 62 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 63 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 64 __GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 68 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 70 any start function.
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 73 initialization function of this driver:
<> 144:ef7eb2e8f9f7 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
<> 144:ef7eb2e8f9f7 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
<> 144:ef7eb2e8f9f7 76 Output Compare signal.
<> 144:ef7eb2e8f9f7 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
<> 144:ef7eb2e8f9f7 78 PWM signal.
<> 144:ef7eb2e8f9f7 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
<> 144:ef7eb2e8f9f7 80 external signal.
<> 144:ef7eb2e8f9f7 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
<> 144:ef7eb2e8f9f7 82 in One Pulse Mode.
<> 144:ef7eb2e8f9f7 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
<> 144:ef7eb2e8f9f7 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
<> 144:ef7eb2e8f9f7 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
<> 144:ef7eb2e8f9f7 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
<> 144:ef7eb2e8f9f7 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
<> 144:ef7eb2e8f9f7 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
<> 144:ef7eb2e8f9f7 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 (#) The DMA Burst is managed with the two following functions:
<> 144:ef7eb2e8f9f7 94 HAL_TIM_DMABurst_WriteStart()
<> 144:ef7eb2e8f9f7 95 HAL_TIM_DMABurst_ReadStart()
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 @endverbatim
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 * @attention
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 104 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 105 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 106 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 108 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 109 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 111 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 112 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 113 *
<> 144:ef7eb2e8f9f7 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 ******************************************************************************
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 129 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** @defgroup TIM TIM
<> 144:ef7eb2e8f9f7 136 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 137 * @{
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146 /** @addtogroup TIM_Private_Functions
<> 144:ef7eb2e8f9f7 147 * @{
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 150 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 151 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 152 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 153 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 154 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 155 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 156 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 157 uint32_t TIM_ICFilter);
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
<> 144:ef7eb2e8f9f7 160 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 161 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 162 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 163 TIM_SlaveConfigTypeDef * sSlaveConfig);
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @}
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
<> 144:ef7eb2e8f9f7 174 * @brief Time Base functions
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 @verbatim
<> 144:ef7eb2e8f9f7 177 ==============================================================================
<> 144:ef7eb2e8f9f7 178 ##### Time Base functions #####
<> 144:ef7eb2e8f9f7 179 ==============================================================================
<> 144:ef7eb2e8f9f7 180 [..]
<> 144:ef7eb2e8f9f7 181 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 182 (+) Initialize and configure the TIM base.
<> 144:ef7eb2e8f9f7 183 (+) De-initialize the TIM base.
<> 144:ef7eb2e8f9f7 184 (+) Start the Time Base.
<> 144:ef7eb2e8f9f7 185 (+) Stop the Time Base.
<> 144:ef7eb2e8f9f7 186 (+) Start the Time Base and enable interrupt.
<> 144:ef7eb2e8f9f7 187 (+) Stop the Time Base and disable interrupt.
<> 144:ef7eb2e8f9f7 188 (+) Start the Time Base and enable DMA transfer.
<> 144:ef7eb2e8f9f7 189 (+) Stop the Time Base and disable DMA transfer.
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 @endverbatim
<> 144:ef7eb2e8f9f7 192 * @{
<> 144:ef7eb2e8f9f7 193 */
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @brief Initializes the TIM Time base Unit according to the specified
<> 144:ef7eb2e8f9f7 196 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 197 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 198 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 199 * @retval HAL status
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 204 if(htim == NULL)
<> 144:ef7eb2e8f9f7 205 {
<> 144:ef7eb2e8f9f7 206 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* Check the parameters */
<> 144:ef7eb2e8f9f7 210 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 211 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 212 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 215 {
<> 144:ef7eb2e8f9f7 216 /* Init the low level hardware : GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 217 HAL_TIM_Base_MspInit(htim);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 221 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Set the Time Base configuration */
<> 144:ef7eb2e8f9f7 224 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 227 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 return HAL_OK;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /**
<> 144:ef7eb2e8f9f7 233 * @brief DeInitializes the TIM Base peripheral
<> 144:ef7eb2e8f9f7 234 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 235 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 236 * @retval HAL status
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 /* Check the parameters */
<> 144:ef7eb2e8f9f7 241 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 246 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 249 HAL_TIM_Base_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Change TIM state */
<> 144:ef7eb2e8f9f7 252 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Release Lock */
<> 144:ef7eb2e8f9f7 255 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 return HAL_OK;
<> 144:ef7eb2e8f9f7 258 }
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @brief Initializes the TIM Base MSP.
<> 144:ef7eb2e8f9f7 262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 263 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 264 * @retval None
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 269 UNUSED(htim);
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 272 the HAL_TIM_Base_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief DeInitializes TIM Base MSP.
<> 144:ef7eb2e8f9f7 278 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 279 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 280 * @retval None
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 285 UNUSED(htim);
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @brief Starts the TIM Base generation.
<> 144:ef7eb2e8f9f7 294 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 295 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 296 * @retval HAL status
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 /* Check the parameters */
<> 144:ef7eb2e8f9f7 301 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 304 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 307 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 310 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Return function status */
<> 144:ef7eb2e8f9f7 313 return HAL_OK;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Stops the TIM Base generation.
<> 144:ef7eb2e8f9f7 318 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 319 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 320 * @retval HAL status
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 323 {
<> 144:ef7eb2e8f9f7 324 /* Check the parameters */
<> 144:ef7eb2e8f9f7 325 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 328 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 331 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Change the TIM state*/
<> 144:ef7eb2e8f9f7 334 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Return function status */
<> 144:ef7eb2e8f9f7 337 return HAL_OK;
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /**
<> 144:ef7eb2e8f9f7 341 * @brief Starts the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 342 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 343 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 344 * @retval HAL status
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* Check the parameters */
<> 144:ef7eb2e8f9f7 349 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /* Enable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 352 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 355 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Return function status */
<> 144:ef7eb2e8f9f7 358 return HAL_OK;
<> 144:ef7eb2e8f9f7 359 }
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @brief Stops the TIM Base generation in interrupt mode.
<> 144:ef7eb2e8f9f7 363 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 364 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 365 * @retval HAL status
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 368 {
<> 144:ef7eb2e8f9f7 369 /* Check the parameters */
<> 144:ef7eb2e8f9f7 370 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 371 /* Disable the TIM Update interrupt */
<> 144:ef7eb2e8f9f7 372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 375 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Return function status */
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief Starts the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 383 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 384 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 385 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 386 * @param Length: The length of data to be transferred from memory to peripheral.
<> 144:ef7eb2e8f9f7 387 * @retval HAL status
<> 144:ef7eb2e8f9f7 388 */
<> 144:ef7eb2e8f9f7 389 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 390 {
<> 144:ef7eb2e8f9f7 391 /* Check the parameters */
<> 144:ef7eb2e8f9f7 392 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 395 {
<> 144:ef7eb2e8f9f7 396 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 399 {
<> 144:ef7eb2e8f9f7 400 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 401 {
<> 144:ef7eb2e8f9f7 402 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 else
<> 144:ef7eb2e8f9f7 405 {
<> 144:ef7eb2e8f9f7 406 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 410 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 413 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 416 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Enable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 419 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 422 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Return function status */
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Stops the TIM Base generation in DMA mode.
<> 144:ef7eb2e8f9f7 430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 431 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 432 * @retval HAL status
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Check the parameters */
<> 144:ef7eb2e8f9f7 437 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 440 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
<> 144:ef7eb2e8f9f7 441
<> 144:ef7eb2e8f9f7 442 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 443 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Change the htim state */
<> 144:ef7eb2e8f9f7 446 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Return function status */
<> 144:ef7eb2e8f9f7 449 return HAL_OK;
<> 144:ef7eb2e8f9f7 450 }
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /**
<> 144:ef7eb2e8f9f7 453 * @}
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
<> 144:ef7eb2e8f9f7 457 * @brief Time Output Compare functions
<> 144:ef7eb2e8f9f7 458 *
<> 144:ef7eb2e8f9f7 459 @verbatim
<> 144:ef7eb2e8f9f7 460 ==============================================================================
<> 144:ef7eb2e8f9f7 461 ##### Time Output Compare functions #####
<> 144:ef7eb2e8f9f7 462 ==============================================================================
<> 144:ef7eb2e8f9f7 463 [..]
<> 144:ef7eb2e8f9f7 464 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 465 (+) Initialize and configure the TIM Output Compare.
<> 144:ef7eb2e8f9f7 466 (+) De-initialize the TIM Output Compare.
<> 144:ef7eb2e8f9f7 467 (+) Start the Time Output Compare.
<> 144:ef7eb2e8f9f7 468 (+) Stop the Time Output Compare.
<> 144:ef7eb2e8f9f7 469 (+) Start the Time Output Compare and enable interrupt.
<> 144:ef7eb2e8f9f7 470 (+) Stop the Time Output Compare and disable interrupt.
<> 144:ef7eb2e8f9f7 471 (+) Start the Time Output Compare and enable DMA transfer.
<> 144:ef7eb2e8f9f7 472 (+) Stop the Time Output Compare and disable DMA transfer.
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 @endverbatim
<> 144:ef7eb2e8f9f7 475 * @{
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Initializes the TIM Output Compare according to the specified
<> 144:ef7eb2e8f9f7 479 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 480 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 481 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 482 * @retval HAL status
<> 144:ef7eb2e8f9f7 483 */
<> 144:ef7eb2e8f9f7 484 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 487 if(htim == NULL)
<> 144:ef7eb2e8f9f7 488 {
<> 144:ef7eb2e8f9f7 489 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 493 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 494 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 495 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 500 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 501 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 502 HAL_TIM_OC_MspInit(htim);
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 506 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Init the base time for the Output Compare */
<> 144:ef7eb2e8f9f7 509 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 512 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 return HAL_OK;
<> 144:ef7eb2e8f9f7 515 }
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /**
<> 144:ef7eb2e8f9f7 518 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 519 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 520 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 521 * @retval HAL status
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 /* Check the parameters */
<> 144:ef7eb2e8f9f7 526 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 531 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 534 HAL_TIM_OC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Change TIM state */
<> 144:ef7eb2e8f9f7 537 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /* Release Lock */
<> 144:ef7eb2e8f9f7 540 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 return HAL_OK;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /**
<> 144:ef7eb2e8f9f7 546 * @brief Initializes the TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 547 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 548 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 549 * @retval None
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 554 UNUSED(htim);
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 557 the HAL_TIM_OC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 }
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief DeInitializes TIM Output Compare MSP.
<> 144:ef7eb2e8f9f7 563 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 564 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 565 * @retval None
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 568 {
<> 144:ef7eb2e8f9f7 569 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 570 UNUSED(htim);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 573 the HAL_TIM_OC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 574 */
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /**
<> 144:ef7eb2e8f9f7 578 * @brief Starts the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 579 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 580 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 581 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 582 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 583 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 584 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 585 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 586 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 587 * @retval HAL status
<> 144:ef7eb2e8f9f7 588 */
<> 144:ef7eb2e8f9f7 589 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 /* Check the parameters */
<> 144:ef7eb2e8f9f7 592 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 595 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 /* Enable the main output */
<> 144:ef7eb2e8f9f7 600 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 604 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Return function status */
<> 144:ef7eb2e8f9f7 607 return HAL_OK;
<> 144:ef7eb2e8f9f7 608 }
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /**
<> 144:ef7eb2e8f9f7 611 * @brief Stops the TIM Output Compare signal generation.
<> 144:ef7eb2e8f9f7 612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 613 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 614 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 615 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 620 * @retval HAL status
<> 144:ef7eb2e8f9f7 621 */
<> 144:ef7eb2e8f9f7 622 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 /* Check the parameters */
<> 144:ef7eb2e8f9f7 625 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 633 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 637 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /* Return function status */
<> 144:ef7eb2e8f9f7 640 return HAL_OK;
<> 144:ef7eb2e8f9f7 641 }
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 645 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 646 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 647 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 648 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 649 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 650 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 651 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 652 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 653 * @retval HAL status
<> 144:ef7eb2e8f9f7 654 */
<> 144:ef7eb2e8f9f7 655 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 656 {
<> 144:ef7eb2e8f9f7 657 /* Check the parameters */
<> 144:ef7eb2e8f9f7 658 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 switch (Channel)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 665 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667 break;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 672 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674 break;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 677 {
<> 144:ef7eb2e8f9f7 678 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 679 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 break;
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 684 {
<> 144:ef7eb2e8f9f7 685 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 break;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 default:
<> 144:ef7eb2e8f9f7 691 break;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 695 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 698 {
<> 144:ef7eb2e8f9f7 699 /* Enable the main output */
<> 144:ef7eb2e8f9f7 700 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 704 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Return function status */
<> 144:ef7eb2e8f9f7 707 return HAL_OK;
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 712 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 713 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 714 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 715 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 716 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 717 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 718 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 719 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 720 * @retval HAL status
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 723 {
<> 144:ef7eb2e8f9f7 724 /* Check the parameters */
<> 144:ef7eb2e8f9f7 725 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 switch (Channel)
<> 144:ef7eb2e8f9f7 728 {
<> 144:ef7eb2e8f9f7 729 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 733 }
<> 144:ef7eb2e8f9f7 734 break;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 737 {
<> 144:ef7eb2e8f9f7 738 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 break;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 747 }
<> 144:ef7eb2e8f9f7 748 break;
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 751 {
<> 144:ef7eb2e8f9f7 752 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 753 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 break;
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 default:
<> 144:ef7eb2e8f9f7 758 break;
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 762 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 765 {
<> 144:ef7eb2e8f9f7 766 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 767 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 771 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /* Return function status */
<> 144:ef7eb2e8f9f7 774 return HAL_OK;
<> 144:ef7eb2e8f9f7 775 }
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /**
<> 144:ef7eb2e8f9f7 778 * @brief Starts the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 779 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 780 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 781 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 782 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 783 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 784 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 785 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 786 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 787 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 788 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 789 * @retval HAL status
<> 144:ef7eb2e8f9f7 790 */
<> 144:ef7eb2e8f9f7 791 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 /* Check the parameters */
<> 144:ef7eb2e8f9f7 794 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 else
<> 144:ef7eb2e8f9f7 807 {
<> 144:ef7eb2e8f9f7 808 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 809 }
<> 144:ef7eb2e8f9f7 810 }
<> 144:ef7eb2e8f9f7 811 switch (Channel)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 816 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 819 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 822 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 825 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 break;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 832 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 833
<> 144:ef7eb2e8f9f7 834 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 835 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 838 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 841 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843 break;
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 848 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 851 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 854 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 857 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 break;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 862 {
<> 144:ef7eb2e8f9f7 863 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 864 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 867 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 870 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 873 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875 break;
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 default:
<> 144:ef7eb2e8f9f7 878 break;
<> 144:ef7eb2e8f9f7 879 }
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /* Enable the Output compare channel */
<> 144:ef7eb2e8f9f7 882 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 /* Enable the main output */
<> 144:ef7eb2e8f9f7 887 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 891 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Return function status */
<> 144:ef7eb2e8f9f7 894 return HAL_OK;
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Stops the TIM Output Compare signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 899 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 900 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 901 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 902 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 907 * @retval HAL status
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 910 {
<> 144:ef7eb2e8f9f7 911 /* Check the parameters */
<> 144:ef7eb2e8f9f7 912 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 switch (Channel)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921 break;
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928 break;
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 931 {
<> 144:ef7eb2e8f9f7 932 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 933 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 934 }
<> 144:ef7eb2e8f9f7 935 break;
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 940 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942 break;
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 default:
<> 144:ef7eb2e8f9f7 945 break;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Disable the Output compare channel */
<> 144:ef7eb2e8f9f7 949 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 952 {
<> 144:ef7eb2e8f9f7 953 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 954 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 958 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Change the htim state */
<> 144:ef7eb2e8f9f7 961 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /* Return function status */
<> 144:ef7eb2e8f9f7 964 return HAL_OK;
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /**
<> 144:ef7eb2e8f9f7 968 * @}
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
<> 144:ef7eb2e8f9f7 972 * @brief Time PWM functions
<> 144:ef7eb2e8f9f7 973 *
<> 144:ef7eb2e8f9f7 974 @verbatim
<> 144:ef7eb2e8f9f7 975 ==============================================================================
<> 144:ef7eb2e8f9f7 976 ##### Time PWM functions #####
<> 144:ef7eb2e8f9f7 977 ==============================================================================
<> 144:ef7eb2e8f9f7 978 [..]
<> 144:ef7eb2e8f9f7 979 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 980 (+) Initialize and configure the TIM OPWM.
<> 144:ef7eb2e8f9f7 981 (+) De-initialize the TIM PWM.
<> 144:ef7eb2e8f9f7 982 (+) Start the Time PWM.
<> 144:ef7eb2e8f9f7 983 (+) Stop the Time PWM.
<> 144:ef7eb2e8f9f7 984 (+) Start the Time PWM and enable interrupt.
<> 144:ef7eb2e8f9f7 985 (+) Stop the Time PWM and disable interrupt.
<> 144:ef7eb2e8f9f7 986 (+) Start the Time PWM and enable DMA transfer.
<> 144:ef7eb2e8f9f7 987 (+) Stop the Time PWM and disable DMA transfer.
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 @endverbatim
<> 144:ef7eb2e8f9f7 990 * @{
<> 144:ef7eb2e8f9f7 991 */
<> 144:ef7eb2e8f9f7 992 /**
<> 144:ef7eb2e8f9f7 993 * @brief Initializes the TIM PWM Time Base according to the specified
<> 144:ef7eb2e8f9f7 994 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 995 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 996 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 997 * @retval HAL status
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1000 {
<> 144:ef7eb2e8f9f7 1001 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1002 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1008 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1009 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1010 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1015 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1016 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1017 HAL_TIM_PWM_MspInit(htim);
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1021 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 /* Init the base time for the PWM */
<> 144:ef7eb2e8f9f7 1024 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1027 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 return HAL_OK;
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031
<> 144:ef7eb2e8f9f7 1032 /**
<> 144:ef7eb2e8f9f7 1033 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1034 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1035 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1036 * @retval HAL status
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1041 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1046 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1049 HAL_TIM_PWM_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1052 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* Release Lock */
<> 144:ef7eb2e8f9f7 1055 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 return HAL_OK;
<> 144:ef7eb2e8f9f7 1058 }
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /**
<> 144:ef7eb2e8f9f7 1061 * @brief Initializes the TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1062 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1063 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1064 * @retval None
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1069 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1072 the HAL_TIM_PWM_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1073 */
<> 144:ef7eb2e8f9f7 1074 }
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @brief DeInitializes TIM PWM MSP.
<> 144:ef7eb2e8f9f7 1078 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1079 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1080 * @retval None
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1083 {
<> 144:ef7eb2e8f9f7 1084 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1085 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1086
<> 144:ef7eb2e8f9f7 1087 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1088 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1089 */
<> 144:ef7eb2e8f9f7 1090 }
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /**
<> 144:ef7eb2e8f9f7 1093 * @brief Starts the PWM signal generation.
<> 144:ef7eb2e8f9f7 1094 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1095 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1096 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1097 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1098 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1099 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1100 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1102 * @retval HAL status
<> 144:ef7eb2e8f9f7 1103 */
<> 144:ef7eb2e8f9f7 1104 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1105 {
<> 144:ef7eb2e8f9f7 1106 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1107 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1110 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1115 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117
<> 144:ef7eb2e8f9f7 1118 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1119 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /* Return function status */
<> 144:ef7eb2e8f9f7 1122 return HAL_OK;
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /**
<> 144:ef7eb2e8f9f7 1126 * @brief Stops the PWM signal generation.
<> 144:ef7eb2e8f9f7 1127 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1128 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1129 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1130 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1133 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1134 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1135 * @retval HAL status
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1138 {
<> 144:ef7eb2e8f9f7 1139 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1140 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1143 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1148 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1149 }
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1152 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1155 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Return function status */
<> 144:ef7eb2e8f9f7 1158 return HAL_OK;
<> 144:ef7eb2e8f9f7 1159 }
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /**
<> 144:ef7eb2e8f9f7 1162 * @brief Starts the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1163 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1164 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1165 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1166 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1167 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1168 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1169 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1170 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1171 * @retval HAL status
<> 144:ef7eb2e8f9f7 1172 */
<> 144:ef7eb2e8f9f7 1173 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1174 {
<> 144:ef7eb2e8f9f7 1175 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1176 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 switch (Channel)
<> 144:ef7eb2e8f9f7 1179 {
<> 144:ef7eb2e8f9f7 1180 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1181 {
<> 144:ef7eb2e8f9f7 1182 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1184 }
<> 144:ef7eb2e8f9f7 1185 break;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1191 }
<> 144:ef7eb2e8f9f7 1192 break;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1195 {
<> 144:ef7eb2e8f9f7 1196 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1198 }
<> 144:ef7eb2e8f9f7 1199 break;
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1202 {
<> 144:ef7eb2e8f9f7 1203 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1204 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1205 }
<> 144:ef7eb2e8f9f7 1206 break;
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 default:
<> 144:ef7eb2e8f9f7 1209 break;
<> 144:ef7eb2e8f9f7 1210 }
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1213 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1218 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1219 }
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1222 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Return function status */
<> 144:ef7eb2e8f9f7 1225 return HAL_OK;
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /**
<> 144:ef7eb2e8f9f7 1229 * @brief Stops the PWM signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 1230 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1231 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1232 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1233 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1234 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1235 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1236 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1237 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1238 * @retval HAL status
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1241 {
<> 144:ef7eb2e8f9f7 1242 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1243 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 switch (Channel)
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1248 {
<> 144:ef7eb2e8f9f7 1249 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1250 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1251 }
<> 144:ef7eb2e8f9f7 1252 break;
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1255 {
<> 144:ef7eb2e8f9f7 1256 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1257 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1258 }
<> 144:ef7eb2e8f9f7 1259 break;
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1262 {
<> 144:ef7eb2e8f9f7 1263 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1264 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1265 }
<> 144:ef7eb2e8f9f7 1266 break;
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1269 {
<> 144:ef7eb2e8f9f7 1270 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1271 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1272 }
<> 144:ef7eb2e8f9f7 1273 break;
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 default:
<> 144:ef7eb2e8f9f7 1276 break;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1280 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1283 {
<> 144:ef7eb2e8f9f7 1284 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1285 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1289 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1290
<> 144:ef7eb2e8f9f7 1291 /* Return function status */
<> 144:ef7eb2e8f9f7 1292 return HAL_OK;
<> 144:ef7eb2e8f9f7 1293 }
<> 144:ef7eb2e8f9f7 1294
<> 144:ef7eb2e8f9f7 1295 /**
<> 144:ef7eb2e8f9f7 1296 * @brief Starts the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1297 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1298 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1299 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1300 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1301 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1302 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1303 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1304 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1305 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1306 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1307 * @retval HAL status
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1310 {
<> 144:ef7eb2e8f9f7 1311 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1312 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1315 {
<> 144:ef7eb2e8f9f7 1316 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1317 }
<> 144:ef7eb2e8f9f7 1318 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1319 {
<> 144:ef7eb2e8f9f7 1320 if(((uint32_t)pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1321 {
<> 144:ef7eb2e8f9f7 1322 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1323 }
<> 144:ef7eb2e8f9f7 1324 else
<> 144:ef7eb2e8f9f7 1325 {
<> 144:ef7eb2e8f9f7 1326 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1327 }
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329 switch (Channel)
<> 144:ef7eb2e8f9f7 1330 {
<> 144:ef7eb2e8f9f7 1331 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1332 {
<> 144:ef7eb2e8f9f7 1333 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1334 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1335
<> 144:ef7eb2e8f9f7 1336 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1337 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1340 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1343 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1344 }
<> 144:ef7eb2e8f9f7 1345 break;
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1348 {
<> 144:ef7eb2e8f9f7 1349 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1350 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1353 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1356 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1359 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1360 }
<> 144:ef7eb2e8f9f7 1361 break;
<> 144:ef7eb2e8f9f7 1362
<> 144:ef7eb2e8f9f7 1363 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1364 {
<> 144:ef7eb2e8f9f7 1365 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1366 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1369 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1370
<> 144:ef7eb2e8f9f7 1371 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1372 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 /* Enable the TIM Output Capture/Compare 3 request */
<> 144:ef7eb2e8f9f7 1375 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1376 }
<> 144:ef7eb2e8f9f7 1377 break;
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1380 {
<> 144:ef7eb2e8f9f7 1381 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1382 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1385 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1388 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1391 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1392 }
<> 144:ef7eb2e8f9f7 1393 break;
<> 144:ef7eb2e8f9f7 1394
<> 144:ef7eb2e8f9f7 1395 default:
<> 144:ef7eb2e8f9f7 1396 break;
<> 144:ef7eb2e8f9f7 1397 }
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1400 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1403 {
<> 144:ef7eb2e8f9f7 1404 /* Enable the main output */
<> 144:ef7eb2e8f9f7 1405 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1406 }
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1409 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Return function status */
<> 144:ef7eb2e8f9f7 1412 return HAL_OK;
<> 144:ef7eb2e8f9f7 1413 }
<> 144:ef7eb2e8f9f7 1414
<> 144:ef7eb2e8f9f7 1415 /**
<> 144:ef7eb2e8f9f7 1416 * @brief Stops the TIM PWM signal generation in DMA mode.
<> 144:ef7eb2e8f9f7 1417 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1418 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1419 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1420 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1421 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1422 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1423 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1424 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1425 * @retval HAL status
<> 144:ef7eb2e8f9f7 1426 */
<> 144:ef7eb2e8f9f7 1427 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1430 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 switch (Channel)
<> 144:ef7eb2e8f9f7 1433 {
<> 144:ef7eb2e8f9f7 1434 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1435 {
<> 144:ef7eb2e8f9f7 1436 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1437 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 break;
<> 144:ef7eb2e8f9f7 1440
<> 144:ef7eb2e8f9f7 1441 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1442 {
<> 144:ef7eb2e8f9f7 1443 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1444 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1445 }
<> 144:ef7eb2e8f9f7 1446 break;
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1449 {
<> 144:ef7eb2e8f9f7 1450 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1451 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1452 }
<> 144:ef7eb2e8f9f7 1453 break;
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1456 {
<> 144:ef7eb2e8f9f7 1457 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1458 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1459 }
<> 144:ef7eb2e8f9f7 1460 break;
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 default:
<> 144:ef7eb2e8f9f7 1463 break;
<> 144:ef7eb2e8f9f7 1464 }
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /* Disable the Capture compare channel */
<> 144:ef7eb2e8f9f7 1467 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1468
<> 144:ef7eb2e8f9f7 1469 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 1470 {
<> 144:ef7eb2e8f9f7 1471 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1472 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1473 }
<> 144:ef7eb2e8f9f7 1474
<> 144:ef7eb2e8f9f7 1475 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1476 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1479 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /* Return function status */
<> 144:ef7eb2e8f9f7 1482 return HAL_OK;
<> 144:ef7eb2e8f9f7 1483 }
<> 144:ef7eb2e8f9f7 1484
<> 144:ef7eb2e8f9f7 1485 /**
<> 144:ef7eb2e8f9f7 1486 * @}
<> 144:ef7eb2e8f9f7 1487 */
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
<> 144:ef7eb2e8f9f7 1490 * @brief Time Input Capture functions
<> 144:ef7eb2e8f9f7 1491 *
<> 144:ef7eb2e8f9f7 1492 @verbatim
<> 144:ef7eb2e8f9f7 1493 ==============================================================================
<> 144:ef7eb2e8f9f7 1494 ##### Time Input Capture functions #####
<> 144:ef7eb2e8f9f7 1495 ==============================================================================
<> 144:ef7eb2e8f9f7 1496 [..]
<> 144:ef7eb2e8f9f7 1497 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1498 (+) Initialize and configure the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1499 (+) De-initialize the TIM Input Capture.
<> 144:ef7eb2e8f9f7 1500 (+) Start the Time Input Capture.
<> 144:ef7eb2e8f9f7 1501 (+) Stop the Time Input Capture.
<> 144:ef7eb2e8f9f7 1502 (+) Start the Time Input Capture and enable interrupt.
<> 144:ef7eb2e8f9f7 1503 (+) Stop the Time Input Capture and disable interrupt.
<> 144:ef7eb2e8f9f7 1504 (+) Start the Time Input Capture and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1505 (+) Stop the Time Input Capture and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 @endverbatim
<> 144:ef7eb2e8f9f7 1508 * @{
<> 144:ef7eb2e8f9f7 1509 */
<> 144:ef7eb2e8f9f7 1510 /**
<> 144:ef7eb2e8f9f7 1511 * @brief Initializes the TIM Input Capture Time base according to the specified
<> 144:ef7eb2e8f9f7 1512 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1514 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1515 * @retval HAL status
<> 144:ef7eb2e8f9f7 1516 */
<> 144:ef7eb2e8f9f7 1517 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1518 {
<> 144:ef7eb2e8f9f7 1519 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 1520 if(htim == NULL)
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1523 }
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1526 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1527 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 1528 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 1531 {
<> 144:ef7eb2e8f9f7 1532 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 1533 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 1534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1535 HAL_TIM_IC_MspInit(htim);
<> 144:ef7eb2e8f9f7 1536 }
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 1539 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /* Init the base time for the input capture */
<> 144:ef7eb2e8f9f7 1542 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 1545 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 return HAL_OK;
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /**
<> 144:ef7eb2e8f9f7 1551 * @brief DeInitializes the TIM peripheral
<> 144:ef7eb2e8f9f7 1552 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1553 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1554 * @retval HAL status
<> 144:ef7eb2e8f9f7 1555 */
<> 144:ef7eb2e8f9f7 1556 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1557 {
<> 144:ef7eb2e8f9f7 1558 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1559 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1562
<> 144:ef7eb2e8f9f7 1563 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 1564 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 1567 HAL_TIM_IC_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 /* Change TIM state */
<> 144:ef7eb2e8f9f7 1570 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 /* Release Lock */
<> 144:ef7eb2e8f9f7 1573 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1574
<> 144:ef7eb2e8f9f7 1575 return HAL_OK;
<> 144:ef7eb2e8f9f7 1576 }
<> 144:ef7eb2e8f9f7 1577
<> 144:ef7eb2e8f9f7 1578 /**
<> 144:ef7eb2e8f9f7 1579 * @brief Initializes the TIM INput Capture MSP.
<> 144:ef7eb2e8f9f7 1580 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1581 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1582 * @retval None
<> 144:ef7eb2e8f9f7 1583 */
<> 144:ef7eb2e8f9f7 1584 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1585 {
<> 144:ef7eb2e8f9f7 1586 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1587 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1588
<> 144:ef7eb2e8f9f7 1589 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1590 the HAL_TIM_IC_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1591 */
<> 144:ef7eb2e8f9f7 1592 }
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /**
<> 144:ef7eb2e8f9f7 1595 * @brief DeInitializes TIM Input Capture MSP.
<> 144:ef7eb2e8f9f7 1596 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1597 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1598 * @retval None
<> 144:ef7eb2e8f9f7 1599 */
<> 144:ef7eb2e8f9f7 1600 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1601 {
<> 144:ef7eb2e8f9f7 1602 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1603 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1606 the HAL_TIM_IC_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 1607 */
<> 144:ef7eb2e8f9f7 1608 }
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /**
<> 144:ef7eb2e8f9f7 1611 * @brief Starts the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1612 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1613 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1614 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1615 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1616 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1617 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1618 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1619 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1620 * @retval HAL status
<> 144:ef7eb2e8f9f7 1621 */
<> 144:ef7eb2e8f9f7 1622 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1623 {
<> 144:ef7eb2e8f9f7 1624 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1625 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1628 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1631 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Return function status */
<> 144:ef7eb2e8f9f7 1634 return HAL_OK;
<> 144:ef7eb2e8f9f7 1635 }
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /**
<> 144:ef7eb2e8f9f7 1638 * @brief Stops the TIM Input Capture measurement.
<> 144:ef7eb2e8f9f7 1639 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1640 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1641 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1642 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1643 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1644 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1645 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1646 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1647 * @retval HAL status
<> 144:ef7eb2e8f9f7 1648 */
<> 144:ef7eb2e8f9f7 1649 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1650 {
<> 144:ef7eb2e8f9f7 1651 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1652 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1655 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1658 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 /* Return function status */
<> 144:ef7eb2e8f9f7 1661 return HAL_OK;
<> 144:ef7eb2e8f9f7 1662 }
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /**
<> 144:ef7eb2e8f9f7 1665 * @brief Starts the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1666 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1667 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1668 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1669 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1670 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1671 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1672 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1673 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1674 * @retval HAL status
<> 144:ef7eb2e8f9f7 1675 */
<> 144:ef7eb2e8f9f7 1676 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1677 {
<> 144:ef7eb2e8f9f7 1678 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1679 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1680
<> 144:ef7eb2e8f9f7 1681 switch (Channel)
<> 144:ef7eb2e8f9f7 1682 {
<> 144:ef7eb2e8f9f7 1683 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1684 {
<> 144:ef7eb2e8f9f7 1685 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1686 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1687 }
<> 144:ef7eb2e8f9f7 1688 break;
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1691 {
<> 144:ef7eb2e8f9f7 1692 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1693 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1694 }
<> 144:ef7eb2e8f9f7 1695 break;
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1698 {
<> 144:ef7eb2e8f9f7 1699 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1700 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1701 }
<> 144:ef7eb2e8f9f7 1702 break;
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1705 {
<> 144:ef7eb2e8f9f7 1706 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1707 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1708 }
<> 144:ef7eb2e8f9f7 1709 break;
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 default:
<> 144:ef7eb2e8f9f7 1712 break;
<> 144:ef7eb2e8f9f7 1713 }
<> 144:ef7eb2e8f9f7 1714 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1715 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1718 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 /* Return function status */
<> 144:ef7eb2e8f9f7 1721 return HAL_OK;
<> 144:ef7eb2e8f9f7 1722 }
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 /**
<> 144:ef7eb2e8f9f7 1725 * @brief Stops the TIM Input Capture measurement in interrupt mode.
<> 144:ef7eb2e8f9f7 1726 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1727 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1728 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1729 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1730 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1731 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1732 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1733 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1734 * @retval HAL status
<> 144:ef7eb2e8f9f7 1735 */
<> 144:ef7eb2e8f9f7 1736 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1737 {
<> 144:ef7eb2e8f9f7 1738 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1739 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1740
<> 144:ef7eb2e8f9f7 1741 switch (Channel)
<> 144:ef7eb2e8f9f7 1742 {
<> 144:ef7eb2e8f9f7 1743 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1744 {
<> 144:ef7eb2e8f9f7 1745 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1747 }
<> 144:ef7eb2e8f9f7 1748 break;
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1751 {
<> 144:ef7eb2e8f9f7 1752 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1753 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1754 }
<> 144:ef7eb2e8f9f7 1755 break;
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1760 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1761 }
<> 144:ef7eb2e8f9f7 1762 break;
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1765 {
<> 144:ef7eb2e8f9f7 1766 /* Disable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1767 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1768 }
<> 144:ef7eb2e8f9f7 1769 break;
<> 144:ef7eb2e8f9f7 1770
<> 144:ef7eb2e8f9f7 1771 default:
<> 144:ef7eb2e8f9f7 1772 break;
<> 144:ef7eb2e8f9f7 1773 }
<> 144:ef7eb2e8f9f7 1774
<> 144:ef7eb2e8f9f7 1775 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1776 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1777
<> 144:ef7eb2e8f9f7 1778 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1779 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1780
<> 144:ef7eb2e8f9f7 1781 /* Return function status */
<> 144:ef7eb2e8f9f7 1782 return HAL_OK;
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /**
<> 144:ef7eb2e8f9f7 1786 * @brief Starts the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1787 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1788 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1789 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 1790 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1791 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1792 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1793 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1794 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1795 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 1796 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 1797 * @retval HAL status
<> 144:ef7eb2e8f9f7 1798 */
<> 144:ef7eb2e8f9f7 1799 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1800 {
<> 144:ef7eb2e8f9f7 1801 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1802 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1803 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1804
<> 144:ef7eb2e8f9f7 1805 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1806 {
<> 144:ef7eb2e8f9f7 1807 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1808 }
<> 144:ef7eb2e8f9f7 1809 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 if((pData == 0 ) && (Length > 0))
<> 144:ef7eb2e8f9f7 1812 {
<> 144:ef7eb2e8f9f7 1813 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1814 }
<> 144:ef7eb2e8f9f7 1815 else
<> 144:ef7eb2e8f9f7 1816 {
<> 144:ef7eb2e8f9f7 1817 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1818 }
<> 144:ef7eb2e8f9f7 1819 }
<> 144:ef7eb2e8f9f7 1820
<> 144:ef7eb2e8f9f7 1821 switch (Channel)
<> 144:ef7eb2e8f9f7 1822 {
<> 144:ef7eb2e8f9f7 1823 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1824 {
<> 144:ef7eb2e8f9f7 1825 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1826 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1827
<> 144:ef7eb2e8f9f7 1828 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1829 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1832 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1833
<> 144:ef7eb2e8f9f7 1834 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1835 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1836 }
<> 144:ef7eb2e8f9f7 1837 break;
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1840 {
<> 144:ef7eb2e8f9f7 1841 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1842 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1845 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1848 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1849
<> 144:ef7eb2e8f9f7 1850 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1851 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1852 }
<> 144:ef7eb2e8f9f7 1853 break;
<> 144:ef7eb2e8f9f7 1854
<> 144:ef7eb2e8f9f7 1855 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1856 {
<> 144:ef7eb2e8f9f7 1857 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1858 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1859
<> 144:ef7eb2e8f9f7 1860 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1861 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1862
<> 144:ef7eb2e8f9f7 1863 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1864 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1867 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1868 }
<> 144:ef7eb2e8f9f7 1869 break;
<> 144:ef7eb2e8f9f7 1870
<> 144:ef7eb2e8f9f7 1871 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1872 {
<> 144:ef7eb2e8f9f7 1873 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1874 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1877 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1878
<> 144:ef7eb2e8f9f7 1879 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1880 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1883 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1884 }
<> 144:ef7eb2e8f9f7 1885 break;
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 default:
<> 144:ef7eb2e8f9f7 1888 break;
<> 144:ef7eb2e8f9f7 1889 }
<> 144:ef7eb2e8f9f7 1890
<> 144:ef7eb2e8f9f7 1891 /* Enable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1892 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 1893
<> 144:ef7eb2e8f9f7 1894 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1895 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1896
<> 144:ef7eb2e8f9f7 1897 /* Return function status */
<> 144:ef7eb2e8f9f7 1898 return HAL_OK;
<> 144:ef7eb2e8f9f7 1899 }
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /**
<> 144:ef7eb2e8f9f7 1902 * @brief Stops the TIM Input Capture measurement on in DMA mode.
<> 144:ef7eb2e8f9f7 1903 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1904 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1905 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 1906 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1907 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1908 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1909 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1910 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1911 * @retval HAL status
<> 144:ef7eb2e8f9f7 1912 */
<> 144:ef7eb2e8f9f7 1913 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1914 {
<> 144:ef7eb2e8f9f7 1915 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1916 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1917 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 switch (Channel)
<> 144:ef7eb2e8f9f7 1920 {
<> 144:ef7eb2e8f9f7 1921 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1922 {
<> 144:ef7eb2e8f9f7 1923 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1924 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1925 }
<> 144:ef7eb2e8f9f7 1926 break;
<> 144:ef7eb2e8f9f7 1927
<> 144:ef7eb2e8f9f7 1928 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1929 {
<> 144:ef7eb2e8f9f7 1930 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1931 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1932 }
<> 144:ef7eb2e8f9f7 1933 break;
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1936 {
<> 144:ef7eb2e8f9f7 1937 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1938 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1939 }
<> 144:ef7eb2e8f9f7 1940 break;
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1943 {
<> 144:ef7eb2e8f9f7 1944 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1945 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1946 }
<> 144:ef7eb2e8f9f7 1947 break;
<> 144:ef7eb2e8f9f7 1948
<> 144:ef7eb2e8f9f7 1949 default:
<> 144:ef7eb2e8f9f7 1950 break;
<> 144:ef7eb2e8f9f7 1951 }
<> 144:ef7eb2e8f9f7 1952
<> 144:ef7eb2e8f9f7 1953 /* Disable the Input Capture channel */
<> 144:ef7eb2e8f9f7 1954 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 1955
<> 144:ef7eb2e8f9f7 1956 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1957 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1960 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1961
<> 144:ef7eb2e8f9f7 1962 /* Return function status */
<> 144:ef7eb2e8f9f7 1963 return HAL_OK;
<> 144:ef7eb2e8f9f7 1964 }
<> 144:ef7eb2e8f9f7 1965 /**
<> 144:ef7eb2e8f9f7 1966 * @}
<> 144:ef7eb2e8f9f7 1967 */
<> 144:ef7eb2e8f9f7 1968
<> 144:ef7eb2e8f9f7 1969 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
<> 144:ef7eb2e8f9f7 1970 * @brief Time One Pulse functions
<> 144:ef7eb2e8f9f7 1971 *
<> 144:ef7eb2e8f9f7 1972 @verbatim
<> 144:ef7eb2e8f9f7 1973 ==============================================================================
<> 144:ef7eb2e8f9f7 1974 ##### Time One Pulse functions #####
<> 144:ef7eb2e8f9f7 1975 ==============================================================================
<> 144:ef7eb2e8f9f7 1976 [..]
<> 144:ef7eb2e8f9f7 1977 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1978 (+) Initialize and configure the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1979 (+) De-initialize the TIM One Pulse.
<> 144:ef7eb2e8f9f7 1980 (+) Start the Time One Pulse.
<> 144:ef7eb2e8f9f7 1981 (+) Stop the Time One Pulse.
<> 144:ef7eb2e8f9f7 1982 (+) Start the Time One Pulse and enable interrupt.
<> 144:ef7eb2e8f9f7 1983 (+) Stop the Time One Pulse and disable interrupt.
<> 144:ef7eb2e8f9f7 1984 (+) Start the Time One Pulse and enable DMA transfer.
<> 144:ef7eb2e8f9f7 1985 (+) Stop the Time One Pulse and disable DMA transfer.
<> 144:ef7eb2e8f9f7 1986
<> 144:ef7eb2e8f9f7 1987 @endverbatim
<> 144:ef7eb2e8f9f7 1988 * @{
<> 144:ef7eb2e8f9f7 1989 */
<> 144:ef7eb2e8f9f7 1990 /**
<> 144:ef7eb2e8f9f7 1991 * @brief Initializes the TIM One Pulse Time Base according to the specified
<> 144:ef7eb2e8f9f7 1992 * parameters in the TIM_HandleTypeDef and create the associated handle.
<> 144:ef7eb2e8f9f7 1993 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1994 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1995 * @param OnePulseMode: Select the One pulse mode.
<> 144:ef7eb2e8f9f7 1996 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1997 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
<> 144:ef7eb2e8f9f7 1998 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
<> 144:ef7eb2e8f9f7 1999 * @retval HAL status
<> 144:ef7eb2e8f9f7 2000 */
<> 144:ef7eb2e8f9f7 2001 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
<> 144:ef7eb2e8f9f7 2002 {
<> 144:ef7eb2e8f9f7 2003 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2004 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2005 {
<> 144:ef7eb2e8f9f7 2006 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2007 }
<> 144:ef7eb2e8f9f7 2008
<> 144:ef7eb2e8f9f7 2009 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2010 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2011 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 2012 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 2013 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
<> 144:ef7eb2e8f9f7 2014
<> 144:ef7eb2e8f9f7 2015 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2016 {
<> 144:ef7eb2e8f9f7 2017 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2018 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2019 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2020 HAL_TIM_OnePulse_MspInit(htim);
<> 144:ef7eb2e8f9f7 2021 }
<> 144:ef7eb2e8f9f7 2022
<> 144:ef7eb2e8f9f7 2023 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2024 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2025
<> 144:ef7eb2e8f9f7 2026 /* Configure the Time base in the One Pulse Mode */
<> 144:ef7eb2e8f9f7 2027 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2028
<> 144:ef7eb2e8f9f7 2029 /* Reset the OPM Bit */
<> 144:ef7eb2e8f9f7 2030 htim->Instance->CR1 &= ~TIM_CR1_OPM;
<> 144:ef7eb2e8f9f7 2031
<> 144:ef7eb2e8f9f7 2032 /* Configure the OPM Mode */
<> 144:ef7eb2e8f9f7 2033 htim->Instance->CR1 |= OnePulseMode;
<> 144:ef7eb2e8f9f7 2034
<> 144:ef7eb2e8f9f7 2035 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2036 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2037
<> 144:ef7eb2e8f9f7 2038 return HAL_OK;
<> 144:ef7eb2e8f9f7 2039 }
<> 144:ef7eb2e8f9f7 2040
<> 144:ef7eb2e8f9f7 2041 /**
<> 144:ef7eb2e8f9f7 2042 * @brief DeInitializes the TIM One Pulse
<> 144:ef7eb2e8f9f7 2043 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2044 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2045 * @retval HAL status
<> 144:ef7eb2e8f9f7 2046 */
<> 144:ef7eb2e8f9f7 2047 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2048 {
<> 144:ef7eb2e8f9f7 2049 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2050 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2053
<> 144:ef7eb2e8f9f7 2054 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2055 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2058 HAL_TIM_OnePulse_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2059
<> 144:ef7eb2e8f9f7 2060 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2061 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2062
<> 144:ef7eb2e8f9f7 2063 /* Release Lock */
<> 144:ef7eb2e8f9f7 2064 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2065
<> 144:ef7eb2e8f9f7 2066 return HAL_OK;
<> 144:ef7eb2e8f9f7 2067 }
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /**
<> 144:ef7eb2e8f9f7 2070 * @brief Initializes the TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2071 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2072 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2073 * @retval None
<> 144:ef7eb2e8f9f7 2074 */
<> 144:ef7eb2e8f9f7 2075 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2076 {
<> 144:ef7eb2e8f9f7 2077 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2078 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2079
<> 144:ef7eb2e8f9f7 2080 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2081 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2082 */
<> 144:ef7eb2e8f9f7 2083 }
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /**
<> 144:ef7eb2e8f9f7 2086 * @brief DeInitializes TIM One Pulse MSP.
<> 144:ef7eb2e8f9f7 2087 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2088 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2089 * @retval None
<> 144:ef7eb2e8f9f7 2090 */
<> 144:ef7eb2e8f9f7 2091 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2092 {
<> 144:ef7eb2e8f9f7 2093 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2094 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2097 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2098 */
<> 144:ef7eb2e8f9f7 2099 }
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 /**
<> 144:ef7eb2e8f9f7 2102 * @brief Starts the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2103 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2104 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2105 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2106 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2109 * @retval HAL status
<> 144:ef7eb2e8f9f7 2110 */
<> 144:ef7eb2e8f9f7 2111 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2112 {
<> 144:ef7eb2e8f9f7 2113 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2114 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2115 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2116 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2117 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2120 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2121
<> 144:ef7eb2e8f9f7 2122 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2123 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2124
<> 144:ef7eb2e8f9f7 2125 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2126 {
<> 144:ef7eb2e8f9f7 2127 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2128 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2129 }
<> 144:ef7eb2e8f9f7 2130
<> 144:ef7eb2e8f9f7 2131 /* Return function status */
<> 144:ef7eb2e8f9f7 2132 return HAL_OK;
<> 144:ef7eb2e8f9f7 2133 }
<> 144:ef7eb2e8f9f7 2134
<> 144:ef7eb2e8f9f7 2135 /**
<> 144:ef7eb2e8f9f7 2136 * @brief Stops the TIM One Pulse signal generation.
<> 144:ef7eb2e8f9f7 2137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2138 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2139 * @param OutputChannel : TIM Channels to be disable.
<> 144:ef7eb2e8f9f7 2140 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2143 * @retval HAL status
<> 144:ef7eb2e8f9f7 2144 */
<> 144:ef7eb2e8f9f7 2145 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2146 {
<> 144:ef7eb2e8f9f7 2147 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2152
<> 144:ef7eb2e8f9f7 2153 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2154 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2155
<> 144:ef7eb2e8f9f7 2156 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2157 {
<> 144:ef7eb2e8f9f7 2158 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 2159 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2160 }
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2163 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2164
<> 144:ef7eb2e8f9f7 2165 /* Return function status */
<> 144:ef7eb2e8f9f7 2166 return HAL_OK;
<> 144:ef7eb2e8f9f7 2167 }
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /**
<> 144:ef7eb2e8f9f7 2170 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2171 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2172 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2173 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2174 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2175 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2176 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2177 * @retval HAL status
<> 144:ef7eb2e8f9f7 2178 */
<> 144:ef7eb2e8f9f7 2179 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2180 {
<> 144:ef7eb2e8f9f7 2181 /* Enable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2182 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2183 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2184 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2185 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
<> 144:ef7eb2e8f9f7 2186
<> 144:ef7eb2e8f9f7 2187 No need to enable the counter, it's enabled automatically by hardware
<> 144:ef7eb2e8f9f7 2188 (the counter starts in response to a stimulus and generate a pulse */
<> 144:ef7eb2e8f9f7 2189
<> 144:ef7eb2e8f9f7 2190 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2191 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2192
<> 144:ef7eb2e8f9f7 2193 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2194 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2195
<> 144:ef7eb2e8f9f7 2196 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2197 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2200 {
<> 144:ef7eb2e8f9f7 2201 /* Enable the main output */
<> 144:ef7eb2e8f9f7 2202 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2203 }
<> 144:ef7eb2e8f9f7 2204
<> 144:ef7eb2e8f9f7 2205 /* Return function status */
<> 144:ef7eb2e8f9f7 2206 return HAL_OK;
<> 144:ef7eb2e8f9f7 2207 }
<> 144:ef7eb2e8f9f7 2208
<> 144:ef7eb2e8f9f7 2209 /**
<> 144:ef7eb2e8f9f7 2210 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
<> 144:ef7eb2e8f9f7 2211 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2212 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2213 * @param OutputChannel : TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2214 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2217 * @retval HAL status
<> 144:ef7eb2e8f9f7 2218 */
<> 144:ef7eb2e8f9f7 2219 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 2220 {
<> 144:ef7eb2e8f9f7 2221 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 2222 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2223
<> 144:ef7eb2e8f9f7 2224 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 2225 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2226
<> 144:ef7eb2e8f9f7 2227 /* Disable the Capture compare and the Input Capture channels
<> 144:ef7eb2e8f9f7 2228 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2229 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
<> 144:ef7eb2e8f9f7 2230 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
<> 144:ef7eb2e8f9f7 2231 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
<> 144:ef7eb2e8f9f7 2232 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2233 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2234
<> 144:ef7eb2e8f9f7 2235 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
<> 144:ef7eb2e8f9f7 2236 {
<> 144:ef7eb2e8f9f7 2237 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 2238 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2239 }
<> 144:ef7eb2e8f9f7 2240
<> 144:ef7eb2e8f9f7 2241 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2242 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2243
<> 144:ef7eb2e8f9f7 2244 /* Return function status */
<> 144:ef7eb2e8f9f7 2245 return HAL_OK;
<> 144:ef7eb2e8f9f7 2246 }
<> 144:ef7eb2e8f9f7 2247
<> 144:ef7eb2e8f9f7 2248 /**
<> 144:ef7eb2e8f9f7 2249 * @}
<> 144:ef7eb2e8f9f7 2250 */
<> 144:ef7eb2e8f9f7 2251
<> 144:ef7eb2e8f9f7 2252 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
<> 144:ef7eb2e8f9f7 2253 * @brief Time Encoder functions
<> 144:ef7eb2e8f9f7 2254 *
<> 144:ef7eb2e8f9f7 2255 @verbatim
<> 144:ef7eb2e8f9f7 2256 ==============================================================================
<> 144:ef7eb2e8f9f7 2257 ##### Time Encoder functions #####
<> 144:ef7eb2e8f9f7 2258 ==============================================================================
<> 144:ef7eb2e8f9f7 2259 [..]
<> 144:ef7eb2e8f9f7 2260 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2261 (+) Initialize and configure the TIM Encoder.
<> 144:ef7eb2e8f9f7 2262 (+) De-initialize the TIM Encoder.
<> 144:ef7eb2e8f9f7 2263 (+) Start the Time Encoder.
<> 144:ef7eb2e8f9f7 2264 (+) Stop the Time Encoder.
<> 144:ef7eb2e8f9f7 2265 (+) Start the Time Encoder and enable interrupt.
<> 144:ef7eb2e8f9f7 2266 (+) Stop the Time Encoder and disable interrupt.
<> 144:ef7eb2e8f9f7 2267 (+) Start the Time Encoder and enable DMA transfer.
<> 144:ef7eb2e8f9f7 2268 (+) Stop the Time Encoder and disable DMA transfer.
<> 144:ef7eb2e8f9f7 2269
<> 144:ef7eb2e8f9f7 2270 @endverbatim
<> 144:ef7eb2e8f9f7 2271 * @{
<> 144:ef7eb2e8f9f7 2272 */
<> 144:ef7eb2e8f9f7 2273 /**
<> 144:ef7eb2e8f9f7 2274 * @brief Initializes the TIM Encoder Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 2275 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2276 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2277 * @param sConfig: TIM Encoder Interface configuration structure
<> 144:ef7eb2e8f9f7 2278 * @retval HAL status
<> 144:ef7eb2e8f9f7 2279 */
<> 144:ef7eb2e8f9f7 2280 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 2281 {
<> 144:ef7eb2e8f9f7 2282 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 2283 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 2284 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 2285
<> 144:ef7eb2e8f9f7 2286 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 2287 if(htim == NULL)
<> 144:ef7eb2e8f9f7 2288 {
<> 144:ef7eb2e8f9f7 2289 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2290 }
<> 144:ef7eb2e8f9f7 2291
<> 144:ef7eb2e8f9f7 2292 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2293 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2294 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
<> 144:ef7eb2e8f9f7 2295 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
<> 144:ef7eb2e8f9f7 2296 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
<> 144:ef7eb2e8f9f7 2297 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 2298 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
<> 144:ef7eb2e8f9f7 2299 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 2300 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
<> 144:ef7eb2e8f9f7 2301 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 2302 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
<> 144:ef7eb2e8f9f7 2303
<> 144:ef7eb2e8f9f7 2304 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 2305 {
<> 144:ef7eb2e8f9f7 2306 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 2307 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 2308 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 2309 HAL_TIM_Encoder_MspInit(htim);
<> 144:ef7eb2e8f9f7 2310 }
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 2313 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2314
<> 144:ef7eb2e8f9f7 2315 /* Reset the SMS bits */
<> 144:ef7eb2e8f9f7 2316 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 2317
<> 144:ef7eb2e8f9f7 2318 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 2319 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 2320
<> 144:ef7eb2e8f9f7 2321 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 2322 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 2323
<> 144:ef7eb2e8f9f7 2324 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 2325 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 2326
<> 144:ef7eb2e8f9f7 2327 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 2328 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 2329
<> 144:ef7eb2e8f9f7 2330 /* Set the encoder Mode */
<> 144:ef7eb2e8f9f7 2331 tmpsmcr |= sConfig->EncoderMode;
<> 144:ef7eb2e8f9f7 2332
<> 144:ef7eb2e8f9f7 2333 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
<> 144:ef7eb2e8f9f7 2334 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
<> 144:ef7eb2e8f9f7 2335 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
<> 144:ef7eb2e8f9f7 2336
<> 144:ef7eb2e8f9f7 2337 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
<> 144:ef7eb2e8f9f7 2338 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
<> 144:ef7eb2e8f9f7 2339 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 2340 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
<> 144:ef7eb2e8f9f7 2341 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
<> 144:ef7eb2e8f9f7 2342
<> 144:ef7eb2e8f9f7 2343 /* Set the TI1 and the TI2 Polarities */
<> 144:ef7eb2e8f9f7 2344 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
<> 144:ef7eb2e8f9f7 2345 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 2346 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
<> 144:ef7eb2e8f9f7 2347
<> 144:ef7eb2e8f9f7 2348 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 2349 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 2350
<> 144:ef7eb2e8f9f7 2351 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 2352 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 2353
<> 144:ef7eb2e8f9f7 2354 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 2355 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 2356
<> 144:ef7eb2e8f9f7 2357 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 2358 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2359
<> 144:ef7eb2e8f9f7 2360 return HAL_OK;
<> 144:ef7eb2e8f9f7 2361 }
<> 144:ef7eb2e8f9f7 2362
<> 144:ef7eb2e8f9f7 2363 /**
<> 144:ef7eb2e8f9f7 2364 * @brief DeInitializes the TIM Encoder interface
<> 144:ef7eb2e8f9f7 2365 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2366 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2367 * @retval HAL status
<> 144:ef7eb2e8f9f7 2368 */
<> 144:ef7eb2e8f9f7 2369 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2370 {
<> 144:ef7eb2e8f9f7 2371 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2372 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2375
<> 144:ef7eb2e8f9f7 2376 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 2377 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2378
<> 144:ef7eb2e8f9f7 2379 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 2380 HAL_TIM_Encoder_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 2381
<> 144:ef7eb2e8f9f7 2382 /* Change TIM state */
<> 144:ef7eb2e8f9f7 2383 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 2384
<> 144:ef7eb2e8f9f7 2385 /* Release Lock */
<> 144:ef7eb2e8f9f7 2386 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 2387
<> 144:ef7eb2e8f9f7 2388 return HAL_OK;
<> 144:ef7eb2e8f9f7 2389 }
<> 144:ef7eb2e8f9f7 2390
<> 144:ef7eb2e8f9f7 2391 /**
<> 144:ef7eb2e8f9f7 2392 * @brief Initializes the TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2393 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2394 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2395 * @retval None
<> 144:ef7eb2e8f9f7 2396 */
<> 144:ef7eb2e8f9f7 2397 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2398 {
<> 144:ef7eb2e8f9f7 2399 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2400 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2401
<> 144:ef7eb2e8f9f7 2402 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2403 the HAL_TIM_Encoder_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2404 */
<> 144:ef7eb2e8f9f7 2405 }
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 /**
<> 144:ef7eb2e8f9f7 2408 * @brief DeInitializes TIM Encoder Interface MSP.
<> 144:ef7eb2e8f9f7 2409 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2410 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2411 * @retval None
<> 144:ef7eb2e8f9f7 2412 */
<> 144:ef7eb2e8f9f7 2413 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2414 {
<> 144:ef7eb2e8f9f7 2415 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 2416 UNUSED(htim);
<> 144:ef7eb2e8f9f7 2417
<> 144:ef7eb2e8f9f7 2418 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 2419 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 2420 */
<> 144:ef7eb2e8f9f7 2421 }
<> 144:ef7eb2e8f9f7 2422
<> 144:ef7eb2e8f9f7 2423 /**
<> 144:ef7eb2e8f9f7 2424 * @brief Starts the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2425 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2426 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2427 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2428 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2429 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2430 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2431 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2432 * @retval HAL status
<> 144:ef7eb2e8f9f7 2433 */
<> 144:ef7eb2e8f9f7 2434 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2435 {
<> 144:ef7eb2e8f9f7 2436 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2437 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2438
<> 144:ef7eb2e8f9f7 2439 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2440 switch (Channel)
<> 144:ef7eb2e8f9f7 2441 {
<> 144:ef7eb2e8f9f7 2442 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2443 {
<> 144:ef7eb2e8f9f7 2444 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2445 break;
<> 144:ef7eb2e8f9f7 2446 }
<> 144:ef7eb2e8f9f7 2447 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2448 {
<> 144:ef7eb2e8f9f7 2449 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2450 break;
<> 144:ef7eb2e8f9f7 2451 }
<> 144:ef7eb2e8f9f7 2452 default :
<> 144:ef7eb2e8f9f7 2453 {
<> 144:ef7eb2e8f9f7 2454 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2455 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2456 break;
<> 144:ef7eb2e8f9f7 2457 }
<> 144:ef7eb2e8f9f7 2458 }
<> 144:ef7eb2e8f9f7 2459 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2460 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2461
<> 144:ef7eb2e8f9f7 2462 /* Return function status */
<> 144:ef7eb2e8f9f7 2463 return HAL_OK;
<> 144:ef7eb2e8f9f7 2464 }
<> 144:ef7eb2e8f9f7 2465
<> 144:ef7eb2e8f9f7 2466 /**
<> 144:ef7eb2e8f9f7 2467 * @brief Stops the TIM Encoder Interface.
<> 144:ef7eb2e8f9f7 2468 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2469 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2470 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2471 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2472 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2473 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2474 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2475 * @retval HAL status
<> 144:ef7eb2e8f9f7 2476 */
<> 144:ef7eb2e8f9f7 2477 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2478 {
<> 144:ef7eb2e8f9f7 2479 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2480 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2481
<> 144:ef7eb2e8f9f7 2482 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2483 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2484 switch (Channel)
<> 144:ef7eb2e8f9f7 2485 {
<> 144:ef7eb2e8f9f7 2486 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2487 {
<> 144:ef7eb2e8f9f7 2488 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2489 break;
<> 144:ef7eb2e8f9f7 2490 }
<> 144:ef7eb2e8f9f7 2491 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2492 {
<> 144:ef7eb2e8f9f7 2493 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2494 break;
<> 144:ef7eb2e8f9f7 2495 }
<> 144:ef7eb2e8f9f7 2496 default :
<> 144:ef7eb2e8f9f7 2497 {
<> 144:ef7eb2e8f9f7 2498 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2499 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2500 break;
<> 144:ef7eb2e8f9f7 2501 }
<> 144:ef7eb2e8f9f7 2502 }
<> 144:ef7eb2e8f9f7 2503 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2504 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2505
<> 144:ef7eb2e8f9f7 2506 /* Return function status */
<> 144:ef7eb2e8f9f7 2507 return HAL_OK;
<> 144:ef7eb2e8f9f7 2508 }
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 /**
<> 144:ef7eb2e8f9f7 2511 * @brief Starts the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2512 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2513 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2514 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2515 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2516 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2517 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2518 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2519 * @retval HAL status
<> 144:ef7eb2e8f9f7 2520 */
<> 144:ef7eb2e8f9f7 2521 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2522 {
<> 144:ef7eb2e8f9f7 2523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2524 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2525
<> 144:ef7eb2e8f9f7 2526 /* Enable the encoder interface channels */
<> 144:ef7eb2e8f9f7 2527 /* Enable the capture compare Interrupts 1 and/or 2 */
<> 144:ef7eb2e8f9f7 2528 switch (Channel)
<> 144:ef7eb2e8f9f7 2529 {
<> 144:ef7eb2e8f9f7 2530 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2531 {
<> 144:ef7eb2e8f9f7 2532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2533 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2534 break;
<> 144:ef7eb2e8f9f7 2535 }
<> 144:ef7eb2e8f9f7 2536 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2537 {
<> 144:ef7eb2e8f9f7 2538 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2539 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2540 break;
<> 144:ef7eb2e8f9f7 2541 }
<> 144:ef7eb2e8f9f7 2542 default :
<> 144:ef7eb2e8f9f7 2543 {
<> 144:ef7eb2e8f9f7 2544 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2545 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2546 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2547 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2548 break;
<> 144:ef7eb2e8f9f7 2549 }
<> 144:ef7eb2e8f9f7 2550 }
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2553 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2554
<> 144:ef7eb2e8f9f7 2555 /* Return function status */
<> 144:ef7eb2e8f9f7 2556 return HAL_OK;
<> 144:ef7eb2e8f9f7 2557 }
<> 144:ef7eb2e8f9f7 2558
<> 144:ef7eb2e8f9f7 2559 /**
<> 144:ef7eb2e8f9f7 2560 * @brief Stops the TIM Encoder Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 2561 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2562 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2563 * @param Channel: TIM Channels to be disabled.
<> 144:ef7eb2e8f9f7 2564 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2565 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2566 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2567 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2568 * @retval HAL status
<> 144:ef7eb2e8f9f7 2569 */
<> 144:ef7eb2e8f9f7 2570 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2571 {
<> 144:ef7eb2e8f9f7 2572 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2573 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2574
<> 144:ef7eb2e8f9f7 2575 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2576 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2577 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2578 {
<> 144:ef7eb2e8f9f7 2579 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2580
<> 144:ef7eb2e8f9f7 2581 /* Disable the capture compare Interrupts 1 */
<> 144:ef7eb2e8f9f7 2582 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2583 }
<> 144:ef7eb2e8f9f7 2584 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2585 {
<> 144:ef7eb2e8f9f7 2586 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 /* Disable the capture compare Interrupts 2 */
<> 144:ef7eb2e8f9f7 2589 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2590 }
<> 144:ef7eb2e8f9f7 2591 else
<> 144:ef7eb2e8f9f7 2592 {
<> 144:ef7eb2e8f9f7 2593 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2594 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2595
<> 144:ef7eb2e8f9f7 2596 /* Disable the capture compare Interrupts 1 and 2 */
<> 144:ef7eb2e8f9f7 2597 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2598 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2599 }
<> 144:ef7eb2e8f9f7 2600
<> 144:ef7eb2e8f9f7 2601 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2602 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2603
<> 144:ef7eb2e8f9f7 2604 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2605 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2606
<> 144:ef7eb2e8f9f7 2607 /* Return function status */
<> 144:ef7eb2e8f9f7 2608 return HAL_OK;
<> 144:ef7eb2e8f9f7 2609 }
<> 144:ef7eb2e8f9f7 2610
<> 144:ef7eb2e8f9f7 2611 /**
<> 144:ef7eb2e8f9f7 2612 * @brief Starts the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2613 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2614 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2615 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2616 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2617 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2618 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2619 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2620 * @param pData1: The destination Buffer address for IC1.
<> 144:ef7eb2e8f9f7 2621 * @param pData2: The destination Buffer address for IC2.
<> 144:ef7eb2e8f9f7 2622 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 2623 * @retval HAL status
<> 144:ef7eb2e8f9f7 2624 */
<> 144:ef7eb2e8f9f7 2625 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
<> 144:ef7eb2e8f9f7 2626 {
<> 144:ef7eb2e8f9f7 2627 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2628 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2629
<> 144:ef7eb2e8f9f7 2630 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 2631 {
<> 144:ef7eb2e8f9f7 2632 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 2633 }
<> 144:ef7eb2e8f9f7 2634 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 2635 {
<> 144:ef7eb2e8f9f7 2636 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
<> 144:ef7eb2e8f9f7 2637 {
<> 144:ef7eb2e8f9f7 2638 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 2639 }
<> 144:ef7eb2e8f9f7 2640 else
<> 144:ef7eb2e8f9f7 2641 {
<> 144:ef7eb2e8f9f7 2642 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2643 }
<> 144:ef7eb2e8f9f7 2644 }
<> 144:ef7eb2e8f9f7 2645
<> 144:ef7eb2e8f9f7 2646 switch (Channel)
<> 144:ef7eb2e8f9f7 2647 {
<> 144:ef7eb2e8f9f7 2648 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2649 {
<> 144:ef7eb2e8f9f7 2650 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2651 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2652
<> 144:ef7eb2e8f9f7 2653 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2654 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2655
<> 144:ef7eb2e8f9f7 2656 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
<> 144:ef7eb2e8f9f7 2658
<> 144:ef7eb2e8f9f7 2659 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2660 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2661
<> 144:ef7eb2e8f9f7 2662 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2663 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2664
<> 144:ef7eb2e8f9f7 2665 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2666 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2667 }
<> 144:ef7eb2e8f9f7 2668 break;
<> 144:ef7eb2e8f9f7 2669
<> 144:ef7eb2e8f9f7 2670 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 2671 {
<> 144:ef7eb2e8f9f7 2672 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2673 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2676 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
<> 144:ef7eb2e8f9f7 2677 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2678 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2679
<> 144:ef7eb2e8f9f7 2680 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2681 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2682
<> 144:ef7eb2e8f9f7 2683 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2684 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2685
<> 144:ef7eb2e8f9f7 2686 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2687 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2688 }
<> 144:ef7eb2e8f9f7 2689 break;
<> 144:ef7eb2e8f9f7 2690
<> 144:ef7eb2e8f9f7 2691 case TIM_CHANNEL_ALL:
<> 144:ef7eb2e8f9f7 2692 {
<> 144:ef7eb2e8f9f7 2693 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2694 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2695
<> 144:ef7eb2e8f9f7 2696 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2697 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2698
<> 144:ef7eb2e8f9f7 2699 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2700 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
<> 144:ef7eb2e8f9f7 2701
<> 144:ef7eb2e8f9f7 2702 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 2703 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 2704
<> 144:ef7eb2e8f9f7 2705 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 2706 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 2707
<> 144:ef7eb2e8f9f7 2708 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 2709 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
<> 144:ef7eb2e8f9f7 2710
<> 144:ef7eb2e8f9f7 2711 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 2712 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 2713
<> 144:ef7eb2e8f9f7 2714 /* Enable the Capture compare channel */
<> 144:ef7eb2e8f9f7 2715 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2716 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 2717
<> 144:ef7eb2e8f9f7 2718 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2719 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2720 /* Enable the TIM Input Capture DMA request */
<> 144:ef7eb2e8f9f7 2721 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2722 }
<> 144:ef7eb2e8f9f7 2723 break;
<> 144:ef7eb2e8f9f7 2724
<> 144:ef7eb2e8f9f7 2725 default:
<> 144:ef7eb2e8f9f7 2726 break;
<> 144:ef7eb2e8f9f7 2727 }
<> 144:ef7eb2e8f9f7 2728 /* Return function status */
<> 144:ef7eb2e8f9f7 2729 return HAL_OK;
<> 144:ef7eb2e8f9f7 2730 }
<> 144:ef7eb2e8f9f7 2731
<> 144:ef7eb2e8f9f7 2732 /**
<> 144:ef7eb2e8f9f7 2733 * @brief Stops the TIM Encoder Interface in DMA mode.
<> 144:ef7eb2e8f9f7 2734 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2735 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2736 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2737 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2738 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2739 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2740 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
<> 144:ef7eb2e8f9f7 2741 * @retval HAL status
<> 144:ef7eb2e8f9f7 2742 */
<> 144:ef7eb2e8f9f7 2743 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2744 {
<> 144:ef7eb2e8f9f7 2745 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2746 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2747
<> 144:ef7eb2e8f9f7 2748 /* Disable the Input Capture channels 1 and 2
<> 144:ef7eb2e8f9f7 2749 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
<> 144:ef7eb2e8f9f7 2750 if(Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 2751 {
<> 144:ef7eb2e8f9f7 2752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2753
<> 144:ef7eb2e8f9f7 2754 /* Disable the capture compare DMA Request 1 */
<> 144:ef7eb2e8f9f7 2755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2756 }
<> 144:ef7eb2e8f9f7 2757 else if(Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 2758 {
<> 144:ef7eb2e8f9f7 2759 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2760
<> 144:ef7eb2e8f9f7 2761 /* Disable the capture compare DMA Request 2 */
<> 144:ef7eb2e8f9f7 2762 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2763 }
<> 144:ef7eb2e8f9f7 2764 else
<> 144:ef7eb2e8f9f7 2765 {
<> 144:ef7eb2e8f9f7 2766 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2767 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 /* Disable the capture compare DMA Request 1 and 2 */
<> 144:ef7eb2e8f9f7 2770 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 2771 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 2772 }
<> 144:ef7eb2e8f9f7 2773
<> 144:ef7eb2e8f9f7 2774 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 2775 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 2776
<> 144:ef7eb2e8f9f7 2777 /* Change the htim state */
<> 144:ef7eb2e8f9f7 2778 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 2779
<> 144:ef7eb2e8f9f7 2780 /* Return function status */
<> 144:ef7eb2e8f9f7 2781 return HAL_OK;
<> 144:ef7eb2e8f9f7 2782 }
<> 144:ef7eb2e8f9f7 2783
<> 144:ef7eb2e8f9f7 2784 /**
<> 144:ef7eb2e8f9f7 2785 * @}
<> 144:ef7eb2e8f9f7 2786 */
<> 144:ef7eb2e8f9f7 2787 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
<> 144:ef7eb2e8f9f7 2788 * @brief IRQ handler management
<> 144:ef7eb2e8f9f7 2789 *
<> 144:ef7eb2e8f9f7 2790 @verbatim
<> 144:ef7eb2e8f9f7 2791 ==============================================================================
<> 144:ef7eb2e8f9f7 2792 ##### IRQ handler management #####
<> 144:ef7eb2e8f9f7 2793 ==============================================================================
<> 144:ef7eb2e8f9f7 2794 [..]
<> 144:ef7eb2e8f9f7 2795 This section provides Timer IRQ handler function.
<> 144:ef7eb2e8f9f7 2796
<> 144:ef7eb2e8f9f7 2797 @endverbatim
<> 144:ef7eb2e8f9f7 2798 * @{
<> 144:ef7eb2e8f9f7 2799 */
<> 144:ef7eb2e8f9f7 2800 /**
<> 144:ef7eb2e8f9f7 2801 * @brief This function handles TIM interrupts requests.
<> 144:ef7eb2e8f9f7 2802 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2803 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2804 * @retval None
<> 144:ef7eb2e8f9f7 2805 */
<> 144:ef7eb2e8f9f7 2806 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 2807 {
<> 144:ef7eb2e8f9f7 2808 /* Capture compare 1 event */
<> 144:ef7eb2e8f9f7 2809 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
<> 144:ef7eb2e8f9f7 2810 {
<> 144:ef7eb2e8f9f7 2811 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
<> 144:ef7eb2e8f9f7 2812 {
<> 144:ef7eb2e8f9f7 2813 {
<> 144:ef7eb2e8f9f7 2814 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 2816
<> 144:ef7eb2e8f9f7 2817 /* Input capture event */
<> 144:ef7eb2e8f9f7 2818 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
<> 144:ef7eb2e8f9f7 2819 {
<> 144:ef7eb2e8f9f7 2820 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2821 }
<> 144:ef7eb2e8f9f7 2822 /* Output compare event */
<> 144:ef7eb2e8f9f7 2823 else
<> 144:ef7eb2e8f9f7 2824 {
<> 144:ef7eb2e8f9f7 2825 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2826 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2827 }
<> 144:ef7eb2e8f9f7 2828 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2829 }
<> 144:ef7eb2e8f9f7 2830 }
<> 144:ef7eb2e8f9f7 2831 }
<> 144:ef7eb2e8f9f7 2832 /* Capture compare 2 event */
<> 144:ef7eb2e8f9f7 2833 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
<> 144:ef7eb2e8f9f7 2834 {
<> 144:ef7eb2e8f9f7 2835 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
<> 144:ef7eb2e8f9f7 2836 {
<> 144:ef7eb2e8f9f7 2837 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 2838 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 2839 /* Input capture event */
<> 144:ef7eb2e8f9f7 2840 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
<> 144:ef7eb2e8f9f7 2841 {
<> 144:ef7eb2e8f9f7 2842 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2843 }
<> 144:ef7eb2e8f9f7 2844 /* Output compare event */
<> 144:ef7eb2e8f9f7 2845 else
<> 144:ef7eb2e8f9f7 2846 {
<> 144:ef7eb2e8f9f7 2847 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2848 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2849 }
<> 144:ef7eb2e8f9f7 2850 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2851 }
<> 144:ef7eb2e8f9f7 2852 }
<> 144:ef7eb2e8f9f7 2853 /* Capture compare 3 event */
<> 144:ef7eb2e8f9f7 2854 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
<> 144:ef7eb2e8f9f7 2855 {
<> 144:ef7eb2e8f9f7 2856 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
<> 144:ef7eb2e8f9f7 2857 {
<> 144:ef7eb2e8f9f7 2858 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 2859 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 2860 /* Input capture event */
<> 144:ef7eb2e8f9f7 2861 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
<> 144:ef7eb2e8f9f7 2862 {
<> 144:ef7eb2e8f9f7 2863 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2864 }
<> 144:ef7eb2e8f9f7 2865 /* Output compare event */
<> 144:ef7eb2e8f9f7 2866 else
<> 144:ef7eb2e8f9f7 2867 {
<> 144:ef7eb2e8f9f7 2868 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2869 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2870 }
<> 144:ef7eb2e8f9f7 2871 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2872 }
<> 144:ef7eb2e8f9f7 2873 }
<> 144:ef7eb2e8f9f7 2874 /* Capture compare 4 event */
<> 144:ef7eb2e8f9f7 2875 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
<> 144:ef7eb2e8f9f7 2876 {
<> 144:ef7eb2e8f9f7 2877 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
<> 144:ef7eb2e8f9f7 2878 {
<> 144:ef7eb2e8f9f7 2879 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 2880 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 2881 /* Input capture event */
<> 144:ef7eb2e8f9f7 2882 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
<> 144:ef7eb2e8f9f7 2883 {
<> 144:ef7eb2e8f9f7 2884 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 2885 }
<> 144:ef7eb2e8f9f7 2886 /* Output compare event */
<> 144:ef7eb2e8f9f7 2887 else
<> 144:ef7eb2e8f9f7 2888 {
<> 144:ef7eb2e8f9f7 2889 HAL_TIM_OC_DelayElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2890 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 2891 }
<> 144:ef7eb2e8f9f7 2892 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 2893 }
<> 144:ef7eb2e8f9f7 2894 }
<> 144:ef7eb2e8f9f7 2895 /* TIM Update event */
<> 144:ef7eb2e8f9f7 2896 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
<> 144:ef7eb2e8f9f7 2897 {
<> 144:ef7eb2e8f9f7 2898 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
<> 144:ef7eb2e8f9f7 2899 {
<> 144:ef7eb2e8f9f7 2900 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
<> 144:ef7eb2e8f9f7 2901 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 2902 }
<> 144:ef7eb2e8f9f7 2903 }
<> 144:ef7eb2e8f9f7 2904 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2905 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
<> 144:ef7eb2e8f9f7 2906 {
<> 144:ef7eb2e8f9f7 2907 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2908 {
<> 144:ef7eb2e8f9f7 2909 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2910 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2911 }
<> 144:ef7eb2e8f9f7 2912 }
<> 144:ef7eb2e8f9f7 2913
<> 144:ef7eb2e8f9f7 2914 /* TIM Break input event */
<> 144:ef7eb2e8f9f7 2915 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
<> 144:ef7eb2e8f9f7 2916 {
<> 144:ef7eb2e8f9f7 2917 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
<> 144:ef7eb2e8f9f7 2918 {
<> 144:ef7eb2e8f9f7 2919 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 2920 HAL_TIMEx_BreakCallback(htim);
<> 144:ef7eb2e8f9f7 2921 }
<> 144:ef7eb2e8f9f7 2922 }
<> 144:ef7eb2e8f9f7 2923
<> 144:ef7eb2e8f9f7 2924 /* TIM Trigger detection event */
<> 144:ef7eb2e8f9f7 2925 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
<> 144:ef7eb2e8f9f7 2926 {
<> 144:ef7eb2e8f9f7 2927 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
<> 144:ef7eb2e8f9f7 2928 {
<> 144:ef7eb2e8f9f7 2929 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 2930 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 2931 }
<> 144:ef7eb2e8f9f7 2932 }
<> 144:ef7eb2e8f9f7 2933 /* TIM commutation event */
<> 144:ef7eb2e8f9f7 2934 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
<> 144:ef7eb2e8f9f7 2935 {
<> 144:ef7eb2e8f9f7 2936 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
<> 144:ef7eb2e8f9f7 2937 {
<> 144:ef7eb2e8f9f7 2938 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
<> 144:ef7eb2e8f9f7 2939 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 2940 }
<> 144:ef7eb2e8f9f7 2941 }
<> 144:ef7eb2e8f9f7 2942 }
<> 144:ef7eb2e8f9f7 2943
<> 144:ef7eb2e8f9f7 2944 /**
<> 144:ef7eb2e8f9f7 2945 * @}
<> 144:ef7eb2e8f9f7 2946 */
<> 144:ef7eb2e8f9f7 2947
<> 144:ef7eb2e8f9f7 2948 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<> 144:ef7eb2e8f9f7 2949 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 2950 *
<> 144:ef7eb2e8f9f7 2951 @verbatim
<> 144:ef7eb2e8f9f7 2952 ==============================================================================
<> 144:ef7eb2e8f9f7 2953 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 2954 ==============================================================================
<> 144:ef7eb2e8f9f7 2955 [..]
<> 144:ef7eb2e8f9f7 2956 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 2957 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 2958 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 2959 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 2960 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 2961 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 2962
<> 144:ef7eb2e8f9f7 2963 @endverbatim
<> 144:ef7eb2e8f9f7 2964 * @{
<> 144:ef7eb2e8f9f7 2965 */
<> 144:ef7eb2e8f9f7 2966
<> 144:ef7eb2e8f9f7 2967 /**
<> 144:ef7eb2e8f9f7 2968 * @brief Initializes the TIM Output Compare Channels according to the specified
<> 144:ef7eb2e8f9f7 2969 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 2970 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 2971 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 2972 * @param sConfig: TIM Output Compare configuration structure
<> 144:ef7eb2e8f9f7 2973 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 2974 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 2975 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 2976 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 2977 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 2978 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 2979 * @retval HAL status
<> 144:ef7eb2e8f9f7 2980 */
<> 144:ef7eb2e8f9f7 2981 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 2982 {
<> 144:ef7eb2e8f9f7 2983 /* Check the parameters */
<> 144:ef7eb2e8f9f7 2984 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 2985 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 2986 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 2987
<> 144:ef7eb2e8f9f7 2988 /* Check input state */
<> 144:ef7eb2e8f9f7 2989 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 2990
<> 144:ef7eb2e8f9f7 2991 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 2992
<> 144:ef7eb2e8f9f7 2993 switch (Channel)
<> 144:ef7eb2e8f9f7 2994 {
<> 144:ef7eb2e8f9f7 2995 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 2996 {
<> 144:ef7eb2e8f9f7 2997 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 2998 /* Configure the TIM Channel 1 in Output Compare */
<> 144:ef7eb2e8f9f7 2999 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3000 }
<> 144:ef7eb2e8f9f7 3001 break;
<> 144:ef7eb2e8f9f7 3002
<> 144:ef7eb2e8f9f7 3003 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3004 {
<> 144:ef7eb2e8f9f7 3005 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3006 /* Configure the TIM Channel 2 in Output Compare */
<> 144:ef7eb2e8f9f7 3007 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3008 }
<> 144:ef7eb2e8f9f7 3009 break;
<> 144:ef7eb2e8f9f7 3010
<> 144:ef7eb2e8f9f7 3011 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3012 {
<> 144:ef7eb2e8f9f7 3013 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3014 /* Configure the TIM Channel 3 in Output Compare */
<> 144:ef7eb2e8f9f7 3015 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3016 }
<> 144:ef7eb2e8f9f7 3017 break;
<> 144:ef7eb2e8f9f7 3018
<> 144:ef7eb2e8f9f7 3019 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3020 {
<> 144:ef7eb2e8f9f7 3021 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3022 /* Configure the TIM Channel 4 in Output Compare */
<> 144:ef7eb2e8f9f7 3023 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3024 }
<> 144:ef7eb2e8f9f7 3025 break;
<> 144:ef7eb2e8f9f7 3026
<> 144:ef7eb2e8f9f7 3027 default:
<> 144:ef7eb2e8f9f7 3028 break;
<> 144:ef7eb2e8f9f7 3029 }
<> 144:ef7eb2e8f9f7 3030 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3031
<> 144:ef7eb2e8f9f7 3032 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3033
<> 144:ef7eb2e8f9f7 3034 return HAL_OK;
<> 144:ef7eb2e8f9f7 3035 }
<> 144:ef7eb2e8f9f7 3036
<> 144:ef7eb2e8f9f7 3037 /**
<> 144:ef7eb2e8f9f7 3038 * @brief Initializes the TIM Input Capture Channels according to the specified
<> 144:ef7eb2e8f9f7 3039 * parameters in the TIM_IC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3040 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3041 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3042 * @param sConfig: TIM Input Capture configuration structure
<> 144:ef7eb2e8f9f7 3043 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3044 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3045 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3046 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3047 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3048 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3049 * @retval HAL status
<> 144:ef7eb2e8f9f7 3050 */
<> 144:ef7eb2e8f9f7 3051 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3052 {
<> 144:ef7eb2e8f9f7 3053 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3054 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3055 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
<> 144:ef7eb2e8f9f7 3056 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
<> 144:ef7eb2e8f9f7 3057 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
<> 144:ef7eb2e8f9f7 3058 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
<> 144:ef7eb2e8f9f7 3059
<> 144:ef7eb2e8f9f7 3060 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3061
<> 144:ef7eb2e8f9f7 3062 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3063
<> 144:ef7eb2e8f9f7 3064 if (Channel == TIM_CHANNEL_1)
<> 144:ef7eb2e8f9f7 3065 {
<> 144:ef7eb2e8f9f7 3066 /* TI1 Configuration */
<> 144:ef7eb2e8f9f7 3067 TIM_TI1_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3068 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3069 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3070 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3071
<> 144:ef7eb2e8f9f7 3072 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3073 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3074
<> 144:ef7eb2e8f9f7 3075 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 3076 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3077 }
<> 144:ef7eb2e8f9f7 3078 else if (Channel == TIM_CHANNEL_2)
<> 144:ef7eb2e8f9f7 3079 {
<> 144:ef7eb2e8f9f7 3080 /* TI2 Configuration */
<> 144:ef7eb2e8f9f7 3081 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3082
<> 144:ef7eb2e8f9f7 3083 TIM_TI2_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3084 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3085 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3086 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3087
<> 144:ef7eb2e8f9f7 3088 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3089 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3090
<> 144:ef7eb2e8f9f7 3091 /* Set the IC2PSC value */
<> 144:ef7eb2e8f9f7 3092 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
<> 144:ef7eb2e8f9f7 3093 }
<> 144:ef7eb2e8f9f7 3094 else if (Channel == TIM_CHANNEL_3)
<> 144:ef7eb2e8f9f7 3095 {
<> 144:ef7eb2e8f9f7 3096 /* TI3 Configuration */
<> 144:ef7eb2e8f9f7 3097 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3098
<> 144:ef7eb2e8f9f7 3099 TIM_TI3_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3100 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3101 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3102 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3103
<> 144:ef7eb2e8f9f7 3104 /* Reset the IC3PSC Bits */
<> 144:ef7eb2e8f9f7 3105 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
<> 144:ef7eb2e8f9f7 3106
<> 144:ef7eb2e8f9f7 3107 /* Set the IC3PSC value */
<> 144:ef7eb2e8f9f7 3108 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
<> 144:ef7eb2e8f9f7 3109 }
<> 144:ef7eb2e8f9f7 3110 else
<> 144:ef7eb2e8f9f7 3111 {
<> 144:ef7eb2e8f9f7 3112 /* TI4 Configuration */
<> 144:ef7eb2e8f9f7 3113 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3114
<> 144:ef7eb2e8f9f7 3115 TIM_TI4_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3116 sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3117 sConfig->ICSelection,
<> 144:ef7eb2e8f9f7 3118 sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3119
<> 144:ef7eb2e8f9f7 3120 /* Reset the IC4PSC Bits */
<> 144:ef7eb2e8f9f7 3121 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
<> 144:ef7eb2e8f9f7 3122
<> 144:ef7eb2e8f9f7 3123 /* Set the IC4PSC value */
<> 144:ef7eb2e8f9f7 3124 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
<> 144:ef7eb2e8f9f7 3125 }
<> 144:ef7eb2e8f9f7 3126
<> 144:ef7eb2e8f9f7 3127 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3128
<> 144:ef7eb2e8f9f7 3129 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3130
<> 144:ef7eb2e8f9f7 3131 return HAL_OK;
<> 144:ef7eb2e8f9f7 3132 }
<> 144:ef7eb2e8f9f7 3133
<> 144:ef7eb2e8f9f7 3134 /**
<> 144:ef7eb2e8f9f7 3135 * @brief Initializes the TIM PWM channels according to the specified
<> 144:ef7eb2e8f9f7 3136 * parameters in the TIM_OC_InitTypeDef.
<> 144:ef7eb2e8f9f7 3137 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3138 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3139 * @param sConfig: TIM PWM configuration structure
<> 144:ef7eb2e8f9f7 3140 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3141 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3142 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3143 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3144 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3145 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3146 * @retval HAL status
<> 144:ef7eb2e8f9f7 3147 */
<> 144:ef7eb2e8f9f7 3148 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3149 {
<> 144:ef7eb2e8f9f7 3150 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3151
<> 144:ef7eb2e8f9f7 3152 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3153 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3154 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<> 144:ef7eb2e8f9f7 3155 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<> 144:ef7eb2e8f9f7 3156 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<> 144:ef7eb2e8f9f7 3157
<> 144:ef7eb2e8f9f7 3158 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3159
<> 144:ef7eb2e8f9f7 3160 switch (Channel)
<> 144:ef7eb2e8f9f7 3161 {
<> 144:ef7eb2e8f9f7 3162 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3163 {
<> 144:ef7eb2e8f9f7 3164 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3165 /* Configure the Channel 1 in PWM mode */
<> 144:ef7eb2e8f9f7 3166 TIM_OC1_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3167
<> 144:ef7eb2e8f9f7 3168 /* Set the Preload enable bit for channel1 */
<> 144:ef7eb2e8f9f7 3169 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
<> 144:ef7eb2e8f9f7 3170
<> 144:ef7eb2e8f9f7 3171 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3172 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<> 144:ef7eb2e8f9f7 3173 htim->Instance->CCMR1 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3174 }
<> 144:ef7eb2e8f9f7 3175 break;
<> 144:ef7eb2e8f9f7 3176
<> 144:ef7eb2e8f9f7 3177 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3178 {
<> 144:ef7eb2e8f9f7 3179 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3180 /* Configure the Channel 2 in PWM mode */
<> 144:ef7eb2e8f9f7 3181 TIM_OC2_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3182
<> 144:ef7eb2e8f9f7 3183 /* Set the Preload enable bit for channel2 */
<> 144:ef7eb2e8f9f7 3184 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
<> 144:ef7eb2e8f9f7 3185
<> 144:ef7eb2e8f9f7 3186 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3187 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<> 144:ef7eb2e8f9f7 3188 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 3189 }
<> 144:ef7eb2e8f9f7 3190 break;
<> 144:ef7eb2e8f9f7 3191
<> 144:ef7eb2e8f9f7 3192 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3193 {
<> 144:ef7eb2e8f9f7 3194 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3195 /* Configure the Channel 3 in PWM mode */
<> 144:ef7eb2e8f9f7 3196 TIM_OC3_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3197
<> 144:ef7eb2e8f9f7 3198 /* Set the Preload enable bit for channel3 */
<> 144:ef7eb2e8f9f7 3199 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
<> 144:ef7eb2e8f9f7 3200
<> 144:ef7eb2e8f9f7 3201 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3202 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<> 144:ef7eb2e8f9f7 3203 htim->Instance->CCMR2 |= sConfig->OCFastMode;
<> 144:ef7eb2e8f9f7 3204 }
<> 144:ef7eb2e8f9f7 3205 break;
<> 144:ef7eb2e8f9f7 3206
<> 144:ef7eb2e8f9f7 3207 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3208 {
<> 144:ef7eb2e8f9f7 3209 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3210 /* Configure the Channel 4 in PWM mode */
<> 144:ef7eb2e8f9f7 3211 TIM_OC4_SetConfig(htim->Instance, sConfig);
<> 144:ef7eb2e8f9f7 3212
<> 144:ef7eb2e8f9f7 3213 /* Set the Preload enable bit for channel4 */
<> 144:ef7eb2e8f9f7 3214 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
<> 144:ef7eb2e8f9f7 3215
<> 144:ef7eb2e8f9f7 3216 /* Configure the Output Fast mode */
<> 144:ef7eb2e8f9f7 3217 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<> 144:ef7eb2e8f9f7 3218 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
<> 144:ef7eb2e8f9f7 3219 }
<> 144:ef7eb2e8f9f7 3220 break;
<> 144:ef7eb2e8f9f7 3221
<> 144:ef7eb2e8f9f7 3222 default:
<> 144:ef7eb2e8f9f7 3223 break;
<> 144:ef7eb2e8f9f7 3224 }
<> 144:ef7eb2e8f9f7 3225
<> 144:ef7eb2e8f9f7 3226 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3227
<> 144:ef7eb2e8f9f7 3228 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3229
<> 144:ef7eb2e8f9f7 3230 return HAL_OK;
<> 144:ef7eb2e8f9f7 3231 }
<> 144:ef7eb2e8f9f7 3232
<> 144:ef7eb2e8f9f7 3233 /**
<> 144:ef7eb2e8f9f7 3234 * @brief Initializes the TIM One Pulse Channels according to the specified
<> 144:ef7eb2e8f9f7 3235 * parameters in the TIM_OnePulse_InitTypeDef.
<> 144:ef7eb2e8f9f7 3236 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3237 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3238 * @param sConfig: TIM One Pulse configuration structure
<> 144:ef7eb2e8f9f7 3239 * @param OutputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3240 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3241 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3242 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3243 * @param InputChannel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 3244 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3245 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3246 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3247 * @retval HAL status
<> 144:ef7eb2e8f9f7 3248 */
<> 144:ef7eb2e8f9f7 3249 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
<> 144:ef7eb2e8f9f7 3250 {
<> 144:ef7eb2e8f9f7 3251 TIM_OC_InitTypeDef temp1;
<> 144:ef7eb2e8f9f7 3252
<> 144:ef7eb2e8f9f7 3253 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3254 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
<> 144:ef7eb2e8f9f7 3255 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
<> 144:ef7eb2e8f9f7 3256
<> 144:ef7eb2e8f9f7 3257 if(OutputChannel != InputChannel)
<> 144:ef7eb2e8f9f7 3258 {
<> 144:ef7eb2e8f9f7 3259 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3260
<> 144:ef7eb2e8f9f7 3261 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3262
<> 144:ef7eb2e8f9f7 3263 /* Extract the Output compare configuration from sConfig structure */
<> 144:ef7eb2e8f9f7 3264 temp1.OCMode = sConfig->OCMode;
<> 144:ef7eb2e8f9f7 3265 temp1.Pulse = sConfig->Pulse;
<> 144:ef7eb2e8f9f7 3266 temp1.OCPolarity = sConfig->OCPolarity;
<> 144:ef7eb2e8f9f7 3267 temp1.OCNPolarity = sConfig->OCNPolarity;
<> 144:ef7eb2e8f9f7 3268 temp1.OCIdleState = sConfig->OCIdleState;
<> 144:ef7eb2e8f9f7 3269 temp1.OCNIdleState = sConfig->OCNIdleState;
<> 144:ef7eb2e8f9f7 3270
<> 144:ef7eb2e8f9f7 3271 switch (OutputChannel)
<> 144:ef7eb2e8f9f7 3272 {
<> 144:ef7eb2e8f9f7 3273 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3274 {
<> 144:ef7eb2e8f9f7 3275 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3276
<> 144:ef7eb2e8f9f7 3277 TIM_OC1_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3278 }
<> 144:ef7eb2e8f9f7 3279 break;
<> 144:ef7eb2e8f9f7 3280 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3281 {
<> 144:ef7eb2e8f9f7 3282 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3283
<> 144:ef7eb2e8f9f7 3284 TIM_OC2_SetConfig(htim->Instance, &temp1);
<> 144:ef7eb2e8f9f7 3285 }
<> 144:ef7eb2e8f9f7 3286 break;
<> 144:ef7eb2e8f9f7 3287 default:
<> 144:ef7eb2e8f9f7 3288 break;
<> 144:ef7eb2e8f9f7 3289 }
<> 144:ef7eb2e8f9f7 3290 switch (InputChannel)
<> 144:ef7eb2e8f9f7 3291 {
<> 144:ef7eb2e8f9f7 3292 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3293 {
<> 144:ef7eb2e8f9f7 3294 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3295
<> 144:ef7eb2e8f9f7 3296 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3297 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3298
<> 144:ef7eb2e8f9f7 3299 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 3300 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 3301
<> 144:ef7eb2e8f9f7 3302 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3303 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3304 htim->Instance->SMCR |= TIM_TS_TI1FP1;
<> 144:ef7eb2e8f9f7 3305
<> 144:ef7eb2e8f9f7 3306 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3307 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3308 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3309 }
<> 144:ef7eb2e8f9f7 3310 break;
<> 144:ef7eb2e8f9f7 3311 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3312 {
<> 144:ef7eb2e8f9f7 3313 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3314
<> 144:ef7eb2e8f9f7 3315 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
<> 144:ef7eb2e8f9f7 3316 sConfig->ICSelection, sConfig->ICFilter);
<> 144:ef7eb2e8f9f7 3317
<> 144:ef7eb2e8f9f7 3318 /* Reset the IC2PSC Bits */
<> 144:ef7eb2e8f9f7 3319 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
<> 144:ef7eb2e8f9f7 3320
<> 144:ef7eb2e8f9f7 3321 /* Select the Trigger source */
<> 144:ef7eb2e8f9f7 3322 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 3323 htim->Instance->SMCR |= TIM_TS_TI2FP2;
<> 144:ef7eb2e8f9f7 3324
<> 144:ef7eb2e8f9f7 3325 /* Select the Slave Mode */
<> 144:ef7eb2e8f9f7 3326 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3327 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
<> 144:ef7eb2e8f9f7 3328 }
<> 144:ef7eb2e8f9f7 3329 break;
<> 144:ef7eb2e8f9f7 3330
<> 144:ef7eb2e8f9f7 3331 default:
<> 144:ef7eb2e8f9f7 3332 break;
<> 144:ef7eb2e8f9f7 3333 }
<> 144:ef7eb2e8f9f7 3334
<> 144:ef7eb2e8f9f7 3335 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3336
<> 144:ef7eb2e8f9f7 3337 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3338
<> 144:ef7eb2e8f9f7 3339 return HAL_OK;
<> 144:ef7eb2e8f9f7 3340 }
<> 144:ef7eb2e8f9f7 3341 else
<> 144:ef7eb2e8f9f7 3342 {
<> 144:ef7eb2e8f9f7 3343 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3344 }
<> 144:ef7eb2e8f9f7 3345 }
<> 144:ef7eb2e8f9f7 3346
<> 144:ef7eb2e8f9f7 3347 /**
<> 144:ef7eb2e8f9f7 3348 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
<> 144:ef7eb2e8f9f7 3349 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3350 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3351 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
<> 144:ef7eb2e8f9f7 3352 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3353 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3354 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3355 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3356 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3357 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3358 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3359 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3360 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3361 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3362 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3363 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3364 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3365 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3366 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3367 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3368 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3369 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3370 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3371 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3372 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3373 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3374 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3375 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3376 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3377 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3378 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3379 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3380 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3381 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3382 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3383 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3384 * @retval HAL status
<> 144:ef7eb2e8f9f7 3385 */
<> 144:ef7eb2e8f9f7 3386 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3387 uint32_t* BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3388 {
<> 144:ef7eb2e8f9f7 3389 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3390 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3391 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3392 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3393 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3394
<> 144:ef7eb2e8f9f7 3395 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3396 {
<> 144:ef7eb2e8f9f7 3397 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3398 }
<> 144:ef7eb2e8f9f7 3399 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3400 {
<> 144:ef7eb2e8f9f7 3401 if((BurstBuffer == 0 ) && (BurstLength > 0))
<> 144:ef7eb2e8f9f7 3402 {
<> 144:ef7eb2e8f9f7 3403 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3404 }
<> 144:ef7eb2e8f9f7 3405 else
<> 144:ef7eb2e8f9f7 3406 {
<> 144:ef7eb2e8f9f7 3407 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3408 }
<> 144:ef7eb2e8f9f7 3409 }
<> 144:ef7eb2e8f9f7 3410 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3411 {
<> 144:ef7eb2e8f9f7 3412 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3413 {
<> 144:ef7eb2e8f9f7 3414 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3415 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3416
<> 144:ef7eb2e8f9f7 3417 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3418 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3419
<> 144:ef7eb2e8f9f7 3420 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3421 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3422 }
<> 144:ef7eb2e8f9f7 3423 break;
<> 144:ef7eb2e8f9f7 3424 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3425 {
<> 144:ef7eb2e8f9f7 3426 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3427 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3428
<> 144:ef7eb2e8f9f7 3429 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3430 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3431
<> 144:ef7eb2e8f9f7 3432 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3433 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3434 }
<> 144:ef7eb2e8f9f7 3435 break;
<> 144:ef7eb2e8f9f7 3436 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3437 {
<> 144:ef7eb2e8f9f7 3438 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3439 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3442 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3443
<> 144:ef7eb2e8f9f7 3444 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3445 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3446 }
<> 144:ef7eb2e8f9f7 3447 break;
<> 144:ef7eb2e8f9f7 3448 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3449 {
<> 144:ef7eb2e8f9f7 3450 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3451 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3452
<> 144:ef7eb2e8f9f7 3453 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3454 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3455
<> 144:ef7eb2e8f9f7 3456 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3457 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3458 }
<> 144:ef7eb2e8f9f7 3459 break;
<> 144:ef7eb2e8f9f7 3460 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3461 {
<> 144:ef7eb2e8f9f7 3462 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3463 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 3464
<> 144:ef7eb2e8f9f7 3465 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3466 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3467
<> 144:ef7eb2e8f9f7 3468 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3469 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3470 }
<> 144:ef7eb2e8f9f7 3471 break;
<> 144:ef7eb2e8f9f7 3472 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3473 {
<> 144:ef7eb2e8f9f7 3474 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3475 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3476
<> 144:ef7eb2e8f9f7 3477 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3478 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3479
<> 144:ef7eb2e8f9f7 3480 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3481 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3482 }
<> 144:ef7eb2e8f9f7 3483 break;
<> 144:ef7eb2e8f9f7 3484 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3485 {
<> 144:ef7eb2e8f9f7 3486 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3487 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3488
<> 144:ef7eb2e8f9f7 3489 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3490 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3491
<> 144:ef7eb2e8f9f7 3492 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3493 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3494 }
<> 144:ef7eb2e8f9f7 3495 break;
<> 144:ef7eb2e8f9f7 3496 default:
<> 144:ef7eb2e8f9f7 3497 break;
<> 144:ef7eb2e8f9f7 3498 }
<> 144:ef7eb2e8f9f7 3499 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3500 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3501
<> 144:ef7eb2e8f9f7 3502 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3503 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3504
<> 144:ef7eb2e8f9f7 3505 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3506
<> 144:ef7eb2e8f9f7 3507 /* Return function status */
<> 144:ef7eb2e8f9f7 3508 return HAL_OK;
<> 144:ef7eb2e8f9f7 3509 }
<> 144:ef7eb2e8f9f7 3510
<> 144:ef7eb2e8f9f7 3511 /**
<> 144:ef7eb2e8f9f7 3512 * @brief Stops the TIM DMA Burst mode
<> 144:ef7eb2e8f9f7 3513 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3514 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3515 * @param BurstRequestSrc: TIM DMA Request sources to disable
<> 144:ef7eb2e8f9f7 3516 * @retval HAL status
<> 144:ef7eb2e8f9f7 3517 */
<> 144:ef7eb2e8f9f7 3518 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3519 {
<> 144:ef7eb2e8f9f7 3520 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3521 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3522
<> 144:ef7eb2e8f9f7 3523 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3524 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3525 {
<> 144:ef7eb2e8f9f7 3526 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3527 {
<> 144:ef7eb2e8f9f7 3528 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3529 }
<> 144:ef7eb2e8f9f7 3530 break;
<> 144:ef7eb2e8f9f7 3531 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3532 {
<> 144:ef7eb2e8f9f7 3533 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3534 }
<> 144:ef7eb2e8f9f7 3535 break;
<> 144:ef7eb2e8f9f7 3536 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3537 {
<> 144:ef7eb2e8f9f7 3538 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3539 }
<> 144:ef7eb2e8f9f7 3540 break;
<> 144:ef7eb2e8f9f7 3541 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3542 {
<> 144:ef7eb2e8f9f7 3543 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3544 }
<> 144:ef7eb2e8f9f7 3545 break;
<> 144:ef7eb2e8f9f7 3546 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3547 {
<> 144:ef7eb2e8f9f7 3548 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3549 }
<> 144:ef7eb2e8f9f7 3550 break;
<> 144:ef7eb2e8f9f7 3551 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3552 {
<> 144:ef7eb2e8f9f7 3553 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3554 }
<> 144:ef7eb2e8f9f7 3555 break;
<> 144:ef7eb2e8f9f7 3556 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3557 {
<> 144:ef7eb2e8f9f7 3558 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3559 }
<> 144:ef7eb2e8f9f7 3560 break;
<> 144:ef7eb2e8f9f7 3561 default:
<> 144:ef7eb2e8f9f7 3562 break;
<> 144:ef7eb2e8f9f7 3563 }
<> 144:ef7eb2e8f9f7 3564
<> 144:ef7eb2e8f9f7 3565 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3566 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3567
<> 144:ef7eb2e8f9f7 3568 /* Return function status */
<> 144:ef7eb2e8f9f7 3569 return HAL_OK;
<> 144:ef7eb2e8f9f7 3570 }
<> 144:ef7eb2e8f9f7 3571
<> 144:ef7eb2e8f9f7 3572 /**
<> 144:ef7eb2e8f9f7 3573 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
<> 144:ef7eb2e8f9f7 3574 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3575 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3576 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
<> 144:ef7eb2e8f9f7 3577 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3578 * @arg TIM_DMABASE_CR1
<> 144:ef7eb2e8f9f7 3579 * @arg TIM_DMABASE_CR2
<> 144:ef7eb2e8f9f7 3580 * @arg TIM_DMABASE_SMCR
<> 144:ef7eb2e8f9f7 3581 * @arg TIM_DMABASE_DIER
<> 144:ef7eb2e8f9f7 3582 * @arg TIM_DMABASE_SR
<> 144:ef7eb2e8f9f7 3583 * @arg TIM_DMABASE_EGR
<> 144:ef7eb2e8f9f7 3584 * @arg TIM_DMABASE_CCMR1
<> 144:ef7eb2e8f9f7 3585 * @arg TIM_DMABASE_CCMR2
<> 144:ef7eb2e8f9f7 3586 * @arg TIM_DMABASE_CCER
<> 144:ef7eb2e8f9f7 3587 * @arg TIM_DMABASE_CNT
<> 144:ef7eb2e8f9f7 3588 * @arg TIM_DMABASE_PSC
<> 144:ef7eb2e8f9f7 3589 * @arg TIM_DMABASE_ARR
<> 144:ef7eb2e8f9f7 3590 * @arg TIM_DMABASE_RCR
<> 144:ef7eb2e8f9f7 3591 * @arg TIM_DMABASE_CCR1
<> 144:ef7eb2e8f9f7 3592 * @arg TIM_DMABASE_CCR2
<> 144:ef7eb2e8f9f7 3593 * @arg TIM_DMABASE_CCR3
<> 144:ef7eb2e8f9f7 3594 * @arg TIM_DMABASE_CCR4
<> 144:ef7eb2e8f9f7 3595 * @arg TIM_DMABASE_BDTR
<> 144:ef7eb2e8f9f7 3596 * @arg TIM_DMABASE_DCR
<> 144:ef7eb2e8f9f7 3597 * @param BurstRequestSrc: TIM DMA Request sources.
<> 144:ef7eb2e8f9f7 3598 * This parameters can be on of the following values:
<> 144:ef7eb2e8f9f7 3599 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
<> 144:ef7eb2e8f9f7 3600 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
<> 144:ef7eb2e8f9f7 3601 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
<> 144:ef7eb2e8f9f7 3602 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
<> 144:ef7eb2e8f9f7 3603 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
<> 144:ef7eb2e8f9f7 3604 * @arg TIM_DMA_COM: TIM Commutation DMA source
<> 144:ef7eb2e8f9f7 3605 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
<> 144:ef7eb2e8f9f7 3606 * @param BurstBuffer: The Buffer address.
<> 144:ef7eb2e8f9f7 3607 * @param BurstLength: DMA Burst length. This parameter can be one value
<> 144:ef7eb2e8f9f7 3608 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
<> 144:ef7eb2e8f9f7 3609 * @retval HAL status
<> 144:ef7eb2e8f9f7 3610 */
<> 144:ef7eb2e8f9f7 3611 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
<> 144:ef7eb2e8f9f7 3612 uint32_t *BurstBuffer, uint32_t BurstLength)
<> 144:ef7eb2e8f9f7 3613 {
<> 144:ef7eb2e8f9f7 3614 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3615 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3616 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
<> 144:ef7eb2e8f9f7 3617 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3618 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
<> 144:ef7eb2e8f9f7 3619
<> 144:ef7eb2e8f9f7 3620 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 3621 {
<> 144:ef7eb2e8f9f7 3622 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 3623 }
<> 144:ef7eb2e8f9f7 3624 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 3625 {
<> 144:ef7eb2e8f9f7 3626 if((BurstBuffer == 0 ) && (BurstLength > 0))
<> 144:ef7eb2e8f9f7 3627 {
<> 144:ef7eb2e8f9f7 3628 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 3629 }
<> 144:ef7eb2e8f9f7 3630 else
<> 144:ef7eb2e8f9f7 3631 {
<> 144:ef7eb2e8f9f7 3632 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3633 }
<> 144:ef7eb2e8f9f7 3634 }
<> 144:ef7eb2e8f9f7 3635 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3636 {
<> 144:ef7eb2e8f9f7 3637 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3638 {
<> 144:ef7eb2e8f9f7 3639 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3640 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
<> 144:ef7eb2e8f9f7 3641
<> 144:ef7eb2e8f9f7 3642 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3643 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3644
<> 144:ef7eb2e8f9f7 3645 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3646 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3647 }
<> 144:ef7eb2e8f9f7 3648 break;
<> 144:ef7eb2e8f9f7 3649 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3650 {
<> 144:ef7eb2e8f9f7 3651 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3652 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3653
<> 144:ef7eb2e8f9f7 3654 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3655 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3656
<> 144:ef7eb2e8f9f7 3657 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3658 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3659 }
<> 144:ef7eb2e8f9f7 3660 break;
<> 144:ef7eb2e8f9f7 3661 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3662 {
<> 144:ef7eb2e8f9f7 3663 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3664 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3665
<> 144:ef7eb2e8f9f7 3666 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3667 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3668
<> 144:ef7eb2e8f9f7 3669 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3670 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3671 }
<> 144:ef7eb2e8f9f7 3672 break;
<> 144:ef7eb2e8f9f7 3673 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3674 {
<> 144:ef7eb2e8f9f7 3675 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3676 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3677
<> 144:ef7eb2e8f9f7 3678 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3679 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3680
<> 144:ef7eb2e8f9f7 3681 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3682 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3683 }
<> 144:ef7eb2e8f9f7 3684 break;
<> 144:ef7eb2e8f9f7 3685 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3686 {
<> 144:ef7eb2e8f9f7 3687 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3688 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 3689
<> 144:ef7eb2e8f9f7 3690 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3691 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3694 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3695 }
<> 144:ef7eb2e8f9f7 3696 break;
<> 144:ef7eb2e8f9f7 3697 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3698 {
<> 144:ef7eb2e8f9f7 3699 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3700 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 3701
<> 144:ef7eb2e8f9f7 3702 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3703 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3704
<> 144:ef7eb2e8f9f7 3705 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3706 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3707 }
<> 144:ef7eb2e8f9f7 3708 break;
<> 144:ef7eb2e8f9f7 3709 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3710 {
<> 144:ef7eb2e8f9f7 3711 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 3712 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
<> 144:ef7eb2e8f9f7 3713
<> 144:ef7eb2e8f9f7 3714 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 3715 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
<> 144:ef7eb2e8f9f7 3716
<> 144:ef7eb2e8f9f7 3717 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 3718 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
<> 144:ef7eb2e8f9f7 3719 }
<> 144:ef7eb2e8f9f7 3720 break;
<> 144:ef7eb2e8f9f7 3721 default:
<> 144:ef7eb2e8f9f7 3722 break;
<> 144:ef7eb2e8f9f7 3723 }
<> 144:ef7eb2e8f9f7 3724
<> 144:ef7eb2e8f9f7 3725 /* configure the DMA Burst Mode */
<> 144:ef7eb2e8f9f7 3726 htim->Instance->DCR = BurstBaseAddress | BurstLength;
<> 144:ef7eb2e8f9f7 3727
<> 144:ef7eb2e8f9f7 3728 /* Enable the TIM DMA Request */
<> 144:ef7eb2e8f9f7 3729 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3730
<> 144:ef7eb2e8f9f7 3731 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3732
<> 144:ef7eb2e8f9f7 3733 /* Return function status */
<> 144:ef7eb2e8f9f7 3734 return HAL_OK;
<> 144:ef7eb2e8f9f7 3735 }
<> 144:ef7eb2e8f9f7 3736
<> 144:ef7eb2e8f9f7 3737 /**
<> 144:ef7eb2e8f9f7 3738 * @brief Stop the DMA burst reading
<> 144:ef7eb2e8f9f7 3739 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3740 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3741 * @param BurstRequestSrc: TIM DMA Request sources to disable.
<> 144:ef7eb2e8f9f7 3742 * @retval HAL status
<> 144:ef7eb2e8f9f7 3743 */
<> 144:ef7eb2e8f9f7 3744 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3745 {
<> 144:ef7eb2e8f9f7 3746 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3747 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
<> 144:ef7eb2e8f9f7 3748
<> 144:ef7eb2e8f9f7 3749 /* Abort the DMA transfer (at least disable the DMA channel) */
<> 144:ef7eb2e8f9f7 3750 switch(BurstRequestSrc)
<> 144:ef7eb2e8f9f7 3751 {
<> 144:ef7eb2e8f9f7 3752 case TIM_DMA_UPDATE:
<> 144:ef7eb2e8f9f7 3753 {
<> 144:ef7eb2e8f9f7 3754 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
<> 144:ef7eb2e8f9f7 3755 }
<> 144:ef7eb2e8f9f7 3756 break;
<> 144:ef7eb2e8f9f7 3757 case TIM_DMA_CC1:
<> 144:ef7eb2e8f9f7 3758 {
<> 144:ef7eb2e8f9f7 3759 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
<> 144:ef7eb2e8f9f7 3760 }
<> 144:ef7eb2e8f9f7 3761 break;
<> 144:ef7eb2e8f9f7 3762 case TIM_DMA_CC2:
<> 144:ef7eb2e8f9f7 3763 {
<> 144:ef7eb2e8f9f7 3764 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
<> 144:ef7eb2e8f9f7 3765 }
<> 144:ef7eb2e8f9f7 3766 break;
<> 144:ef7eb2e8f9f7 3767 case TIM_DMA_CC3:
<> 144:ef7eb2e8f9f7 3768 {
<> 144:ef7eb2e8f9f7 3769 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
<> 144:ef7eb2e8f9f7 3770 }
<> 144:ef7eb2e8f9f7 3771 break;
<> 144:ef7eb2e8f9f7 3772 case TIM_DMA_CC4:
<> 144:ef7eb2e8f9f7 3773 {
<> 144:ef7eb2e8f9f7 3774 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
<> 144:ef7eb2e8f9f7 3775 }
<> 144:ef7eb2e8f9f7 3776 break;
<> 144:ef7eb2e8f9f7 3777 case TIM_DMA_COM:
<> 144:ef7eb2e8f9f7 3778 {
<> 144:ef7eb2e8f9f7 3779 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
<> 144:ef7eb2e8f9f7 3780 }
<> 144:ef7eb2e8f9f7 3781 break;
<> 144:ef7eb2e8f9f7 3782 case TIM_DMA_TRIGGER:
<> 144:ef7eb2e8f9f7 3783 {
<> 144:ef7eb2e8f9f7 3784 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
<> 144:ef7eb2e8f9f7 3785 }
<> 144:ef7eb2e8f9f7 3786 break;
<> 144:ef7eb2e8f9f7 3787 default:
<> 144:ef7eb2e8f9f7 3788 break;
<> 144:ef7eb2e8f9f7 3789 }
<> 144:ef7eb2e8f9f7 3790
<> 144:ef7eb2e8f9f7 3791 /* Disable the TIM Update DMA request */
<> 144:ef7eb2e8f9f7 3792 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
<> 144:ef7eb2e8f9f7 3793
<> 144:ef7eb2e8f9f7 3794 /* Return function status */
<> 144:ef7eb2e8f9f7 3795 return HAL_OK;
<> 144:ef7eb2e8f9f7 3796 }
<> 144:ef7eb2e8f9f7 3797
<> 144:ef7eb2e8f9f7 3798 /**
<> 144:ef7eb2e8f9f7 3799 * @brief Generate a software event
<> 144:ef7eb2e8f9f7 3800 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3801 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3802 * @param EventSource: specifies the event source.
<> 144:ef7eb2e8f9f7 3803 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3804 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
<> 144:ef7eb2e8f9f7 3805 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
<> 144:ef7eb2e8f9f7 3806 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
<> 144:ef7eb2e8f9f7 3807 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
<> 144:ef7eb2e8f9f7 3808 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
<> 144:ef7eb2e8f9f7 3809 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
<> 144:ef7eb2e8f9f7 3810 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
<> 144:ef7eb2e8f9f7 3811 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
<> 144:ef7eb2e8f9f7 3812 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
<> 144:ef7eb2e8f9f7 3813 * @note TIM6 and TIM7 can only generate an update event.
<> 144:ef7eb2e8f9f7 3814 * @note TIM_EVENTSOURCE_COM, TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are used only with TIM1 and TIM8.
<> 144:ef7eb2e8f9f7 3815 * @retval HAL status
<> 144:ef7eb2e8f9f7 3816 */
<> 144:ef7eb2e8f9f7 3817
<> 144:ef7eb2e8f9f7 3818 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
<> 144:ef7eb2e8f9f7 3819 {
<> 144:ef7eb2e8f9f7 3820 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3821 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3822 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
<> 144:ef7eb2e8f9f7 3823
<> 144:ef7eb2e8f9f7 3824 /* Process Locked */
<> 144:ef7eb2e8f9f7 3825 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3826
<> 144:ef7eb2e8f9f7 3827 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3828 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3829
<> 144:ef7eb2e8f9f7 3830 /* Set the event sources */
<> 144:ef7eb2e8f9f7 3831 htim->Instance->EGR = EventSource;
<> 144:ef7eb2e8f9f7 3832
<> 144:ef7eb2e8f9f7 3833 /* Change the TIM state */
<> 144:ef7eb2e8f9f7 3834 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3835
<> 144:ef7eb2e8f9f7 3836 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3837
<> 144:ef7eb2e8f9f7 3838 /* Return function status */
<> 144:ef7eb2e8f9f7 3839 return HAL_OK;
<> 144:ef7eb2e8f9f7 3840 }
<> 144:ef7eb2e8f9f7 3841
<> 144:ef7eb2e8f9f7 3842 /**
<> 144:ef7eb2e8f9f7 3843 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 3844 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3845 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3846 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3847 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3848 * @param Channel: specifies the TIM Channel.
<> 144:ef7eb2e8f9f7 3849 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 3850 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 3851 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 3852 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 3853 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 3854 * @retval HAL status
<> 144:ef7eb2e8f9f7 3855 */
<> 144:ef7eb2e8f9f7 3856 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 3857 {
<> 144:ef7eb2e8f9f7 3858 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3859 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3860 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 3861 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 3862
<> 144:ef7eb2e8f9f7 3863 /* Process Locked */
<> 144:ef7eb2e8f9f7 3864 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3865
<> 144:ef7eb2e8f9f7 3866 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3867
<> 144:ef7eb2e8f9f7 3868 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
<> 144:ef7eb2e8f9f7 3869 {
<> 144:ef7eb2e8f9f7 3870 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 3871 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 3872 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 3873
<> 144:ef7eb2e8f9f7 3874 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3875 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 3876 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 3877 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 3878 }
<> 144:ef7eb2e8f9f7 3879
<> 144:ef7eb2e8f9f7 3880 switch (Channel)
<> 144:ef7eb2e8f9f7 3881 {
<> 144:ef7eb2e8f9f7 3882 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 3883 {
<> 144:ef7eb2e8f9f7 3884 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3885 {
<> 144:ef7eb2e8f9f7 3886 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3887 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3888 }
<> 144:ef7eb2e8f9f7 3889 else
<> 144:ef7eb2e8f9f7 3890 {
<> 144:ef7eb2e8f9f7 3891 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 3892 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 3893 }
<> 144:ef7eb2e8f9f7 3894 }
<> 144:ef7eb2e8f9f7 3895 break;
<> 144:ef7eb2e8f9f7 3896 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 3897 {
<> 144:ef7eb2e8f9f7 3898 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3899 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3900 {
<> 144:ef7eb2e8f9f7 3901 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3902 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3903 }
<> 144:ef7eb2e8f9f7 3904 else
<> 144:ef7eb2e8f9f7 3905 {
<> 144:ef7eb2e8f9f7 3906 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 3907 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 3908 }
<> 144:ef7eb2e8f9f7 3909 }
<> 144:ef7eb2e8f9f7 3910 break;
<> 144:ef7eb2e8f9f7 3911 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 3912 {
<> 144:ef7eb2e8f9f7 3913 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3914 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3915 {
<> 144:ef7eb2e8f9f7 3916 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3917 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3918 }
<> 144:ef7eb2e8f9f7 3919 else
<> 144:ef7eb2e8f9f7 3920 {
<> 144:ef7eb2e8f9f7 3921 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 3922 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 3923 }
<> 144:ef7eb2e8f9f7 3924 }
<> 144:ef7eb2e8f9f7 3925 break;
<> 144:ef7eb2e8f9f7 3926 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 3927 {
<> 144:ef7eb2e8f9f7 3928 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3929 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 3930 {
<> 144:ef7eb2e8f9f7 3931 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3932 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3933 }
<> 144:ef7eb2e8f9f7 3934 else
<> 144:ef7eb2e8f9f7 3935 {
<> 144:ef7eb2e8f9f7 3936 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 3937 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 3938 }
<> 144:ef7eb2e8f9f7 3939 }
<> 144:ef7eb2e8f9f7 3940 break;
<> 144:ef7eb2e8f9f7 3941 default:
<> 144:ef7eb2e8f9f7 3942 break;
<> 144:ef7eb2e8f9f7 3943 }
<> 144:ef7eb2e8f9f7 3944
<> 144:ef7eb2e8f9f7 3945 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 3946
<> 144:ef7eb2e8f9f7 3947 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 3948
<> 144:ef7eb2e8f9f7 3949 return HAL_OK;
<> 144:ef7eb2e8f9f7 3950 }
<> 144:ef7eb2e8f9f7 3951
<> 144:ef7eb2e8f9f7 3952 /**
<> 144:ef7eb2e8f9f7 3953 * @brief Configures the clock source to be used
<> 144:ef7eb2e8f9f7 3954 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 3955 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 3956 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 3957 * contains the clock source information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 3958 * @retval HAL status
<> 144:ef7eb2e8f9f7 3959 */
<> 144:ef7eb2e8f9f7 3960 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
<> 144:ef7eb2e8f9f7 3961 {
<> 144:ef7eb2e8f9f7 3962 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 3963
<> 144:ef7eb2e8f9f7 3964 /* Process Locked */
<> 144:ef7eb2e8f9f7 3965 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 3966
<> 144:ef7eb2e8f9f7 3967 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 3968
<> 144:ef7eb2e8f9f7 3969 /* Check the parameters */
<> 144:ef7eb2e8f9f7 3970 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
<> 144:ef7eb2e8f9f7 3971
<> 144:ef7eb2e8f9f7 3972 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
<> 144:ef7eb2e8f9f7 3973 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 3974 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 3975 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 3976 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 3977
<> 144:ef7eb2e8f9f7 3978 switch (sClockSourceConfig->ClockSource)
<> 144:ef7eb2e8f9f7 3979 {
<> 144:ef7eb2e8f9f7 3980 case TIM_CLOCKSOURCE_INTERNAL:
<> 144:ef7eb2e8f9f7 3981 {
<> 144:ef7eb2e8f9f7 3982 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3983 /* Disable slave mode to clock the prescaler directly with the internal clock */
<> 144:ef7eb2e8f9f7 3984 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 3985 }
<> 144:ef7eb2e8f9f7 3986 break;
<> 144:ef7eb2e8f9f7 3987
<> 144:ef7eb2e8f9f7 3988 case TIM_CLOCKSOURCE_ETRMODE1:
<> 144:ef7eb2e8f9f7 3989 {
<> 144:ef7eb2e8f9f7 3990 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 3991 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 3992 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 3993 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 3994 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 3995 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 3996 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 3997 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 3998 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 3999 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4000 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4001 /* Reset the SMS and TS Bits */
<> 144:ef7eb2e8f9f7 4002 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
<> 144:ef7eb2e8f9f7 4003 /* Select the External clock mode1 and the ETRF trigger */
<> 144:ef7eb2e8f9f7 4004 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
<> 144:ef7eb2e8f9f7 4005 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4006 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4007 }
<> 144:ef7eb2e8f9f7 4008 break;
<> 144:ef7eb2e8f9f7 4009
<> 144:ef7eb2e8f9f7 4010 case TIM_CLOCKSOURCE_ETRMODE2:
<> 144:ef7eb2e8f9f7 4011 {
<> 144:ef7eb2e8f9f7 4012 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4013 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4014 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
<> 144:ef7eb2e8f9f7 4015 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4016
<> 144:ef7eb2e8f9f7 4017 /* Configure the ETR Clock source */
<> 144:ef7eb2e8f9f7 4018 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4019 sClockSourceConfig->ClockPrescaler,
<> 144:ef7eb2e8f9f7 4020 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4021 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4022 /* Enable the External clock mode2 */
<> 144:ef7eb2e8f9f7 4023 htim->Instance->SMCR |= TIM_SMCR_ECE;
<> 144:ef7eb2e8f9f7 4024 }
<> 144:ef7eb2e8f9f7 4025 break;
<> 144:ef7eb2e8f9f7 4026
<> 144:ef7eb2e8f9f7 4027 case TIM_CLOCKSOURCE_TI1:
<> 144:ef7eb2e8f9f7 4028 {
<> 144:ef7eb2e8f9f7 4029 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4030
<> 144:ef7eb2e8f9f7 4031 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4032 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4033 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4034
<> 144:ef7eb2e8f9f7 4035 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4036 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4037 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4038 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
<> 144:ef7eb2e8f9f7 4039 }
<> 144:ef7eb2e8f9f7 4040 break;
<> 144:ef7eb2e8f9f7 4041 case TIM_CLOCKSOURCE_TI2:
<> 144:ef7eb2e8f9f7 4042 {
<> 144:ef7eb2e8f9f7 4043 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4044
<> 144:ef7eb2e8f9f7 4045 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4046 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4047 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4048
<> 144:ef7eb2e8f9f7 4049 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4050 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4051 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4052 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
<> 144:ef7eb2e8f9f7 4053 }
<> 144:ef7eb2e8f9f7 4054 break;
<> 144:ef7eb2e8f9f7 4055 case TIM_CLOCKSOURCE_TI1ED:
<> 144:ef7eb2e8f9f7 4056 {
<> 144:ef7eb2e8f9f7 4057 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4058 /* Check TI1 input conditioning related parameters */
<> 144:ef7eb2e8f9f7 4059 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
<> 144:ef7eb2e8f9f7 4060 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
<> 144:ef7eb2e8f9f7 4061
<> 144:ef7eb2e8f9f7 4062 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4063 sClockSourceConfig->ClockPolarity,
<> 144:ef7eb2e8f9f7 4064 sClockSourceConfig->ClockFilter);
<> 144:ef7eb2e8f9f7 4065 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
<> 144:ef7eb2e8f9f7 4066 }
<> 144:ef7eb2e8f9f7 4067 break;
<> 144:ef7eb2e8f9f7 4068 case TIM_CLOCKSOURCE_ITR0:
<> 144:ef7eb2e8f9f7 4069 {
<> 144:ef7eb2e8f9f7 4070 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4071 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
<> 144:ef7eb2e8f9f7 4072 }
<> 144:ef7eb2e8f9f7 4073 break;
<> 144:ef7eb2e8f9f7 4074 case TIM_CLOCKSOURCE_ITR1:
<> 144:ef7eb2e8f9f7 4075 {
<> 144:ef7eb2e8f9f7 4076 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4077 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
<> 144:ef7eb2e8f9f7 4078 }
<> 144:ef7eb2e8f9f7 4079 break;
<> 144:ef7eb2e8f9f7 4080 case TIM_CLOCKSOURCE_ITR2:
<> 144:ef7eb2e8f9f7 4081 {
<> 144:ef7eb2e8f9f7 4082 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4083 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
<> 144:ef7eb2e8f9f7 4084 }
<> 144:ef7eb2e8f9f7 4085 break;
<> 144:ef7eb2e8f9f7 4086 case TIM_CLOCKSOURCE_ITR3:
<> 144:ef7eb2e8f9f7 4087 {
<> 144:ef7eb2e8f9f7 4088 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4089 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
<> 144:ef7eb2e8f9f7 4090 }
<> 144:ef7eb2e8f9f7 4091 break;
<> 144:ef7eb2e8f9f7 4092
<> 144:ef7eb2e8f9f7 4093 default:
<> 144:ef7eb2e8f9f7 4094 break;
<> 144:ef7eb2e8f9f7 4095 }
<> 144:ef7eb2e8f9f7 4096 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4097
<> 144:ef7eb2e8f9f7 4098 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4099
<> 144:ef7eb2e8f9f7 4100 return HAL_OK;
<> 144:ef7eb2e8f9f7 4101 }
<> 144:ef7eb2e8f9f7 4102
<> 144:ef7eb2e8f9f7 4103 /**
<> 144:ef7eb2e8f9f7 4104 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
<> 144:ef7eb2e8f9f7 4105 * or a XOR combination between CH1_input, CH2_input & CH3_input
<> 144:ef7eb2e8f9f7 4106 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4107 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4108 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
<> 144:ef7eb2e8f9f7 4109 * output of a XOR gate.
<> 144:ef7eb2e8f9f7 4110 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4111 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
<> 144:ef7eb2e8f9f7 4112 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
<> 144:ef7eb2e8f9f7 4113 * pins are connected to the TI1 input (XOR combination)
<> 144:ef7eb2e8f9f7 4114 * @retval HAL status
<> 144:ef7eb2e8f9f7 4115 */
<> 144:ef7eb2e8f9f7 4116 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
<> 144:ef7eb2e8f9f7 4117 {
<> 144:ef7eb2e8f9f7 4118 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4119
<> 144:ef7eb2e8f9f7 4120 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4121 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4122 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
<> 144:ef7eb2e8f9f7 4123
<> 144:ef7eb2e8f9f7 4124 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4125 tmpcr2 = htim->Instance->CR2;
<> 144:ef7eb2e8f9f7 4126
<> 144:ef7eb2e8f9f7 4127 /* Reset the TI1 selection */
<> 144:ef7eb2e8f9f7 4128 tmpcr2 &= ~TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 4129
<> 144:ef7eb2e8f9f7 4130 /* Set the TI1 selection */
<> 144:ef7eb2e8f9f7 4131 tmpcr2 |= TI1_Selection;
<> 144:ef7eb2e8f9f7 4132
<> 144:ef7eb2e8f9f7 4133 /* Write to TIMxCR2 */
<> 144:ef7eb2e8f9f7 4134 htim->Instance->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4135
<> 144:ef7eb2e8f9f7 4136 return HAL_OK;
<> 144:ef7eb2e8f9f7 4137 }
<> 144:ef7eb2e8f9f7 4138
<> 144:ef7eb2e8f9f7 4139 /**
<> 144:ef7eb2e8f9f7 4140 * @brief Configures the TIM in Slave mode
<> 144:ef7eb2e8f9f7 4141 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4142 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4143 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4144 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4145 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4146 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4147 * @retval HAL status
<> 144:ef7eb2e8f9f7 4148 */
<> 144:ef7eb2e8f9f7 4149 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4150 {
<> 144:ef7eb2e8f9f7 4151 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 4152 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 4153 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4154
<> 144:ef7eb2e8f9f7 4155 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4156 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4157 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4158 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4159
<> 144:ef7eb2e8f9f7 4160 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4161
<> 144:ef7eb2e8f9f7 4162 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4163
<> 144:ef7eb2e8f9f7 4164 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 4165 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 4166
<> 144:ef7eb2e8f9f7 4167 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 4168 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 4169 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 4170 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 4171
<> 144:ef7eb2e8f9f7 4172 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 4173 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 4174 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 4175 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 4176
<> 144:ef7eb2e8f9f7 4177 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 4178 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 4179
<> 144:ef7eb2e8f9f7 4180 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 4181 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 4182 {
<> 144:ef7eb2e8f9f7 4183 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 4184 {
<> 144:ef7eb2e8f9f7 4185 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4186 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4187 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 4188 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4189 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4190 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 4191 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 4192 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 4193 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4194 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4195 }
<> 144:ef7eb2e8f9f7 4196 break;
<> 144:ef7eb2e8f9f7 4197
<> 144:ef7eb2e8f9f7 4198 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 4199 {
<> 144:ef7eb2e8f9f7 4200 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4201 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4202 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4203
<> 144:ef7eb2e8f9f7 4204 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4205 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 4206 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4207 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 4208
<> 144:ef7eb2e8f9f7 4209 /* Set the filter */
<> 144:ef7eb2e8f9f7 4210 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 4211 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
<> 144:ef7eb2e8f9f7 4212
<> 144:ef7eb2e8f9f7 4213 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 4214 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 4215 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4216
<> 144:ef7eb2e8f9f7 4217 }
<> 144:ef7eb2e8f9f7 4218 break;
<> 144:ef7eb2e8f9f7 4219
<> 144:ef7eb2e8f9f7 4220 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 4221 {
<> 144:ef7eb2e8f9f7 4222 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4223 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4224 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4225 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4226
<> 144:ef7eb2e8f9f7 4227 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4228 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4229 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4230 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4231 }
<> 144:ef7eb2e8f9f7 4232 break;
<> 144:ef7eb2e8f9f7 4233
<> 144:ef7eb2e8f9f7 4234 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 4235 {
<> 144:ef7eb2e8f9f7 4236 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4237 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4238 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 4239 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 4240
<> 144:ef7eb2e8f9f7 4241 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 4242 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 4243 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 4244 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 4245 }
<> 144:ef7eb2e8f9f7 4246 break;
<> 144:ef7eb2e8f9f7 4247
<> 144:ef7eb2e8f9f7 4248 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 4249 {
<> 144:ef7eb2e8f9f7 4250 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4251 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4252 }
<> 144:ef7eb2e8f9f7 4253 break;
<> 144:ef7eb2e8f9f7 4254
<> 144:ef7eb2e8f9f7 4255 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 4256 {
<> 144:ef7eb2e8f9f7 4257 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4258 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4259 }
<> 144:ef7eb2e8f9f7 4260 break;
<> 144:ef7eb2e8f9f7 4261
<> 144:ef7eb2e8f9f7 4262 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 4263 {
<> 144:ef7eb2e8f9f7 4264 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4265 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4266 }
<> 144:ef7eb2e8f9f7 4267 break;
<> 144:ef7eb2e8f9f7 4268
<> 144:ef7eb2e8f9f7 4269 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 4270 {
<> 144:ef7eb2e8f9f7 4271 /* Check the parameter */
<> 144:ef7eb2e8f9f7 4272 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4273 }
<> 144:ef7eb2e8f9f7 4274 break;
<> 144:ef7eb2e8f9f7 4275
<> 144:ef7eb2e8f9f7 4276 default:
<> 144:ef7eb2e8f9f7 4277 break;
<> 144:ef7eb2e8f9f7 4278 }
<> 144:ef7eb2e8f9f7 4279
<> 144:ef7eb2e8f9f7 4280 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4281
<> 144:ef7eb2e8f9f7 4282 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4283
<> 144:ef7eb2e8f9f7 4284 return HAL_OK;
<> 144:ef7eb2e8f9f7 4285 }
<> 144:ef7eb2e8f9f7 4286
<> 144:ef7eb2e8f9f7 4287 /**
<> 144:ef7eb2e8f9f7 4288 * @brief Configures the TIM in Slave mode in interrupt mode
<> 144:ef7eb2e8f9f7 4289 * @param htim: TIM handle.
<> 144:ef7eb2e8f9f7 4290 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 4291 * contains the selected trigger (internal trigger input, filtered
<> 144:ef7eb2e8f9f7 4292 * timer input or external trigger input) and the ) and the Slave
<> 144:ef7eb2e8f9f7 4293 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
<> 144:ef7eb2e8f9f7 4294 * @retval HAL status
<> 144:ef7eb2e8f9f7 4295 */
<> 144:ef7eb2e8f9f7 4296 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 4297 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 4298 {
<> 144:ef7eb2e8f9f7 4299 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4300 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4301 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
<> 144:ef7eb2e8f9f7 4302 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
<> 144:ef7eb2e8f9f7 4303
<> 144:ef7eb2e8f9f7 4304 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4305
<> 144:ef7eb2e8f9f7 4306 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 4307
<> 144:ef7eb2e8f9f7 4308 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
<> 144:ef7eb2e8f9f7 4309
<> 144:ef7eb2e8f9f7 4310 /* Enable Trigger Interrupt */
<> 144:ef7eb2e8f9f7 4311 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 /* Disable Trigger DMA request */
<> 144:ef7eb2e8f9f7 4314 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
<> 144:ef7eb2e8f9f7 4315
<> 144:ef7eb2e8f9f7 4316 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4317
<> 144:ef7eb2e8f9f7 4318 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4319
<> 144:ef7eb2e8f9f7 4320 return HAL_OK;
<> 144:ef7eb2e8f9f7 4321 }
<> 144:ef7eb2e8f9f7 4322
<> 144:ef7eb2e8f9f7 4323 /**
<> 144:ef7eb2e8f9f7 4324 * @brief Read the captured value from Capture Compare unit
<> 144:ef7eb2e8f9f7 4325 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4326 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4327 * @param Channel: TIM Channels to be enabled.
<> 144:ef7eb2e8f9f7 4328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 4329 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 4330 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 4331 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 4332 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 4333 * @retval Captured value
<> 144:ef7eb2e8f9f7 4334 */
<> 144:ef7eb2e8f9f7 4335 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 4336 {
<> 144:ef7eb2e8f9f7 4337 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 4338
<> 144:ef7eb2e8f9f7 4339 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 4340
<> 144:ef7eb2e8f9f7 4341 switch (Channel)
<> 144:ef7eb2e8f9f7 4342 {
<> 144:ef7eb2e8f9f7 4343 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 4344 {
<> 144:ef7eb2e8f9f7 4345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4346 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4347
<> 144:ef7eb2e8f9f7 4348 /* Return the capture 1 value */
<> 144:ef7eb2e8f9f7 4349 tmpreg = htim->Instance->CCR1;
<> 144:ef7eb2e8f9f7 4350
<> 144:ef7eb2e8f9f7 4351 break;
<> 144:ef7eb2e8f9f7 4352 }
<> 144:ef7eb2e8f9f7 4353 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 4354 {
<> 144:ef7eb2e8f9f7 4355 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4356 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4357
<> 144:ef7eb2e8f9f7 4358 /* Return the capture 2 value */
<> 144:ef7eb2e8f9f7 4359 tmpreg = htim->Instance->CCR2;
<> 144:ef7eb2e8f9f7 4360
<> 144:ef7eb2e8f9f7 4361 break;
<> 144:ef7eb2e8f9f7 4362 }
<> 144:ef7eb2e8f9f7 4363
<> 144:ef7eb2e8f9f7 4364 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 4365 {
<> 144:ef7eb2e8f9f7 4366 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4367 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4368
<> 144:ef7eb2e8f9f7 4369 /* Return the capture 3 value */
<> 144:ef7eb2e8f9f7 4370 tmpreg = htim->Instance->CCR3;
<> 144:ef7eb2e8f9f7 4371
<> 144:ef7eb2e8f9f7 4372 break;
<> 144:ef7eb2e8f9f7 4373 }
<> 144:ef7eb2e8f9f7 4374
<> 144:ef7eb2e8f9f7 4375 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 4376 {
<> 144:ef7eb2e8f9f7 4377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 4378 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 4379
<> 144:ef7eb2e8f9f7 4380 /* Return the capture 4 value */
<> 144:ef7eb2e8f9f7 4381 tmpreg = htim->Instance->CCR4;
<> 144:ef7eb2e8f9f7 4382
<> 144:ef7eb2e8f9f7 4383 break;
<> 144:ef7eb2e8f9f7 4384 }
<> 144:ef7eb2e8f9f7 4385
<> 144:ef7eb2e8f9f7 4386 default:
<> 144:ef7eb2e8f9f7 4387 break;
<> 144:ef7eb2e8f9f7 4388 }
<> 144:ef7eb2e8f9f7 4389
<> 144:ef7eb2e8f9f7 4390 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 4391 return tmpreg;
<> 144:ef7eb2e8f9f7 4392 }
<> 144:ef7eb2e8f9f7 4393
<> 144:ef7eb2e8f9f7 4394 /**
<> 144:ef7eb2e8f9f7 4395 * @}
<> 144:ef7eb2e8f9f7 4396 */
<> 144:ef7eb2e8f9f7 4397
<> 144:ef7eb2e8f9f7 4398 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4399 * @brief TIM Callbacks functions
<> 144:ef7eb2e8f9f7 4400 *
<> 144:ef7eb2e8f9f7 4401 @verbatim
<> 144:ef7eb2e8f9f7 4402 ==============================================================================
<> 144:ef7eb2e8f9f7 4403 ##### TIM Callbacks functions #####
<> 144:ef7eb2e8f9f7 4404 ==============================================================================
<> 144:ef7eb2e8f9f7 4405 [..]
<> 144:ef7eb2e8f9f7 4406 This section provides TIM callback functions:
<> 144:ef7eb2e8f9f7 4407 (+) Timer Period elapsed callback
<> 144:ef7eb2e8f9f7 4408 (+) Timer Output Compare callback
<> 144:ef7eb2e8f9f7 4409 (+) Timer Input capture callback
<> 144:ef7eb2e8f9f7 4410 (+) Timer Trigger callback
<> 144:ef7eb2e8f9f7 4411 (+) Timer Error callback
<> 144:ef7eb2e8f9f7 4412
<> 144:ef7eb2e8f9f7 4413 @endverbatim
<> 144:ef7eb2e8f9f7 4414 * @{
<> 144:ef7eb2e8f9f7 4415 */
<> 144:ef7eb2e8f9f7 4416
<> 144:ef7eb2e8f9f7 4417 /**
<> 144:ef7eb2e8f9f7 4418 * @brief Period elapsed callback in non blocking mode
<> 144:ef7eb2e8f9f7 4419 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4420 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4421 * @retval None
<> 144:ef7eb2e8f9f7 4422 */
<> 144:ef7eb2e8f9f7 4423 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4424 {
<> 144:ef7eb2e8f9f7 4425 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4426 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4427
<> 144:ef7eb2e8f9f7 4428 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4429 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4430 */
<> 144:ef7eb2e8f9f7 4431
<> 144:ef7eb2e8f9f7 4432 }
<> 144:ef7eb2e8f9f7 4433 /**
<> 144:ef7eb2e8f9f7 4434 * @brief Output Compare callback in non blocking mode
<> 144:ef7eb2e8f9f7 4435 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4436 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4437 * @retval None
<> 144:ef7eb2e8f9f7 4438 */
<> 144:ef7eb2e8f9f7 4439 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4440 {
<> 144:ef7eb2e8f9f7 4441 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4442 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4443
<> 144:ef7eb2e8f9f7 4444 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4445 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4446 */
<> 144:ef7eb2e8f9f7 4447 }
<> 144:ef7eb2e8f9f7 4448 /**
<> 144:ef7eb2e8f9f7 4449 * @brief Input Capture callback in non blocking mode
<> 144:ef7eb2e8f9f7 4450 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4451 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4452 * @retval None
<> 144:ef7eb2e8f9f7 4453 */
<> 144:ef7eb2e8f9f7 4454 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4455 {
<> 144:ef7eb2e8f9f7 4456 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4457 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4458
<> 144:ef7eb2e8f9f7 4459 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4460 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4461 */
<> 144:ef7eb2e8f9f7 4462 }
<> 144:ef7eb2e8f9f7 4463
<> 144:ef7eb2e8f9f7 4464 /**
<> 144:ef7eb2e8f9f7 4465 * @brief PWM Pulse finished callback in non blocking mode
<> 144:ef7eb2e8f9f7 4466 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4467 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4468 * @retval None
<> 144:ef7eb2e8f9f7 4469 */
<> 144:ef7eb2e8f9f7 4470 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4471 {
<> 144:ef7eb2e8f9f7 4472 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4473 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4474
<> 144:ef7eb2e8f9f7 4475 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4476 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4477 */
<> 144:ef7eb2e8f9f7 4478 }
<> 144:ef7eb2e8f9f7 4479
<> 144:ef7eb2e8f9f7 4480 /**
<> 144:ef7eb2e8f9f7 4481 * @brief Hall Trigger detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 4482 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4483 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4484 * @retval None
<> 144:ef7eb2e8f9f7 4485 */
<> 144:ef7eb2e8f9f7 4486 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4487 {
<> 144:ef7eb2e8f9f7 4488 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4489 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4490
<> 144:ef7eb2e8f9f7 4491 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4492 the HAL_TIM_TriggerCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4493 */
<> 144:ef7eb2e8f9f7 4494 }
<> 144:ef7eb2e8f9f7 4495
<> 144:ef7eb2e8f9f7 4496 /**
<> 144:ef7eb2e8f9f7 4497 * @brief Timer error callback in non blocking mode
<> 144:ef7eb2e8f9f7 4498 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4499 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4500 * @retval None
<> 144:ef7eb2e8f9f7 4501 */
<> 144:ef7eb2e8f9f7 4502 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4503 {
<> 144:ef7eb2e8f9f7 4504 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 4505 UNUSED(htim);
<> 144:ef7eb2e8f9f7 4506
<> 144:ef7eb2e8f9f7 4507 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 4508 the HAL_TIM_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 4509 */
<> 144:ef7eb2e8f9f7 4510 }
<> 144:ef7eb2e8f9f7 4511
<> 144:ef7eb2e8f9f7 4512 /**
<> 144:ef7eb2e8f9f7 4513 * @}
<> 144:ef7eb2e8f9f7 4514 */
<> 144:ef7eb2e8f9f7 4515
<> 144:ef7eb2e8f9f7 4516 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<> 144:ef7eb2e8f9f7 4517 * @brief Peripheral State functions
<> 144:ef7eb2e8f9f7 4518 *
<> 144:ef7eb2e8f9f7 4519 @verbatim
<> 144:ef7eb2e8f9f7 4520 ==============================================================================
<> 144:ef7eb2e8f9f7 4521 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 4522 ==============================================================================
<> 144:ef7eb2e8f9f7 4523 [..]
<> 144:ef7eb2e8f9f7 4524 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 4525 and the data flow.
<> 144:ef7eb2e8f9f7 4526
<> 144:ef7eb2e8f9f7 4527 @endverbatim
<> 144:ef7eb2e8f9f7 4528 * @{
<> 144:ef7eb2e8f9f7 4529 */
<> 144:ef7eb2e8f9f7 4530
<> 144:ef7eb2e8f9f7 4531 /**
<> 144:ef7eb2e8f9f7 4532 * @brief Return the TIM Base state
<> 144:ef7eb2e8f9f7 4533 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4534 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4535 * @retval HAL state
<> 144:ef7eb2e8f9f7 4536 */
<> 144:ef7eb2e8f9f7 4537 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4538 {
<> 144:ef7eb2e8f9f7 4539 return htim->State;
<> 144:ef7eb2e8f9f7 4540 }
<> 144:ef7eb2e8f9f7 4541
<> 144:ef7eb2e8f9f7 4542 /**
<> 144:ef7eb2e8f9f7 4543 * @brief Return the TIM OC state
<> 144:ef7eb2e8f9f7 4544 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4545 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4546 * @retval HAL state
<> 144:ef7eb2e8f9f7 4547 */
<> 144:ef7eb2e8f9f7 4548 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4549 {
<> 144:ef7eb2e8f9f7 4550 return htim->State;
<> 144:ef7eb2e8f9f7 4551 }
<> 144:ef7eb2e8f9f7 4552
<> 144:ef7eb2e8f9f7 4553 /**
<> 144:ef7eb2e8f9f7 4554 * @brief Return the TIM PWM state
<> 144:ef7eb2e8f9f7 4555 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4556 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4557 * @retval HAL state
<> 144:ef7eb2e8f9f7 4558 */
<> 144:ef7eb2e8f9f7 4559 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4560 {
<> 144:ef7eb2e8f9f7 4561 return htim->State;
<> 144:ef7eb2e8f9f7 4562 }
<> 144:ef7eb2e8f9f7 4563
<> 144:ef7eb2e8f9f7 4564 /**
<> 144:ef7eb2e8f9f7 4565 * @brief Return the TIM Input Capture state
<> 144:ef7eb2e8f9f7 4566 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4567 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4568 * @retval HAL state
<> 144:ef7eb2e8f9f7 4569 */
<> 144:ef7eb2e8f9f7 4570 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4571 {
<> 144:ef7eb2e8f9f7 4572 return htim->State;
<> 144:ef7eb2e8f9f7 4573 }
<> 144:ef7eb2e8f9f7 4574
<> 144:ef7eb2e8f9f7 4575 /**
<> 144:ef7eb2e8f9f7 4576 * @brief Return the TIM One Pulse Mode state
<> 144:ef7eb2e8f9f7 4577 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4578 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4579 * @retval HAL state
<> 144:ef7eb2e8f9f7 4580 */
<> 144:ef7eb2e8f9f7 4581 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4582 {
<> 144:ef7eb2e8f9f7 4583 return htim->State;
<> 144:ef7eb2e8f9f7 4584 }
<> 144:ef7eb2e8f9f7 4585
<> 144:ef7eb2e8f9f7 4586 /**
<> 144:ef7eb2e8f9f7 4587 * @brief Return the TIM Encoder Mode state
<> 144:ef7eb2e8f9f7 4588 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4589 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 4590 * @retval HAL state
<> 144:ef7eb2e8f9f7 4591 */
<> 144:ef7eb2e8f9f7 4592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 4593 {
<> 144:ef7eb2e8f9f7 4594 return htim->State;
<> 144:ef7eb2e8f9f7 4595 }
<> 144:ef7eb2e8f9f7 4596
<> 144:ef7eb2e8f9f7 4597 /**
<> 144:ef7eb2e8f9f7 4598 * @}
<> 144:ef7eb2e8f9f7 4599 */
<> 144:ef7eb2e8f9f7 4600
<> 144:ef7eb2e8f9f7 4601 /**
<> 144:ef7eb2e8f9f7 4602 * @brief TIM DMA error callback
<> 144:ef7eb2e8f9f7 4603 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4604 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4605 * @retval None
<> 144:ef7eb2e8f9f7 4606 */
<> 144:ef7eb2e8f9f7 4607 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4608 {
<> 144:ef7eb2e8f9f7 4609 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4610
<> 144:ef7eb2e8f9f7 4611 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4612
<> 144:ef7eb2e8f9f7 4613 HAL_TIM_ErrorCallback(htim);
<> 144:ef7eb2e8f9f7 4614 }
<> 144:ef7eb2e8f9f7 4615
<> 144:ef7eb2e8f9f7 4616 /**
<> 144:ef7eb2e8f9f7 4617 * @brief TIM DMA Delay Pulse complete callback.
<> 144:ef7eb2e8f9f7 4618 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4619 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4620 * @retval None
<> 144:ef7eb2e8f9f7 4621 */
<> 144:ef7eb2e8f9f7 4622 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4623 {
<> 144:ef7eb2e8f9f7 4624 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4625
<> 144:ef7eb2e8f9f7 4626 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4627
<> 144:ef7eb2e8f9f7 4628 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4629 {
<> 144:ef7eb2e8f9f7 4630 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4631 }
<> 144:ef7eb2e8f9f7 4632 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4633 {
<> 144:ef7eb2e8f9f7 4634 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4635 }
<> 144:ef7eb2e8f9f7 4636 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4637 {
<> 144:ef7eb2e8f9f7 4638 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4639 }
<> 144:ef7eb2e8f9f7 4640 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4641 {
<> 144:ef7eb2e8f9f7 4642 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4643 }
<> 144:ef7eb2e8f9f7 4644
<> 144:ef7eb2e8f9f7 4645 HAL_TIM_PWM_PulseFinishedCallback(htim);
<> 144:ef7eb2e8f9f7 4646
<> 144:ef7eb2e8f9f7 4647 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4648 }
<> 144:ef7eb2e8f9f7 4649 /**
<> 144:ef7eb2e8f9f7 4650 * @brief TIM DMA Capture complete callback.
<> 144:ef7eb2e8f9f7 4651 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4652 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4653 * @retval None
<> 144:ef7eb2e8f9f7 4654 */
<> 144:ef7eb2e8f9f7 4655 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4656 {
<> 144:ef7eb2e8f9f7 4657 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4658
<> 144:ef7eb2e8f9f7 4659 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4660
<> 144:ef7eb2e8f9f7 4661 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
<> 144:ef7eb2e8f9f7 4662 {
<> 144:ef7eb2e8f9f7 4663 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
<> 144:ef7eb2e8f9f7 4664 }
<> 144:ef7eb2e8f9f7 4665 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
<> 144:ef7eb2e8f9f7 4666 {
<> 144:ef7eb2e8f9f7 4667 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
<> 144:ef7eb2e8f9f7 4668 }
<> 144:ef7eb2e8f9f7 4669 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
<> 144:ef7eb2e8f9f7 4670 {
<> 144:ef7eb2e8f9f7 4671 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
<> 144:ef7eb2e8f9f7 4672 }
<> 144:ef7eb2e8f9f7 4673 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
<> 144:ef7eb2e8f9f7 4674 {
<> 144:ef7eb2e8f9f7 4675 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
<> 144:ef7eb2e8f9f7 4676 }
<> 144:ef7eb2e8f9f7 4677
<> 144:ef7eb2e8f9f7 4678 HAL_TIM_IC_CaptureCallback(htim);
<> 144:ef7eb2e8f9f7 4679
<> 144:ef7eb2e8f9f7 4680 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
<> 144:ef7eb2e8f9f7 4681
<> 144:ef7eb2e8f9f7 4682 }
<> 144:ef7eb2e8f9f7 4683
<> 144:ef7eb2e8f9f7 4684 /**
<> 144:ef7eb2e8f9f7 4685 * @brief TIM DMA Period Elapse complete callback.
<> 144:ef7eb2e8f9f7 4686 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4687 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4688 * @retval None
<> 144:ef7eb2e8f9f7 4689 */
<> 144:ef7eb2e8f9f7 4690 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4691 {
<> 144:ef7eb2e8f9f7 4692 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4693
<> 144:ef7eb2e8f9f7 4694 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4695
<> 144:ef7eb2e8f9f7 4696 HAL_TIM_PeriodElapsedCallback(htim);
<> 144:ef7eb2e8f9f7 4697 }
<> 144:ef7eb2e8f9f7 4698
<> 144:ef7eb2e8f9f7 4699 /**
<> 144:ef7eb2e8f9f7 4700 * @brief TIM DMA Trigger callback.
<> 144:ef7eb2e8f9f7 4701 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 4702 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 4703 * @retval None
<> 144:ef7eb2e8f9f7 4704 */
<> 144:ef7eb2e8f9f7 4705 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 4706 {
<> 144:ef7eb2e8f9f7 4707 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 4708
<> 144:ef7eb2e8f9f7 4709 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 4710
<> 144:ef7eb2e8f9f7 4711 HAL_TIM_TriggerCallback(htim);
<> 144:ef7eb2e8f9f7 4712 }
<> 144:ef7eb2e8f9f7 4713
<> 144:ef7eb2e8f9f7 4714 /**
<> 144:ef7eb2e8f9f7 4715 * @brief Time Base configuration
<> 144:ef7eb2e8f9f7 4716 * @param TIMx: TIM peripheral
<> 144:ef7eb2e8f9f7 4717 * @param Structure: pointer on TIM Time Base required parameters
<> 144:ef7eb2e8f9f7 4718 * @retval None
<> 144:ef7eb2e8f9f7 4719 */
<> 144:ef7eb2e8f9f7 4720 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
<> 144:ef7eb2e8f9f7 4721 {
<> 144:ef7eb2e8f9f7 4722 uint32_t tmpcr1 = 0;
<> 144:ef7eb2e8f9f7 4723 tmpcr1 = TIMx->CR1;
<> 144:ef7eb2e8f9f7 4724
<> 144:ef7eb2e8f9f7 4725 /* Set TIM Time Base Unit parameters ---------------------------------------*/
<> 144:ef7eb2e8f9f7 4726 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4727 {
<> 144:ef7eb2e8f9f7 4728 /* Select the Counter Mode */
<> 144:ef7eb2e8f9f7 4729 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
<> 144:ef7eb2e8f9f7 4730 tmpcr1 |= Structure->CounterMode;
<> 144:ef7eb2e8f9f7 4731 }
<> 144:ef7eb2e8f9f7 4732
<> 144:ef7eb2e8f9f7 4733 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4734 {
<> 144:ef7eb2e8f9f7 4735 /* Set the clock division */
<> 144:ef7eb2e8f9f7 4736 tmpcr1 &= ~TIM_CR1_CKD;
<> 144:ef7eb2e8f9f7 4737 tmpcr1 |= (uint32_t)Structure->ClockDivision;
<> 144:ef7eb2e8f9f7 4738 }
<> 144:ef7eb2e8f9f7 4739
<> 144:ef7eb2e8f9f7 4740 TIMx->CR1 = tmpcr1;
<> 144:ef7eb2e8f9f7 4741
<> 144:ef7eb2e8f9f7 4742 /* Set the Auto-reload value */
<> 144:ef7eb2e8f9f7 4743 TIMx->ARR = (uint32_t)Structure->Period ;
<> 144:ef7eb2e8f9f7 4744
<> 144:ef7eb2e8f9f7 4745 /* Set the Prescaler value */
<> 144:ef7eb2e8f9f7 4746 TIMx->PSC = (uint32_t)Structure->Prescaler;
<> 144:ef7eb2e8f9f7 4747
<> 144:ef7eb2e8f9f7 4748 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4749 {
<> 144:ef7eb2e8f9f7 4750 /* Set the Repetition Counter value */
<> 144:ef7eb2e8f9f7 4751 TIMx->RCR = Structure->RepetitionCounter;
<> 144:ef7eb2e8f9f7 4752 }
<> 144:ef7eb2e8f9f7 4753
<> 144:ef7eb2e8f9f7 4754 /* Generate an update event to reload the Prescaler
<> 144:ef7eb2e8f9f7 4755 and the repetition counter(only for TIM1 and TIM8) value immediately */
<> 144:ef7eb2e8f9f7 4756 TIMx->EGR = TIM_EGR_UG;
<> 144:ef7eb2e8f9f7 4757 }
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /**
<> 144:ef7eb2e8f9f7 4760 * @brief Time Output Compare 1 configuration
<> 144:ef7eb2e8f9f7 4761 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4762 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4763 * @retval None
<> 144:ef7eb2e8f9f7 4764 */
<> 144:ef7eb2e8f9f7 4765 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4766 {
<> 144:ef7eb2e8f9f7 4767 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4768 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4769 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4770
<> 144:ef7eb2e8f9f7 4771 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 4772 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 4773
<> 144:ef7eb2e8f9f7 4774 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4775 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4776 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4777 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4778
<> 144:ef7eb2e8f9f7 4779 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4780 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4781
<> 144:ef7eb2e8f9f7 4782 /* Reset the Output Compare Mode Bits */
<> 144:ef7eb2e8f9f7 4783 tmpccmrx &= ~TIM_CCMR1_OC1M;
<> 144:ef7eb2e8f9f7 4784 tmpccmrx &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 4785 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4786 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4787
<> 144:ef7eb2e8f9f7 4788 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4789 tmpccer &= ~TIM_CCER_CC1P;
<> 144:ef7eb2e8f9f7 4790 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4791 tmpccer |= OC_Config->OCPolarity;
<> 144:ef7eb2e8f9f7 4792
<> 144:ef7eb2e8f9f7 4793
<> 144:ef7eb2e8f9f7 4794 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4795 {
<> 144:ef7eb2e8f9f7 4796 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4797 tmpccer &= ~TIM_CCER_CC1NP;
<> 144:ef7eb2e8f9f7 4798 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4799 tmpccer |= OC_Config->OCNPolarity;
<> 144:ef7eb2e8f9f7 4800 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4801 tmpccer &= ~TIM_CCER_CC1NE;
<> 144:ef7eb2e8f9f7 4802
<> 144:ef7eb2e8f9f7 4803 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4804 tmpcr2 &= ~TIM_CR2_OIS1;
<> 144:ef7eb2e8f9f7 4805 tmpcr2 &= ~TIM_CR2_OIS1N;
<> 144:ef7eb2e8f9f7 4806 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4807 tmpcr2 |= OC_Config->OCIdleState;
<> 144:ef7eb2e8f9f7 4808 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4809 tmpcr2 |= OC_Config->OCNIdleState;
<> 144:ef7eb2e8f9f7 4810 }
<> 144:ef7eb2e8f9f7 4811 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4812 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4813
<> 144:ef7eb2e8f9f7 4814 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4815 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4816
<> 144:ef7eb2e8f9f7 4817 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4818 TIMx->CCR1 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4819
<> 144:ef7eb2e8f9f7 4820 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4821 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4822 }
<> 144:ef7eb2e8f9f7 4823
<> 144:ef7eb2e8f9f7 4824 /**
<> 144:ef7eb2e8f9f7 4825 * @brief Time Output Compare 2 configuration
<> 144:ef7eb2e8f9f7 4826 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4827 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4828 * @retval None
<> 144:ef7eb2e8f9f7 4829 */
<> 144:ef7eb2e8f9f7 4830 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4831 {
<> 144:ef7eb2e8f9f7 4832 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4833 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4834 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4835
<> 144:ef7eb2e8f9f7 4836 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4837 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 4838
<> 144:ef7eb2e8f9f7 4839 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4840 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4841 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4842 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4843
<> 144:ef7eb2e8f9f7 4844 /* Get the TIMx CCMR1 register value */
<> 144:ef7eb2e8f9f7 4845 tmpccmrx = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 4846
<> 144:ef7eb2e8f9f7 4847 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4848 tmpccmrx &= ~TIM_CCMR1_OC2M;
<> 144:ef7eb2e8f9f7 4849 tmpccmrx &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 4850
<> 144:ef7eb2e8f9f7 4851 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4852 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 4853
<> 144:ef7eb2e8f9f7 4854 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4855 tmpccer &= ~TIM_CCER_CC2P;
<> 144:ef7eb2e8f9f7 4856 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4857 tmpccer |= (OC_Config->OCPolarity << 4);
<> 144:ef7eb2e8f9f7 4858
<> 144:ef7eb2e8f9f7 4859 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4860 {
<> 144:ef7eb2e8f9f7 4861 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4862
<> 144:ef7eb2e8f9f7 4863 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4864 tmpccer &= ~TIM_CCER_CC2NP;
<> 144:ef7eb2e8f9f7 4865 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4866 tmpccer |= (OC_Config->OCNPolarity << 4);
<> 144:ef7eb2e8f9f7 4867 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4868 tmpccer &= ~TIM_CCER_CC2NE;
<> 144:ef7eb2e8f9f7 4869
<> 144:ef7eb2e8f9f7 4870 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4871 tmpcr2 &= ~TIM_CR2_OIS2;
<> 144:ef7eb2e8f9f7 4872 tmpcr2 &= ~TIM_CR2_OIS2N;
<> 144:ef7eb2e8f9f7 4873 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4874 tmpcr2 |= (OC_Config->OCIdleState << 2);
<> 144:ef7eb2e8f9f7 4875 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4876 tmpcr2 |= (OC_Config->OCNIdleState << 2);
<> 144:ef7eb2e8f9f7 4877 }
<> 144:ef7eb2e8f9f7 4878 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4879 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4880
<> 144:ef7eb2e8f9f7 4881 /* Write to TIMx CCMR1 */
<> 144:ef7eb2e8f9f7 4882 TIMx->CCMR1 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4883
<> 144:ef7eb2e8f9f7 4884 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4885 TIMx->CCR2 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4886
<> 144:ef7eb2e8f9f7 4887 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4888 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4889 }
<> 144:ef7eb2e8f9f7 4890
<> 144:ef7eb2e8f9f7 4891 /**
<> 144:ef7eb2e8f9f7 4892 * @brief Time Output Compare 3 configuration
<> 144:ef7eb2e8f9f7 4893 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4894 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4895 * @retval None
<> 144:ef7eb2e8f9f7 4896 */
<> 144:ef7eb2e8f9f7 4897 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4898 {
<> 144:ef7eb2e8f9f7 4899 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4900 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4901 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4902
<> 144:ef7eb2e8f9f7 4903 /* Disable the Channel 3: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 4904 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 4905
<> 144:ef7eb2e8f9f7 4906 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4907 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4908 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4909 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4910
<> 144:ef7eb2e8f9f7 4911 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4912 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4913
<> 144:ef7eb2e8f9f7 4914 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4915 tmpccmrx &= ~TIM_CCMR2_OC3M;
<> 144:ef7eb2e8f9f7 4916 tmpccmrx &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 4917 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4918 tmpccmrx |= OC_Config->OCMode;
<> 144:ef7eb2e8f9f7 4919
<> 144:ef7eb2e8f9f7 4920 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4921 tmpccer &= ~TIM_CCER_CC3P;
<> 144:ef7eb2e8f9f7 4922 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4923 tmpccer |= (OC_Config->OCPolarity << 8);
<> 144:ef7eb2e8f9f7 4924
<> 144:ef7eb2e8f9f7 4925 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4926 {
<> 144:ef7eb2e8f9f7 4927 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /* Reset the Output N Polarity level */
<> 144:ef7eb2e8f9f7 4930 tmpccer &= ~TIM_CCER_CC3NP;
<> 144:ef7eb2e8f9f7 4931 /* Set the Output N Polarity */
<> 144:ef7eb2e8f9f7 4932 tmpccer |= (OC_Config->OCNPolarity << 8);
<> 144:ef7eb2e8f9f7 4933 /* Reset the Output N State */
<> 144:ef7eb2e8f9f7 4934 tmpccer &= ~TIM_CCER_CC3NE;
<> 144:ef7eb2e8f9f7 4935
<> 144:ef7eb2e8f9f7 4936 /* Reset the Output Compare and Output Compare N IDLE State */
<> 144:ef7eb2e8f9f7 4937 tmpcr2 &= ~TIM_CR2_OIS3;
<> 144:ef7eb2e8f9f7 4938 tmpcr2 &= ~TIM_CR2_OIS3N;
<> 144:ef7eb2e8f9f7 4939 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4940 tmpcr2 |= (OC_Config->OCIdleState << 4);
<> 144:ef7eb2e8f9f7 4941 /* Set the Output N Idle state */
<> 144:ef7eb2e8f9f7 4942 tmpcr2 |= (OC_Config->OCNIdleState << 4);
<> 144:ef7eb2e8f9f7 4943 }
<> 144:ef7eb2e8f9f7 4944 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 4945 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 4946
<> 144:ef7eb2e8f9f7 4947 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 4948 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 4949
<> 144:ef7eb2e8f9f7 4950 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 4951 TIMx->CCR3 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 4952
<> 144:ef7eb2e8f9f7 4953 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 4954 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 4955 }
<> 144:ef7eb2e8f9f7 4956
<> 144:ef7eb2e8f9f7 4957 /**
<> 144:ef7eb2e8f9f7 4958 * @brief Time Output Compare 4 configuration
<> 144:ef7eb2e8f9f7 4959 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 4960 * @param OC_Config: The output configuration structure
<> 144:ef7eb2e8f9f7 4961 * @retval None
<> 144:ef7eb2e8f9f7 4962 */
<> 144:ef7eb2e8f9f7 4963 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
<> 144:ef7eb2e8f9f7 4964 {
<> 144:ef7eb2e8f9f7 4965 uint32_t tmpccmrx = 0;
<> 144:ef7eb2e8f9f7 4966 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 4967 uint32_t tmpcr2 = 0;
<> 144:ef7eb2e8f9f7 4968
<> 144:ef7eb2e8f9f7 4969 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 4970 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 4971
<> 144:ef7eb2e8f9f7 4972 /* Get the TIMx CCER register value */
<> 144:ef7eb2e8f9f7 4973 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 4974 /* Get the TIMx CR2 register value */
<> 144:ef7eb2e8f9f7 4975 tmpcr2 = TIMx->CR2;
<> 144:ef7eb2e8f9f7 4976
<> 144:ef7eb2e8f9f7 4977 /* Get the TIMx CCMR2 register value */
<> 144:ef7eb2e8f9f7 4978 tmpccmrx = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 4979
<> 144:ef7eb2e8f9f7 4980 /* Reset the Output Compare mode and Capture/Compare selection Bits */
<> 144:ef7eb2e8f9f7 4981 tmpccmrx &= ~TIM_CCMR2_OC4M;
<> 144:ef7eb2e8f9f7 4982 tmpccmrx &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 4983
<> 144:ef7eb2e8f9f7 4984 /* Select the Output Compare Mode */
<> 144:ef7eb2e8f9f7 4985 tmpccmrx |= (OC_Config->OCMode << 8);
<> 144:ef7eb2e8f9f7 4986
<> 144:ef7eb2e8f9f7 4987 /* Reset the Output Polarity level */
<> 144:ef7eb2e8f9f7 4988 tmpccer &= ~TIM_CCER_CC4P;
<> 144:ef7eb2e8f9f7 4989 /* Set the Output Compare Polarity */
<> 144:ef7eb2e8f9f7 4990 tmpccer |= (OC_Config->OCPolarity << 12);
<> 144:ef7eb2e8f9f7 4991
<> 144:ef7eb2e8f9f7 4992 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
<> 144:ef7eb2e8f9f7 4993 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 4994 {
<> 144:ef7eb2e8f9f7 4995 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
<> 144:ef7eb2e8f9f7 4996 /* Reset the Output Compare IDLE State */
<> 144:ef7eb2e8f9f7 4997 tmpcr2 &= ~TIM_CR2_OIS4;
<> 144:ef7eb2e8f9f7 4998 /* Set the Output Idle state */
<> 144:ef7eb2e8f9f7 4999 tmpcr2 |= (OC_Config->OCIdleState << 6);
<> 144:ef7eb2e8f9f7 5000 }
<> 144:ef7eb2e8f9f7 5001 /* Write to TIMx CR2 */
<> 144:ef7eb2e8f9f7 5002 TIMx->CR2 = tmpcr2;
<> 144:ef7eb2e8f9f7 5003
<> 144:ef7eb2e8f9f7 5004 /* Write to TIMx CCMR2 */
<> 144:ef7eb2e8f9f7 5005 TIMx->CCMR2 = tmpccmrx;
<> 144:ef7eb2e8f9f7 5006
<> 144:ef7eb2e8f9f7 5007 /* Set the Capture Compare Register value */
<> 144:ef7eb2e8f9f7 5008 TIMx->CCR4 = OC_Config->Pulse;
<> 144:ef7eb2e8f9f7 5009
<> 144:ef7eb2e8f9f7 5010 /* Write to TIMx CCER */
<> 144:ef7eb2e8f9f7 5011 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5012 }
<> 144:ef7eb2e8f9f7 5013
<> 144:ef7eb2e8f9f7 5014 /**
<> 144:ef7eb2e8f9f7 5015 * @brief Time Output Compare 4 configuration
<> 144:ef7eb2e8f9f7 5016 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 5017 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 5018 * @param sSlaveConfig: The slave configuration structure
<> 144:ef7eb2e8f9f7 5019 * @retval None
<> 144:ef7eb2e8f9f7 5020 */
<> 144:ef7eb2e8f9f7 5021 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 5022 TIM_SlaveConfigTypeDef * sSlaveConfig)
<> 144:ef7eb2e8f9f7 5023 {
<> 144:ef7eb2e8f9f7 5024 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 5025 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5026 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5027
<> 144:ef7eb2e8f9f7 5028 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5029 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 5030
<> 144:ef7eb2e8f9f7 5031 /* Reset the Trigger Selection Bits */
<> 144:ef7eb2e8f9f7 5032 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5033 /* Set the Input Trigger source */
<> 144:ef7eb2e8f9f7 5034 tmpsmcr |= sSlaveConfig->InputTrigger;
<> 144:ef7eb2e8f9f7 5035
<> 144:ef7eb2e8f9f7 5036 /* Reset the slave mode Bits */
<> 144:ef7eb2e8f9f7 5037 tmpsmcr &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 5038 /* Set the slave mode */
<> 144:ef7eb2e8f9f7 5039 tmpsmcr |= sSlaveConfig->SlaveMode;
<> 144:ef7eb2e8f9f7 5040
<> 144:ef7eb2e8f9f7 5041 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5042 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5043
<> 144:ef7eb2e8f9f7 5044 /* Configure the trigger prescaler, filter, and polarity */
<> 144:ef7eb2e8f9f7 5045 switch (sSlaveConfig->InputTrigger)
<> 144:ef7eb2e8f9f7 5046 {
<> 144:ef7eb2e8f9f7 5047 case TIM_TS_ETRF:
<> 144:ef7eb2e8f9f7 5048 {
<> 144:ef7eb2e8f9f7 5049 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5050 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5051 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
<> 144:ef7eb2e8f9f7 5052 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5053 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5054 /* Configure the ETR Trigger source */
<> 144:ef7eb2e8f9f7 5055 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 5056 sSlaveConfig->TriggerPrescaler,
<> 144:ef7eb2e8f9f7 5057 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5058 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5059 }
<> 144:ef7eb2e8f9f7 5060 break;
<> 144:ef7eb2e8f9f7 5061
<> 144:ef7eb2e8f9f7 5062 case TIM_TS_TI1F_ED:
<> 144:ef7eb2e8f9f7 5063 {
<> 144:ef7eb2e8f9f7 5064 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5065 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5066 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5067 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5068
<> 144:ef7eb2e8f9f7 5069 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5070 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 5071 htim->Instance->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5072 tmpccmr1 = htim->Instance->CCMR1;
<> 144:ef7eb2e8f9f7 5073
<> 144:ef7eb2e8f9f7 5074 /* Set the filter */
<> 144:ef7eb2e8f9f7 5075 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5076 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
<> 144:ef7eb2e8f9f7 5077
<> 144:ef7eb2e8f9f7 5078 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5079 htim->Instance->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5080 htim->Instance->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5081
<> 144:ef7eb2e8f9f7 5082 }
<> 144:ef7eb2e8f9f7 5083 break;
<> 144:ef7eb2e8f9f7 5084
<> 144:ef7eb2e8f9f7 5085 case TIM_TS_TI1FP1:
<> 144:ef7eb2e8f9f7 5086 {
<> 144:ef7eb2e8f9f7 5087 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5088 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5089 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5090 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5091
<> 144:ef7eb2e8f9f7 5092 /* Configure TI1 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5093 TIM_TI1_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5094 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5095 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5096 }
<> 144:ef7eb2e8f9f7 5097 break;
<> 144:ef7eb2e8f9f7 5098
<> 144:ef7eb2e8f9f7 5099 case TIM_TS_TI2FP2:
<> 144:ef7eb2e8f9f7 5100 {
<> 144:ef7eb2e8f9f7 5101 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5102 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5103 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
<> 144:ef7eb2e8f9f7 5104 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
<> 144:ef7eb2e8f9f7 5105
<> 144:ef7eb2e8f9f7 5106 /* Configure TI2 Filter and Polarity */
<> 144:ef7eb2e8f9f7 5107 TIM_TI2_ConfigInputStage(htim->Instance,
<> 144:ef7eb2e8f9f7 5108 sSlaveConfig->TriggerPolarity,
<> 144:ef7eb2e8f9f7 5109 sSlaveConfig->TriggerFilter);
<> 144:ef7eb2e8f9f7 5110 }
<> 144:ef7eb2e8f9f7 5111 break;
<> 144:ef7eb2e8f9f7 5112
<> 144:ef7eb2e8f9f7 5113 case TIM_TS_ITR0:
<> 144:ef7eb2e8f9f7 5114 {
<> 144:ef7eb2e8f9f7 5115 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5116 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5117 }
<> 144:ef7eb2e8f9f7 5118 break;
<> 144:ef7eb2e8f9f7 5119
<> 144:ef7eb2e8f9f7 5120 case TIM_TS_ITR1:
<> 144:ef7eb2e8f9f7 5121 {
<> 144:ef7eb2e8f9f7 5122 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5123 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5124 }
<> 144:ef7eb2e8f9f7 5125 break;
<> 144:ef7eb2e8f9f7 5126
<> 144:ef7eb2e8f9f7 5127 case TIM_TS_ITR2:
<> 144:ef7eb2e8f9f7 5128 {
<> 144:ef7eb2e8f9f7 5129 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5130 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5131 }
<> 144:ef7eb2e8f9f7 5132 break;
<> 144:ef7eb2e8f9f7 5133
<> 144:ef7eb2e8f9f7 5134 case TIM_TS_ITR3:
<> 144:ef7eb2e8f9f7 5135 {
<> 144:ef7eb2e8f9f7 5136 /* Check the parameter */
<> 144:ef7eb2e8f9f7 5137 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 5138 }
<> 144:ef7eb2e8f9f7 5139 break;
<> 144:ef7eb2e8f9f7 5140
<> 144:ef7eb2e8f9f7 5141 default:
<> 144:ef7eb2e8f9f7 5142 break;
<> 144:ef7eb2e8f9f7 5143 }
<> 144:ef7eb2e8f9f7 5144 }
<> 144:ef7eb2e8f9f7 5145
<> 144:ef7eb2e8f9f7 5146 /**
<> 144:ef7eb2e8f9f7 5147 * @brief Configure the TI1 as Input.
<> 144:ef7eb2e8f9f7 5148 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5149 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5150 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5151 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5152 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5153 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5154 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5155 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5156 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5157 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5158 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5159 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5160 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5161 * @retval None
<> 144:ef7eb2e8f9f7 5162 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
<> 144:ef7eb2e8f9f7 5163 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5164 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5165 */
<> 144:ef7eb2e8f9f7 5166 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5167 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5168 {
<> 144:ef7eb2e8f9f7 5169 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5170 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5171
<> 144:ef7eb2e8f9f7 5172 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5173 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5174 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5175 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5176
<> 144:ef7eb2e8f9f7 5177 /* Select the Input */
<> 144:ef7eb2e8f9f7 5178 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
<> 144:ef7eb2e8f9f7 5179 {
<> 144:ef7eb2e8f9f7 5180 tmpccmr1 &= ~TIM_CCMR1_CC1S;
<> 144:ef7eb2e8f9f7 5181 tmpccmr1 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5182 }
<> 144:ef7eb2e8f9f7 5183 else
<> 144:ef7eb2e8f9f7 5184 {
<> 144:ef7eb2e8f9f7 5185 tmpccmr1 |= TIM_CCMR1_CC1S_0;
<> 144:ef7eb2e8f9f7 5186 }
<> 144:ef7eb2e8f9f7 5187
<> 144:ef7eb2e8f9f7 5188 /* Set the filter */
<> 144:ef7eb2e8f9f7 5189 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5190 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
<> 144:ef7eb2e8f9f7 5191
<> 144:ef7eb2e8f9f7 5192 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5193 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5194 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
<> 144:ef7eb2e8f9f7 5195
<> 144:ef7eb2e8f9f7 5196 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5197 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5198 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5199 }
<> 144:ef7eb2e8f9f7 5200
<> 144:ef7eb2e8f9f7 5201 /**
<> 144:ef7eb2e8f9f7 5202 * @brief Configure the Polarity and Filter for TI1.
<> 144:ef7eb2e8f9f7 5203 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5204 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5205 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5206 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5207 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5208 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5209 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5210 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5211 * @retval None
<> 144:ef7eb2e8f9f7 5212 */
<> 144:ef7eb2e8f9f7 5213 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5214 {
<> 144:ef7eb2e8f9f7 5215 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5216 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5217
<> 144:ef7eb2e8f9f7 5218 /* Disable the Channel 1: Reset the CC1E Bit */
<> 144:ef7eb2e8f9f7 5219 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5220 TIMx->CCER &= ~TIM_CCER_CC1E;
<> 144:ef7eb2e8f9f7 5221 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5222
<> 144:ef7eb2e8f9f7 5223 /* Set the filter */
<> 144:ef7eb2e8f9f7 5224 tmpccmr1 &= ~TIM_CCMR1_IC1F;
<> 144:ef7eb2e8f9f7 5225 tmpccmr1 |= (TIM_ICFilter << 4);
<> 144:ef7eb2e8f9f7 5226
<> 144:ef7eb2e8f9f7 5227 /* Select the Polarity and set the CC1E Bit */
<> 144:ef7eb2e8f9f7 5228 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
<> 144:ef7eb2e8f9f7 5229 tmpccer |= TIM_ICPolarity;
<> 144:ef7eb2e8f9f7 5230
<> 144:ef7eb2e8f9f7 5231 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5232 TIMx->CCMR1 = tmpccmr1;
<> 144:ef7eb2e8f9f7 5233 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5234 }
<> 144:ef7eb2e8f9f7 5235
<> 144:ef7eb2e8f9f7 5236 /**
<> 144:ef7eb2e8f9f7 5237 * @brief Configure the TI2 as Input.
<> 144:ef7eb2e8f9f7 5238 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5239 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5240 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5241 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5242 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5243 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5244 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5245 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5246 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
<> 144:ef7eb2e8f9f7 5247 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
<> 144:ef7eb2e8f9f7 5248 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5249 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5250 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5251 * @retval None
<> 144:ef7eb2e8f9f7 5252 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
<> 144:ef7eb2e8f9f7 5253 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
<> 144:ef7eb2e8f9f7 5254 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5255 */
<> 144:ef7eb2e8f9f7 5256 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5257 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5258 {
<> 144:ef7eb2e8f9f7 5259 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5260 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5261
<> 144:ef7eb2e8f9f7 5262 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5263 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5264 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5265 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5266
<> 144:ef7eb2e8f9f7 5267 /* Select the Input */
<> 144:ef7eb2e8f9f7 5268 tmpccmr1 &= ~TIM_CCMR1_CC2S;
<> 144:ef7eb2e8f9f7 5269 tmpccmr1 |= (TIM_ICSelection << 8);
<> 144:ef7eb2e8f9f7 5270
<> 144:ef7eb2e8f9f7 5271 /* Set the filter */
<> 144:ef7eb2e8f9f7 5272 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5273 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
<> 144:ef7eb2e8f9f7 5274
<> 144:ef7eb2e8f9f7 5275 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5276 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5277 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
<> 144:ef7eb2e8f9f7 5278
<> 144:ef7eb2e8f9f7 5279 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5280 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5281 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5282 }
<> 144:ef7eb2e8f9f7 5283
<> 144:ef7eb2e8f9f7 5284 /**
<> 144:ef7eb2e8f9f7 5285 * @brief Configure the Polarity and Filter for TI2.
<> 144:ef7eb2e8f9f7 5286 * @param TIMx to select the TIM peripheral.
<> 144:ef7eb2e8f9f7 5287 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5288 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5289 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5290 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5291 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5292 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5293 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5294 * @retval None
<> 144:ef7eb2e8f9f7 5295 */
<> 144:ef7eb2e8f9f7 5296 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5297 {
<> 144:ef7eb2e8f9f7 5298 uint32_t tmpccmr1 = 0;
<> 144:ef7eb2e8f9f7 5299 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5300
<> 144:ef7eb2e8f9f7 5301 /* Disable the Channel 2: Reset the CC2E Bit */
<> 144:ef7eb2e8f9f7 5302 TIMx->CCER &= ~TIM_CCER_CC2E;
<> 144:ef7eb2e8f9f7 5303 tmpccmr1 = TIMx->CCMR1;
<> 144:ef7eb2e8f9f7 5304 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5305
<> 144:ef7eb2e8f9f7 5306 /* Set the filter */
<> 144:ef7eb2e8f9f7 5307 tmpccmr1 &= ~TIM_CCMR1_IC2F;
<> 144:ef7eb2e8f9f7 5308 tmpccmr1 |= (TIM_ICFilter << 12);
<> 144:ef7eb2e8f9f7 5309
<> 144:ef7eb2e8f9f7 5310 /* Select the Polarity and set the CC2E Bit */
<> 144:ef7eb2e8f9f7 5311 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
<> 144:ef7eb2e8f9f7 5312 tmpccer |= (TIM_ICPolarity << 4);
<> 144:ef7eb2e8f9f7 5313
<> 144:ef7eb2e8f9f7 5314 /* Write to TIMx CCMR1 and CCER registers */
<> 144:ef7eb2e8f9f7 5315 TIMx->CCMR1 = tmpccmr1 ;
<> 144:ef7eb2e8f9f7 5316 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5317 }
<> 144:ef7eb2e8f9f7 5318
<> 144:ef7eb2e8f9f7 5319 /**
<> 144:ef7eb2e8f9f7 5320 * @brief Configure the TI3 as Input.
<> 144:ef7eb2e8f9f7 5321 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5322 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5323 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5324 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5325 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5326 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5327 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5329 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5330 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5331 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5332 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5333 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5334 * @retval None
<> 144:ef7eb2e8f9f7 5335 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
<> 144:ef7eb2e8f9f7 5336 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5337 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5338 */
<> 144:ef7eb2e8f9f7 5339 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5340 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5341 {
<> 144:ef7eb2e8f9f7 5342 uint32_t tmpccmr2 = 0;
<> 144:ef7eb2e8f9f7 5343 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5344
<> 144:ef7eb2e8f9f7 5345 /* Disable the Channel 3: Reset the CC3E Bit */
<> 144:ef7eb2e8f9f7 5346 TIMx->CCER &= ~TIM_CCER_CC3E;
<> 144:ef7eb2e8f9f7 5347 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5348 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5349
<> 144:ef7eb2e8f9f7 5350 /* Select the Input */
<> 144:ef7eb2e8f9f7 5351 tmpccmr2 &= ~TIM_CCMR2_CC3S;
<> 144:ef7eb2e8f9f7 5352 tmpccmr2 |= TIM_ICSelection;
<> 144:ef7eb2e8f9f7 5353
<> 144:ef7eb2e8f9f7 5354 /* Set the filter */
<> 144:ef7eb2e8f9f7 5355 tmpccmr2 &= ~TIM_CCMR2_IC3F;
<> 144:ef7eb2e8f9f7 5356 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
<> 144:ef7eb2e8f9f7 5357
<> 144:ef7eb2e8f9f7 5358 /* Select the Polarity and set the CC3E Bit */
<> 144:ef7eb2e8f9f7 5359 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
<> 144:ef7eb2e8f9f7 5360 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
<> 144:ef7eb2e8f9f7 5361
<> 144:ef7eb2e8f9f7 5362 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5363 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5364 TIMx->CCER = tmpccer;
<> 144:ef7eb2e8f9f7 5365 }
<> 144:ef7eb2e8f9f7 5366
<> 144:ef7eb2e8f9f7 5367 /**
<> 144:ef7eb2e8f9f7 5368 * @brief Configure the TI4 as Input.
<> 144:ef7eb2e8f9f7 5369 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5370 * @param TIM_ICPolarity : The Input Polarity.
<> 144:ef7eb2e8f9f7 5371 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5372 * @arg TIM_ICPolarity_Rising
<> 144:ef7eb2e8f9f7 5373 * @arg TIM_ICPolarity_Falling
<> 144:ef7eb2e8f9f7 5374 * @arg TIM_ICPolarity_BothEdge
<> 144:ef7eb2e8f9f7 5375 * @param TIM_ICSelection: specifies the input to be used.
<> 144:ef7eb2e8f9f7 5376 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5377 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
<> 144:ef7eb2e8f9f7 5378 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
<> 144:ef7eb2e8f9f7 5379 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
<> 144:ef7eb2e8f9f7 5380 * @param TIM_ICFilter: Specifies the Input Capture Filter.
<> 144:ef7eb2e8f9f7 5381 * This parameter must be a value between 0x00 and 0x0F.
<> 144:ef7eb2e8f9f7 5382 * @retval None
<> 144:ef7eb2e8f9f7 5383 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
<> 144:ef7eb2e8f9f7 5384 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
<> 144:ef7eb2e8f9f7 5385 * protected against un-initialized filter and polarity values.
<> 144:ef7eb2e8f9f7 5386 */
<> 144:ef7eb2e8f9f7 5387 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
<> 144:ef7eb2e8f9f7 5388 uint32_t TIM_ICFilter)
<> 144:ef7eb2e8f9f7 5389 {
<> 144:ef7eb2e8f9f7 5390 uint32_t tmpccmr2 = 0;
<> 144:ef7eb2e8f9f7 5391 uint32_t tmpccer = 0;
<> 144:ef7eb2e8f9f7 5392
<> 144:ef7eb2e8f9f7 5393 /* Disable the Channel 4: Reset the CC4E Bit */
<> 144:ef7eb2e8f9f7 5394 TIMx->CCER &= ~TIM_CCER_CC4E;
<> 144:ef7eb2e8f9f7 5395 tmpccmr2 = TIMx->CCMR2;
<> 144:ef7eb2e8f9f7 5396 tmpccer = TIMx->CCER;
<> 144:ef7eb2e8f9f7 5397
<> 144:ef7eb2e8f9f7 5398 /* Select the Input */
<> 144:ef7eb2e8f9f7 5399 tmpccmr2 &= ~TIM_CCMR2_CC4S;
<> 144:ef7eb2e8f9f7 5400 tmpccmr2 |= (TIM_ICSelection << 8);
<> 144:ef7eb2e8f9f7 5401
<> 144:ef7eb2e8f9f7 5402 /* Set the filter */
<> 144:ef7eb2e8f9f7 5403 tmpccmr2 &= ~TIM_CCMR2_IC4F;
<> 144:ef7eb2e8f9f7 5404 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
<> 144:ef7eb2e8f9f7 5405
<> 144:ef7eb2e8f9f7 5406 /* Select the Polarity and set the CC4E Bit */
<> 144:ef7eb2e8f9f7 5407 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
<> 144:ef7eb2e8f9f7 5408 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
<> 144:ef7eb2e8f9f7 5409
<> 144:ef7eb2e8f9f7 5410 /* Write to TIMx CCMR2 and CCER registers */
<> 144:ef7eb2e8f9f7 5411 TIMx->CCMR2 = tmpccmr2;
<> 144:ef7eb2e8f9f7 5412 TIMx->CCER = tmpccer ;
<> 144:ef7eb2e8f9f7 5413 }
<> 144:ef7eb2e8f9f7 5414
<> 144:ef7eb2e8f9f7 5415 /**
<> 144:ef7eb2e8f9f7 5416 * @brief Selects the Input Trigger source
<> 144:ef7eb2e8f9f7 5417 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5418 * @param TIM_ITRx: The Input Trigger source.
<> 144:ef7eb2e8f9f7 5419 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5420 * @arg TIM_TS_ITR0: Internal Trigger 0
<> 144:ef7eb2e8f9f7 5421 * @arg TIM_TS_ITR1: Internal Trigger 1
<> 144:ef7eb2e8f9f7 5422 * @arg TIM_TS_ITR2: Internal Trigger 2
<> 144:ef7eb2e8f9f7 5423 * @arg TIM_TS_ITR3: Internal Trigger 3
<> 144:ef7eb2e8f9f7 5424 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
<> 144:ef7eb2e8f9f7 5425 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
<> 144:ef7eb2e8f9f7 5426 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
<> 144:ef7eb2e8f9f7 5427 * @arg TIM_TS_ETRF: External Trigger input
<> 144:ef7eb2e8f9f7 5428 * @retval None
<> 144:ef7eb2e8f9f7 5429 */
<> 144:ef7eb2e8f9f7 5430 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
<> 144:ef7eb2e8f9f7 5431 {
<> 144:ef7eb2e8f9f7 5432 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 5433
<> 144:ef7eb2e8f9f7 5434 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 5435 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5436 /* Reset the TS Bits */
<> 144:ef7eb2e8f9f7 5437 tmpsmcr &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 5438 /* Set the Input Trigger source and the slave mode*/
<> 144:ef7eb2e8f9f7 5439 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
<> 144:ef7eb2e8f9f7 5440 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5441 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5442 }
<> 144:ef7eb2e8f9f7 5443
<> 144:ef7eb2e8f9f7 5444 /**
<> 144:ef7eb2e8f9f7 5445 * @brief Configures the TIMx External Trigger (ETR).
<> 144:ef7eb2e8f9f7 5446 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5447 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
<> 144:ef7eb2e8f9f7 5448 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5449 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
<> 144:ef7eb2e8f9f7 5450 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
<> 144:ef7eb2e8f9f7 5451 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
<> 144:ef7eb2e8f9f7 5452 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
<> 144:ef7eb2e8f9f7 5453 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
<> 144:ef7eb2e8f9f7 5454 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5455 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
<> 144:ef7eb2e8f9f7 5456 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
<> 144:ef7eb2e8f9f7 5457 * @param ExtTRGFilter: External Trigger Filter.
<> 144:ef7eb2e8f9f7 5458 * This parameter must be a value between 0x00 and 0x0F
<> 144:ef7eb2e8f9f7 5459 * @retval None
<> 144:ef7eb2e8f9f7 5460 */
<> 144:ef7eb2e8f9f7 5461 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
<> 144:ef7eb2e8f9f7 5462 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
<> 144:ef7eb2e8f9f7 5463 {
<> 144:ef7eb2e8f9f7 5464 uint32_t tmpsmcr = 0;
<> 144:ef7eb2e8f9f7 5465
<> 144:ef7eb2e8f9f7 5466 tmpsmcr = TIMx->SMCR;
<> 144:ef7eb2e8f9f7 5467
<> 144:ef7eb2e8f9f7 5468 /* Reset the ETR Bits */
<> 144:ef7eb2e8f9f7 5469 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 5470
<> 144:ef7eb2e8f9f7 5471 /* Set the Prescaler, the Filter value and the Polarity */
<> 144:ef7eb2e8f9f7 5472 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
<> 144:ef7eb2e8f9f7 5473
<> 144:ef7eb2e8f9f7 5474 /* Write to TIMx SMCR */
<> 144:ef7eb2e8f9f7 5475 TIMx->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 5476 }
<> 144:ef7eb2e8f9f7 5477
<> 144:ef7eb2e8f9f7 5478 /**
<> 144:ef7eb2e8f9f7 5479 * @brief Enables or disables the TIM Capture Compare Channel x.
<> 144:ef7eb2e8f9f7 5480 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 5481 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 5482 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 5483 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 5484 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 5485 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 5486 * @arg TIM_Channel_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 5487 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
<> 144:ef7eb2e8f9f7 5488 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
<> 144:ef7eb2e8f9f7 5489 * @retval None
<> 144:ef7eb2e8f9f7 5490 */
<> 144:ef7eb2e8f9f7 5491 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
<> 144:ef7eb2e8f9f7 5492 {
<> 144:ef7eb2e8f9f7 5493 uint32_t tmp = 0;
<> 144:ef7eb2e8f9f7 5494
<> 144:ef7eb2e8f9f7 5495 /* Check the parameters */
<> 144:ef7eb2e8f9f7 5496 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 5497 assert_param(IS_TIM_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 5498
<> 144:ef7eb2e8f9f7 5499 tmp = TIM_CCER_CC1E << Channel;
<> 144:ef7eb2e8f9f7 5500
<> 144:ef7eb2e8f9f7 5501 /* Reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5502 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 5503
<> 144:ef7eb2e8f9f7 5504 /* Set or reset the CCxE Bit */
<> 144:ef7eb2e8f9f7 5505 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
<> 144:ef7eb2e8f9f7 5506 }
<> 144:ef7eb2e8f9f7 5507
<> 144:ef7eb2e8f9f7 5508
<> 144:ef7eb2e8f9f7 5509 /**
<> 144:ef7eb2e8f9f7 5510 * @}
<> 144:ef7eb2e8f9f7 5511 */
<> 144:ef7eb2e8f9f7 5512
<> 144:ef7eb2e8f9f7 5513 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 5514 /**
<> 144:ef7eb2e8f9f7 5515 * @}
<> 144:ef7eb2e8f9f7 5516 */
<> 144:ef7eb2e8f9f7 5517
<> 144:ef7eb2e8f9f7 5518 /**
<> 144:ef7eb2e8f9f7 5519 * @}
<> 144:ef7eb2e8f9f7 5520 */
<> 144:ef7eb2e8f9f7 5521 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/