mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 83:a036322b8637

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_rcc_ex.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.0
<>	144:ef7eb2e8f9f7	6	* @date 22-April-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL Extension module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F7xx_HAL_RCC_EX_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F7xx_HAL_RCC_EX_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f7xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup RCCEx
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t PLLState; /*!< The new state of the PLL.
<>	144:ef7eb2e8f9f7	68	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
<>	144:ef7eb2e8f9f7	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	72
<>	144:ef7eb2e8f9f7	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
<>	144:ef7eb2e8f9f7	74	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
<>	144:ef7eb2e8f9f7	77	This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
<>	144:ef7eb2e8f9f7	83	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
<>	144:ef7eb2e8f9f7	84	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	85	uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
<>	144:ef7eb2e8f9f7	86	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
<>	144:ef7eb2e8f9f7	87	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	}RCC_PLLInitTypeDef;
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	/**
<>	144:ef7eb2e8f9f7	92	* @brief PLLI2S Clock structure definition
<>	144:ef7eb2e8f9f7	93	*/
<>	144:ef7eb2e8f9f7	94	typedef struct
<>	144:ef7eb2e8f9f7	95	{
<>	144:ef7eb2e8f9f7	96	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
<>	144:ef7eb2e8f9f7	97	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	98	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
<>	144:ef7eb2e8f9f7	101	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	102	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
<>	144:ef7eb2e8f9f7	105	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	106	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
<>	144:ef7eb2e8f9f7	109	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
<>	144:ef7eb2e8f9f7	110	This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
<>	144:ef7eb2e8f9f7	111	}RCC_PLLI2SInitTypeDef;
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/**
<>	144:ef7eb2e8f9f7	114	* @brief PLLSAI Clock structure definition
<>	144:ef7eb2e8f9f7	115	*/
<>	144:ef7eb2e8f9f7	116	typedef struct
<>	144:ef7eb2e8f9f7	117	{
<>	144:ef7eb2e8f9f7	118	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
<>	144:ef7eb2e8f9f7	119	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	120	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
<>	144:ef7eb2e8f9f7	123	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	124	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
<>	144:ef7eb2e8f9f7	127	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	128	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
<>	144:ef7eb2e8f9f7	131	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
<>	144:ef7eb2e8f9f7	132	This parameter will be used only when PLLSAI is disabled */
<>	144:ef7eb2e8f9f7	133	}RCC_PLLSAIInitTypeDef;
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	/**
<>	144:ef7eb2e8f9f7	136	* @brief RCC extended clocks structure definition
<>	144:ef7eb2e8f9f7	137	*/
<>	144:ef7eb2e8f9f7	138	typedef struct
<>	144:ef7eb2e8f9f7	139	{
<>	144:ef7eb2e8f9f7	140	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<>	144:ef7eb2e8f9f7	141	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
<>	144:ef7eb2e8f9f7	144	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
<>	144:ef7eb2e8f9f7	147	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
<>	144:ef7eb2e8f9f7	148
<>	144:ef7eb2e8f9f7	149	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
<>	144:ef7eb2e8f9f7	150	This parameter must be a number between Min_Data = 1 and Max_Data = 32
<>	144:ef7eb2e8f9f7	151	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
<>	144:ef7eb2e8f9f7	154	This parameter must be a number between Min_Data = 1 and Max_Data = 32
<>	144:ef7eb2e8f9f7	155	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
<>	144:ef7eb2e8f9f7	158	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
<>	144:ef7eb2e8f9f7	161	This parameter can be a value of @ref RCC_RTC_Clock_Source */
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
<>	144:ef7eb2e8f9f7	164	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
<>	144:ef7eb2e8f9f7	167	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
<>	144:ef7eb2e8f9f7	170	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
<>	144:ef7eb2e8f9f7	173	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	uint32_t Usart1ClockSelection; /*!< USART1 clock source
<>	144:ef7eb2e8f9f7	176	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	uint32_t Usart2ClockSelection; /*!< USART2 clock source
<>	144:ef7eb2e8f9f7	179	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
<>	144:ef7eb2e8f9f7	180
<>	144:ef7eb2e8f9f7	181	uint32_t Usart3ClockSelection; /*!< USART3 clock source
<>	144:ef7eb2e8f9f7	182	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
<>	144:ef7eb2e8f9f7	183
<>	144:ef7eb2e8f9f7	184	uint32_t Uart4ClockSelection; /*!< UART4 clock source
<>	144:ef7eb2e8f9f7	185	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	uint32_t Uart5ClockSelection; /*!< UART5 clock source
<>	144:ef7eb2e8f9f7	188	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	uint32_t Usart6ClockSelection; /*!< USART6 clock source
<>	144:ef7eb2e8f9f7	191	This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	uint32_t Uart7ClockSelection; /*!< UART7 clock source
<>	144:ef7eb2e8f9f7	194	This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	uint32_t Uart8ClockSelection; /*!< UART8 clock source
<>	144:ef7eb2e8f9f7	197	This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
<>	144:ef7eb2e8f9f7	200	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
<>	144:ef7eb2e8f9f7	203	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
<>	144:ef7eb2e8f9f7	206	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	uint32_t I2c4ClockSelection; /*!< I2C4 clock source
<>	144:ef7eb2e8f9f7	209	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
<>	144:ef7eb2e8f9f7	212	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
<>	144:ef7eb2e8f9f7	213
<>	144:ef7eb2e8f9f7	214	uint32_t CecClockSelection; /*!< CEC clock source
<>	144:ef7eb2e8f9f7	215	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
<>	144:ef7eb2e8f9f7	218	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
<>	144:ef7eb2e8f9f7	219
<>	144:ef7eb2e8f9f7	220	uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
<>	144:ef7eb2e8f9f7	221	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	224	uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
<>	144:ef7eb2e8f9f7	225	This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227	uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
<>	144:ef7eb2e8f9f7	228	This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
<>	144:ef7eb2e8f9f7	229
<>	144:ef7eb2e8f9f7	230	uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
<>	144:ef7eb2e8f9f7	231	This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
<>	144:ef7eb2e8f9f7	232	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	233	}RCC_PeriphCLKInitTypeDef;
<>	144:ef7eb2e8f9f7	234	/**
<>	144:ef7eb2e8f9f7	235	* @}
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	239	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<>	144:ef7eb2e8f9f7	240	* @{
<>	144:ef7eb2e8f9f7	241	*/
<>	144:ef7eb2e8f9f7	242
<>	144:ef7eb2e8f9f7	243	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
<>	144:ef7eb2e8f9f7	244	* @{
<>	144:ef7eb2e8f9f7	245	*/
<>	144:ef7eb2e8f9f7	246	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	247	#if defined(STM32F746xx) \|\| defined(STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	248	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
<>	144:ef7eb2e8f9f7	249	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	250	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
<>	144:ef7eb2e8f9f7	251	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
<>	144:ef7eb2e8f9f7	252	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
<>	144:ef7eb2e8f9f7	253	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
<>	144:ef7eb2e8f9f7	254	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	255	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
<>	144:ef7eb2e8f9f7	256	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
<>	144:ef7eb2e8f9f7	257	#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
<>	144:ef7eb2e8f9f7	258	#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
<>	144:ef7eb2e8f9f7	259	#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
<>	144:ef7eb2e8f9f7	260	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
<>	144:ef7eb2e8f9f7	261	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
<>	144:ef7eb2e8f9f7	262	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
<>	144:ef7eb2e8f9f7	263	#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
<>	144:ef7eb2e8f9f7	264	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
<>	144:ef7eb2e8f9f7	265	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
<>	144:ef7eb2e8f9f7	266	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
<>	144:ef7eb2e8f9f7	267	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
<>	144:ef7eb2e8f9f7	268	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
<>	144:ef7eb2e8f9f7	269	#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
<>	144:ef7eb2e8f9f7	270	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
<>	144:ef7eb2e8f9f7	271	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
<>	144:ef7eb2e8f9f7	272	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	273	#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
<>	144:ef7eb2e8f9f7	274	#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
<>	144:ef7eb2e8f9f7	275	#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
<>	144:ef7eb2e8f9f7	276	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278	/**
<>	144:ef7eb2e8f9f7	279	* @}
<>	144:ef7eb2e8f9f7	280	*/
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
<>	144:ef7eb2e8f9f7	283	* @{
<>	144:ef7eb2e8f9f7	284	*/
<>	144:ef7eb2e8f9f7	285	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	286	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	287	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	288	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	289	/**
<>	144:ef7eb2e8f9f7	290	* @}
<>	144:ef7eb2e8f9f7	291	*/
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
<>	144:ef7eb2e8f9f7	294	* @{
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	297	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
<>	144:ef7eb2e8f9f7	298	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
<>	144:ef7eb2e8f9f7	299	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @}
<>	144:ef7eb2e8f9f7	302	*/
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
<>	144:ef7eb2e8f9f7	305	* @{
<>	144:ef7eb2e8f9f7	306	*/
<>	144:ef7eb2e8f9f7	307	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	308	#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
<>	144:ef7eb2e8f9f7	309	#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
<>	144:ef7eb2e8f9f7	310	#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
<>	144:ef7eb2e8f9f7	311	/**
<>	144:ef7eb2e8f9f7	312	* @}
<>	144:ef7eb2e8f9f7	313	*/
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
<>	144:ef7eb2e8f9f7	316	* @{
<>	144:ef7eb2e8f9f7	317	*/
<>	144:ef7eb2e8f9f7	318	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	319	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	/**
<>	144:ef7eb2e8f9f7	322	* @}
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325
<>	144:ef7eb2e8f9f7	326	/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
<>	144:ef7eb2e8f9f7	327	* @{
<>	144:ef7eb2e8f9f7	328	*/
<>	144:ef7eb2e8f9f7	329	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	330	#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
<>	144:ef7eb2e8f9f7	331	#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
<>	144:ef7eb2e8f9f7	332	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	333	#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
<>	144:ef7eb2e8f9f7	334	#endif /* STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	335	/**
<>	144:ef7eb2e8f9f7	336	* @}
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
<>	144:ef7eb2e8f9f7	340	* @{
<>	144:ef7eb2e8f9f7	341	*/
<>	144:ef7eb2e8f9f7	342	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	343	#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
<>	144:ef7eb2e8f9f7	344	#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
<>	144:ef7eb2e8f9f7	345	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	346	#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
<>	144:ef7eb2e8f9f7	347	#endif /* STM32F765xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	348	/**
<>	144:ef7eb2e8f9f7	349	* @}
<>	144:ef7eb2e8f9f7	350	*/
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
<>	144:ef7eb2e8f9f7	353	* @{
<>	144:ef7eb2e8f9f7	354	*/
<>	144:ef7eb2e8f9f7	355	#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	356	#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
<>	144:ef7eb2e8f9f7	357	/**
<>	144:ef7eb2e8f9f7	358	* @}
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
<>	144:ef7eb2e8f9f7	362	* @{
<>	144:ef7eb2e8f9f7	363	*/
<>	144:ef7eb2e8f9f7	364	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	365	#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
<>	144:ef7eb2e8f9f7	366	#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
<>	144:ef7eb2e8f9f7	367	#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
<>	144:ef7eb2e8f9f7	368	/**
<>	144:ef7eb2e8f9f7	369	* @}
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371
<>	144:ef7eb2e8f9f7	372	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
<>	144:ef7eb2e8f9f7	373	* @{
<>	144:ef7eb2e8f9f7	374	*/
<>	144:ef7eb2e8f9f7	375	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	376	#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
<>	144:ef7eb2e8f9f7	377	#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
<>	144:ef7eb2e8f9f7	378	#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
<>	144:ef7eb2e8f9f7	379	/**
<>	144:ef7eb2e8f9f7	380	* @}
<>	144:ef7eb2e8f9f7	381	*/
<>	144:ef7eb2e8f9f7	382
<>	144:ef7eb2e8f9f7	383	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
<>	144:ef7eb2e8f9f7	384	* @{
<>	144:ef7eb2e8f9f7	385	*/
<>	144:ef7eb2e8f9f7	386	#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	387	#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
<>	144:ef7eb2e8f9f7	388	#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
<>	144:ef7eb2e8f9f7	389	#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
<>	144:ef7eb2e8f9f7	390	/**
<>	144:ef7eb2e8f9f7	391	* @}
<>	144:ef7eb2e8f9f7	392	*/
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
<>	144:ef7eb2e8f9f7	395	* @{
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397	#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	398	#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
<>	144:ef7eb2e8f9f7	399	#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
<>	144:ef7eb2e8f9f7	400	#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
<>	144:ef7eb2e8f9f7	401	/**
<>	144:ef7eb2e8f9f7	402	* @}
<>	144:ef7eb2e8f9f7	403	*/
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
<>	144:ef7eb2e8f9f7	406	* @{
<>	144:ef7eb2e8f9f7	407	*/
<>	144:ef7eb2e8f9f7	408	#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	409	#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
<>	144:ef7eb2e8f9f7	410	#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
<>	144:ef7eb2e8f9f7	411	#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
<>	144:ef7eb2e8f9f7	412	/**
<>	144:ef7eb2e8f9f7	413	* @}
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
<>	144:ef7eb2e8f9f7	417	* @{
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419	#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	420	#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
<>	144:ef7eb2e8f9f7	421	#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
<>	144:ef7eb2e8f9f7	422	#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
<>	144:ef7eb2e8f9f7	423	/**
<>	144:ef7eb2e8f9f7	424	* @}
<>	144:ef7eb2e8f9f7	425	*/
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
<>	144:ef7eb2e8f9f7	428	* @{
<>	144:ef7eb2e8f9f7	429	*/
<>	144:ef7eb2e8f9f7	430	#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	431	#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
<>	144:ef7eb2e8f9f7	432	#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
<>	144:ef7eb2e8f9f7	433	#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
<>	144:ef7eb2e8f9f7	434	/**
<>	144:ef7eb2e8f9f7	435	* @}
<>	144:ef7eb2e8f9f7	436	*/
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
<>	144:ef7eb2e8f9f7	439	* @{
<>	144:ef7eb2e8f9f7	440	*/
<>	144:ef7eb2e8f9f7	441	#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	442	#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
<>	144:ef7eb2e8f9f7	443	#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
<>	144:ef7eb2e8f9f7	444	#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
<>	144:ef7eb2e8f9f7	445	/**
<>	144:ef7eb2e8f9f7	446	* @}
<>	144:ef7eb2e8f9f7	447	*/
<>	144:ef7eb2e8f9f7	448
<>	144:ef7eb2e8f9f7	449	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
<>	144:ef7eb2e8f9f7	450	* @{
<>	144:ef7eb2e8f9f7	451	*/
<>	144:ef7eb2e8f9f7	452	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	453	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
<>	144:ef7eb2e8f9f7	454	#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
<>	144:ef7eb2e8f9f7	455	/**
<>	144:ef7eb2e8f9f7	456	* @}
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
<>	144:ef7eb2e8f9f7	460	* @{
<>	144:ef7eb2e8f9f7	461	*/
<>	144:ef7eb2e8f9f7	462	#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	463	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
<>	144:ef7eb2e8f9f7	464	#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/**
<>	144:ef7eb2e8f9f7	467	* @}
<>	144:ef7eb2e8f9f7	468	*/
<>	144:ef7eb2e8f9f7	469
<>	144:ef7eb2e8f9f7	470	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
<>	144:ef7eb2e8f9f7	471	* @{
<>	144:ef7eb2e8f9f7	472	*/
<>	144:ef7eb2e8f9f7	473	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	474	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
<>	144:ef7eb2e8f9f7	475	#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
<>	144:ef7eb2e8f9f7	476	/**
<>	144:ef7eb2e8f9f7	477	* @}
<>	144:ef7eb2e8f9f7	478	*/
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
<>	144:ef7eb2e8f9f7	481	* @{
<>	144:ef7eb2e8f9f7	482	*/
<>	144:ef7eb2e8f9f7	483	#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	484	#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
<>	144:ef7eb2e8f9f7	485	#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
<>	144:ef7eb2e8f9f7	486	/**
<>	144:ef7eb2e8f9f7	487	* @}
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489
<>	144:ef7eb2e8f9f7	490	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
<>	144:ef7eb2e8f9f7	491	* @{
<>	144:ef7eb2e8f9f7	492	*/
<>	144:ef7eb2e8f9f7	493	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	494	#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
<>	144:ef7eb2e8f9f7	495	#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
<>	144:ef7eb2e8f9f7	496	#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/**
<>	144:ef7eb2e8f9f7	499	* @}
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501
<>	144:ef7eb2e8f9f7	502	/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
<>	144:ef7eb2e8f9f7	503	* @{
<>	144:ef7eb2e8f9f7	504	*/
<>	144:ef7eb2e8f9f7	505	#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	506	#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @}
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
<>	144:ef7eb2e8f9f7	512	* @{
<>	144:ef7eb2e8f9f7	513	*/
<>	144:ef7eb2e8f9f7	514	#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	515	#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
<>	144:ef7eb2e8f9f7	516	/**
<>	144:ef7eb2e8f9f7	517	* @}
<>	144:ef7eb2e8f9f7	518	*/
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
<>	144:ef7eb2e8f9f7	521	* @{
<>	144:ef7eb2e8f9f7	522	*/
<>	144:ef7eb2e8f9f7	523	#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	524	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
<>	144:ef7eb2e8f9f7	525	/**
<>	144:ef7eb2e8f9f7	526	* @}
<>	144:ef7eb2e8f9f7	527	*/
<>	144:ef7eb2e8f9f7	528
<>	144:ef7eb2e8f9f7	529	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	530	/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
<>	144:ef7eb2e8f9f7	531	* @{
<>	144:ef7eb2e8f9f7	532	*/
<>	144:ef7eb2e8f9f7	533	#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	534	#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
<>	144:ef7eb2e8f9f7	535	/**
<>	144:ef7eb2e8f9f7	536	* @}
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538
<>	144:ef7eb2e8f9f7	539	/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
<>	144:ef7eb2e8f9f7	540	* @{
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542	#define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	543	#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
<>	144:ef7eb2e8f9f7	544	/**
<>	144:ef7eb2e8f9f7	545	* @}
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547
<>	144:ef7eb2e8f9f7	548	/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
<>	144:ef7eb2e8f9f7	549	* @{
<>	144:ef7eb2e8f9f7	550	*/
<>	144:ef7eb2e8f9f7	551	#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	552	#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
<>	144:ef7eb2e8f9f7	553	/**
<>	144:ef7eb2e8f9f7	554	* @}
<>	144:ef7eb2e8f9f7	555	*/
<>	144:ef7eb2e8f9f7	556	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	559	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
<>	144:ef7eb2e8f9f7	560	* @{
<>	144:ef7eb2e8f9f7	561	*/
<>	144:ef7eb2e8f9f7	562	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	563	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
<>	144:ef7eb2e8f9f7	564	/**
<>	144:ef7eb2e8f9f7	565	* @}
<>	144:ef7eb2e8f9f7	566	*/
<>	144:ef7eb2e8f9f7	567	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/**
<>	144:ef7eb2e8f9f7	570	* @}
<>	144:ef7eb2e8f9f7	571	*/
<>	144:ef7eb2e8f9f7	572
<>	144:ef7eb2e8f9f7	573	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	574	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
<>	144:ef7eb2e8f9f7	575	* @{
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
<>	144:ef7eb2e8f9f7	578	* @brief Enables or disables the AHB/APB peripheral clock.
<>	144:ef7eb2e8f9f7	579	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	580	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	581	* using it.
<>	144:ef7eb2e8f9f7	582	* @{
<>	144:ef7eb2e8f9f7	583	*/
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	/** @brief Enables or disables the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	586	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	587	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	588	* using it.
<>	144:ef7eb2e8f9f7	589	*/
<>	144:ef7eb2e8f9f7	590	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	591	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	592	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<>	144:ef7eb2e8f9f7	593	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	594	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
<>	144:ef7eb2e8f9f7	595	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	596	} while(0)
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	599	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	600	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
<>	144:ef7eb2e8f9f7	601	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	602	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
<>	144:ef7eb2e8f9f7	603	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	604	} while(0)
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	607	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	608	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	609	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	610	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
<>	144:ef7eb2e8f9f7	611	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	612	} while(0)
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	615	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	616	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<>	144:ef7eb2e8f9f7	617	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	618	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
<>	144:ef7eb2e8f9f7	619	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	620	} while(0)
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	623	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	624	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<>	144:ef7eb2e8f9f7	625	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	626	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
<>	144:ef7eb2e8f9f7	627	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	628	} while(0)
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	631	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	632	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<>	144:ef7eb2e8f9f7	633	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	634	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
<>	144:ef7eb2e8f9f7	635	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	636	} while(0)
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	639	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	640	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	641	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	642	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	643	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	644	} while(0)
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	647	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	648	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	649	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	650	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	651	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	652	} while(0)
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	655	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	656	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	657	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	658	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	659	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	660	} while(0)
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	663	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	664	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<>	144:ef7eb2e8f9f7	665	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	666	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
<>	144:ef7eb2e8f9f7	667	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	668	} while(0)
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	671	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	672	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<>	144:ef7eb2e8f9f7	673	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	674	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
<>	144:ef7eb2e8f9f7	675	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	676	} while(0)
<>	144:ef7eb2e8f9f7	677
<>	144:ef7eb2e8f9f7	678	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	679	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	680	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<>	144:ef7eb2e8f9f7	681	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	682	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
<>	144:ef7eb2e8f9f7	683	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	684	} while(0)
<>	144:ef7eb2e8f9f7	685
<>	144:ef7eb2e8f9f7	686	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	687	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	688	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<>	144:ef7eb2e8f9f7	689	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	690	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
<>	144:ef7eb2e8f9f7	691	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	692	} while(0)
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	695	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	696	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	697	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	698	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	699	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	700	} while(0)
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	703	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	704	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<>	144:ef7eb2e8f9f7	705	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	706	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
<>	144:ef7eb2e8f9f7	707	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	708	} while(0)
<>	144:ef7eb2e8f9f7	709
<>	144:ef7eb2e8f9f7	710	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	711	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	712	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
<>	144:ef7eb2e8f9f7	713	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	714	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
<>	144:ef7eb2e8f9f7	715	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	716	} while(0)
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	719	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	720	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
<>	144:ef7eb2e8f9f7	721	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	722	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
<>	144:ef7eb2e8f9f7	723	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	724	} while(0)
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
<>	144:ef7eb2e8f9f7	727	#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
<>	144:ef7eb2e8f9f7	728	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
<>	144:ef7eb2e8f9f7	729	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
<>	144:ef7eb2e8f9f7	730	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
<>	144:ef7eb2e8f9f7	731	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
<>	144:ef7eb2e8f9f7	732	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
<>	144:ef7eb2e8f9f7	733	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
<>	144:ef7eb2e8f9f7	734	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
<>	144:ef7eb2e8f9f7	735	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
<>	144:ef7eb2e8f9f7	736	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
<>	144:ef7eb2e8f9f7	737	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
<>	144:ef7eb2e8f9f7	738	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
<>	144:ef7eb2e8f9f7	739	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
<>	144:ef7eb2e8f9f7	740	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
<>	144:ef7eb2e8f9f7	741	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
<>	144:ef7eb2e8f9f7	742	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
<>	144:ef7eb2e8f9f7	743	/**
<>	144:ef7eb2e8f9f7	744	* @brief Enable ETHERNET clock.
<>	144:ef7eb2e8f9f7	745	*/
<>	144:ef7eb2e8f9f7	746	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	747	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	748	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<>	144:ef7eb2e8f9f7	749	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	750	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
<>	144:ef7eb2e8f9f7	751	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	752	} while(0)
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	755	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	756	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<>	144:ef7eb2e8f9f7	757	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	758	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
<>	144:ef7eb2e8f9f7	759	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	760	} while(0)
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	763	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	764	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<>	144:ef7eb2e8f9f7	765	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	766	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
<>	144:ef7eb2e8f9f7	767	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	768	} while(0)
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	771	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	772	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<>	144:ef7eb2e8f9f7	773	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	774	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
<>	144:ef7eb2e8f9f7	775	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	776	} while(0)
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	779	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
<>	144:ef7eb2e8f9f7	780	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
<>	144:ef7eb2e8f9f7	781	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
<>	144:ef7eb2e8f9f7	782	} while(0)
<>	144:ef7eb2e8f9f7	783	/**
<>	144:ef7eb2e8f9f7	784	* @brief Disable ETHERNET clock.
<>	144:ef7eb2e8f9f7	785	*/
<>	144:ef7eb2e8f9f7	786	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
<>	144:ef7eb2e8f9f7	787	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
<>	144:ef7eb2e8f9f7	788	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
<>	144:ef7eb2e8f9f7	789	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
<>	144:ef7eb2e8f9f7	790	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
<>	144:ef7eb2e8f9f7	791	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
<>	144:ef7eb2e8f9f7	792	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
<>	144:ef7eb2e8f9f7	793	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
<>	144:ef7eb2e8f9f7	794	} while(0)
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/** @brief Enable or disable the AHB2 peripheral clock.
<>	144:ef7eb2e8f9f7	797	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	798	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	799	* using it.
<>	144:ef7eb2e8f9f7	800	*/
<>	144:ef7eb2e8f9f7	801	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	802	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	803	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<>	144:ef7eb2e8f9f7	804	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	805	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
<>	144:ef7eb2e8f9f7	806	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	807	} while(0)
<>	144:ef7eb2e8f9f7	808
<>	144:ef7eb2e8f9f7	809	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	810	#define __HAL_RCC_JPEG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	811	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	812	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
<>	144:ef7eb2e8f9f7	813	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	814	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
<>	144:ef7eb2e8f9f7	815	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	816	} while(0)
<>	144:ef7eb2e8f9f7	817	#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
<>	144:ef7eb2e8f9f7	818	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	819
<>	144:ef7eb2e8f9f7	820	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	821	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	822	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<>	144:ef7eb2e8f9f7	823	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	824	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
<>	144:ef7eb2e8f9f7	825	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	826	} while(0)
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	829	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	830	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
<>	144:ef7eb2e8f9f7	831	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	832	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
<>	144:ef7eb2e8f9f7	833	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	834	__HAL_RCC_SYSCFG_CLK_ENABLE();\
<>	144:ef7eb2e8f9f7	835	} while(0)
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
<>	144:ef7eb2e8f9f7	838	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
<>	144:ef7eb2e8f9f7	841	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	842	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	843	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	844	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<>	144:ef7eb2e8f9f7	845	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	846	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
<>	144:ef7eb2e8f9f7	847	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	848	} while(0)
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	851	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	852	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<>	144:ef7eb2e8f9f7	853	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	854	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
<>	144:ef7eb2e8f9f7	855	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	856	} while(0)
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
<>	144:ef7eb2e8f9f7	859	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
<>	144:ef7eb2e8f9f7	860	#endif /* STM32F756x \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862	/** @brief Enables or disables the AHB3 peripheral clock.
<>	144:ef7eb2e8f9f7	863	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	864	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	865	* using it.
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	868	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	869	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
<>	144:ef7eb2e8f9f7	870	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	871	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
<>	144:ef7eb2e8f9f7	872	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	873	} while(0)
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	876	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	877	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
<>	144:ef7eb2e8f9f7	878	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	879	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
<>	144:ef7eb2e8f9f7	880	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	881	} while(0)
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
<>	144:ef7eb2e8f9f7	884	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	887	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	888	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	889	* using it.
<>	144:ef7eb2e8f9f7	890	*/
<>	144:ef7eb2e8f9f7	891	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	892	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	893	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	894	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	895	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
<>	144:ef7eb2e8f9f7	896	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	897	} while(0)
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	900	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	901	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	902	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	903	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
<>	144:ef7eb2e8f9f7	904	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	905	} while(0)
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	908	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	909	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<>	144:ef7eb2e8f9f7	910	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	911	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<>	144:ef7eb2e8f9f7	912	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	913	} while(0)
<>	144:ef7eb2e8f9f7	914
<>	144:ef7eb2e8f9f7	915	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	916	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	917	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	918	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	919	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<>	144:ef7eb2e8f9f7	920	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	921	} while(0)
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	924	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	925	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<>	144:ef7eb2e8f9f7	926	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	927	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<>	144:ef7eb2e8f9f7	928	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	929	} while(0)
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	932	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	933	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<>	144:ef7eb2e8f9f7	934	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	935	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<>	144:ef7eb2e8f9f7	936	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	937	} while(0)
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	940	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	941	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<>	144:ef7eb2e8f9f7	942	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	943	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<>	144:ef7eb2e8f9f7	944	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	945	} while(0)
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	948	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	949	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<>	144:ef7eb2e8f9f7	950	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	951	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<>	144:ef7eb2e8f9f7	952	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	953	} while(0)
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	956	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	957	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<>	144:ef7eb2e8f9f7	958	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	959	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<>	144:ef7eb2e8f9f7	960	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	961	} while(0)
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	964	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	965	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
<>	144:ef7eb2e8f9f7	966	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	967	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
<>	144:ef7eb2e8f9f7	968	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	969	} while(0)
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	972	#define __HAL_RCC_RTC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	973	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	974	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
<>	144:ef7eb2e8f9f7	975	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	976	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
<>	144:ef7eb2e8f9f7	977	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	978	} while(0)
<>	144:ef7eb2e8f9f7	979
<>	144:ef7eb2e8f9f7	980	#define __HAL_RCC_CAN3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	981	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	982	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
<>	144:ef7eb2e8f9f7	983	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	984	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
<>	144:ef7eb2e8f9f7	985	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	986	} while(0)
<>	144:ef7eb2e8f9f7	987	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	990	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	991	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	992	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	993	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<>	144:ef7eb2e8f9f7	994	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	995	} while(0)
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	998	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	999	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<>	144:ef7eb2e8f9f7	1000	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1001	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<>	144:ef7eb2e8f9f7	1002	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1003	} while(0)
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1006	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<>	144:ef7eb2e8f9f7	1008	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
<>	144:ef7eb2e8f9f7	1010	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1011	} while(0)
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1014	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1015	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	1016	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1017	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
<>	144:ef7eb2e8f9f7	1018	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1019	} while(0)
<>	144:ef7eb2e8f9f7	1020
<>	144:ef7eb2e8f9f7	1021	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1022	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<>	144:ef7eb2e8f9f7	1024	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<>	144:ef7eb2e8f9f7	1026	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1027	} while(0)
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1030	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1031	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<>	144:ef7eb2e8f9f7	1032	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1033	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<>	144:ef7eb2e8f9f7	1034	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1035	} while(0)
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1038	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1039	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<>	144:ef7eb2e8f9f7	1040	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1041	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<>	144:ef7eb2e8f9f7	1042	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1043	} while(0)
<>	144:ef7eb2e8f9f7	1044
<>	144:ef7eb2e8f9f7	1045	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1046	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1047	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	1048	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1049	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
<>	144:ef7eb2e8f9f7	1050	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1051	} while(0)
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1054	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1055	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	1056	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1057	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<>	144:ef7eb2e8f9f7	1058	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1059	} while(0)
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1062	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1063	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<>	144:ef7eb2e8f9f7	1064	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1065	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
<>	144:ef7eb2e8f9f7	1066	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1067	} while(0)
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1070	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1071	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<>	144:ef7eb2e8f9f7	1072	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1073	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
<>	144:ef7eb2e8f9f7	1074	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1075	} while(0)
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1078	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1079	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<>	144:ef7eb2e8f9f7	1080	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1081	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<>	144:ef7eb2e8f9f7	1082	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1083	} while(0)
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1086	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1087	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<>	144:ef7eb2e8f9f7	1088	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1089	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<>	144:ef7eb2e8f9f7	1090	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1091	} while(0)
<>	144:ef7eb2e8f9f7	1092
<>	144:ef7eb2e8f9f7	1093	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1094	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1095	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<>	144:ef7eb2e8f9f7	1096	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1097	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<>	144:ef7eb2e8f9f7	1098	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1099	} while(0)
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1102	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1103	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<>	144:ef7eb2e8f9f7	1104	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1105	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<>	144:ef7eb2e8f9f7	1106	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1107	} while(0)
<>	144:ef7eb2e8f9f7	1108
<>	144:ef7eb2e8f9f7	1109	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1110	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1111	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
<>	144:ef7eb2e8f9f7	1112	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1113	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
<>	144:ef7eb2e8f9f7	1114	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1115	} while(0)
<>	144:ef7eb2e8f9f7	1116
<>	144:ef7eb2e8f9f7	1117	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1118	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1119	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
<>	144:ef7eb2e8f9f7	1120	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1121	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
<>	144:ef7eb2e8f9f7	1122	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1123	} while(0)
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
<>	144:ef7eb2e8f9f7	1126	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
<>	144:ef7eb2e8f9f7	1127	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<>	144:ef7eb2e8f9f7	1128	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<>	144:ef7eb2e8f9f7	1129	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<>	144:ef7eb2e8f9f7	1130	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<>	144:ef7eb2e8f9f7	1131	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<>	144:ef7eb2e8f9f7	1132	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<>	144:ef7eb2e8f9f7	1133	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<>	144:ef7eb2e8f9f7	1134	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
<>	144:ef7eb2e8f9f7	1135	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1136	#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
<>	144:ef7eb2e8f9f7	1137	#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
<>	144:ef7eb2e8f9f7	1138	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1139	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<>	144:ef7eb2e8f9f7	1140	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<>	144:ef7eb2e8f9f7	1141	#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
<>	144:ef7eb2e8f9f7	1142	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
<>	144:ef7eb2e8f9f7	1143	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<>	144:ef7eb2e8f9f7	1144	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<>	144:ef7eb2e8f9f7	1145	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<>	144:ef7eb2e8f9f7	1146	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
<>	144:ef7eb2e8f9f7	1147	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<>	144:ef7eb2e8f9f7	1148	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
<>	144:ef7eb2e8f9f7	1149	#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
<>	144:ef7eb2e8f9f7	1150	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<>	144:ef7eb2e8f9f7	1151	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<>	144:ef7eb2e8f9f7	1152	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<>	144:ef7eb2e8f9f7	1153	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<>	144:ef7eb2e8f9f7	1154	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
<>	144:ef7eb2e8f9f7	1155	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
<>	144:ef7eb2e8f9f7	1156
<>	144:ef7eb2e8f9f7	1157	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	1158	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1159	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1160	* using it.
<>	144:ef7eb2e8f9f7	1161	*/
<>	144:ef7eb2e8f9f7	1162	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1163	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1164	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	1165	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1166	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
<>	144:ef7eb2e8f9f7	1167	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1168	} while(0)
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1171	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1172	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<>	144:ef7eb2e8f9f7	1173	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1174	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<>	144:ef7eb2e8f9f7	1175	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1176	} while(0)
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1179	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1180	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	1181	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1182	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
<>	144:ef7eb2e8f9f7	1183	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1184	} while(0)
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1187	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1188	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	1189	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1190	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
<>	144:ef7eb2e8f9f7	1191	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1192	} while(0)
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1195	#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1196	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1197	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
<>	144:ef7eb2e8f9f7	1198	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1199	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
<>	144:ef7eb2e8f9f7	1200	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1201	} while(0)
<>	144:ef7eb2e8f9f7	1202	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1205	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1206	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	1207	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1208	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
<>	144:ef7eb2e8f9f7	1209	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1210	} while(0)
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1213	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1214	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<>	144:ef7eb2e8f9f7	1215	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1216	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<>	144:ef7eb2e8f9f7	1217	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1218	} while(0)
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1221	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1222	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<>	144:ef7eb2e8f9f7	1223	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1224	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<>	144:ef7eb2e8f9f7	1225	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1226	} while(0)
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1229	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1230	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
<>	144:ef7eb2e8f9f7	1231	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1232	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
<>	144:ef7eb2e8f9f7	1233	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1234	} while(0)
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1237	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1238	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	1239	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1240	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
<>	144:ef7eb2e8f9f7	1241	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1242	} while(0)
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1245	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
<>	144:ef7eb2e8f9f7	1247	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
<>	144:ef7eb2e8f9f7	1249	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1250	} while(0)
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1253	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	1255	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<>	144:ef7eb2e8f9f7	1257	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1258	} while(0)
<>	144:ef7eb2e8f9f7	1259
<>	144:ef7eb2e8f9f7	1260	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1261	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1262	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<>	144:ef7eb2e8f9f7	1263	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1264	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<>	144:ef7eb2e8f9f7	1265	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1266	} while(0)
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1269	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1270	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	1271	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1272	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<>	144:ef7eb2e8f9f7	1273	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1274	} while(0)
<>	144:ef7eb2e8f9f7	1275
<>	144:ef7eb2e8f9f7	1276	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1277	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1278	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
<>	144:ef7eb2e8f9f7	1279	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1280	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
<>	144:ef7eb2e8f9f7	1281	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1282	} while(0)
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1285	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1286	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
<>	144:ef7eb2e8f9f7	1287	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1288	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
<>	144:ef7eb2e8f9f7	1289	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1290	} while(0)
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1293	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1294	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
<>	144:ef7eb2e8f9f7	1295	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1296	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
<>	144:ef7eb2e8f9f7	1297	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1298	} while(0)
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1301	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1302	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
<>	144:ef7eb2e8f9f7	1303	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1304	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
<>	144:ef7eb2e8f9f7	1305	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1306	} while(0)
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1309	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1310	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1311	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
<>	144:ef7eb2e8f9f7	1312	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1313	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
<>	144:ef7eb2e8f9f7	1314	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1315	} while(0)
<>	144:ef7eb2e8f9f7	1316	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1317
<>	144:ef7eb2e8f9f7	1318	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1319	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1320	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1321	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
<>	144:ef7eb2e8f9f7	1322	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1323	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
<>	144:ef7eb2e8f9f7	1324	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1325	} while(0)
<>	144:ef7eb2e8f9f7	1326	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1329	#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1330	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1331	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
<>	144:ef7eb2e8f9f7	1332	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1333	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
<>	144:ef7eb2e8f9f7	1334	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1335	} while(0)
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	#define __HAL_RCC_MDIO_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	1338	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1339	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
<>	144:ef7eb2e8f9f7	1340	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	1341	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
<>	144:ef7eb2e8f9f7	1342	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1343	} while(0)
<>	144:ef7eb2e8f9f7	1344	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1345
<>	144:ef7eb2e8f9f7	1346	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
<>	144:ef7eb2e8f9f7	1347	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
<>	144:ef7eb2e8f9f7	1348	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
<>	144:ef7eb2e8f9f7	1349	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
<>	144:ef7eb2e8f9f7	1350	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1351	#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
<>	144:ef7eb2e8f9f7	1352	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1353	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
<>	144:ef7eb2e8f9f7	1354	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
<>	144:ef7eb2e8f9f7	1355	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
<>	144:ef7eb2e8f9f7	1356	#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
<>	144:ef7eb2e8f9f7	1357	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
<>	144:ef7eb2e8f9f7	1358	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
<>	144:ef7eb2e8f9f7	1359	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<>	144:ef7eb2e8f9f7	1360	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
<>	144:ef7eb2e8f9f7	1361	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<>	144:ef7eb2e8f9f7	1362	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
<>	144:ef7eb2e8f9f7	1363	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
<>	144:ef7eb2e8f9f7	1364	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
<>	144:ef7eb2e8f9f7	1365	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
<>	144:ef7eb2e8f9f7	1366	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1367	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
<>	144:ef7eb2e8f9f7	1368	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1369	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1370	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
<>	144:ef7eb2e8f9f7	1371	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1372	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1373	#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
<>	144:ef7eb2e8f9f7	1374	#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
<>	144:ef7eb2e8f9f7	1375	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/**
<>	144:ef7eb2e8f9f7	1378	* @}
<>	144:ef7eb2e8f9f7	1379	*/
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381
<>	144:ef7eb2e8f9f7	1382	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
<>	144:ef7eb2e8f9f7	1383	* @brief Get the enable or disable status of the AHB/APB peripheral clock.
<>	144:ef7eb2e8f9f7	1384	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1385	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1386	* using it.
<>	144:ef7eb2e8f9f7	1387	* @{
<>	144:ef7eb2e8f9f7	1388	*/
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	/** @brief Get the enable or disable status of the AHB1 peripheral clock.
<>	144:ef7eb2e8f9f7	1391	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1392	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1393	* using it.
<>	144:ef7eb2e8f9f7	1394	*/
<>	144:ef7eb2e8f9f7	1395	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
<>	144:ef7eb2e8f9f7	1396	#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
<>	144:ef7eb2e8f9f7	1397	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1398	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
<>	144:ef7eb2e8f9f7	1399	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
<>	144:ef7eb2e8f9f7	1400	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
<>	144:ef7eb2e8f9f7	1401	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
<>	144:ef7eb2e8f9f7	1402	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
<>	144:ef7eb2e8f9f7	1403	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
<>	144:ef7eb2e8f9f7	1404	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
<>	144:ef7eb2e8f9f7	1405	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
<>	144:ef7eb2e8f9f7	1406	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
<>	144:ef7eb2e8f9f7	1407	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
<>	144:ef7eb2e8f9f7	1408	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
<>	144:ef7eb2e8f9f7	1409	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
<>	144:ef7eb2e8f9f7	1410	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
<>	144:ef7eb2e8f9f7	1411	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
<>	144:ef7eb2e8f9f7	1414	#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
<>	144:ef7eb2e8f9f7	1415	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1416	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
<>	144:ef7eb2e8f9f7	1417	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
<>	144:ef7eb2e8f9f7	1418	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
<>	144:ef7eb2e8f9f7	1419	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
<>	144:ef7eb2e8f9f7	1420	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
<>	144:ef7eb2e8f9f7	1421	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
<>	144:ef7eb2e8f9f7	1422	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
<>	144:ef7eb2e8f9f7	1423	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
<>	144:ef7eb2e8f9f7	1424	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
<>	144:ef7eb2e8f9f7	1425	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
<>	144:ef7eb2e8f9f7	1426	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
<>	144:ef7eb2e8f9f7	1427	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
<>	144:ef7eb2e8f9f7	1428	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
<>	144:ef7eb2e8f9f7	1429	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
<>	144:ef7eb2e8f9f7	1430	/**
<>	144:ef7eb2e8f9f7	1431	* @brief Enable ETHERNET clock.
<>	144:ef7eb2e8f9f7	1432	*/
<>	144:ef7eb2e8f9f7	1433	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
<>	144:ef7eb2e8f9f7	1434	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
<>	144:ef7eb2e8f9f7	1435	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
<>	144:ef7eb2e8f9f7	1436	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
<>	144:ef7eb2e8f9f7	1437	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
<>	144:ef7eb2e8f9f7	1438	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
<>	144:ef7eb2e8f9f7	1439	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/**
<>	144:ef7eb2e8f9f7	1442	* @brief Disable ETHERNET clock.
<>	144:ef7eb2e8f9f7	1443	*/
<>	144:ef7eb2e8f9f7	1444	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
<>	144:ef7eb2e8f9f7	1445	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
<>	144:ef7eb2e8f9f7	1446	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
<>	144:ef7eb2e8f9f7	1447	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
<>	144:ef7eb2e8f9f7	1448	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
<>	144:ef7eb2e8f9f7	1449	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
<>	144:ef7eb2e8f9f7	1450	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	/** @brief Get the enable or disable status of the AHB2 peripheral clock.
<>	144:ef7eb2e8f9f7	1453	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1454	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1455	* using it.
<>	144:ef7eb2e8f9f7	1456	*/
<>	144:ef7eb2e8f9f7	1457	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
<>	144:ef7eb2e8f9f7	1458	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
<>	144:ef7eb2e8f9f7	1459	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
<>	144:ef7eb2e8f9f7	1462	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
<>	144:ef7eb2e8f9f7	1463	#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1466	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
<>	144:ef7eb2e8f9f7	1467	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
<>	144:ef7eb2e8f9f7	1468	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
<>	144:ef7eb2e8f9f7	1469	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
<>	144:ef7eb2e8f9f7	1470	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1471
<>	144:ef7eb2e8f9f7	1472	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1473	#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
<>	144:ef7eb2e8f9f7	1474	#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
<>	144:ef7eb2e8f9f7	1475	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1476
<>	144:ef7eb2e8f9f7	1477	/** @brief Get the enable or disable status of the AHB3 peripheral clock.
<>	144:ef7eb2e8f9f7	1478	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1479	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1480	* using it.
<>	144:ef7eb2e8f9f7	1481	*/
<>	144:ef7eb2e8f9f7	1482	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
<>	144:ef7eb2e8f9f7	1483	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
<>	144:ef7eb2e8f9f7	1484
<>	144:ef7eb2e8f9f7	1485	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
<>	144:ef7eb2e8f9f7	1486	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
<>	144:ef7eb2e8f9f7	1487
<>	144:ef7eb2e8f9f7	1488	/** @brief Get the enable or disable status of the APB1 peripheral clock.
<>	144:ef7eb2e8f9f7	1489	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1490	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1491	* using it.
<>	144:ef7eb2e8f9f7	1492	*/
<>	144:ef7eb2e8f9f7	1493	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1494	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1495	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<>	144:ef7eb2e8f9f7	1496	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
<>	144:ef7eb2e8f9f7	1497	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<>	144:ef7eb2e8f9f7	1498	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<>	144:ef7eb2e8f9f7	1499	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<>	144:ef7eb2e8f9f7	1500	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<>	144:ef7eb2e8f9f7	1501	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<>	144:ef7eb2e8f9f7	1502	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1503	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1504	#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
<>	144:ef7eb2e8f9f7	1505	#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1506	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1507	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1508	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1509	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
<>	144:ef7eb2e8f9f7	1510	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1511	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1512	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<>	144:ef7eb2e8f9f7	1513	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<>	144:ef7eb2e8f9f7	1514	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1515	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1516	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1517	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
<>	144:ef7eb2e8f9f7	1518	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1519	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1520	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<>	144:ef7eb2e8f9f7	1521	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<>	144:ef7eb2e8f9f7	1522	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
<>	144:ef7eb2e8f9f7	1523	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1526	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1527	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
<>	144:ef7eb2e8f9f7	1528	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
<>	144:ef7eb2e8f9f7	1529	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<>	144:ef7eb2e8f9f7	1530	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<>	144:ef7eb2e8f9f7	1531	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
<>	144:ef7eb2e8f9f7	1532	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
<>	144:ef7eb2e8f9f7	1533	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
<>	144:ef7eb2e8f9f7	1534	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1535	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1536	#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
<>	144:ef7eb2e8f9f7	1537	#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1538	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1539	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1540	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1541	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
<>	144:ef7eb2e8f9f7	1542	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1543	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1544	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
<>	144:ef7eb2e8f9f7	1545	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
<>	144:ef7eb2e8f9f7	1546	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1547	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1548	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1549	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
<>	144:ef7eb2e8f9f7	1550	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1551	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1552	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<>	144:ef7eb2e8f9f7	1553	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
<>	144:ef7eb2e8f9f7	1554	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
<>	144:ef7eb2e8f9f7	1555	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/** @brief Get the enable or disable status of the APB2 peripheral clock.
<>	144:ef7eb2e8f9f7	1558	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	1559	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	1560	* using it.
<>	144:ef7eb2e8f9f7	1561	*/
<>	144:ef7eb2e8f9f7	1562	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1563	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
<>	144:ef7eb2e8f9f7	1564	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1565	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
<>	144:ef7eb2e8f9f7	1566	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1567	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1568	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
<>	144:ef7eb2e8f9f7	1569	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1570	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1571	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
<>	144:ef7eb2e8f9f7	1572	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
<>	144:ef7eb2e8f9f7	1573	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
<>	144:ef7eb2e8f9f7	1574	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
<>	144:ef7eb2e8f9f7	1575	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
<>	144:ef7eb2e8f9f7	1576	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
<>	144:ef7eb2e8f9f7	1577	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1578	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1579	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1580	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
<>	144:ef7eb2e8f9f7	1581	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1582	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1583	#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
<>	144:ef7eb2e8f9f7	1584	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1585	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1586	#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
<>	144:ef7eb2e8f9f7	1587	#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
<>	144:ef7eb2e8f9f7	1588	#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
<>	144:ef7eb2e8f9f7	1589	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1590	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1591	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
<>	144:ef7eb2e8f9f7	1592	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1593	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
<>	144:ef7eb2e8f9f7	1594	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1595	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1596	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
<>	144:ef7eb2e8f9f7	1597	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1598	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1599	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
<>	144:ef7eb2e8f9f7	1600	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
<>	144:ef7eb2e8f9f7	1601	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
<>	144:ef7eb2e8f9f7	1602	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
<>	144:ef7eb2e8f9f7	1603	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
<>	144:ef7eb2e8f9f7	1604	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
<>	144:ef7eb2e8f9f7	1605	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1606	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1607	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1608	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
<>	144:ef7eb2e8f9f7	1609	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1610	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1611	#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
<>	144:ef7eb2e8f9f7	1612	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1613	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1614	#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
<>	144:ef7eb2e8f9f7	1615	#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
<>	144:ef7eb2e8f9f7	1616	#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
<>	144:ef7eb2e8f9f7	1617	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1618	/**
<>	144:ef7eb2e8f9f7	1619	* @}
<>	144:ef7eb2e8f9f7	1620	*/
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
<>	144:ef7eb2e8f9f7	1623	* @brief Forces or releases AHB/APB peripheral reset.
<>	144:ef7eb2e8f9f7	1624	* @{
<>	144:ef7eb2e8f9f7	1625	*/
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	/** @brief Force or release AHB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1628	*/
<>	144:ef7eb2e8f9f7	1629	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	1630	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
<>	144:ef7eb2e8f9f7	1631	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
<>	144:ef7eb2e8f9f7	1632	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
<>	144:ef7eb2e8f9f7	1633	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	1634	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	1635	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	1636	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
<>	144:ef7eb2e8f9f7	1637	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
<>	144:ef7eb2e8f9f7	1638	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
<>	144:ef7eb2e8f9f7	1639	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
<>	144:ef7eb2e8f9f7	1640	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	1641	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
<>	144:ef7eb2e8f9f7	1642	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
<>	144:ef7eb2e8f9f7	1643	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
<>	144:ef7eb2e8f9f7	1646	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
<>	144:ef7eb2e8f9f7	1647	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
<>	144:ef7eb2e8f9f7	1648	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
<>	144:ef7eb2e8f9f7	1649	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	1650	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	1651	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	1652	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
<>	144:ef7eb2e8f9f7	1653	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
<>	144:ef7eb2e8f9f7	1654	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
<>	144:ef7eb2e8f9f7	1655	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
<>	144:ef7eb2e8f9f7	1656	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	1657	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
<>	144:ef7eb2e8f9f7	1658	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
<>	144:ef7eb2e8f9f7	1659	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/** @brief Force or release AHB2 peripheral reset.
<>	144:ef7eb2e8f9f7	1662	*/
<>	144:ef7eb2e8f9f7	1663	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1664	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
<>	144:ef7eb2e8f9f7	1665	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
<>	144:ef7eb2e8f9f7	1666	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
<>	144:ef7eb2e8f9f7	1667
<>	144:ef7eb2e8f9f7	1668	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1669	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
<>	144:ef7eb2e8f9f7	1670	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
<>	144:ef7eb2e8f9f7	1671	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1674	#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_JPEGRST))
<>	144:ef7eb2e8f9f7	1675	#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
<>	144:ef7eb2e8f9f7	1676	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1677
<>	144:ef7eb2e8f9f7	1678	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1679	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
<>	144:ef7eb2e8f9f7	1680	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
<>	144:ef7eb2e8f9f7	1681	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
<>	144:ef7eb2e8f9f7	1682	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
<>	144:ef7eb2e8f9f7	1683	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1684
<>	144:ef7eb2e8f9f7	1685	/** @brief Force or release AHB3 peripheral reset
<>	144:ef7eb2e8f9f7	1686	*/
<>	144:ef7eb2e8f9f7	1687	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
<>	144:ef7eb2e8f9f7	1688	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
<>	144:ef7eb2e8f9f7	1689	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
<>	144:ef7eb2e8f9f7	1690
<>	144:ef7eb2e8f9f7	1691	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
<>	144:ef7eb2e8f9f7	1692	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
<>	144:ef7eb2e8f9f7	1693	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/** @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	1696	*/
<>	144:ef7eb2e8f9f7	1697	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	1698	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	1699	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
<>	144:ef7eb2e8f9f7	1700	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	1701	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
<>	144:ef7eb2e8f9f7	1702	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
<>	144:ef7eb2e8f9f7	1703	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
<>	144:ef7eb2e8f9f7	1704	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
<>	144:ef7eb2e8f9f7	1705	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
<>	144:ef7eb2e8f9f7	1706	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
<>	144:ef7eb2e8f9f7	1707	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1708	#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN3RST))
<>	144:ef7eb2e8f9f7	1709	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1710	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	1711	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
<>	144:ef7eb2e8f9f7	1712	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
<>	144:ef7eb2e8f9f7	1713	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	1714	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
<>	144:ef7eb2e8f9f7	1715	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
<>	144:ef7eb2e8f9f7	1716	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
<>	144:ef7eb2e8f9f7	1717	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	1718	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	1719	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
<>	144:ef7eb2e8f9f7	1720	#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C4RST))
<>	144:ef7eb2e8f9f7	1721	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
<>	144:ef7eb2e8f9f7	1722	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
<>	144:ef7eb2e8f9f7	1723	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
<>	144:ef7eb2e8f9f7	1724	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
<>	144:ef7eb2e8f9f7	1725	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
<>	144:ef7eb2e8f9f7	1726	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
<>	144:ef7eb2e8f9f7	1729	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
<>	144:ef7eb2e8f9f7	1730	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<>	144:ef7eb2e8f9f7	1731	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<>	144:ef7eb2e8f9f7	1732	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<>	144:ef7eb2e8f9f7	1733	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<>	144:ef7eb2e8f9f7	1734	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
<>	144:ef7eb2e8f9f7	1735	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
<>	144:ef7eb2e8f9f7	1736	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<>	144:ef7eb2e8f9f7	1737	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
<>	144:ef7eb2e8f9f7	1738	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1739	#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
<>	144:ef7eb2e8f9f7	1740	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1741	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<>	144:ef7eb2e8f9f7	1742	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<>	144:ef7eb2e8f9f7	1743	#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
<>	144:ef7eb2e8f9f7	1744	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
<>	144:ef7eb2e8f9f7	1745	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<>	144:ef7eb2e8f9f7	1746	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<>	144:ef7eb2e8f9f7	1747	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<>	144:ef7eb2e8f9f7	1748	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
<>	144:ef7eb2e8f9f7	1749	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<>	144:ef7eb2e8f9f7	1750	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
<>	144:ef7eb2e8f9f7	1751	#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
<>	144:ef7eb2e8f9f7	1752	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<>	144:ef7eb2e8f9f7	1753	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
<>	144:ef7eb2e8f9f7	1754	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<>	144:ef7eb2e8f9f7	1755	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<>	144:ef7eb2e8f9f7	1756	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
<>	144:ef7eb2e8f9f7	1757	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
<>	144:ef7eb2e8f9f7	1758
<>	144:ef7eb2e8f9f7	1759	/** @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	1760	*/
<>	144:ef7eb2e8f9f7	1761	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	1762	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
<>	144:ef7eb2e8f9f7	1763	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	1764	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	1765	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	1766	#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC1RST))
<>	144:ef7eb2e8f9f7	1767	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	1768	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
<>	144:ef7eb2e8f9f7	1769	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	1770	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
<>	144:ef7eb2e8f9f7	1771	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	1772	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
<>	144:ef7eb2e8f9f7	1773	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
<>	144:ef7eb2e8f9f7	1774	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
<>	144:ef7eb2e8f9f7	1775	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
<>	144:ef7eb2e8f9f7	1776	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1777	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
<>	144:ef7eb2e8f9f7	1778	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
<>	144:ef7eb2e8f9f7	1781	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<>	144:ef7eb2e8f9f7	1782	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
<>	144:ef7eb2e8f9f7	1783	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
<>	144:ef7eb2e8f9f7	1784	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
<>	144:ef7eb2e8f9f7	1785	#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
<>	144:ef7eb2e8f9f7	1786	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
<>	144:ef7eb2e8f9f7	1787	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
<>	144:ef7eb2e8f9f7	1788	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<>	144:ef7eb2e8f9f7	1789	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
<>	144:ef7eb2e8f9f7	1790	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<>	144:ef7eb2e8f9f7	1791	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
<>	144:ef7eb2e8f9f7	1792	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
<>	144:ef7eb2e8f9f7	1793	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
<>	144:ef7eb2e8f9f7	1794	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
<>	144:ef7eb2e8f9f7	1795	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1796	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
<>	144:ef7eb2e8f9f7	1797	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1798
<>	144:ef7eb2e8f9f7	1799	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1800	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
<>	144:ef7eb2e8f9f7	1801	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
<>	144:ef7eb2e8f9f7	1802	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1803
<>	144:ef7eb2e8f9f7	1804	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1805	#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC2RST))
<>	144:ef7eb2e8f9f7	1806	#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DFSDM1RST))
<>	144:ef7eb2e8f9f7	1807	#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_MDIORST))
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
<>	144:ef7eb2e8f9f7	1810	#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
<>	144:ef7eb2e8f9f7	1811	#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
<>	144:ef7eb2e8f9f7	1812	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1813	/**
<>	144:ef7eb2e8f9f7	1814	* @}
<>	144:ef7eb2e8f9f7	1815	*/
<>	144:ef7eb2e8f9f7	1816
<>	144:ef7eb2e8f9f7	1817	/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	1818	* @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1819	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1820	* power consumption.
<>	144:ef7eb2e8f9f7	1821	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1822	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1823	* @{
<>	144:ef7eb2e8f9f7	1824	*/
<>	144:ef7eb2e8f9f7	1825
<>	144:ef7eb2e8f9f7	1826	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1827	*/
<>	144:ef7eb2e8f9f7	1828	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
<>	144:ef7eb2e8f9f7	1829	#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_AXILPEN))
<>	144:ef7eb2e8f9f7	1830	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
<>	144:ef7eb2e8f9f7	1831	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
<>	144:ef7eb2e8f9f7	1832	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
<>	144:ef7eb2e8f9f7	1833	#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DTCMLPEN))
<>	144:ef7eb2e8f9f7	1834	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	1835	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
<>	144:ef7eb2e8f9f7	1836	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
<>	144:ef7eb2e8f9f7	1837	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
<>	144:ef7eb2e8f9f7	1838	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
<>	144:ef7eb2e8f9f7	1839	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
<>	144:ef7eb2e8f9f7	1840	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
<>	144:ef7eb2e8f9f7	1841	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
<>	144:ef7eb2e8f9f7	1842	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	1843	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	1844	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	1845	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
<>	144:ef7eb2e8f9f7	1846	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
<>	144:ef7eb2e8f9f7	1847	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
<>	144:ef7eb2e8f9f7	1848	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
<>	144:ef7eb2e8f9f7	1849	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	1850	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
<>	144:ef7eb2e8f9f7	1851	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
<>	144:ef7eb2e8f9f7	1852	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
<>	144:ef7eb2e8f9f7	1853
<>	144:ef7eb2e8f9f7	1854	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
<>	144:ef7eb2e8f9f7	1855	#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
<>	144:ef7eb2e8f9f7	1856	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
<>	144:ef7eb2e8f9f7	1857	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
<>	144:ef7eb2e8f9f7	1858	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
<>	144:ef7eb2e8f9f7	1859	#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
<>	144:ef7eb2e8f9f7	1860	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
<>	144:ef7eb2e8f9f7	1861	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
<>	144:ef7eb2e8f9f7	1862	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
<>	144:ef7eb2e8f9f7	1863	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
<>	144:ef7eb2e8f9f7	1864	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
<>	144:ef7eb2e8f9f7	1865	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
<>	144:ef7eb2e8f9f7	1866	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
<>	144:ef7eb2e8f9f7	1867	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
<>	144:ef7eb2e8f9f7	1868	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
<>	144:ef7eb2e8f9f7	1869	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
<>	144:ef7eb2e8f9f7	1870	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
<>	144:ef7eb2e8f9f7	1871	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
<>	144:ef7eb2e8f9f7	1872	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
<>	144:ef7eb2e8f9f7	1873	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
<>	144:ef7eb2e8f9f7	1874	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
<>	144:ef7eb2e8f9f7	1875	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
<>	144:ef7eb2e8f9f7	1876	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
<>	144:ef7eb2e8f9f7	1877	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
<>	144:ef7eb2e8f9f7	1878	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
<>	144:ef7eb2e8f9f7	1879
<>	144:ef7eb2e8f9f7	1880	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1881	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1882	* power consumption.
<>	144:ef7eb2e8f9f7	1883	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1884	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1885	*/
<>	144:ef7eb2e8f9f7	1886	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
<>	144:ef7eb2e8f9f7	1887	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
<>	144:ef7eb2e8f9f7	1888
<>	144:ef7eb2e8f9f7	1889	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1890	#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_JPEGLPEN))
<>	144:ef7eb2e8f9f7	1891	#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
<>	144:ef7eb2e8f9f7	1892	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
<>	144:ef7eb2e8f9f7	1895	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
<>	144:ef7eb2e8f9f7	1896
<>	144:ef7eb2e8f9f7	1897	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
<>	144:ef7eb2e8f9f7	1898	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1901	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
<>	144:ef7eb2e8f9f7	1902	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
<>	144:ef7eb2e8f9f7	1903
<>	144:ef7eb2e8f9f7	1904	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
<>	144:ef7eb2e8f9f7	1905	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
<>	144:ef7eb2e8f9f7	1906	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1907
<>	144:ef7eb2e8f9f7	1908	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1909	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1910	* power consumption.
<>	144:ef7eb2e8f9f7	1911	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1912	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1913	*/
<>	144:ef7eb2e8f9f7	1914	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
<>	144:ef7eb2e8f9f7	1915	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
<>	144:ef7eb2e8f9f7	1916
<>	144:ef7eb2e8f9f7	1917	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
<>	144:ef7eb2e8f9f7	1918	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
<>	144:ef7eb2e8f9f7	1919
<>	144:ef7eb2e8f9f7	1920	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1921	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1922	* power consumption.
<>	144:ef7eb2e8f9f7	1923	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1924	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1925	*/
<>	144:ef7eb2e8f9f7	1926	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
<>	144:ef7eb2e8f9f7	1927	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
<>	144:ef7eb2e8f9f7	1928	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
<>	144:ef7eb2e8f9f7	1929	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	1930	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
<>	144:ef7eb2e8f9f7	1931	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
<>	144:ef7eb2e8f9f7	1932	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
<>	144:ef7eb2e8f9f7	1933	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
<>	144:ef7eb2e8f9f7	1934	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
<>	144:ef7eb2e8f9f7	1935	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
<>	144:ef7eb2e8f9f7	1936	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1937	#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCLPEN))
<>	144:ef7eb2e8f9f7	1938	#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN3LPEN))
<>	144:ef7eb2e8f9f7	1939	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1940	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	1941	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
<>	144:ef7eb2e8f9f7	1942	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
<>	144:ef7eb2e8f9f7	1943	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	1944	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
<>	144:ef7eb2e8f9f7	1945	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
<>	144:ef7eb2e8f9f7	1946	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
<>	144:ef7eb2e8f9f7	1947	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	1948	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	1949	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
<>	144:ef7eb2e8f9f7	1950	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C4LPEN))
<>	144:ef7eb2e8f9f7	1951	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
<>	144:ef7eb2e8f9f7	1952	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
<>	144:ef7eb2e8f9f7	1953	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
<>	144:ef7eb2e8f9f7	1954	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
<>	144:ef7eb2e8f9f7	1955	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
<>	144:ef7eb2e8f9f7	1956	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
<>	144:ef7eb2e8f9f7	1957
<>	144:ef7eb2e8f9f7	1958	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
<>	144:ef7eb2e8f9f7	1959	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
<>	144:ef7eb2e8f9f7	1960	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
<>	144:ef7eb2e8f9f7	1961	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
<>	144:ef7eb2e8f9f7	1962	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
<>	144:ef7eb2e8f9f7	1963	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
<>	144:ef7eb2e8f9f7	1964	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
<>	144:ef7eb2e8f9f7	1965	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
<>	144:ef7eb2e8f9f7	1966	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
<>	144:ef7eb2e8f9f7	1967	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
<>	144:ef7eb2e8f9f7	1968	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	1969	#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
<>	144:ef7eb2e8f9f7	1970	#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
<>	144:ef7eb2e8f9f7	1971	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1972	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
<>	144:ef7eb2e8f9f7	1973	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
<>	144:ef7eb2e8f9f7	1974	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
<>	144:ef7eb2e8f9f7	1975	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
<>	144:ef7eb2e8f9f7	1976	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
<>	144:ef7eb2e8f9f7	1977	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
<>	144:ef7eb2e8f9f7	1978	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
<>	144:ef7eb2e8f9f7	1979	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
<>	144:ef7eb2e8f9f7	1980	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
<>	144:ef7eb2e8f9f7	1981	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
<>	144:ef7eb2e8f9f7	1982	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
<>	144:ef7eb2e8f9f7	1983	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
<>	144:ef7eb2e8f9f7	1984	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
<>	144:ef7eb2e8f9f7	1985	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
<>	144:ef7eb2e8f9f7	1986	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
<>	144:ef7eb2e8f9f7	1987	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
<>	144:ef7eb2e8f9f7	1988	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	1991	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	1992	* power consumption.
<>	144:ef7eb2e8f9f7	1993	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	1994	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	1995	*/
<>	144:ef7eb2e8f9f7	1996	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	1997	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
<>	144:ef7eb2e8f9f7	1998	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	1999	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	2000	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	2001	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
<>	144:ef7eb2e8f9f7	2002	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
<>	144:ef7eb2e8f9f7	2003	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC1LPEN))
<>	144:ef7eb2e8f9f7	2004	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	2005	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
<>	144:ef7eb2e8f9f7	2006	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	2007	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
<>	144:ef7eb2e8f9f7	2008	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	2009	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
<>	144:ef7eb2e8f9f7	2010	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
<>	144:ef7eb2e8f9f7	2011	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
<>	144:ef7eb2e8f9f7	2012	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
<>	144:ef7eb2e8f9f7	2013	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2014	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
<>	144:ef7eb2e8f9f7	2015	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2016
<>	144:ef7eb2e8f9f7	2017	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
<>	144:ef7eb2e8f9f7	2018	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
<>	144:ef7eb2e8f9f7	2019	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
<>	144:ef7eb2e8f9f7	2020	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
<>	144:ef7eb2e8f9f7	2021	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
<>	144:ef7eb2e8f9f7	2022	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
<>	144:ef7eb2e8f9f7	2023	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
<>	144:ef7eb2e8f9f7	2024	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
<>	144:ef7eb2e8f9f7	2025	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
<>	144:ef7eb2e8f9f7	2026	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
<>	144:ef7eb2e8f9f7	2027	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
<>	144:ef7eb2e8f9f7	2028	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
<>	144:ef7eb2e8f9f7	2029	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
<>	144:ef7eb2e8f9f7	2030	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
<>	144:ef7eb2e8f9f7	2031	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
<>	144:ef7eb2e8f9f7	2032	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
<>	144:ef7eb2e8f9f7	2033	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
<>	144:ef7eb2e8f9f7	2034	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2035	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
<>	144:ef7eb2e8f9f7	2036	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2037	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2038	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
<>	144:ef7eb2e8f9f7	2039	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
<>	144:ef7eb2e8f9f7	2040	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2041	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2042	#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC2LPEN))
<>	144:ef7eb2e8f9f7	2043	#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DFSDM1LPEN))
<>	144:ef7eb2e8f9f7	2044	#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_MDIOLPEN))
<>	144:ef7eb2e8f9f7	2045
<>	144:ef7eb2e8f9f7	2046	#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
<>	144:ef7eb2e8f9f7	2047	#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
<>	144:ef7eb2e8f9f7	2048	#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
<>	144:ef7eb2e8f9f7	2049	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2050	/**
<>	144:ef7eb2e8f9f7	2051	* @}
<>	144:ef7eb2e8f9f7	2052	*/
<>	144:ef7eb2e8f9f7	2053
<>	144:ef7eb2e8f9f7	2054	/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
<>	144:ef7eb2e8f9f7	2055	* @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2056	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2057	* power consumption.
<>	144:ef7eb2e8f9f7	2058	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2059	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2060	* @{
<>	144:ef7eb2e8f9f7	2061	*/
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2064	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2065	* power consumption.
<>	144:ef7eb2e8f9f7	2066	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2067	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2068	*/
<>	144:ef7eb2e8f9f7	2069	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2070	#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2071	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2072	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2073	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2074	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2075	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2076	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2077	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2078	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2079	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2080	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2081	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2082	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2083	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2084	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2085	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2086	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2087	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2088	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2089	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2090	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2091	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2092	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2093	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2094
<>	144:ef7eb2e8f9f7	2095	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2096	#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2097	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2098	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2099	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2100	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2101	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2102	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2103	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2104	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2105	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2106	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2107	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2108	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2109	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2110	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2111	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2112	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2113	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2114	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2115	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2116	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2117	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2118	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2119	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2122	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2123	* power consumption.
<>	144:ef7eb2e8f9f7	2124	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2125	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2126	*/
<>	144:ef7eb2e8f9f7	2127	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2128	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2129
<>	144:ef7eb2e8f9f7	2130	#if defined(STM32F767xx) \|\| defined(STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2131	#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2132	#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2133	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2134
<>	144:ef7eb2e8f9f7	2135	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2136	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2137
<>	144:ef7eb2e8f9f7	2138	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2139	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2140
<>	144:ef7eb2e8f9f7	2141	#if defined(STM32F756xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2142	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2143	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2144
<>	144:ef7eb2e8f9f7	2145	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2146	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2147	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2148
<>	144:ef7eb2e8f9f7	2149	/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2150	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2151	* power consumption.
<>	144:ef7eb2e8f9f7	2152	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2153	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2154	*/
<>	144:ef7eb2e8f9f7	2155	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2156	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2157
<>	144:ef7eb2e8f9f7	2158	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2159	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2160
<>	144:ef7eb2e8f9f7	2161	/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2162	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2163	* power consumption.
<>	144:ef7eb2e8f9f7	2164	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2165	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2166	*/
<>	144:ef7eb2e8f9f7	2167	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2168	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2169	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2170	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2171	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2172	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2173	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2174	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2175	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2176	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2177	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2178	#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2179	#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2180	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2181	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2182	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2183	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2184	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2185	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2186	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2187	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2188	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2189	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2190	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2191	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2192	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2193	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2194	#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2195	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2196	#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2197	#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2198
<>	144:ef7eb2e8f9f7	2199	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2200	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2201	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2202	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2203	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2204	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2205	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2206	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2207	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2208	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2209	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2210	#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2211	#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2212	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2213	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2214	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2215	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2216	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2217	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2218	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2219	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2220	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2221	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2222	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2223	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2224	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2225	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2226	#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2227	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2228	#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2229	#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2230
<>	144:ef7eb2e8f9f7	2231	/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	2232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	2233	* power consumption.
<>	144:ef7eb2e8f9f7	2234	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	2235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	2236	*/
<>	144:ef7eb2e8f9f7	2237	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2238	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2239	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2240	#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2241	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2242	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2243	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2244	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2245	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2246	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2247	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2248	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2249	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2250	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2251	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2252	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2253	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2254	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2255	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2256	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2257	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2258	#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2259	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2260	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2261	#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2262	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2263	#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
<>	144:ef7eb2e8f9f7	2264	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2265
<>	144:ef7eb2e8f9f7	2266	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2267	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2268	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2269	#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2270	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2271	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2272	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2273	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2274	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2275	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2276	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2277	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2278	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2279	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2280	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2281	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2282	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2283	#if defined (STM32F746xx) \|\| defined (STM32F756xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2284	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2285	#endif /* STM32F746xx \|\| STM32F756xx \|\| STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2286	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2287	#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2288	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2289	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2290	#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2291	#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2292	#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
<>	144:ef7eb2e8f9f7	2293	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2294	/**
<>	144:ef7eb2e8f9f7	2295	* @}
<>	144:ef7eb2e8f9f7	2296	*/
<>	144:ef7eb2e8f9f7	2297
<>	144:ef7eb2e8f9f7	2298	/------------------------------- PLL Configuration --------------------------/
<>	144:ef7eb2e8f9f7	2299	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2300	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	2301	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	2302	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	2303	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2304	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	2305	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	2306	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
<>	144:ef7eb2e8f9f7	2307	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	2308	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	2309	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	2310	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	2311	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	2312	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
<>	144:ef7eb2e8f9f7	2313	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	2314	* @note You have to set the PLLN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	2315	* output frequency is between 100 and 432 MHz.
<>	144:ef7eb2e8f9f7	2316	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
<>	144:ef7eb2e8f9f7	2317	* This parameter must be a number in the range {2, 4, 6, or 8}.
<>	144:ef7eb2e8f9f7	2318	* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
<>	144:ef7eb2e8f9f7	2319	* the System clock frequency.
<>	144:ef7eb2e8f9f7	2320	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
<>	144:ef7eb2e8f9f7	2321	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	2322	* @note If the USB OTG FS is used in your application, you have to set the
<>	144:ef7eb2e8f9f7	2323	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<>	144:ef7eb2e8f9f7	2324	* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
<>	144:ef7eb2e8f9f7	2325	* correctly.
<>	144:ef7eb2e8f9f7	2326	* @param __PLLR__: specifies the division factor for DSI clock
<>	144:ef7eb2e8f9f7	2327	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	2328	*/
<>	144:ef7eb2e8f9f7	2329	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
<>	144:ef7eb2e8f9f7	2330	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
<>	144:ef7eb2e8f9f7	2331	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
<>	144:ef7eb2e8f9f7	2332	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
<>	144:ef7eb2e8f9f7	2333	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
<>	144:ef7eb2e8f9f7	2334	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
<>	144:ef7eb2e8f9f7	2335	#else
<>	144:ef7eb2e8f9f7	2336	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	2337	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	2338	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	2339	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2340	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	2341	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	2342	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
<>	144:ef7eb2e8f9f7	2343	* @param __PLLM__: specifies the division factor for PLL VCO input clock
<>	144:ef7eb2e8f9f7	2344	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
<>	144:ef7eb2e8f9f7	2345	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
<>	144:ef7eb2e8f9f7	2346	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
<>	144:ef7eb2e8f9f7	2347	* of 2 MHz to limit PLL jitter.
<>	144:ef7eb2e8f9f7	2348	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
<>	144:ef7eb2e8f9f7	2349	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	2350	* @note You have to set the PLLN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	2351	* output frequency is between 100 and 432 MHz.
<>	144:ef7eb2e8f9f7	2352	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
<>	144:ef7eb2e8f9f7	2353	* This parameter must be a number in the range {2, 4, 6, or 8}.
<>	144:ef7eb2e8f9f7	2354	* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
<>	144:ef7eb2e8f9f7	2355	* the System clock frequency.
<>	144:ef7eb2e8f9f7	2356	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
<>	144:ef7eb2e8f9f7	2357	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	2358	* @note If the USB OTG FS is used in your application, you have to set the
<>	144:ef7eb2e8f9f7	2359	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
<>	144:ef7eb2e8f9f7	2360	* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
<>	144:ef7eb2e8f9f7	2361	* correctly.
<>	144:ef7eb2e8f9f7	2362	*/
<>	144:ef7eb2e8f9f7	2363	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
<>	144:ef7eb2e8f9f7	2364	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
<>	144:ef7eb2e8f9f7	2365	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
<>	144:ef7eb2e8f9f7	2366	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
<>	144:ef7eb2e8f9f7	2367	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
<>	144:ef7eb2e8f9f7	2368	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2369	/---------------------------------------------------------------------------------------------/
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/** @brief Macro to configure the Timers clocks prescalers
<>	144:ef7eb2e8f9f7	2372	* @param __PRESC__ : specifies the Timers clocks prescalers selection
<>	144:ef7eb2e8f9f7	2373	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2374	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
<>	144:ef7eb2e8f9f7	2375	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
<>	144:ef7eb2e8f9f7	2376	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
<>	144:ef7eb2e8f9f7	2377	* division by 4 or more.
<>	144:ef7eb2e8f9f7	2378	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
<>	144:ef7eb2e8f9f7	2379	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
<>	144:ef7eb2e8f9f7	2380	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
<>	144:ef7eb2e8f9f7	2381	* to division by 8 or more.
<>	144:ef7eb2e8f9f7	2382	*/
<>	144:ef7eb2e8f9f7	2383	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
<>	144:ef7eb2e8f9f7	2384	RCC->DCKCFGR1 \|= (__PRESC__); \
<>	144:ef7eb2e8f9f7	2385	}while(0)
<>	144:ef7eb2e8f9f7	2386
<>	144:ef7eb2e8f9f7	2387	/** @brief Macros to Enable or Disable the PLLISAI.
<>	144:ef7eb2e8f9f7	2388	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	2389	*/
<>	144:ef7eb2e8f9f7	2390	#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR \|= (RCC_CR_PLLSAION))
<>	144:ef7eb2e8f9f7	2391	#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
<>	144:ef7eb2e8f9f7	2392
<>	144:ef7eb2e8f9f7	2393	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
<>	144:ef7eb2e8f9f7	2394	* @note This function must be used only when the PLLSAI is disabled.
<>	144:ef7eb2e8f9f7	2395	* @note PLLSAI clock source is common with the main PLL (configured in
<>	144:ef7eb2e8f9f7	2396	* RCC_PLLConfig function )
<>	144:ef7eb2e8f9f7	2397	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
<>	144:ef7eb2e8f9f7	2398	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	2399	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	2400	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<>	144:ef7eb2e8f9f7	2401	* @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
<>	144:ef7eb2e8f9f7	2402	* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
<>	144:ef7eb2e8f9f7	2403	* @param __PLLSAIQ__: specifies the division factor for SAI clock
<>	144:ef7eb2e8f9f7	2404	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	2405	* @param __PLLSAIR__: specifies the division factor for LTDC clock
<>	144:ef7eb2e8f9f7	2406	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	2407	*/
<>	144:ef7eb2e8f9f7	2408	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
<>	144:ef7eb2e8f9f7	2409	(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
<>	144:ef7eb2e8f9f7	2410	((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
<>	144:ef7eb2e8f9f7	2411	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
<>	144:ef7eb2e8f9f7	2412	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
<>	144:ef7eb2e8f9f7	2413
<>	144:ef7eb2e8f9f7	2414	/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
<>	144:ef7eb2e8f9f7	2415	* @note This macro must be used only when the PLLI2S is disabled.
<>	144:ef7eb2e8f9f7	2416	* @note PLLI2S clock source is common with the main PLL (configured in
<>	144:ef7eb2e8f9f7	2417	* HAL_RCC_ClockConfig() API)
<>	144:ef7eb2e8f9f7	2418	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
<>	144:ef7eb2e8f9f7	2419	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
<>	144:ef7eb2e8f9f7	2420	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
<>	144:ef7eb2e8f9f7	2421	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
<>	144:ef7eb2e8f9f7	2422	* @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
<>	144:ef7eb2e8f9f7	2423	* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
<>	144:ef7eb2e8f9f7	2424	* @param __PLLI2SQ__: specifies the division factor for SAI clock.
<>	144:ef7eb2e8f9f7	2425	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
<>	144:ef7eb2e8f9f7	2426	* @param __PLLI2SR__: specifies the division factor for I2S clock
<>	144:ef7eb2e8f9f7	2427	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
<>	144:ef7eb2e8f9f7	2428	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
<>	144:ef7eb2e8f9f7	2429	* on the I2S clock frequency.
<>	144:ef7eb2e8f9f7	2430	*/
<>	144:ef7eb2e8f9f7	2431	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
<>	144:ef7eb2e8f9f7	2432	(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
<>	144:ef7eb2e8f9f7	2433	((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
<>	144:ef7eb2e8f9f7	2434	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
<>	144:ef7eb2e8f9f7	2435	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
<>	144:ef7eb2e8f9f7	2436
<>	144:ef7eb2e8f9f7	2437	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
<>	144:ef7eb2e8f9f7	2438	* @note This function must be called before enabling the PLLI2S.
<>	144:ef7eb2e8f9f7	2439	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
<>	144:ef7eb2e8f9f7	2440	* This parameter must be a number between 1 and 32.
<>	144:ef7eb2e8f9f7	2441	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
<>	144:ef7eb2e8f9f7	2442	*/
<>	144:ef7eb2e8f9f7	2443	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
<>	144:ef7eb2e8f9f7	2444
<>	144:ef7eb2e8f9f7	2445	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
<>	144:ef7eb2e8f9f7	2446	* @note This function must be called before enabling the PLLSAI.
<>	144:ef7eb2e8f9f7	2447	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
<>	144:ef7eb2e8f9f7	2448	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
<>	144:ef7eb2e8f9f7	2449	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
<>	144:ef7eb2e8f9f7	2450	*/
<>	144:ef7eb2e8f9f7	2451	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
<>	144:ef7eb2e8f9f7	2452
<>	144:ef7eb2e8f9f7	2453	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
<>	144:ef7eb2e8f9f7	2454	*
<>	144:ef7eb2e8f9f7	2455	* @note This function must be called before enabling the PLLSAI.
<>	144:ef7eb2e8f9f7	2456	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
<>	144:ef7eb2e8f9f7	2457	* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
<>	144:ef7eb2e8f9f7	2458	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
<>	144:ef7eb2e8f9f7	2459	*/
<>	144:ef7eb2e8f9f7	2460	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
<>	144:ef7eb2e8f9f7	2461	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
<>	144:ef7eb2e8f9f7	2462
<>	144:ef7eb2e8f9f7	2463	/** @brief Macro to configure SAI1 clock source selection.
<>	144:ef7eb2e8f9f7	2464	* @note This function must be called before enabling PLLSAI, PLLI2S and
<>	144:ef7eb2e8f9f7	2465	* the SAI clock.
<>	144:ef7eb2e8f9f7	2466	* @param __SOURCE__: specifies the SAI1 clock source.
<>	144:ef7eb2e8f9f7	2467	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2468	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<>	144:ef7eb2e8f9f7	2469	* as SAI1 clock.
<>	144:ef7eb2e8f9f7	2470	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<>	144:ef7eb2e8f9f7	2471	* as SAI1 clock.
<>	144:ef7eb2e8f9f7	2472	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	2473	* used as SAI1 clock.
<>	144:ef7eb2e8f9f7	2474	* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<>	144:ef7eb2e8f9f7	2475	* used as SAI1 clock.
<>	144:ef7eb2e8f9f7	2476	* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<>	144:ef7eb2e8f9f7	2477	*/
<>	144:ef7eb2e8f9f7	2478	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
<>	144:ef7eb2e8f9f7	2479	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
<>	144:ef7eb2e8f9f7	2480
<>	144:ef7eb2e8f9f7	2481	/** @brief Macro to get the SAI1 clock source.
<>	144:ef7eb2e8f9f7	2482	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2483	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<>	144:ef7eb2e8f9f7	2484	* as SAI1 clock.
<>	144:ef7eb2e8f9f7	2485	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<>	144:ef7eb2e8f9f7	2486	* as SAI1 clock.
<>	144:ef7eb2e8f9f7	2487	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	2488	* used as SAI1 clock.
<>	144:ef7eb2e8f9f7	2489	* @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<>	144:ef7eb2e8f9f7	2490	* used as SAI1 clock.
<>	144:ef7eb2e8f9f7	2491	* @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<>	144:ef7eb2e8f9f7	2492	*/
<>	144:ef7eb2e8f9f7	2493	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
<>	144:ef7eb2e8f9f7	2494
<>	144:ef7eb2e8f9f7	2495
<>	144:ef7eb2e8f9f7	2496	/** @brief Macro to configure SAI2 clock source selection.
<>	144:ef7eb2e8f9f7	2497	* @note This function must be called before enabling PLLSAI, PLLI2S and
<>	144:ef7eb2e8f9f7	2498	* the SAI clock.
<>	144:ef7eb2e8f9f7	2499	* @param __SOURCE__: specifies the SAI2 clock source.
<>	144:ef7eb2e8f9f7	2500	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2501	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<>	144:ef7eb2e8f9f7	2502	* as SAI2 clock.
<>	144:ef7eb2e8f9f7	2503	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<>	144:ef7eb2e8f9f7	2504	* as SAI2 clock.
<>	144:ef7eb2e8f9f7	2505	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	2506	* used as SAI2 clock.
<>	144:ef7eb2e8f9f7	2507	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<>	144:ef7eb2e8f9f7	2508	* used as SAI2 clock.
<>	144:ef7eb2e8f9f7	2509	* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<>	144:ef7eb2e8f9f7	2510	*/
<>	144:ef7eb2e8f9f7	2511	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
<>	144:ef7eb2e8f9f7	2512	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
<>	144:ef7eb2e8f9f7	2513
<>	144:ef7eb2e8f9f7	2514
<>	144:ef7eb2e8f9f7	2515	/** @brief Macro to get the SAI2 clock source.
<>	144:ef7eb2e8f9f7	2516	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2517	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
<>	144:ef7eb2e8f9f7	2518	* as SAI2 clock.
<>	144:ef7eb2e8f9f7	2519	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
<>	144:ef7eb2e8f9f7	2520	* as SAI2 clock.
<>	144:ef7eb2e8f9f7	2521	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
<>	144:ef7eb2e8f9f7	2522	* used as SAI2 clock.
<>	144:ef7eb2e8f9f7	2523	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
<>	144:ef7eb2e8f9f7	2524	* used as SAI2 clock.
<>	144:ef7eb2e8f9f7	2525	* @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
<>	144:ef7eb2e8f9f7	2526	*/
<>	144:ef7eb2e8f9f7	2527	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
<>	144:ef7eb2e8f9f7	2528
<>	144:ef7eb2e8f9f7	2529
<>	144:ef7eb2e8f9f7	2530	/** @brief Enable PLLSAI_RDY interrupt.
<>	144:ef7eb2e8f9f7	2531	*/
<>	144:ef7eb2e8f9f7	2532	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
<>	144:ef7eb2e8f9f7	2533
<>	144:ef7eb2e8f9f7	2534	/** @brief Disable PLLSAI_RDY interrupt.
<>	144:ef7eb2e8f9f7	2535	*/
<>	144:ef7eb2e8f9f7	2536	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
<>	144:ef7eb2e8f9f7	2537
<>	144:ef7eb2e8f9f7	2538	/** @brief Clear the PLLSAI RDY interrupt pending bits.
<>	144:ef7eb2e8f9f7	2539	*/
<>	144:ef7eb2e8f9f7	2540	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
<>	144:ef7eb2e8f9f7	2541
<>	144:ef7eb2e8f9f7	2542	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	2543	* @retval The new state (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	2544	*/
<>	144:ef7eb2e8f9f7	2545	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
<>	144:ef7eb2e8f9f7	2546
<>	144:ef7eb2e8f9f7	2547	/** @brief Check PLLSAI RDY flag is set or not.
<>	144:ef7eb2e8f9f7	2548	* @retval The new state (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	2549	*/
<>	144:ef7eb2e8f9f7	2550	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
<>	144:ef7eb2e8f9f7	2551
<>	144:ef7eb2e8f9f7	2552	/** @brief Macro to Get I2S clock source selection.
<>	144:ef7eb2e8f9f7	2553	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2554	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
<>	144:ef7eb2e8f9f7	2555	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
<>	144:ef7eb2e8f9f7	2556	*/
<>	144:ef7eb2e8f9f7	2557	#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
<>	144:ef7eb2e8f9f7	2558
<>	144:ef7eb2e8f9f7	2559	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
<>	144:ef7eb2e8f9f7	2560	*
<>	144:ef7eb2e8f9f7	2561	* @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
<>	144:ef7eb2e8f9f7	2562	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2563	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2564	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2565	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2566	*/
<>	144:ef7eb2e8f9f7	2567	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2568	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2569
<>	144:ef7eb2e8f9f7	2570	/** @brief Macro to get the I2C1 clock source.
<>	144:ef7eb2e8f9f7	2571	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2572	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2573	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2574	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
<>	144:ef7eb2e8f9f7	2575	*/
<>	144:ef7eb2e8f9f7	2576	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
<>	144:ef7eb2e8f9f7	2577
<>	144:ef7eb2e8f9f7	2578	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
<>	144:ef7eb2e8f9f7	2579	*
<>	144:ef7eb2e8f9f7	2580	* @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
<>	144:ef7eb2e8f9f7	2581	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2582	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2583	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2584	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2585	*/
<>	144:ef7eb2e8f9f7	2586	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2587	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2588
<>	144:ef7eb2e8f9f7	2589	/** @brief Macro to get the I2C2 clock source.
<>	144:ef7eb2e8f9f7	2590	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2591	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2592	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2593	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
<>	144:ef7eb2e8f9f7	2594	*/
<>	144:ef7eb2e8f9f7	2595	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
<>	144:ef7eb2e8f9f7	2596
<>	144:ef7eb2e8f9f7	2597	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
<>	144:ef7eb2e8f9f7	2598	*
<>	144:ef7eb2e8f9f7	2599	* @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
<>	144:ef7eb2e8f9f7	2600	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2601	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2602	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2603	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2604	*/
<>	144:ef7eb2e8f9f7	2605	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2606	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2607
<>	144:ef7eb2e8f9f7	2608	/** @brief macro to get the I2C3 clock source.
<>	144:ef7eb2e8f9f7	2609	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2610	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2611	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2612	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
<>	144:ef7eb2e8f9f7	2613	*/
<>	144:ef7eb2e8f9f7	2614	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
<>	144:ef7eb2e8f9f7	2615
<>	144:ef7eb2e8f9f7	2616	/** @brief Macro to configure the I2C4 clock (I2C4CLK).
<>	144:ef7eb2e8f9f7	2617	*
<>	144:ef7eb2e8f9f7	2618	* @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
<>	144:ef7eb2e8f9f7	2619	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2620	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2621	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2622	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2623	*/
<>	144:ef7eb2e8f9f7	2624	#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2625	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2626
<>	144:ef7eb2e8f9f7	2627	/** @brief macro to get the I2C4 clock source.
<>	144:ef7eb2e8f9f7	2628	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2629	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2630	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2631	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
<>	144:ef7eb2e8f9f7	2632	*/
<>	144:ef7eb2e8f9f7	2633	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
<>	144:ef7eb2e8f9f7	2634
<>	144:ef7eb2e8f9f7	2635	/** @brief Macro to configure the USART1 clock (USART1CLK).
<>	144:ef7eb2e8f9f7	2636	*
<>	144:ef7eb2e8f9f7	2637	* @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
<>	144:ef7eb2e8f9f7	2638	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2639	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
<>	144:ef7eb2e8f9f7	2640	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
<>	144:ef7eb2e8f9f7	2641	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
<>	144:ef7eb2e8f9f7	2642	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
<>	144:ef7eb2e8f9f7	2643	*/
<>	144:ef7eb2e8f9f7	2644	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2645	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2646
<>	144:ef7eb2e8f9f7	2647	/** @brief macro to get the USART1 clock source.
<>	144:ef7eb2e8f9f7	2648	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2649	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
<>	144:ef7eb2e8f9f7	2650	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
<>	144:ef7eb2e8f9f7	2651	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
<>	144:ef7eb2e8f9f7	2652	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
<>	144:ef7eb2e8f9f7	2653	*/
<>	144:ef7eb2e8f9f7	2654	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
<>	144:ef7eb2e8f9f7	2655
<>	144:ef7eb2e8f9f7	2656	/** @brief Macro to configure the USART2 clock (USART2CLK).
<>	144:ef7eb2e8f9f7	2657	*
<>	144:ef7eb2e8f9f7	2658	* @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
<>	144:ef7eb2e8f9f7	2659	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2660	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
<>	144:ef7eb2e8f9f7	2661	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
<>	144:ef7eb2e8f9f7	2662	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
<>	144:ef7eb2e8f9f7	2663	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
<>	144:ef7eb2e8f9f7	2664	*/
<>	144:ef7eb2e8f9f7	2665	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2666	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2667
<>	144:ef7eb2e8f9f7	2668	/** @brief macro to get the USART2 clock source.
<>	144:ef7eb2e8f9f7	2669	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2670	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
<>	144:ef7eb2e8f9f7	2671	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
<>	144:ef7eb2e8f9f7	2672	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
<>	144:ef7eb2e8f9f7	2673	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
<>	144:ef7eb2e8f9f7	2674	*/
<>	144:ef7eb2e8f9f7	2675	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
<>	144:ef7eb2e8f9f7	2676
<>	144:ef7eb2e8f9f7	2677	/** @brief Macro to configure the USART3 clock (USART3CLK).
<>	144:ef7eb2e8f9f7	2678	*
<>	144:ef7eb2e8f9f7	2679	* @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
<>	144:ef7eb2e8f9f7	2680	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2681	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
<>	144:ef7eb2e8f9f7	2682	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
<>	144:ef7eb2e8f9f7	2683	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
<>	144:ef7eb2e8f9f7	2684	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
<>	144:ef7eb2e8f9f7	2685	*/
<>	144:ef7eb2e8f9f7	2686	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2687	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2688
<>	144:ef7eb2e8f9f7	2689	/** @brief macro to get the USART3 clock source.
<>	144:ef7eb2e8f9f7	2690	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2691	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
<>	144:ef7eb2e8f9f7	2692	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
<>	144:ef7eb2e8f9f7	2693	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
<>	144:ef7eb2e8f9f7	2694	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
<>	144:ef7eb2e8f9f7	2695	*/
<>	144:ef7eb2e8f9f7	2696	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
<>	144:ef7eb2e8f9f7	2697
<>	144:ef7eb2e8f9f7	2698	/** @brief Macro to configure the UART4 clock (UART4CLK).
<>	144:ef7eb2e8f9f7	2699	*
<>	144:ef7eb2e8f9f7	2700	* @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
<>	144:ef7eb2e8f9f7	2701	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2702	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
<>	144:ef7eb2e8f9f7	2703	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
<>	144:ef7eb2e8f9f7	2704	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
<>	144:ef7eb2e8f9f7	2705	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
<>	144:ef7eb2e8f9f7	2706	*/
<>	144:ef7eb2e8f9f7	2707	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2708	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2709
<>	144:ef7eb2e8f9f7	2710	/** @brief macro to get the UART4 clock source.
<>	144:ef7eb2e8f9f7	2711	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2712	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
<>	144:ef7eb2e8f9f7	2713	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
<>	144:ef7eb2e8f9f7	2714	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
<>	144:ef7eb2e8f9f7	2715	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
<>	144:ef7eb2e8f9f7	2716	*/
<>	144:ef7eb2e8f9f7	2717	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
<>	144:ef7eb2e8f9f7	2718
<>	144:ef7eb2e8f9f7	2719	/** @brief Macro to configure the UART5 clock (UART5CLK).
<>	144:ef7eb2e8f9f7	2720	*
<>	144:ef7eb2e8f9f7	2721	* @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
<>	144:ef7eb2e8f9f7	2722	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2723	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
<>	144:ef7eb2e8f9f7	2724	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
<>	144:ef7eb2e8f9f7	2725	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
<>	144:ef7eb2e8f9f7	2726	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
<>	144:ef7eb2e8f9f7	2727	*/
<>	144:ef7eb2e8f9f7	2728	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2729	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2730
<>	144:ef7eb2e8f9f7	2731	/** @brief macro to get the UART5 clock source.
<>	144:ef7eb2e8f9f7	2732	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2733	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
<>	144:ef7eb2e8f9f7	2734	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
<>	144:ef7eb2e8f9f7	2735	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
<>	144:ef7eb2e8f9f7	2736	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
<>	144:ef7eb2e8f9f7	2737	*/
<>	144:ef7eb2e8f9f7	2738	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
<>	144:ef7eb2e8f9f7	2739
<>	144:ef7eb2e8f9f7	2740	/** @brief Macro to configure the USART6 clock (USART6CLK).
<>	144:ef7eb2e8f9f7	2741	*
<>	144:ef7eb2e8f9f7	2742	* @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
<>	144:ef7eb2e8f9f7	2743	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2744	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
<>	144:ef7eb2e8f9f7	2745	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
<>	144:ef7eb2e8f9f7	2746	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
<>	144:ef7eb2e8f9f7	2747	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
<>	144:ef7eb2e8f9f7	2748	*/
<>	144:ef7eb2e8f9f7	2749	#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2750	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2751
<>	144:ef7eb2e8f9f7	2752	/** @brief macro to get the USART6 clock source.
<>	144:ef7eb2e8f9f7	2753	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2754	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
<>	144:ef7eb2e8f9f7	2755	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
<>	144:ef7eb2e8f9f7	2756	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
<>	144:ef7eb2e8f9f7	2757	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
<>	144:ef7eb2e8f9f7	2758	*/
<>	144:ef7eb2e8f9f7	2759	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
<>	144:ef7eb2e8f9f7	2760
<>	144:ef7eb2e8f9f7	2761	/** @brief Macro to configure the UART7 clock (UART7CLK).
<>	144:ef7eb2e8f9f7	2762	*
<>	144:ef7eb2e8f9f7	2763	* @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
<>	144:ef7eb2e8f9f7	2764	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2765	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
<>	144:ef7eb2e8f9f7	2766	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
<>	144:ef7eb2e8f9f7	2767	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
<>	144:ef7eb2e8f9f7	2768	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
<>	144:ef7eb2e8f9f7	2769	*/
<>	144:ef7eb2e8f9f7	2770	#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2771	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2772
<>	144:ef7eb2e8f9f7	2773	/** @brief macro to get the UART7 clock source.
<>	144:ef7eb2e8f9f7	2774	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2775	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
<>	144:ef7eb2e8f9f7	2776	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
<>	144:ef7eb2e8f9f7	2777	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
<>	144:ef7eb2e8f9f7	2778	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
<>	144:ef7eb2e8f9f7	2779	*/
<>	144:ef7eb2e8f9f7	2780	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
<>	144:ef7eb2e8f9f7	2781
<>	144:ef7eb2e8f9f7	2782	/** @brief Macro to configure the UART8 clock (UART8CLK).
<>	144:ef7eb2e8f9f7	2783	*
<>	144:ef7eb2e8f9f7	2784	* @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
<>	144:ef7eb2e8f9f7	2785	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2786	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
<>	144:ef7eb2e8f9f7	2787	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
<>	144:ef7eb2e8f9f7	2788	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
<>	144:ef7eb2e8f9f7	2789	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
<>	144:ef7eb2e8f9f7	2790	*/
<>	144:ef7eb2e8f9f7	2791	#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2792	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2793
<>	144:ef7eb2e8f9f7	2794	/** @brief macro to get the UART8 clock source.
<>	144:ef7eb2e8f9f7	2795	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2796	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
<>	144:ef7eb2e8f9f7	2797	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
<>	144:ef7eb2e8f9f7	2798	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
<>	144:ef7eb2e8f9f7	2799	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
<>	144:ef7eb2e8f9f7	2800	*/
<>	144:ef7eb2e8f9f7	2801	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
<>	144:ef7eb2e8f9f7	2802
<>	144:ef7eb2e8f9f7	2803	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
<>	144:ef7eb2e8f9f7	2804	*
<>	144:ef7eb2e8f9f7	2805	* @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
<>	144:ef7eb2e8f9f7	2806	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2807	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2808	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2809	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2810	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2811	*/
<>	144:ef7eb2e8f9f7	2812	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2813	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2814
<>	144:ef7eb2e8f9f7	2815	/** @brief macro to get the LPTIM1 clock source.
<>	144:ef7eb2e8f9f7	2816	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2817	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2818	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2819	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2820	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
<>	144:ef7eb2e8f9f7	2821	*/
<>	144:ef7eb2e8f9f7	2822	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
<>	144:ef7eb2e8f9f7	2823
<>	144:ef7eb2e8f9f7	2824	/** @brief Macro to configure the CEC clock (CECCLK).
<>	144:ef7eb2e8f9f7	2825	*
<>	144:ef7eb2e8f9f7	2826	* @param __CEC_CLKSOURCE__: specifies the CEC clock source.
<>	144:ef7eb2e8f9f7	2827	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2828	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
<>	144:ef7eb2e8f9f7	2829	* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
<>	144:ef7eb2e8f9f7	2830	*/
<>	144:ef7eb2e8f9f7	2831	#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2832	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2833
<>	144:ef7eb2e8f9f7	2834	/** @brief macro to get the CEC clock source.
<>	144:ef7eb2e8f9f7	2835	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2836	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
<>	144:ef7eb2e8f9f7	2837	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
<>	144:ef7eb2e8f9f7	2838	*/
<>	144:ef7eb2e8f9f7	2839	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
<>	144:ef7eb2e8f9f7	2840
<>	144:ef7eb2e8f9f7	2841	/** @brief Macro to configure the CLK48 source (CLK48CLK).
<>	144:ef7eb2e8f9f7	2842	*
<>	144:ef7eb2e8f9f7	2843	* @param __CLK48_SOURCE__: specifies the CLK48 clock source.
<>	144:ef7eb2e8f9f7	2844	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2845	* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
<>	144:ef7eb2e8f9f7	2846	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
<>	144:ef7eb2e8f9f7	2847	*/
<>	144:ef7eb2e8f9f7	2848	#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
<>	144:ef7eb2e8f9f7	2849	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
<>	144:ef7eb2e8f9f7	2850
<>	144:ef7eb2e8f9f7	2851	/** @brief macro to get the CLK48 source.
<>	144:ef7eb2e8f9f7	2852	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2853	* @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
<>	144:ef7eb2e8f9f7	2854	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
<>	144:ef7eb2e8f9f7	2855	*/
<>	144:ef7eb2e8f9f7	2856	#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
<>	144:ef7eb2e8f9f7	2857
<>	144:ef7eb2e8f9f7	2858	/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
<>	144:ef7eb2e8f9f7	2859	*
<>	144:ef7eb2e8f9f7	2860	* @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
<>	144:ef7eb2e8f9f7	2861	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2862	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
<>	144:ef7eb2e8f9f7	2863	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
<>	144:ef7eb2e8f9f7	2864	*/
<>	144:ef7eb2e8f9f7	2865	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2866	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2867
<>	144:ef7eb2e8f9f7	2868	/** @brief macro to get the SDMMC1 clock source.
<>	144:ef7eb2e8f9f7	2869	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2870	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
<>	144:ef7eb2e8f9f7	2871	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
<>	144:ef7eb2e8f9f7	2872	*/
<>	144:ef7eb2e8f9f7	2873	#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
<>	144:ef7eb2e8f9f7	2874
<>	144:ef7eb2e8f9f7	2875	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2876	/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
<>	144:ef7eb2e8f9f7	2877	* @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
<>	144:ef7eb2e8f9f7	2878	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2879	* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
<>	144:ef7eb2e8f9f7	2880	* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
<>	144:ef7eb2e8f9f7	2881	*/
<>	144:ef7eb2e8f9f7	2882	#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2883	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2884
<>	144:ef7eb2e8f9f7	2885	/** @brief macro to get the SDMMC2 clock source.
<>	144:ef7eb2e8f9f7	2886	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2887	* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
<>	144:ef7eb2e8f9f7	2888	* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
<>	144:ef7eb2e8f9f7	2889	*/
<>	144:ef7eb2e8f9f7	2890	#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
<>	144:ef7eb2e8f9f7	2891
<>	144:ef7eb2e8f9f7	2892	/** @brief Macro to configure the DFSDM1 clock
<>	144:ef7eb2e8f9f7	2893	* @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
<>	144:ef7eb2e8f9f7	2894	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2895	* @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock
<>	144:ef7eb2e8f9f7	2896	* @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
<>	144:ef7eb2e8f9f7	2897	*/
<>	144:ef7eb2e8f9f7	2898	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2899	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2900
<>	144:ef7eb2e8f9f7	2901	/** @brief Macro to get the DFSDM1 clock source.
<>	144:ef7eb2e8f9f7	2902	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2903	* @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock
<>	144:ef7eb2e8f9f7	2904	* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
<>	144:ef7eb2e8f9f7	2905	*/
<>	144:ef7eb2e8f9f7	2906	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
<>	144:ef7eb2e8f9f7	2907
<>	144:ef7eb2e8f9f7	2908	/** @brief Macro to configure the DFSDM1 Audio clock
<>	144:ef7eb2e8f9f7	2909	* @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
<>	144:ef7eb2e8f9f7	2910	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2911	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
<>	144:ef7eb2e8f9f7	2912	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
<>	144:ef7eb2e8f9f7	2913	*/
<>	144:ef7eb2e8f9f7	2914	#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
<>	144:ef7eb2e8f9f7	2915	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
<>	144:ef7eb2e8f9f7	2916
<>	144:ef7eb2e8f9f7	2917	/** @brief Macro to get the DFSDM1 Audio clock source.
<>	144:ef7eb2e8f9f7	2918	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2919	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
<>	144:ef7eb2e8f9f7	2920	* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
<>	144:ef7eb2e8f9f7	2921	*/
<>	144:ef7eb2e8f9f7	2922	#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
<>	144:ef7eb2e8f9f7	2923	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2924
<>	144:ef7eb2e8f9f7	2925	#if defined (STM32F769xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	2926	/** @brief Macro to configure the DSI clock.
<>	144:ef7eb2e8f9f7	2927	* @param __DSI_CLKSOURCE__: specifies the DSI clock source.
<>	144:ef7eb2e8f9f7	2928	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2929	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
<>	144:ef7eb2e8f9f7	2930	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
<>	144:ef7eb2e8f9f7	2931	*/
<>	144:ef7eb2e8f9f7	2932	#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
<>	144:ef7eb2e8f9f7	2933
<>	144:ef7eb2e8f9f7	2934	/** @brief Macro to Get the DSI clock.
<>	144:ef7eb2e8f9f7	2935	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	2936	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
<>	144:ef7eb2e8f9f7	2937	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
<>	144:ef7eb2e8f9f7	2938	*/
<>	144:ef7eb2e8f9f7	2939	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
<>	144:ef7eb2e8f9f7	2940	#endif /* STM32F769xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	2941	/**
<>	144:ef7eb2e8f9f7	2942	* @}
<>	144:ef7eb2e8f9f7	2943	*/
<>	144:ef7eb2e8f9f7	2944
<>	144:ef7eb2e8f9f7	2945	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2946	/** @addtogroup RCCEx_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	2947	* @{
<>	144:ef7eb2e8f9f7	2948	*/
<>	144:ef7eb2e8f9f7	2949	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<>	144:ef7eb2e8f9f7	2950	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<>	144:ef7eb2e8f9f7	2951	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<>	144:ef7eb2e8f9f7	2952
<>	144:ef7eb2e8f9f7	2953	/**
<>	144:ef7eb2e8f9f7	2954	* @}
<>	144:ef7eb2e8f9f7	2955	*/
<>	144:ef7eb2e8f9f7	2956	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2957	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
<>	144:ef7eb2e8f9f7	2958	* @{
<>	144:ef7eb2e8f9f7	2959	*/
<>	144:ef7eb2e8f9f7	2960	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
<>	144:ef7eb2e8f9f7	2961	* @{
<>	144:ef7eb2e8f9f7	2962	*/
<>	144:ef7eb2e8f9f7	2963	#if defined(STM32F756xx) \|\| defined(STM32F746xx)
<>	144:ef7eb2e8f9f7	2964	#define IS_RCC_PERIPHCLOCK(SELECTION) \
<>	144:ef7eb2e8f9f7	2965	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
<>	144:ef7eb2e8f9f7	2966	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
<>	144:ef7eb2e8f9f7	2967	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
<>	144:ef7eb2e8f9f7	2968	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
<>	144:ef7eb2e8f9f7	2969	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
<>	144:ef7eb2e8f9f7	2970	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
<>	144:ef7eb2e8f9f7	2971	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
<>	144:ef7eb2e8f9f7	2972	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
<>	144:ef7eb2e8f9f7	2973	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
<>	144:ef7eb2e8f9f7	2974	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
<>	144:ef7eb2e8f9f7	2975	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
<>	144:ef7eb2e8f9f7	2976	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
<>	144:ef7eb2e8f9f7	2977	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
<>	144:ef7eb2e8f9f7	2978	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
<>	144:ef7eb2e8f9f7	2979	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
<>	144:ef7eb2e8f9f7	2980	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
<>	144:ef7eb2e8f9f7	2981	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
<>	144:ef7eb2e8f9f7	2982	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
<>	144:ef7eb2e8f9f7	2983	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
<>	144:ef7eb2e8f9f7	2984	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
<>	144:ef7eb2e8f9f7	2985	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
<>	144:ef7eb2e8f9f7	2986	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
<>	144:ef7eb2e8f9f7	2987	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	2988	#elif defined(STM32F745xx)
<>	144:ef7eb2e8f9f7	2989	#define IS_RCC_PERIPHCLOCK(SELECTION) \
<>	144:ef7eb2e8f9f7	2990	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
<>	144:ef7eb2e8f9f7	2991	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
<>	144:ef7eb2e8f9f7	2992	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
<>	144:ef7eb2e8f9f7	2993	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
<>	144:ef7eb2e8f9f7	2994	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
<>	144:ef7eb2e8f9f7	2995	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
<>	144:ef7eb2e8f9f7	2996	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
<>	144:ef7eb2e8f9f7	2997	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
<>	144:ef7eb2e8f9f7	2998	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
<>	144:ef7eb2e8f9f7	2999	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
<>	144:ef7eb2e8f9f7	3000	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
<>	144:ef7eb2e8f9f7	3001	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
<>	144:ef7eb2e8f9f7	3002	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
<>	144:ef7eb2e8f9f7	3003	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
<>	144:ef7eb2e8f9f7	3004	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
<>	144:ef7eb2e8f9f7	3005	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
<>	144:ef7eb2e8f9f7	3006	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
<>	144:ef7eb2e8f9f7	3007	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
<>	144:ef7eb2e8f9f7	3008	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
<>	144:ef7eb2e8f9f7	3009	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
<>	144:ef7eb2e8f9f7	3010	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
<>	144:ef7eb2e8f9f7	3011	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	3012	#elif defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	3013	#define IS_RCC_PERIPHCLOCK(SELECTION) \
<>	144:ef7eb2e8f9f7	3014	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
<>	144:ef7eb2e8f9f7	3015	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
<>	144:ef7eb2e8f9f7	3016	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
<>	144:ef7eb2e8f9f7	3017	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
<>	144:ef7eb2e8f9f7	3018	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
<>	144:ef7eb2e8f9f7	3019	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
<>	144:ef7eb2e8f9f7	3020	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
<>	144:ef7eb2e8f9f7	3021	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
<>	144:ef7eb2e8f9f7	3022	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
<>	144:ef7eb2e8f9f7	3023	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
<>	144:ef7eb2e8f9f7	3024	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
<>	144:ef7eb2e8f9f7	3025	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
<>	144:ef7eb2e8f9f7	3026	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
<>	144:ef7eb2e8f9f7	3027	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
<>	144:ef7eb2e8f9f7	3028	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
<>	144:ef7eb2e8f9f7	3029	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
<>	144:ef7eb2e8f9f7	3030	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
<>	144:ef7eb2e8f9f7	3031	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
<>	144:ef7eb2e8f9f7	3032	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
<>	144:ef7eb2e8f9f7	3033	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
<>	144:ef7eb2e8f9f7	3034	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
<>	144:ef7eb2e8f9f7	3035	(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) \|\| \
<>	144:ef7eb2e8f9f7	3036	(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
<>	144:ef7eb2e8f9f7	3037	(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) \|\| \
<>	144:ef7eb2e8f9f7	3038	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
<>	144:ef7eb2e8f9f7	3039	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	3040	#elif defined (STM32F765xx)
<>	144:ef7eb2e8f9f7	3041	#define IS_RCC_PERIPHCLOCK(SELECTION) \
<>	144:ef7eb2e8f9f7	3042	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
<>	144:ef7eb2e8f9f7	3043	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
<>	144:ef7eb2e8f9f7	3044	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
<>	144:ef7eb2e8f9f7	3045	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
<>	144:ef7eb2e8f9f7	3046	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
<>	144:ef7eb2e8f9f7	3047	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
<>	144:ef7eb2e8f9f7	3048	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
<>	144:ef7eb2e8f9f7	3049	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
<>	144:ef7eb2e8f9f7	3050	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
<>	144:ef7eb2e8f9f7	3051	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
<>	144:ef7eb2e8f9f7	3052	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
<>	144:ef7eb2e8f9f7	3053	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
<>	144:ef7eb2e8f9f7	3054	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
<>	144:ef7eb2e8f9f7	3055	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
<>	144:ef7eb2e8f9f7	3056	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
<>	144:ef7eb2e8f9f7	3057	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
<>	144:ef7eb2e8f9f7	3058	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
<>	144:ef7eb2e8f9f7	3059	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
<>	144:ef7eb2e8f9f7	3060	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
<>	144:ef7eb2e8f9f7	3061	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
<>	144:ef7eb2e8f9f7	3062	(((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) \|\| \
<>	144:ef7eb2e8f9f7	3063	(((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) \|\| \
<>	144:ef7eb2e8f9f7	3064	(((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) \|\| \
<>	144:ef7eb2e8f9f7	3065	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
<>	144:ef7eb2e8f9f7	3066	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
<>	144:ef7eb2e8f9f7	3067	#endif /* STM32F746xx \|\| STM32F756xx */
<>	144:ef7eb2e8f9f7	3068	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<>	144:ef7eb2e8f9f7	3069	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
<>	144:ef7eb2e8f9f7	3070	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
<>	144:ef7eb2e8f9f7	3071	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
<>	144:ef7eb2e8f9f7	3072	((VALUE) == RCC_PLLI2SP_DIV8))
<>	144:ef7eb2e8f9f7	3073	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
<>	144:ef7eb2e8f9f7	3074	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<>	144:ef7eb2e8f9f7	3075
<>	144:ef7eb2e8f9f7	3076	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
<>	144:ef7eb2e8f9f7	3077	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
<>	144:ef7eb2e8f9f7	3078	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
<>	144:ef7eb2e8f9f7	3079	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
<>	144:ef7eb2e8f9f7	3080	((VALUE) == RCC_PLLSAIP_DIV8))
<>	144:ef7eb2e8f9f7	3081	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
<>	144:ef7eb2e8f9f7	3082	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<>	144:ef7eb2e8f9f7	3083
<>	144:ef7eb2e8f9f7	3084	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
<>	144:ef7eb2e8f9f7	3085
<>	144:ef7eb2e8f9f7	3086	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
<>	144:ef7eb2e8f9f7	3087
<>	144:ef7eb2e8f9f7	3088	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
<>	144:ef7eb2e8f9f7	3089	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
<>	144:ef7eb2e8f9f7	3090	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
<>	144:ef7eb2e8f9f7	3091	((VALUE) == RCC_PLLSAIDIVR_16))
<>	144:ef7eb2e8f9f7	3092	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) \|\| \
<>	144:ef7eb2e8f9f7	3093	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
<>	144:ef7eb2e8f9f7	3094
<>	144:ef7eb2e8f9f7	3095	#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3096	((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
<>	144:ef7eb2e8f9f7	3097
<>	144:ef7eb2e8f9f7	3098	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3099	((SOURCE) == RCC_CECCLKSOURCE_LSE))
<>	144:ef7eb2e8f9f7	3100	#define IS_RCC_USART1CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3101	(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
<>	144:ef7eb2e8f9f7	3102	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3103	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3104	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3105
<>	144:ef7eb2e8f9f7	3106	#define IS_RCC_USART2CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3107	(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3108	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3109	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3110	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3111	#define IS_RCC_USART3CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3112	(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3113	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3114	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3115	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3116
<>	144:ef7eb2e8f9f7	3117	#define IS_RCC_UART4CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3118	(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3119	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3120	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3121	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3122
<>	144:ef7eb2e8f9f7	3123	#define IS_RCC_UART5CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3124	(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3125	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3126	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3127	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3128
<>	144:ef7eb2e8f9f7	3129	#define IS_RCC_USART6CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3130	(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) \|\| \
<>	144:ef7eb2e8f9f7	3131	((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3132	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3133	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3134
<>	144:ef7eb2e8f9f7	3135	#define IS_RCC_UART7CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3136	(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3137	((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3138	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3139	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3140
<>	144:ef7eb2e8f9f7	3141	#define IS_RCC_UART8CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3142	(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3143	((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3144	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	3145	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3146	#define IS_RCC_I2C1CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3147	(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3148	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
<>	144:ef7eb2e8f9f7	3149	((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3150	#define IS_RCC_I2C2CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3151	(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3152	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
<>	144:ef7eb2e8f9f7	3153	((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3154
<>	144:ef7eb2e8f9f7	3155	#define IS_RCC_I2C3CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3156	(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3157	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
<>	144:ef7eb2e8f9f7	3158	((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3159	#define IS_RCC_I2C4CLKSOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3160	(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) \|\| \
<>	144:ef7eb2e8f9f7	3161	((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)\|\| \
<>	144:ef7eb2e8f9f7	3162	((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
<>	144:ef7eb2e8f9f7	3163	#define IS_RCC_LPTIM1CLK(SOURCE) \
<>	144:ef7eb2e8f9f7	3164	(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
<>	144:ef7eb2e8f9f7	3165	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	3166	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	3167	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
<>	144:ef7eb2e8f9f7	3168	#define IS_RCC_CLK48SOURCE(SOURCE) \
<>	144:ef7eb2e8f9f7	3169	(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) \|\| \
<>	144:ef7eb2e8f9f7	3170	((SOURCE) == RCC_CLK48SOURCE_PLL))
<>	144:ef7eb2e8f9f7	3171	#define IS_RCC_TIMPRES(VALUE) \
<>	144:ef7eb2e8f9f7	3172	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
<>	144:ef7eb2e8f9f7	3173	((VALUE) == RCC_TIMPRES_ACTIVATED))
<>	144:ef7eb2e8f9f7	3174
<>	144:ef7eb2e8f9f7	3175	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx)
<>	144:ef7eb2e8f9f7	3176	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
<>	144:ef7eb2e8f9f7	3177	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
<>	144:ef7eb2e8f9f7	3178	((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
<>	144:ef7eb2e8f9f7	3179	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
<>	144:ef7eb2e8f9f7	3180	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
<>	144:ef7eb2e8f9f7	3181	((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
<>	144:ef7eb2e8f9f7	3182	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx */
<>	144:ef7eb2e8f9f7	3183
<>	144:ef7eb2e8f9f7	3184	#if defined (STM32F765xx) \|\| defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	3185	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
<>	144:ef7eb2e8f9f7	3186
<>	144:ef7eb2e8f9f7	3187	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
<>	144:ef7eb2e8f9f7	3188	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
<>	144:ef7eb2e8f9f7	3189	((SOURCE) == RCC_SAI1CLKSOURCE_PIN) \|\| \
<>	144:ef7eb2e8f9f7	3190	((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
<>	144:ef7eb2e8f9f7	3191
<>	144:ef7eb2e8f9f7	3192	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
<>	144:ef7eb2e8f9f7	3193	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
<>	144:ef7eb2e8f9f7	3194	((SOURCE) == RCC_SAI2CLKSOURCE_PIN) \|\| \
<>	144:ef7eb2e8f9f7	3195	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
<>	144:ef7eb2e8f9f7	3196
<>	144:ef7eb2e8f9f7	3197	#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	3198	((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
<>	144:ef7eb2e8f9f7	3199
<>	144:ef7eb2e8f9f7	3200	#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) \|\| \
<>	144:ef7eb2e8f9f7	3201	((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
<>	144:ef7eb2e8f9f7	3202
<>	144:ef7eb2e8f9f7	3203	#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) \|\| \
<>	144:ef7eb2e8f9f7	3204	((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
<>	144:ef7eb2e8f9f7	3205	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	3206
<>	144:ef7eb2e8f9f7	3207	#if defined (STM32F767xx) \|\| defined (STM32F769xx) \|\| defined (STM32F777xx) \|\| defined (STM32F779xx)
<>	144:ef7eb2e8f9f7	3208	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
<>	144:ef7eb2e8f9f7	3209	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
<>	144:ef7eb2e8f9f7	3210	#endif /* STM32F767xx \|\| STM32F769xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	3211
<>	144:ef7eb2e8f9f7	3212	/**
<>	144:ef7eb2e8f9f7	3213	* @}
<>	144:ef7eb2e8f9f7	3214	*/
<>	144:ef7eb2e8f9f7	3215
<>	144:ef7eb2e8f9f7	3216	/**
<>	144:ef7eb2e8f9f7	3217	* @}
<>	144:ef7eb2e8f9f7	3218	*/
<>	144:ef7eb2e8f9f7	3219
<>	144:ef7eb2e8f9f7	3220	/**
<>	144:ef7eb2e8f9f7	3221	* @}
<>	144:ef7eb2e8f9f7	3222	*/
<>	144:ef7eb2e8f9f7	3223
<>	144:ef7eb2e8f9f7	3224	/**
<>	144:ef7eb2e8f9f7	3225	* @}
<>	144:ef7eb2e8f9f7	3226	*/
<>	144:ef7eb2e8f9f7	3227	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	3228	}
<>	144:ef7eb2e8f9f7	3229	#endif
<>	144:ef7eb2e8f9f7	3230
<>	144:ef7eb2e8f9f7	3231	#endif /* __STM32F7xx_HAL_RCC_EX_H */
<>	144:ef7eb2e8f9f7	3232
<>	144:ef7eb2e8f9f7	3233	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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