Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_pwr.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 44 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @defgroup PWR PWR
<> 144:ef7eb2e8f9f7 51 * @brief PWR HAL module driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @addtogroup PWR_Private_Constants
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 #define PVD_MODE_IT ((uint32_t)0x00010000U)
<> 144:ef7eb2e8f9f7 67 #define PVD_MODE_EVT ((uint32_t)0x00020000U)
<> 144:ef7eb2e8f9f7 68 #define PVD_RISING_EDGE ((uint32_t)0x00000001U)
<> 144:ef7eb2e8f9f7 69 #define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
<> 144:ef7eb2e8f9f7 70 /**
<> 144:ef7eb2e8f9f7 71 * @}
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 #define PWR_EWUP_MASK ((uint32_t)0x00003F00)
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /**
<> 144:ef7eb2e8f9f7 83 * @}
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 86 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 87 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 88 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @defgroup PWR_Exported_Functions PWR Exported Functions
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 95 * @brief Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 @verbatim
<> 144:ef7eb2e8f9f7 98 ===============================================================================
<> 144:ef7eb2e8f9f7 99 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 100 ===============================================================================
<> 144:ef7eb2e8f9f7 101 [..]
<> 144:ef7eb2e8f9f7 102 After reset, the backup domain (RTC registers, RTC backup data
<> 144:ef7eb2e8f9f7 103 registers and backup SRAM) is protected against possible unwanted
<> 144:ef7eb2e8f9f7 104 write accesses.
<> 144:ef7eb2e8f9f7 105 To enable access to the RTC Domain and RTC registers, proceed as follows:
<> 144:ef7eb2e8f9f7 106 (+) Enable the Power Controller (PWR) APB1 interface clock using the
<> 144:ef7eb2e8f9f7 107 __HAL_RCC_PWR_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 108 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 @endverbatim
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /**
<> 144:ef7eb2e8f9f7 115 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 116 * @retval None
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118 void HAL_PWR_DeInit(void)
<> 144:ef7eb2e8f9f7 119 {
<> 144:ef7eb2e8f9f7 120 __HAL_RCC_PWR_FORCE_RESET();
<> 144:ef7eb2e8f9f7 121 __HAL_RCC_PWR_RELEASE_RESET();
<> 144:ef7eb2e8f9f7 122 }
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief Enables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 126 * backup data registers and backup SRAM).
<> 144:ef7eb2e8f9f7 127 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 128 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 129 * @retval None
<> 144:ef7eb2e8f9f7 130 */
<> 144:ef7eb2e8f9f7 131 void HAL_PWR_EnableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 132 {
<> 144:ef7eb2e8f9f7 133 /* Enable access to RTC and backup registers */
<> 144:ef7eb2e8f9f7 134 SET_BIT(PWR->CR1, PWR_CR1_DBP);
<> 144:ef7eb2e8f9f7 135 }
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief Disables access to the backup domain (RTC registers, RTC
<> 144:ef7eb2e8f9f7 139 * backup data registers and backup SRAM).
<> 144:ef7eb2e8f9f7 140 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
<> 144:ef7eb2e8f9f7 141 * Backup Domain Access should be kept enabled.
<> 144:ef7eb2e8f9f7 142 * @retval None
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144 void HAL_PWR_DisableBkUpAccess(void)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 /* Disable access to RTC and backup registers */
<> 144:ef7eb2e8f9f7 147 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
<> 144:ef7eb2e8f9f7 148 }
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /**
<> 144:ef7eb2e8f9f7 151 * @}
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 155 * @brief Low Power modes configuration functions
<> 144:ef7eb2e8f9f7 156 *
<> 144:ef7eb2e8f9f7 157 @verbatim
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 ===============================================================================
<> 144:ef7eb2e8f9f7 160 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 161 ===============================================================================
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 *** PVD configuration ***
<> 144:ef7eb2e8f9f7 164 =========================
<> 144:ef7eb2e8f9f7 165 [..]
<> 144:ef7eb2e8f9f7 166 (+) The PVD is used to monitor the VDD power supply by comparing it to a
<> 144:ef7eb2e8f9f7 167 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
<> 144:ef7eb2e8f9f7 168 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
<> 144:ef7eb2e8f9f7 169 than the PVD threshold. This event is internally connected to the EXTI
<> 144:ef7eb2e8f9f7 170 line16 and can generate an interrupt if enabled. This is done through
<> 144:ef7eb2e8f9f7 171 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
<> 144:ef7eb2e8f9f7 172 (+) The PVD is stopped in Standby mode.
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 *** Wake-up pin configuration ***
<> 144:ef7eb2e8f9f7 175 ================================
<> 144:ef7eb2e8f9f7 176 [..]
<> 144:ef7eb2e8f9f7 177 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
<> 144:ef7eb2e8f9f7 178 forced in input pull-down configuration and is active on rising edges.
<> 144:ef7eb2e8f9f7 179 (+) There are to 6 Wake-up pin in the STM32F7 devices family
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 *** Low Power modes configuration ***
<> 144:ef7eb2e8f9f7 182 =====================================
<> 144:ef7eb2e8f9f7 183 [..]
<> 144:ef7eb2e8f9f7 184 The devices feature 3 low-power modes:
<> 144:ef7eb2e8f9f7 185 (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
<> 144:ef7eb2e8f9f7 186 (+) Stop mode: all clocks are stopped, regulator running, regulator
<> 144:ef7eb2e8f9f7 187 in low power mode
<> 144:ef7eb2e8f9f7 188 (+) Standby mode: 1.2V domain powered off.
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 *** Sleep mode ***
<> 144:ef7eb2e8f9f7 191 ==================
<> 144:ef7eb2e8f9f7 192 [..]
<> 144:ef7eb2e8f9f7 193 (+) Entry:
<> 144:ef7eb2e8f9f7 194 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 195 functions with
<> 144:ef7eb2e8f9f7 196 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 197 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 -@@- The Regulator parameter is not used for the STM32F7 family
<> 144:ef7eb2e8f9f7 200 and is kept as parameter just to maintain compatibility with the
<> 144:ef7eb2e8f9f7 201 lower power families (STM32L).
<> 144:ef7eb2e8f9f7 202 (+) Exit:
<> 144:ef7eb2e8f9f7 203 Any peripheral interrupt acknowledged by the nested vectored interrupt
<> 144:ef7eb2e8f9f7 204 controller (NVIC) can wake up the device from Sleep mode.
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 *** Stop mode ***
<> 144:ef7eb2e8f9f7 207 =================
<> 144:ef7eb2e8f9f7 208 [..]
<> 144:ef7eb2e8f9f7 209 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
<> 144:ef7eb2e8f9f7 210 and the HSE RC oscillators are disabled. Internal SRAM and register contents
<> 144:ef7eb2e8f9f7 211 are preserved.
<> 144:ef7eb2e8f9f7 212 The voltage regulator can be configured either in normal or low-power mode.
<> 144:ef7eb2e8f9f7 213 To minimize the consumption In Stop mode, FLASH can be powered off before
<> 144:ef7eb2e8f9f7 214 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
<> 144:ef7eb2e8f9f7 215 It can be switched on again by software after exiting the Stop mode using
<> 144:ef7eb2e8f9f7 216 the HAL_PWREx_DisableFlashPowerDown() function.
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 (+) Entry:
<> 144:ef7eb2e8f9f7 219 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
<> 144:ef7eb2e8f9f7 220 function with:
<> 144:ef7eb2e8f9f7 221 (++) Main regulator ON.
<> 144:ef7eb2e8f9f7 222 (++) Low Power regulator ON.
<> 144:ef7eb2e8f9f7 223 (+) Exit:
<> 144:ef7eb2e8f9f7 224 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 *** Standby mode ***
<> 144:ef7eb2e8f9f7 227 ====================
<> 144:ef7eb2e8f9f7 228 [..]
<> 144:ef7eb2e8f9f7 229 (+)
<> 144:ef7eb2e8f9f7 230 The Standby mode allows to achieve the lowest power consumption. It is based
<> 144:ef7eb2e8f9f7 231 on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
<> 144:ef7eb2e8f9f7 232 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
<> 144:ef7eb2e8f9f7 233 the HSE oscillator are also switched off. SRAM and register contents are lost
<> 144:ef7eb2e8f9f7 234 except for the RTC registers, RTC backup registers, backup SRAM and Standby
<> 144:ef7eb2e8f9f7 235 circuitry.
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 The voltage regulator is OFF.
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 (++) Entry:
<> 144:ef7eb2e8f9f7 240 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
<> 144:ef7eb2e8f9f7 241 (++) Exit:
<> 144:ef7eb2e8f9f7 242 (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
<> 144:ef7eb2e8f9f7 243 wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 *** Auto-wakeup (AWU) from low-power mode ***
<> 144:ef7eb2e8f9f7 246 =============================================
<> 144:ef7eb2e8f9f7 247 [..]
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
<> 144:ef7eb2e8f9f7 250 Wakeup event, a tamper event or a time-stamp event, without depending on
<> 144:ef7eb2e8f9f7 251 an external interrupt (Auto-wakeup mode).
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
<> 144:ef7eb2e8f9f7 256 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
<> 144:ef7eb2e8f9f7 259 is necessary to configure the RTC to detect the tamper or time stamp event using the
<> 144:ef7eb2e8f9f7 260 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
<> 144:ef7eb2e8f9f7 263 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 @endverbatim
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 271 * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
<> 144:ef7eb2e8f9f7 272 * information for the PVD.
<> 144:ef7eb2e8f9f7 273 * @note Refer to the electrical characteristics of your device datasheet for
<> 144:ef7eb2e8f9f7 274 * more details about the voltage threshold corresponding to each
<> 144:ef7eb2e8f9f7 275 * detection level.
<> 144:ef7eb2e8f9f7 276 * @retval None
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* Check the parameters */
<> 144:ef7eb2e8f9f7 281 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
<> 144:ef7eb2e8f9f7 282 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /* Set PLS[7:5] bits according to PVDLevel value */
<> 144:ef7eb2e8f9f7 285 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 288 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 289 __HAL_PWR_PVD_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 290 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 291 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 294 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 __HAL_PWR_PVD_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Configure event mode */
<> 144:ef7eb2e8f9f7 300 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
<> 144:ef7eb2e8f9f7 301 {
<> 144:ef7eb2e8f9f7 302 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Configure the edge */
<> 144:ef7eb2e8f9f7 306 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 309 }
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 }
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /**
<> 144:ef7eb2e8f9f7 318 * @brief Enables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 319 * @retval None
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321 void HAL_PWR_EnablePVD(void)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 /* Enable the power voltage detector */
<> 144:ef7eb2e8f9f7 324 SET_BIT(PWR->CR1, PWR_CR1_PVDE);
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @brief Disables the Power Voltage Detector(PVD).
<> 144:ef7eb2e8f9f7 329 * @retval None
<> 144:ef7eb2e8f9f7 330 */
<> 144:ef7eb2e8f9f7 331 void HAL_PWR_DisablePVD(void)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 /* Disable the power voltage detector */
<> 144:ef7eb2e8f9f7 334 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Enable the WakeUp PINx functionality.
<> 144:ef7eb2e8f9f7 339 * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
<> 144:ef7eb2e8f9f7 340 * This parameter can be one of the following legacy values, which sets the default polarity:
<> 144:ef7eb2e8f9f7 341 * detection on high level (rising edge):
<> 144:ef7eb2e8f9f7 342 * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
<> 144:ef7eb2e8f9f7 343 * or one of the following value where the user can explicitly states the enabled pin and
<> 144:ef7eb2e8f9f7 344 * the chosen polarity
<> 144:ef7eb2e8f9f7 345 * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
<> 144:ef7eb2e8f9f7 346 * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
<> 144:ef7eb2e8f9f7 347 * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
<> 144:ef7eb2e8f9f7 348 * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
<> 144:ef7eb2e8f9f7 349 * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
<> 144:ef7eb2e8f9f7 350 * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
<> 144:ef7eb2e8f9f7 351 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
<> 144:ef7eb2e8f9f7 352 * @retval None
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Enable wake-up pin */
<> 144:ef7eb2e8f9f7 359 SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 /* Specifies the Wake-Up pin polarity for the event detection
<> 144:ef7eb2e8f9f7 362 (rising or falling edge) */
<> 144:ef7eb2e8f9f7 363 MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @brief Disables the WakeUp PINx functionality.
<> 144:ef7eb2e8f9f7 368 * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
<> 144:ef7eb2e8f9f7 369 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 370 * @arg PWR_WAKEUP_PIN1
<> 144:ef7eb2e8f9f7 371 * @arg PWR_WAKEUP_PIN2
<> 144:ef7eb2e8f9f7 372 * @arg PWR_WAKEUP_PIN3
<> 144:ef7eb2e8f9f7 373 * @arg PWR_WAKEUP_PIN4
<> 144:ef7eb2e8f9f7 374 * @arg PWR_WAKEUP_PIN5
<> 144:ef7eb2e8f9f7 375 * @arg PWR_WAKEUP_PIN6
<> 144:ef7eb2e8f9f7 376 * @retval None
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
<> 144:ef7eb2e8f9f7 379 {
<> 144:ef7eb2e8f9f7 380 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 CLEAR_BIT(PWR->CSR2, WakeUpPinx);
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @brief Enters Sleep mode.
<> 144:ef7eb2e8f9f7 387 *
<> 144:ef7eb2e8f9f7 388 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 389 *
<> 144:ef7eb2e8f9f7 390 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
<> 144:ef7eb2e8f9f7 391 * systick interrupt when used as time base for Timeout
<> 144:ef7eb2e8f9f7 392 *
<> 144:ef7eb2e8f9f7 393 * @param Regulator: Specifies the regulator state in SLEEP mode.
<> 144:ef7eb2e8f9f7 394 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 395 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
<> 144:ef7eb2e8f9f7 396 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
<> 144:ef7eb2e8f9f7 397 * @note This parameter is not used for the STM32F7 family and is kept as parameter
<> 144:ef7eb2e8f9f7 398 * just to maintain compatibility with the lower power families.
<> 144:ef7eb2e8f9f7 399 * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 400 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 401 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
<> 144:ef7eb2e8f9f7 402 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 /* Check the parameters */
<> 144:ef7eb2e8f9f7 408 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 409 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 412 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /* Select SLEEP mode entry -------------------------------------------------*/
<> 144:ef7eb2e8f9f7 415 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
<> 144:ef7eb2e8f9f7 416 {
<> 144:ef7eb2e8f9f7 417 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 418 __WFI();
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420 else
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 423 __SEV();
<> 144:ef7eb2e8f9f7 424 __WFE();
<> 144:ef7eb2e8f9f7 425 __WFE();
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Enters Stop mode.
<> 144:ef7eb2e8f9f7 431 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 432 * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 433 * the HSI RC oscillator is selected as system clock.
<> 144:ef7eb2e8f9f7 434 * @note When the voltage regulator operates in low power mode, an additional
<> 144:ef7eb2e8f9f7 435 * startup delay is incurred when waking up from Stop mode.
<> 144:ef7eb2e8f9f7 436 * By keeping the internal regulator ON during Stop mode, the consumption
<> 144:ef7eb2e8f9f7 437 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 438 * @param Regulator: Specifies the regulator state in Stop mode.
<> 144:ef7eb2e8f9f7 439 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 440 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
<> 144:ef7eb2e8f9f7 441 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
<> 144:ef7eb2e8f9f7 442 * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 443 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 444 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 445 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 446 * @retval None
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 uint32_t tmpreg = 0;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_PWR_REGULATOR(Regulator));
<> 144:ef7eb2e8f9f7 454 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 /* Select the regulator state in Stop mode ---------------------------------*/
<> 144:ef7eb2e8f9f7 457 tmpreg = PWR->CR1;
<> 144:ef7eb2e8f9f7 458 /* Clear PDDS and LPDS bits */
<> 144:ef7eb2e8f9f7 459 tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
<> 144:ef7eb2e8f9f7 462 tmpreg |= Regulator;
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 /* Store the new value */
<> 144:ef7eb2e8f9f7 465 PWR->CR1 = tmpreg;
<> 144:ef7eb2e8f9f7 466
<> 144:ef7eb2e8f9f7 467 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 468 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 471 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 472 {
<> 144:ef7eb2e8f9f7 473 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 474 __WFI();
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476 else
<> 144:ef7eb2e8f9f7 477 {
<> 144:ef7eb2e8f9f7 478 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 479 __SEV();
<> 144:ef7eb2e8f9f7 480 __WFE();
<> 144:ef7eb2e8f9f7 481 __WFE();
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 484 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /**
<> 144:ef7eb2e8f9f7 488 * @brief Enters Standby mode.
<> 144:ef7eb2e8f9f7 489 * @note In Standby mode, all I/O pins are high impedance except for:
<> 144:ef7eb2e8f9f7 490 * - Reset pad (still available)
<> 144:ef7eb2e8f9f7 491 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
<> 144:ef7eb2e8f9f7 492 * Alarm out, or RTC clock calibration out.
<> 144:ef7eb2e8f9f7 493 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
<> 144:ef7eb2e8f9f7 494 * - WKUP pins if enabled.
<> 144:ef7eb2e8f9f7 495 * @retval None
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497 void HAL_PWR_EnterSTANDBYMode(void)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 /* Select Standby mode */
<> 144:ef7eb2e8f9f7 500 PWR->CR1 |= PWR_CR1_PDDS;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 503 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 506 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 507 __force_stores();
<> 144:ef7eb2e8f9f7 508 #endif
<> 144:ef7eb2e8f9f7 509 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 510 __WFI();
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief This function handles the PWR PVD interrupt request.
<> 144:ef7eb2e8f9f7 515 * @note This API should be called under the PVD_IRQHandler().
<> 144:ef7eb2e8f9f7 516 * @retval None
<> 144:ef7eb2e8f9f7 517 */
<> 144:ef7eb2e8f9f7 518 void HAL_PWR_PVD_IRQHandler(void)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* Check PWR Exti flag */
<> 144:ef7eb2e8f9f7 521 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* PWR PVD interrupt user callback */
<> 144:ef7eb2e8f9f7 524 HAL_PWR_PVDCallback();
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Clear PWR Exti pending bit */
<> 144:ef7eb2e8f9f7 527 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @brief PWR PVD interrupt callback
<> 144:ef7eb2e8f9f7 533 * @retval None
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 __weak void HAL_PWR_PVDCallback(void)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 538 the HAL_PWR_PVDCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 539 */
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 544 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 545 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 546 * Setting this bit is useful when the processor is expected to run only on
<> 144:ef7eb2e8f9f7 547 * interruptions handling.
<> 144:ef7eb2e8f9f7 548 * @retval None
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 void HAL_PWR_EnableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 553 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 /**
<> 144:ef7eb2e8f9f7 557 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
<> 144:ef7eb2e8f9f7 558 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
<> 144:ef7eb2e8f9f7 559 * re-enters SLEEP mode when an interruption handling is over.
<> 144:ef7eb2e8f9f7 560 * @retval None
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562 void HAL_PWR_DisableSleepOnExit(void)
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 565 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /**
<> 144:ef7eb2e8f9f7 569 * @brief Enables CORTEX M4 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 570 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 571 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 572 * @retval None
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 void HAL_PWR_EnableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 575 {
<> 144:ef7eb2e8f9f7 576 /* Set SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 577 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @brief Disables CORTEX M4 SEVONPEND bit.
<> 144:ef7eb2e8f9f7 582 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
<> 144:ef7eb2e8f9f7 583 * WFE to wake up when an interrupt moves from inactive to pended.
<> 144:ef7eb2e8f9f7 584 * @retval None
<> 144:ef7eb2e8f9f7 585 */
<> 144:ef7eb2e8f9f7 586 void HAL_PWR_DisableSEVOnPend(void)
<> 144:ef7eb2e8f9f7 587 {
<> 144:ef7eb2e8f9f7 588 /* Clear SEVONPEND bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 589 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 144:ef7eb2e8f9f7 590 }
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /**
<> 144:ef7eb2e8f9f7 593 * @}
<> 144:ef7eb2e8f9f7 594 */
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /**
<> 144:ef7eb2e8f9f7 597 * @}
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @}
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @}
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/