mbed-dev - added prescaler for 16 bit pwm in LPC1347 target

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added prescaler for 16 bit pwm in LPC1347 target

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 83:a036322b8637

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f7xx_hal_hash_ex.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.1.0
<>	144:ef7eb2e8f9f7	6	* @date 22-April-2016
<>	144:ef7eb2e8f9f7	7	* @brief HASH HAL Extension module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of HASH peripheral:
<>	144:ef7eb2e8f9f7	10	* + Extended HASH processing functions based on SHA224 Algorithm
<>	144:ef7eb2e8f9f7	11	* + Extended HASH processing functions based on SHA256 Algorithm
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	@verbatim
<>	144:ef7eb2e8f9f7	14	==============================================================================
<>	144:ef7eb2e8f9f7	15	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	16	==============================================================================
<>	144:ef7eb2e8f9f7	17	[..]
<>	144:ef7eb2e8f9f7	18	The HASH HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	19	(#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
<>	144:ef7eb2e8f9f7	20	(##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
<>	144:ef7eb2e8f9f7	21	(##) In case of using processing APIs based on interrupts (e.g. HAL_HMACEx_SHA224_Start())
<>	144:ef7eb2e8f9f7	22	(+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
<>	144:ef7eb2e8f9f7	23	(+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
<>	144:ef7eb2e8f9f7	24	(+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
<>	144:ef7eb2e8f9f7	25	(##) In case of using DMA to control data transfer (e.g. HAL_HMACEx_SH224_Start_DMA())
<>	144:ef7eb2e8f9f7	26	(+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
<>	144:ef7eb2e8f9f7	27	(+++) Configure and enable one DMA stream one for managing data transfer from
<>	144:ef7eb2e8f9f7	28	memory to peripheral (input stream). Managing data transfer from
<>	144:ef7eb2e8f9f7	29	peripheral to memory can be performed only using CPU
<>	144:ef7eb2e8f9f7	30	(+++) Associate the initialized DMA handle to the HASH DMA handle
<>	144:ef7eb2e8f9f7	31	using __HAL_LINKDMA()
<>	144:ef7eb2e8f9f7	32	(+++) Configure the priority and enable the NVIC for the transfer complete
<>	144:ef7eb2e8f9f7	33	interrupt on the DMA Stream: HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
<>	144:ef7eb2e8f9f7	34	(#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
<>	144:ef7eb2e8f9f7	35	(##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
<>	144:ef7eb2e8f9f7	36	(##) For HMAC, the encryption key.
<>	144:ef7eb2e8f9f7	37	(##) For HMAC, the key size used for encryption.
<>	144:ef7eb2e8f9f7	38	(#)Three processing functions are available:
<>	144:ef7eb2e8f9f7	39	(##) Polling mode: processing APIs are blocking functions
<>	144:ef7eb2e8f9f7	40	i.e. they process the data and wait till the digest computation is finished
<>	144:ef7eb2e8f9f7	41	e.g. HAL_HASHEx_SHA224_Start()
<>	144:ef7eb2e8f9f7	42	(##) Interrupt mode: encryption and decryption APIs are not blocking functions
<>	144:ef7eb2e8f9f7	43	i.e. they process the data under interrupt
<>	144:ef7eb2e8f9f7	44	e.g. HAL_HASHEx_SHA224_Start_IT()
<>	144:ef7eb2e8f9f7	45	(##) DMA mode: processing APIs are not blocking functions and the CPU is
<>	144:ef7eb2e8f9f7	46	not used for data transfer i.e. the data transfer is ensured by DMA
<>	144:ef7eb2e8f9f7	47	e.g. HAL_HASHEx_SHA224_Start_DMA()
<>	144:ef7eb2e8f9f7	48	(#)When the processing function is called at first time after HAL_HASH_Init()
<>	144:ef7eb2e8f9f7	49	the HASH peripheral is initialized and processes the buffer in input.
<>	144:ef7eb2e8f9f7	50	After that, the digest computation is started.
<>	144:ef7eb2e8f9f7	51	When processing multi-buffer use the accumulate function to write the
<>	144:ef7eb2e8f9f7	52	data in the peripheral without starting the digest computation. In last
<>	144:ef7eb2e8f9f7	53	buffer use the start function to input the last buffer ans start the digest
<>	144:ef7eb2e8f9f7	54	computation.
<>	144:ef7eb2e8f9f7	55	(##) e.g. HAL_HASHEx_SHA224_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
<>	144:ef7eb2e8f9f7	56	(##) write (n-1)th data buffer in the peripheral without starting the digest computation
<>	144:ef7eb2e8f9f7	57	(##) HAL_HASHEx_SHA224_Start() : write (n)th data buffer in the peripheral and start the digest computation
<>	144:ef7eb2e8f9f7	58	(#)In HMAC mode, there is no Accumulate API. Only Start API is available.
<>	144:ef7eb2e8f9f7	59	(#)In case of using DMA, call the DMA start processing e.g. HAL_HASHEx_SHA224_Start_DMA().
<>	144:ef7eb2e8f9f7	60	After that, call the finish function in order to get the digest value
<>	144:ef7eb2e8f9f7	61	e.g. HAL_HASHEx_SHA224_Finish()
<>	144:ef7eb2e8f9f7	62	(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	@endverbatim
<>	144:ef7eb2e8f9f7	65	******************************************************************************
<>	144:ef7eb2e8f9f7	66	* @attention
<>	144:ef7eb2e8f9f7	67	*
<>	144:ef7eb2e8f9f7	68	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	69	*
<>	144:ef7eb2e8f9f7	70	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	71	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	72	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	73	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	74	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	75	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	76	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	77	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	78	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	79	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	80	*
<>	144:ef7eb2e8f9f7	81	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	82	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	83	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	84	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	85	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	86	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	87	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	88	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	89	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	90	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	91	*
<>	144:ef7eb2e8f9f7	92	******************************************************************************
<>	144:ef7eb2e8f9f7	93	*/
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	96	#include "stm32f7xx_hal.h"
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	/** @addtogroup STM32F7xx_HAL_Driver
<>	144:ef7eb2e8f9f7	99	* @{
<>	144:ef7eb2e8f9f7	100	*/
<>	144:ef7eb2e8f9f7	101	#if defined(STM32F756xx) \|\| defined(STM32F777xx) \|\| defined(STM32F779xx)
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	/** @defgroup HASHEx HASHEx
<>	144:ef7eb2e8f9f7	104	* @brief HASH Extension HAL module driver.
<>	144:ef7eb2e8f9f7	105	* @{
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	#ifdef HAL_HASH_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	111	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	112	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	113	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	114	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	115	/** @addtogroup HASHEx_Private_Functions
<>	144:ef7eb2e8f9f7	116	* @{
<>	144:ef7eb2e8f9f7	117	*/
<>	144:ef7eb2e8f9f7	118	static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	119	static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size);
<>	144:ef7eb2e8f9f7	120	static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
<>	144:ef7eb2e8f9f7	121	static void HASHEx_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	122	/**
<>	144:ef7eb2e8f9f7	123	* @}
<>	144:ef7eb2e8f9f7	124	*/
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	/* Private functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	/** @addtogroup HASHEx_Private_Functions
<>	144:ef7eb2e8f9f7	129	* @{
<>	144:ef7eb2e8f9f7	130	*/
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	/**
<>	144:ef7eb2e8f9f7	133	* @brief Writes the input buffer in data register.
<>	144:ef7eb2e8f9f7	134	* @param pInBuffer: Pointer to input buffer
<>	144:ef7eb2e8f9f7	135	* @param Size: The size of input buffer
<>	144:ef7eb2e8f9f7	136	* @retval None
<>	144:ef7eb2e8f9f7	137	*/
<>	144:ef7eb2e8f9f7	138	static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	139	{
<>	144:ef7eb2e8f9f7	140	uint32_t buffercounter;
<>	144:ef7eb2e8f9f7	141	uint32_t inputaddr = (uint32_t) pInBuffer;
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	for(buffercounter = 0; buffercounter < Size; buffercounter+=4)
<>	144:ef7eb2e8f9f7	144	{
<>	144:ef7eb2e8f9f7	145	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	146	inputaddr+=4;
<>	144:ef7eb2e8f9f7	147	}
<>	144:ef7eb2e8f9f7	148	}
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	/**
<>	144:ef7eb2e8f9f7	151	* @brief Provides the message digest result.
<>	144:ef7eb2e8f9f7	152	* @param pMsgDigest: Pointer to the message digest
<>	144:ef7eb2e8f9f7	153	* @param Size: The size of the message digest in bytes
<>	144:ef7eb2e8f9f7	154	* @retval None
<>	144:ef7eb2e8f9f7	155	*/
<>	144:ef7eb2e8f9f7	156	static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
<>	144:ef7eb2e8f9f7	157	{
<>	144:ef7eb2e8f9f7	158	uint32_t msgdigest = (uint32_t)pMsgDigest;
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	switch(Size)
<>	144:ef7eb2e8f9f7	161	{
<>	144:ef7eb2e8f9f7	162	case 16:
<>	144:ef7eb2e8f9f7	163	/* Read the message digest */
<>	144:ef7eb2e8f9f7	164	(uint32_t)(msgdigest) = __REV(HASH->HR[0]);
<>	144:ef7eb2e8f9f7	165	msgdigest+=4;
<>	144:ef7eb2e8f9f7	166	(uint32_t)(msgdigest) = __REV(HASH->HR[1]);
<>	144:ef7eb2e8f9f7	167	msgdigest+=4;
<>	144:ef7eb2e8f9f7	168	(uint32_t)(msgdigest) = __REV(HASH->HR[2]);
<>	144:ef7eb2e8f9f7	169	msgdigest+=4;
<>	144:ef7eb2e8f9f7	170	(uint32_t)(msgdigest) = __REV(HASH->HR[3]);
<>	144:ef7eb2e8f9f7	171	break;
<>	144:ef7eb2e8f9f7	172	case 20:
<>	144:ef7eb2e8f9f7	173	/* Read the message digest */
<>	144:ef7eb2e8f9f7	174	(uint32_t)(msgdigest) = __REV(HASH->HR[0]);
<>	144:ef7eb2e8f9f7	175	msgdigest+=4;
<>	144:ef7eb2e8f9f7	176	(uint32_t)(msgdigest) = __REV(HASH->HR[1]);
<>	144:ef7eb2e8f9f7	177	msgdigest+=4;
<>	144:ef7eb2e8f9f7	178	(uint32_t)(msgdigest) = __REV(HASH->HR[2]);
<>	144:ef7eb2e8f9f7	179	msgdigest+=4;
<>	144:ef7eb2e8f9f7	180	(uint32_t)(msgdigest) = __REV(HASH->HR[3]);
<>	144:ef7eb2e8f9f7	181	msgdigest+=4;
<>	144:ef7eb2e8f9f7	182	(uint32_t)(msgdigest) = __REV(HASH->HR[4]);
<>	144:ef7eb2e8f9f7	183	break;
<>	144:ef7eb2e8f9f7	184	case 28:
<>	144:ef7eb2e8f9f7	185	/* Read the message digest */
<>	144:ef7eb2e8f9f7	186	(uint32_t)(msgdigest) = __REV(HASH->HR[0]);
<>	144:ef7eb2e8f9f7	187	msgdigest+=4;
<>	144:ef7eb2e8f9f7	188	(uint32_t)(msgdigest) = __REV(HASH->HR[1]);
<>	144:ef7eb2e8f9f7	189	msgdigest+=4;
<>	144:ef7eb2e8f9f7	190	(uint32_t)(msgdigest) = __REV(HASH->HR[2]);
<>	144:ef7eb2e8f9f7	191	msgdigest+=4;
<>	144:ef7eb2e8f9f7	192	(uint32_t)(msgdigest) = __REV(HASH->HR[3]);
<>	144:ef7eb2e8f9f7	193	msgdigest+=4;
<>	144:ef7eb2e8f9f7	194	(uint32_t)(msgdigest) = __REV(HASH->HR[4]);
<>	144:ef7eb2e8f9f7	195	msgdigest+=4;
<>	144:ef7eb2e8f9f7	196	(uint32_t)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
<>	144:ef7eb2e8f9f7	197	msgdigest+=4;
<>	144:ef7eb2e8f9f7	198	(uint32_t)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
<>	144:ef7eb2e8f9f7	199	break;
<>	144:ef7eb2e8f9f7	200	case 32:
<>	144:ef7eb2e8f9f7	201	/* Read the message digest */
<>	144:ef7eb2e8f9f7	202	(uint32_t)(msgdigest) = __REV(HASH->HR[0]);
<>	144:ef7eb2e8f9f7	203	msgdigest+=4;
<>	144:ef7eb2e8f9f7	204	(uint32_t)(msgdigest) = __REV(HASH->HR[1]);
<>	144:ef7eb2e8f9f7	205	msgdigest+=4;
<>	144:ef7eb2e8f9f7	206	(uint32_t)(msgdigest) = __REV(HASH->HR[2]);
<>	144:ef7eb2e8f9f7	207	msgdigest+=4;
<>	144:ef7eb2e8f9f7	208	(uint32_t)(msgdigest) = __REV(HASH->HR[3]);
<>	144:ef7eb2e8f9f7	209	msgdigest+=4;
<>	144:ef7eb2e8f9f7	210	(uint32_t)(msgdigest) = __REV(HASH->HR[4]);
<>	144:ef7eb2e8f9f7	211	msgdigest+=4;
<>	144:ef7eb2e8f9f7	212	(uint32_t)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
<>	144:ef7eb2e8f9f7	213	msgdigest+=4;
<>	144:ef7eb2e8f9f7	214	(uint32_t)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
<>	144:ef7eb2e8f9f7	215	msgdigest+=4;
<>	144:ef7eb2e8f9f7	216	(uint32_t)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
<>	144:ef7eb2e8f9f7	217	break;
<>	144:ef7eb2e8f9f7	218	default:
<>	144:ef7eb2e8f9f7	219	break;
<>	144:ef7eb2e8f9f7	220	}
<>	144:ef7eb2e8f9f7	221	}
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/**
<>	144:ef7eb2e8f9f7	224	* @brief DMA HASH Input Data complete callback.
<>	144:ef7eb2e8f9f7	225	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	226	* @retval None
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228	static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	229	{
<>	144:ef7eb2e8f9f7	230	HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	231	uint32_t inputaddr = 0;
<>	144:ef7eb2e8f9f7	232	uint32_t buffersize = 0;
<>	144:ef7eb2e8f9f7	233
<>	144:ef7eb2e8f9f7	234	if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
<>	144:ef7eb2e8f9f7	235	{
<>	144:ef7eb2e8f9f7	236	/* Disable the DMA transfer */
<>	144:ef7eb2e8f9f7	237	HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	238
<>	144:ef7eb2e8f9f7	239	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	240	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/* Call Input data transfer complete callback */
<>	144:ef7eb2e8f9f7	243	HAL_HASH_InCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	244	}
<>	144:ef7eb2e8f9f7	245	else
<>	144:ef7eb2e8f9f7	246	{
<>	144:ef7eb2e8f9f7	247	/* Increment Interrupt counter */
<>	144:ef7eb2e8f9f7	248	hhash->HashInCount++;
<>	144:ef7eb2e8f9f7	249	/* Disable the DMA transfer before starting the next transfer */
<>	144:ef7eb2e8f9f7	250	HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	if(hhash->HashInCount <= 2)
<>	144:ef7eb2e8f9f7	253	{
<>	144:ef7eb2e8f9f7	254	/* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
<>	144:ef7eb2e8f9f7	255	if(hhash->HashInCount == 1)
<>	144:ef7eb2e8f9f7	256	{
<>	144:ef7eb2e8f9f7	257	inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<>	144:ef7eb2e8f9f7	258	buffersize = hhash->HashBuffSize;
<>	144:ef7eb2e8f9f7	259	}
<>	144:ef7eb2e8f9f7	260	/* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
<>	144:ef7eb2e8f9f7	261	else if(hhash->HashInCount == 2)
<>	144:ef7eb2e8f9f7	262	{
<>	144:ef7eb2e8f9f7	263	inputaddr = (uint32_t)hhash->Init.pKey;
<>	144:ef7eb2e8f9f7	264	buffersize = hhash->Init.KeySize;
<>	144:ef7eb2e8f9f7	265	}
<>	144:ef7eb2e8f9f7	266	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	267	MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * (buffersize % 4));
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	/* Set the HASH DMA transfer complete */
<>	144:ef7eb2e8f9f7	270	hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	/* Enable the DMA In DMA Stream */
<>	144:ef7eb2e8f9f7	273	HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4 ? (buffersize+3)/4:buffersize/4));
<>	144:ef7eb2e8f9f7	274
<>	144:ef7eb2e8f9f7	275	/* Enable DMA requests */
<>	144:ef7eb2e8f9f7	276	HASH->CR \|= (HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	277	}
<>	144:ef7eb2e8f9f7	278	else
<>	144:ef7eb2e8f9f7	279	{
<>	144:ef7eb2e8f9f7	280	/* Disable the DMA transfer */
<>	144:ef7eb2e8f9f7	281	HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* Reset the InCount */
<>	144:ef7eb2e8f9f7	284	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	287	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/* Call Input data transfer complete callback */
<>	144:ef7eb2e8f9f7	290	HAL_HASH_InCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	291	}
<>	144:ef7eb2e8f9f7	292	}
<>	144:ef7eb2e8f9f7	293	}
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	/**
<>	144:ef7eb2e8f9f7	296	* @brief DMA HASH communication error callback.
<>	144:ef7eb2e8f9f7	297	* @param hdma: DMA handle
<>	144:ef7eb2e8f9f7	298	* @retval None
<>	144:ef7eb2e8f9f7	299	*/
<>	144:ef7eb2e8f9f7	300	static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	301	{
<>	144:ef7eb2e8f9f7	302	HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	303	hhash->State= HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	304	HAL_HASH_ErrorCallback(hhash);
<>	144:ef7eb2e8f9f7	305	}
<>	144:ef7eb2e8f9f7	306
<>	144:ef7eb2e8f9f7	307	/**
<>	144:ef7eb2e8f9f7	308	* @}
<>	144:ef7eb2e8f9f7	309	*/
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	312	/** @addtogroup HASHEx_Exported_Functions
<>	144:ef7eb2e8f9f7	313	* @{
<>	144:ef7eb2e8f9f7	314	*/
<>	144:ef7eb2e8f9f7	315
<>	144:ef7eb2e8f9f7	316	/** @defgroup HASHEx_Group1 HASH processing functions
<>	144:ef7eb2e8f9f7	317	* @brief processing functions using polling mode
<>	144:ef7eb2e8f9f7	318	*
<>	144:ef7eb2e8f9f7	319	@verbatim
<>	144:ef7eb2e8f9f7	320	===============================================================================
<>	144:ef7eb2e8f9f7	321	##### HASH processing using polling mode functions #####
<>	144:ef7eb2e8f9f7	322	===============================================================================
<>	144:ef7eb2e8f9f7	323	[..] This section provides functions allowing to calculate in polling mode
<>	144:ef7eb2e8f9f7	324	the hash value using one of the following algorithms:
<>	144:ef7eb2e8f9f7	325	(+) SHA224
<>	144:ef7eb2e8f9f7	326	(+) SHA256
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	@endverbatim
<>	144:ef7eb2e8f9f7	329	* @{
<>	144:ef7eb2e8f9f7	330	*/
<>	144:ef7eb2e8f9f7	331
<>	144:ef7eb2e8f9f7	332	/**
<>	144:ef7eb2e8f9f7	333	* @brief Initializes the HASH peripheral in SHA224 mode
<>	144:ef7eb2e8f9f7	334	* then processes pInBuffer. The digest is available in pOutBuffer
<>	144:ef7eb2e8f9f7	335	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	336	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	337	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	338	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	339	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	340	* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
<>	144:ef7eb2e8f9f7	341	* @param Timeout: Specify Timeout value
<>	144:ef7eb2e8f9f7	342	* @retval HAL status
<>	144:ef7eb2e8f9f7	343	*/
<>	144:ef7eb2e8f9f7	344	HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	345	{
<>	144:ef7eb2e8f9f7	346	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/* Process Locked */
<>	144:ef7eb2e8f9f7	349	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	352	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	355	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	356	{
<>	144:ef7eb2e8f9f7	357	/* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	358	the message digest of a new message */
<>	144:ef7eb2e8f9f7	359	HASH->CR \|= HASH_ALGOSELECTION_SHA224 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	360	}
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/* Set the phase */
<>	144:ef7eb2e8f9f7	363	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	366	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	369	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	372	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	/* Get tick */
<>	144:ef7eb2e8f9f7	375	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	378	{
<>	144:ef7eb2e8f9f7	379	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	380	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	381	{
<>	144:ef7eb2e8f9f7	382	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	383	{
<>	144:ef7eb2e8f9f7	384	/* Change state */
<>	144:ef7eb2e8f9f7	385	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	386
<>	144:ef7eb2e8f9f7	387	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	388	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	389
<>	144:ef7eb2e8f9f7	390	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	391	}
<>	144:ef7eb2e8f9f7	392	}
<>	144:ef7eb2e8f9f7	393	}
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/* Read the message digest */
<>	144:ef7eb2e8f9f7	396	HASHEx_GetDigest(pOutBuffer, 28);
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	399	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	402	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	/* Return function status */
<>	144:ef7eb2e8f9f7	405	return HAL_OK;
<>	144:ef7eb2e8f9f7	406	}
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	/**
<>	144:ef7eb2e8f9f7	409	* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
<>	144:ef7eb2e8f9f7	410	The digest is available in pOutBuffer.
<>	144:ef7eb2e8f9f7	411	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	412	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	413	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	414	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	415	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	416	* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
<>	144:ef7eb2e8f9f7	417	* @param Timeout: Specify Timeout value
<>	144:ef7eb2e8f9f7	418	* @retval HAL status
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420	HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	421	{
<>	144:ef7eb2e8f9f7	422	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/* Process Locked */
<>	144:ef7eb2e8f9f7	425	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	426
<>	144:ef7eb2e8f9f7	427	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	428	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	431	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	432	{
<>	144:ef7eb2e8f9f7	433	/* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	434	the message digest of a new message */
<>	144:ef7eb2e8f9f7	435	HASH->CR \|= HASH_ALGOSELECTION_SHA256 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	436	}
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/* Set the phase */
<>	144:ef7eb2e8f9f7	439	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	440
<>	144:ef7eb2e8f9f7	441	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	442	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	445	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	448	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/* Get tick */
<>	144:ef7eb2e8f9f7	451	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	454	{
<>	144:ef7eb2e8f9f7	455	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	456	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	459	{
<>	144:ef7eb2e8f9f7	460	/* Change state */
<>	144:ef7eb2e8f9f7	461	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	462
<>	144:ef7eb2e8f9f7	463	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	464	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	467	}
<>	144:ef7eb2e8f9f7	468	}
<>	144:ef7eb2e8f9f7	469	}
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	/* Read the message digest */
<>	144:ef7eb2e8f9f7	472	HASHEx_GetDigest(pOutBuffer, 32);
<>	144:ef7eb2e8f9f7	473
<>	144:ef7eb2e8f9f7	474	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	475	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	478	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/* Return function status */
<>	144:ef7eb2e8f9f7	481	return HAL_OK;
<>	144:ef7eb2e8f9f7	482	}
<>	144:ef7eb2e8f9f7	483
<>	144:ef7eb2e8f9f7	484
<>	144:ef7eb2e8f9f7	485	/**
<>	144:ef7eb2e8f9f7	486	* @brief Initializes the HASH peripheral in SHA224 mode
<>	144:ef7eb2e8f9f7	487	* then processes pInBuffer. The digest is available in pOutBuffer
<>	144:ef7eb2e8f9f7	488	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	489	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	490	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	491	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	492	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	493	* @retval HAL status
<>	144:ef7eb2e8f9f7	494	*/
<>	144:ef7eb2e8f9f7	495	HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	496	{
<>	144:ef7eb2e8f9f7	497	/* Process Locked */
<>	144:ef7eb2e8f9f7	498	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	499
<>	144:ef7eb2e8f9f7	500	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	501	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	504	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	505	{
<>	144:ef7eb2e8f9f7	506	/* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	507	the message digest of a new message */
<>	144:ef7eb2e8f9f7	508	HASH->CR \|= HASH_ALGOSELECTION_SHA224 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	509	}
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/* Set the phase */
<>	144:ef7eb2e8f9f7	512	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	515	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	516
<>	144:ef7eb2e8f9f7	517	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	518	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	519
<>	144:ef7eb2e8f9f7	520	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	521	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	524	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/* Return function status */
<>	144:ef7eb2e8f9f7	527	return HAL_OK;
<>	144:ef7eb2e8f9f7	528	}
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	/**
<>	144:ef7eb2e8f9f7	532	* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
<>	144:ef7eb2e8f9f7	533	The digest is available in pOutBuffer.
<>	144:ef7eb2e8f9f7	534	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	535	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	536	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	537	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	538	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	539	* @retval HAL status
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541	HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	542	{
<>	144:ef7eb2e8f9f7	543	/* Process Locked */
<>	144:ef7eb2e8f9f7	544	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	545
<>	144:ef7eb2e8f9f7	546	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	547	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	548
<>	144:ef7eb2e8f9f7	549	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	550	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	551	{
<>	144:ef7eb2e8f9f7	552	/* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	553	the message digest of a new message */
<>	144:ef7eb2e8f9f7	554	HASH->CR \|= HASH_ALGOSELECTION_SHA256 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	555	}
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/* Set the phase */
<>	144:ef7eb2e8f9f7	558	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	559
<>	144:ef7eb2e8f9f7	560	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	561	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	564	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	567	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	568
<>	144:ef7eb2e8f9f7	569	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	570	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	571
<>	144:ef7eb2e8f9f7	572	/* Return function status */
<>	144:ef7eb2e8f9f7	573	return HAL_OK;
<>	144:ef7eb2e8f9f7	574	}
<>	144:ef7eb2e8f9f7	575
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	/**
<>	144:ef7eb2e8f9f7	578	* @}
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/** @defgroup HASHEx_Group2 HMAC processing functions using polling mode
<>	144:ef7eb2e8f9f7	582	* @brief HMAC processing functions using polling mode .
<>	144:ef7eb2e8f9f7	583	*
<>	144:ef7eb2e8f9f7	584	@verbatim
<>	144:ef7eb2e8f9f7	585	===============================================================================
<>	144:ef7eb2e8f9f7	586	##### HMAC processing using polling mode functions #####
<>	144:ef7eb2e8f9f7	587	===============================================================================
<>	144:ef7eb2e8f9f7	588	[..] This section provides functions allowing to calculate in polling mode
<>	144:ef7eb2e8f9f7	589	the HMAC value using one of the following algorithms:
<>	144:ef7eb2e8f9f7	590	(+) SHA224
<>	144:ef7eb2e8f9f7	591	(+) SHA256
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	@endverbatim
<>	144:ef7eb2e8f9f7	594	* @{
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/**
<>	144:ef7eb2e8f9f7	598	* @brief Initializes the HASH peripheral in HMAC SHA224 mode
<>	144:ef7eb2e8f9f7	599	* then processes pInBuffer. The digest is available in pOutBuffer.
<>	144:ef7eb2e8f9f7	600	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	601	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	602	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	603	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	604	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	605	* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<>	144:ef7eb2e8f9f7	606	* @param Timeout: Timeout value
<>	144:ef7eb2e8f9f7	607	* @retval HAL status
<>	144:ef7eb2e8f9f7	608	*/
<>	144:ef7eb2e8f9f7	609	HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	610	{
<>	144:ef7eb2e8f9f7	611	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/* Process Locked */
<>	144:ef7eb2e8f9f7	614	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	617	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	618
<>	144:ef7eb2e8f9f7	619	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	620	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	621	{
<>	144:ef7eb2e8f9f7	622	/* Check if key size is greater than 64 bytes */
<>	144:ef7eb2e8f9f7	623	if(hhash->Init.KeySize > 64)
<>	144:ef7eb2e8f9f7	624	{
<>	144:ef7eb2e8f9f7	625	/* Select the HMAC SHA224 mode */
<>	144:ef7eb2e8f9f7	626	HASH->CR \|= (HASH_ALGOSELECTION_SHA224 \| HASH_ALGOMODE_HMAC \| HASH_HMAC_KEYTYPE_LONGKEY \| HASH_CR_INIT);
<>	144:ef7eb2e8f9f7	627	}
<>	144:ef7eb2e8f9f7	628	else
<>	144:ef7eb2e8f9f7	629	{
<>	144:ef7eb2e8f9f7	630	/* Select the HMAC SHA224 mode */
<>	144:ef7eb2e8f9f7	631	HASH->CR \|= (HASH_ALGOSELECTION_SHA224 \| HASH_ALGOMODE_HMAC \| HASH_CR_INIT);
<>	144:ef7eb2e8f9f7	632	}
<>	144:ef7eb2e8f9f7	633	}
<>	144:ef7eb2e8f9f7	634
<>	144:ef7eb2e8f9f7	635	/* Set the phase */
<>	144:ef7eb2e8f9f7	636	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	637
<>	144:ef7eb2e8f9f7	638	/************************ STEP 1 ****************************************/
<>	144:ef7eb2e8f9f7	639	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	640	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	643	HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	644
<>	144:ef7eb2e8f9f7	645	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	646	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	647
<>	144:ef7eb2e8f9f7	648	/* Get tick */
<>	144:ef7eb2e8f9f7	649	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	650
<>	144:ef7eb2e8f9f7	651	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	652	{
<>	144:ef7eb2e8f9f7	653	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	654	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	655	{
<>	144:ef7eb2e8f9f7	656	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	657	{
<>	144:ef7eb2e8f9f7	658	/* Change state */
<>	144:ef7eb2e8f9f7	659	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	662	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	665	}
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667	}
<>	144:ef7eb2e8f9f7	668	/************************ STEP 2 ****************************************/
<>	144:ef7eb2e8f9f7	669	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	670	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	673	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	676	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	677
<>	144:ef7eb2e8f9f7	678	/* Get tick */
<>	144:ef7eb2e8f9f7	679	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	680
<>	144:ef7eb2e8f9f7	681	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	682	{
<>	144:ef7eb2e8f9f7	683	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	684	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	685	{
<>	144:ef7eb2e8f9f7	686	if((HAL_GetTick() - tickstart ) > Timeout)
<>	144:ef7eb2e8f9f7	687	{
<>	144:ef7eb2e8f9f7	688	/* Change state */
<>	144:ef7eb2e8f9f7	689	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	692	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	695	}
<>	144:ef7eb2e8f9f7	696	}
<>	144:ef7eb2e8f9f7	697	}
<>	144:ef7eb2e8f9f7	698	/************************ STEP 3 ****************************************/
<>	144:ef7eb2e8f9f7	699	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	700	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	703	HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	706	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	/* Get tick */
<>	144:ef7eb2e8f9f7	709	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	710
<>	144:ef7eb2e8f9f7	711	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	712	{
<>	144:ef7eb2e8f9f7	713	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	714	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	715	{
<>	144:ef7eb2e8f9f7	716	if((HAL_GetTick() - tickstart ) > Timeout)
<>	144:ef7eb2e8f9f7	717	{
<>	144:ef7eb2e8f9f7	718	/* Change state */
<>	144:ef7eb2e8f9f7	719	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	720
<>	144:ef7eb2e8f9f7	721	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	722	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	725	}
<>	144:ef7eb2e8f9f7	726	}
<>	144:ef7eb2e8f9f7	727	}
<>	144:ef7eb2e8f9f7	728	/* Read the message digest */
<>	144:ef7eb2e8f9f7	729	HASHEx_GetDigest(pOutBuffer, 28);
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	732	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	735	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/* Return function status */
<>	144:ef7eb2e8f9f7	738	return HAL_OK;
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/**
<>	144:ef7eb2e8f9f7	742	* @brief Initializes the HASH peripheral in HMAC SHA256 mode
<>	144:ef7eb2e8f9f7	743	* then processes pInBuffer. The digest is available in pOutBuffer
<>	144:ef7eb2e8f9f7	744	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	745	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	746	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	747	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	748	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	749	* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<>	144:ef7eb2e8f9f7	750	* @param Timeout: Timeout value
<>	144:ef7eb2e8f9f7	751	* @retval HAL status
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753	HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	754	{
<>	144:ef7eb2e8f9f7	755	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	/* Process Locked */
<>	144:ef7eb2e8f9f7	758	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	761	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	764	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	765	{
<>	144:ef7eb2e8f9f7	766	/* Check if key size is greater than 64 bytes */
<>	144:ef7eb2e8f9f7	767	if(hhash->Init.KeySize > 64)
<>	144:ef7eb2e8f9f7	768	{
<>	144:ef7eb2e8f9f7	769	/* Select the HMAC SHA256 mode */
<>	144:ef7eb2e8f9f7	770	HASH->CR \|= (HASH_ALGOSELECTION_SHA256 \| HASH_ALGOMODE_HMAC \| HASH_HMAC_KEYTYPE_LONGKEY);
<>	144:ef7eb2e8f9f7	771	}
<>	144:ef7eb2e8f9f7	772	else
<>	144:ef7eb2e8f9f7	773	{
<>	144:ef7eb2e8f9f7	774	/* Select the HMAC SHA256 mode */
<>	144:ef7eb2e8f9f7	775	HASH->CR \|= (HASH_ALGOSELECTION_SHA256 \| HASH_ALGOMODE_HMAC);
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777	/* Reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	778	the message digest of a new message */
<>	144:ef7eb2e8f9f7	779	HASH->CR \|= HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	780	}
<>	144:ef7eb2e8f9f7	781
<>	144:ef7eb2e8f9f7	782	/* Set the phase */
<>	144:ef7eb2e8f9f7	783	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785	/************************ STEP 1 ****************************************/
<>	144:ef7eb2e8f9f7	786	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	787	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	788
<>	144:ef7eb2e8f9f7	789	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	790	HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	793	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	794
<>	144:ef7eb2e8f9f7	795	/* Get tick */
<>	144:ef7eb2e8f9f7	796	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	799	{
<>	144:ef7eb2e8f9f7	800	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	801	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	802	{
<>	144:ef7eb2e8f9f7	803	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	804	{
<>	144:ef7eb2e8f9f7	805	/* Change state */
<>	144:ef7eb2e8f9f7	806	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	807
<>	144:ef7eb2e8f9f7	808	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	809	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	812	}
<>	144:ef7eb2e8f9f7	813	}
<>	144:ef7eb2e8f9f7	814	}
<>	144:ef7eb2e8f9f7	815	/************************ STEP 2 ****************************************/
<>	144:ef7eb2e8f9f7	816	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	817	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	818
<>	144:ef7eb2e8f9f7	819	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	820	HASHEx_WriteData(pInBuffer, Size);
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	823	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/* Get tick */
<>	144:ef7eb2e8f9f7	826	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	829	{
<>	144:ef7eb2e8f9f7	830	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	831	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	832	{
<>	144:ef7eb2e8f9f7	833	if((HAL_GetTick() - tickstart ) > Timeout)
<>	144:ef7eb2e8f9f7	834	{
<>	144:ef7eb2e8f9f7	835	/* Change state */
<>	144:ef7eb2e8f9f7	836	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	839	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	842	}
<>	144:ef7eb2e8f9f7	843	}
<>	144:ef7eb2e8f9f7	844	}
<>	144:ef7eb2e8f9f7	845	/************************ STEP 3 ****************************************/
<>	144:ef7eb2e8f9f7	846	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	847	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	848
<>	144:ef7eb2e8f9f7	849	/* Write input buffer in data register */
<>	144:ef7eb2e8f9f7	850	HASHEx_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	853	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/* Get tick */
<>	144:ef7eb2e8f9f7	856	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	while((HASH->SR & HASH_FLAG_BUSY) == HASH_FLAG_BUSY)
<>	144:ef7eb2e8f9f7	859	{
<>	144:ef7eb2e8f9f7	860	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	861	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	if((HAL_GetTick() - tickstart ) > Timeout)
<>	144:ef7eb2e8f9f7	864	{
<>	144:ef7eb2e8f9f7	865	/* Change state */
<>	144:ef7eb2e8f9f7	866	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	869	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	872	}
<>	144:ef7eb2e8f9f7	873	}
<>	144:ef7eb2e8f9f7	874	}
<>	144:ef7eb2e8f9f7	875	/* Read the message digest */
<>	144:ef7eb2e8f9f7	876	HASHEx_GetDigest(pOutBuffer, 32);
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	879	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	882	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Return function status */
<>	144:ef7eb2e8f9f7	885	return HAL_OK;
<>	144:ef7eb2e8f9f7	886	}
<>	144:ef7eb2e8f9f7	887
<>	144:ef7eb2e8f9f7	888	/**
<>	144:ef7eb2e8f9f7	889	* @}
<>	144:ef7eb2e8f9f7	890	*/
<>	144:ef7eb2e8f9f7	891
<>	144:ef7eb2e8f9f7	892	/** @defgroup HASHEx_Group3 HASH processing functions using interrupt mode
<>	144:ef7eb2e8f9f7	893	* @brief processing functions using interrupt mode.
<>	144:ef7eb2e8f9f7	894	*
<>	144:ef7eb2e8f9f7	895	@verbatim
<>	144:ef7eb2e8f9f7	896	===============================================================================
<>	144:ef7eb2e8f9f7	897	##### HASH processing using interrupt functions #####
<>	144:ef7eb2e8f9f7	898	===============================================================================
<>	144:ef7eb2e8f9f7	899	[..] This section provides functions allowing to calculate in interrupt mode
<>	144:ef7eb2e8f9f7	900	the hash value using one of the following algorithms:
<>	144:ef7eb2e8f9f7	901	(+) SHA224
<>	144:ef7eb2e8f9f7	902	(+) SHA256
<>	144:ef7eb2e8f9f7	903
<>	144:ef7eb2e8f9f7	904	@endverbatim
<>	144:ef7eb2e8f9f7	905	* @{
<>	144:ef7eb2e8f9f7	906	*/
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/**
<>	144:ef7eb2e8f9f7	909	* @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
<>	144:ef7eb2e8f9f7	910	* The digest is available in pOutBuffer.
<>	144:ef7eb2e8f9f7	911	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	912	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	913	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	914	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	915	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	916	* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<>	144:ef7eb2e8f9f7	917	* @retval HAL status
<>	144:ef7eb2e8f9f7	918	*/
<>	144:ef7eb2e8f9f7	919	HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<>	144:ef7eb2e8f9f7	920	{
<>	144:ef7eb2e8f9f7	921	uint32_t inputaddr;
<>	144:ef7eb2e8f9f7	922	uint32_t buffercounter;
<>	144:ef7eb2e8f9f7	923	uint32_t inputcounter;
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/* Process Locked */
<>	144:ef7eb2e8f9f7	926	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	if(hhash->State == HAL_HASH_STATE_READY)
<>	144:ef7eb2e8f9f7	929	{
<>	144:ef7eb2e8f9f7	930	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	931	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	932
<>	144:ef7eb2e8f9f7	933	hhash->HashInCount = Size;
<>	144:ef7eb2e8f9f7	934	hhash->pHashInBuffPtr = pInBuffer;
<>	144:ef7eb2e8f9f7	935	hhash->pHashOutBuffPtr = pOutBuffer;
<>	144:ef7eb2e8f9f7	936
<>	144:ef7eb2e8f9f7	937	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	938	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	939	{
<>	144:ef7eb2e8f9f7	940	/* Select the SHA224 mode */
<>	144:ef7eb2e8f9f7	941	HASH->CR \|= HASH_ALGOSELECTION_SHA224;
<>	144:ef7eb2e8f9f7	942	/* Reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	943	the message digest of a new message */
<>	144:ef7eb2e8f9f7	944	HASH->CR \|= HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	945	}
<>	144:ef7eb2e8f9f7	946	/* Reset interrupt counter */
<>	144:ef7eb2e8f9f7	947	hhash->HashITCounter = 0;
<>	144:ef7eb2e8f9f7	948	/* Set the phase */
<>	144:ef7eb2e8f9f7	949	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	950
<>	144:ef7eb2e8f9f7	951	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	952	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/* Enable Interrupts */
<>	144:ef7eb2e8f9f7	955	HASH->IMR = (HASH_IT_DINI \| HASH_IT_DCI);
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	/* Return function status */
<>	144:ef7eb2e8f9f7	958	return HAL_OK;
<>	144:ef7eb2e8f9f7	959	}
<>	144:ef7eb2e8f9f7	960	if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<>	144:ef7eb2e8f9f7	961	{
<>	144:ef7eb2e8f9f7	962	/* Read the message digest */
<>	144:ef7eb2e8f9f7	963	HASHEx_GetDigest(hhash->pHashOutBuffPtr, 28);
<>	144:ef7eb2e8f9f7	964	if(hhash->HashInCount == 0)
<>	144:ef7eb2e8f9f7	965	{
<>	144:ef7eb2e8f9f7	966	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	967	HASH->IMR = 0;
<>	144:ef7eb2e8f9f7	968	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	969	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	970	/* Call digest computation complete callback */
<>	144:ef7eb2e8f9f7	971	HAL_HASH_DgstCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	972	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	973	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	/* Return function status */
<>	144:ef7eb2e8f9f7	976	return HAL_OK;
<>	144:ef7eb2e8f9f7	977	}
<>	144:ef7eb2e8f9f7	978	}
<>	144:ef7eb2e8f9f7	979	if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<>	144:ef7eb2e8f9f7	980	{
<>	144:ef7eb2e8f9f7	981	if(hhash->HashInCount >= 68)
<>	144:ef7eb2e8f9f7	982	{
<>	144:ef7eb2e8f9f7	983	inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<>	144:ef7eb2e8f9f7	984	/* Write the Input block in the Data IN register */
<>	144:ef7eb2e8f9f7	985	for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
<>	144:ef7eb2e8f9f7	986	{
<>	144:ef7eb2e8f9f7	987	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	988	inputaddr+=4;
<>	144:ef7eb2e8f9f7	989	}
<>	144:ef7eb2e8f9f7	990	if(hhash->HashITCounter == 0)
<>	144:ef7eb2e8f9f7	991	{
<>	144:ef7eb2e8f9f7	992	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	993	if(hhash->HashInCount >= 68)
<>	144:ef7eb2e8f9f7	994	{
<>	144:ef7eb2e8f9f7	995	/* Decrement buffer counter */
<>	144:ef7eb2e8f9f7	996	hhash->HashInCount -= 68;
<>	144:ef7eb2e8f9f7	997	hhash->pHashInBuffPtr+= 68;
<>	144:ef7eb2e8f9f7	998	}
<>	144:ef7eb2e8f9f7	999	else
<>	144:ef7eb2e8f9f7	1000	{
<>	144:ef7eb2e8f9f7	1001	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1002	hhash->pHashInBuffPtr+= hhash->HashInCount;
<>	144:ef7eb2e8f9f7	1003	}
<>	144:ef7eb2e8f9f7	1004	/* Set Interrupt counter */
<>	144:ef7eb2e8f9f7	1005	hhash->HashITCounter = 1;
<>	144:ef7eb2e8f9f7	1006	}
<>	144:ef7eb2e8f9f7	1007	else
<>	144:ef7eb2e8f9f7	1008	{
<>	144:ef7eb2e8f9f7	1009	/* Decrement buffer counter */
<>	144:ef7eb2e8f9f7	1010	hhash->HashInCount -= 64;
<>	144:ef7eb2e8f9f7	1011	hhash->pHashInBuffPtr+= 64;
<>	144:ef7eb2e8f9f7	1012	}
<>	144:ef7eb2e8f9f7	1013	}
<>	144:ef7eb2e8f9f7	1014	else
<>	144:ef7eb2e8f9f7	1015	{
<>	144:ef7eb2e8f9f7	1016	/* Get the buffer address */
<>	144:ef7eb2e8f9f7	1017	inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<>	144:ef7eb2e8f9f7	1018	/* Get the buffer counter */
<>	144:ef7eb2e8f9f7	1019	inputcounter = hhash->HashInCount;
<>	144:ef7eb2e8f9f7	1020	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	1021	HASH->IMR &= ~(HASH_IT_DINI);
<>	144:ef7eb2e8f9f7	1022	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1023	__HAL_HASH_SET_NBVALIDBITS(inputcounter);
<>	144:ef7eb2e8f9f7	1024
<>	144:ef7eb2e8f9f7	1025	if((inputcounter > 4) && (inputcounter%4))
<>	144:ef7eb2e8f9f7	1026	{
<>	144:ef7eb2e8f9f7	1027	inputcounter = (inputcounter+4-inputcounter%4);
<>	144:ef7eb2e8f9f7	1028	}
<>	144:ef7eb2e8f9f7	1029	else if ((inputcounter < 4) && (inputcounter != 0))
<>	144:ef7eb2e8f9f7	1030	{
<>	144:ef7eb2e8f9f7	1031	inputcounter = 4;
<>	144:ef7eb2e8f9f7	1032	}
<>	144:ef7eb2e8f9f7	1033	/* Write the Input block in the Data IN register */
<>	144:ef7eb2e8f9f7	1034	for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
<>	144:ef7eb2e8f9f7	1035	{
<>	144:ef7eb2e8f9f7	1036	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	1037	inputaddr+=4;
<>	144:ef7eb2e8f9f7	1038	}
<>	144:ef7eb2e8f9f7	1039	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	1040	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	1041	/* Reset buffer counter */
<>	144:ef7eb2e8f9f7	1042	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1043	/* Call Input data transfer complete callback */
<>	144:ef7eb2e8f9f7	1044	HAL_HASH_InCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	1045	}
<>	144:ef7eb2e8f9f7	1046	}
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1049	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1050
<>	144:ef7eb2e8f9f7	1051	/* Return function status */
<>	144:ef7eb2e8f9f7	1052	return HAL_OK;
<>	144:ef7eb2e8f9f7	1053	}
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055
<>	144:ef7eb2e8f9f7	1056	/**
<>	144:ef7eb2e8f9f7	1057	* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
<>	144:ef7eb2e8f9f7	1058	* The digest is available in pOutBuffer.
<>	144:ef7eb2e8f9f7	1059	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1060	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1061	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	1062	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	1063	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	1064	* @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<>	144:ef7eb2e8f9f7	1065	* @retval HAL status
<>	144:ef7eb2e8f9f7	1066	*/
<>	144:ef7eb2e8f9f7	1067	HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<>	144:ef7eb2e8f9f7	1068	{
<>	144:ef7eb2e8f9f7	1069	uint32_t inputaddr;
<>	144:ef7eb2e8f9f7	1070	uint32_t buffercounter;
<>	144:ef7eb2e8f9f7	1071	uint32_t inputcounter;
<>	144:ef7eb2e8f9f7	1072
<>	144:ef7eb2e8f9f7	1073	/* Process Locked */
<>	144:ef7eb2e8f9f7	1074	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1075
<>	144:ef7eb2e8f9f7	1076	if(hhash->State == HAL_HASH_STATE_READY)
<>	144:ef7eb2e8f9f7	1077	{
<>	144:ef7eb2e8f9f7	1078	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1079	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1080
<>	144:ef7eb2e8f9f7	1081	hhash->HashInCount = Size;
<>	144:ef7eb2e8f9f7	1082	hhash->pHashInBuffPtr = pInBuffer;
<>	144:ef7eb2e8f9f7	1083	hhash->pHashOutBuffPtr = pOutBuffer;
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	1086	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	1087	{
<>	144:ef7eb2e8f9f7	1088	/* Select the SHA256 mode */
<>	144:ef7eb2e8f9f7	1089	HASH->CR \|= HASH_ALGOSELECTION_SHA256;
<>	144:ef7eb2e8f9f7	1090	/* Reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	1091	the message digest of a new message */
<>	144:ef7eb2e8f9f7	1092	HASH->CR \|= HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	1093	}
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	/* Reset interrupt counter */
<>	144:ef7eb2e8f9f7	1096	hhash->HashITCounter = 0;
<>	144:ef7eb2e8f9f7	1097
<>	144:ef7eb2e8f9f7	1098	/* Set the phase */
<>	144:ef7eb2e8f9f7	1099	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	1100
<>	144:ef7eb2e8f9f7	1101	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1102	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/* Enable Interrupts */
<>	144:ef7eb2e8f9f7	1105	HASH->IMR = (HASH_IT_DINI \| HASH_IT_DCI);
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/* Return function status */
<>	144:ef7eb2e8f9f7	1108	return HAL_OK;
<>	144:ef7eb2e8f9f7	1109	}
<>	144:ef7eb2e8f9f7	1110	if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<>	144:ef7eb2e8f9f7	1111	{
<>	144:ef7eb2e8f9f7	1112	/* Read the message digest */
<>	144:ef7eb2e8f9f7	1113	HASHEx_GetDigest(hhash->pHashOutBuffPtr, 32);
<>	144:ef7eb2e8f9f7	1114	if(hhash->HashInCount == 0)
<>	144:ef7eb2e8f9f7	1115	{
<>	144:ef7eb2e8f9f7	1116	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	1117	HASH->IMR = 0;
<>	144:ef7eb2e8f9f7	1118	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1119	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	1120	/* Call digest computation complete callback */
<>	144:ef7eb2e8f9f7	1121	HAL_HASH_DgstCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1124	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/* Return function status */
<>	144:ef7eb2e8f9f7	1127	return HAL_OK;
<>	144:ef7eb2e8f9f7	1128	}
<>	144:ef7eb2e8f9f7	1129	}
<>	144:ef7eb2e8f9f7	1130	if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<>	144:ef7eb2e8f9f7	1131	{
<>	144:ef7eb2e8f9f7	1132	if(hhash->HashInCount >= 68)
<>	144:ef7eb2e8f9f7	1133	{
<>	144:ef7eb2e8f9f7	1134	inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<>	144:ef7eb2e8f9f7	1135	/* Write the Input block in the Data IN register */
<>	144:ef7eb2e8f9f7	1136	for(buffercounter = 0; buffercounter < 64; buffercounter+=4)
<>	144:ef7eb2e8f9f7	1137	{
<>	144:ef7eb2e8f9f7	1138	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	1139	inputaddr+=4;
<>	144:ef7eb2e8f9f7	1140	}
<>	144:ef7eb2e8f9f7	1141	if(hhash->HashITCounter == 0)
<>	144:ef7eb2e8f9f7	1142	{
<>	144:ef7eb2e8f9f7	1143	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	1144
<>	144:ef7eb2e8f9f7	1145	if(hhash->HashInCount >= 68)
<>	144:ef7eb2e8f9f7	1146	{
<>	144:ef7eb2e8f9f7	1147	/* Decrement buffer counter */
<>	144:ef7eb2e8f9f7	1148	hhash->HashInCount -= 68;
<>	144:ef7eb2e8f9f7	1149	hhash->pHashInBuffPtr+= 68;
<>	144:ef7eb2e8f9f7	1150	}
<>	144:ef7eb2e8f9f7	1151	else
<>	144:ef7eb2e8f9f7	1152	{
<>	144:ef7eb2e8f9f7	1153	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1154	hhash->pHashInBuffPtr+= hhash->HashInCount;
<>	144:ef7eb2e8f9f7	1155	}
<>	144:ef7eb2e8f9f7	1156	/* Set Interrupt counter */
<>	144:ef7eb2e8f9f7	1157	hhash->HashITCounter = 1;
<>	144:ef7eb2e8f9f7	1158	}
<>	144:ef7eb2e8f9f7	1159	else
<>	144:ef7eb2e8f9f7	1160	{
<>	144:ef7eb2e8f9f7	1161	/* Decrement buffer counter */
<>	144:ef7eb2e8f9f7	1162	hhash->HashInCount -= 64;
<>	144:ef7eb2e8f9f7	1163	hhash->pHashInBuffPtr+= 64;
<>	144:ef7eb2e8f9f7	1164	}
<>	144:ef7eb2e8f9f7	1165	}
<>	144:ef7eb2e8f9f7	1166	else
<>	144:ef7eb2e8f9f7	1167	{
<>	144:ef7eb2e8f9f7	1168	/* Get the buffer address */
<>	144:ef7eb2e8f9f7	1169	inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<>	144:ef7eb2e8f9f7	1170	/* Get the buffer counter */
<>	144:ef7eb2e8f9f7	1171	inputcounter = hhash->HashInCount;
<>	144:ef7eb2e8f9f7	1172	/* Disable Interrupts */
<>	144:ef7eb2e8f9f7	1173	HASH->IMR &= ~(HASH_IT_DINI);
<>	144:ef7eb2e8f9f7	1174	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1175	__HAL_HASH_SET_NBVALIDBITS(inputcounter);
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	if((inputcounter > 4) && (inputcounter%4))
<>	144:ef7eb2e8f9f7	1178	{
<>	144:ef7eb2e8f9f7	1179	inputcounter = (inputcounter+4-inputcounter%4);
<>	144:ef7eb2e8f9f7	1180	}
<>	144:ef7eb2e8f9f7	1181	else if ((inputcounter < 4) && (inputcounter != 0))
<>	144:ef7eb2e8f9f7	1182	{
<>	144:ef7eb2e8f9f7	1183	inputcounter = 4;
<>	144:ef7eb2e8f9f7	1184	}
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/* Write the Input block in the Data IN register */
<>	144:ef7eb2e8f9f7	1187	for(buffercounter = 0; buffercounter < inputcounter/4; buffercounter++)
<>	144:ef7eb2e8f9f7	1188	{
<>	144:ef7eb2e8f9f7	1189	HASH->DIN = (uint32_t)inputaddr;
<>	144:ef7eb2e8f9f7	1190	inputaddr+=4;
<>	144:ef7eb2e8f9f7	1191	}
<>	144:ef7eb2e8f9f7	1192	/* Start the digest calculation */
<>	144:ef7eb2e8f9f7	1193	__HAL_HASH_START_DIGEST();
<>	144:ef7eb2e8f9f7	1194	/* Reset buffer counter */
<>	144:ef7eb2e8f9f7	1195	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1196	/* Call Input data transfer complete callback */
<>	144:ef7eb2e8f9f7	1197	HAL_HASH_InCpltCallback(hhash);
<>	144:ef7eb2e8f9f7	1198	}
<>	144:ef7eb2e8f9f7	1199	}
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1202	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/* Return function status */
<>	144:ef7eb2e8f9f7	1205	return HAL_OK;
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207
<>	144:ef7eb2e8f9f7	1208	/**
<>	144:ef7eb2e8f9f7	1209	* @brief This function handles HASH interrupt request.
<>	144:ef7eb2e8f9f7	1210	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1211	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1212	* @retval None
<>	144:ef7eb2e8f9f7	1213	*/
<>	144:ef7eb2e8f9f7	1214	void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash)
<>	144:ef7eb2e8f9f7	1215	{
<>	144:ef7eb2e8f9f7	1216	switch(HASH->CR & HASH_CR_ALGO)
<>	144:ef7eb2e8f9f7	1217	{
<>	144:ef7eb2e8f9f7	1218
<>	144:ef7eb2e8f9f7	1219	case HASH_ALGOSELECTION_SHA224:
<>	144:ef7eb2e8f9f7	1220	HAL_HASHEx_SHA224_Start_IT(hhash, NULL, 0, NULL);
<>	144:ef7eb2e8f9f7	1221	break;
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	case HASH_ALGOSELECTION_SHA256:
<>	144:ef7eb2e8f9f7	1224	HAL_HASHEx_SHA256_Start_IT(hhash, NULL, 0, NULL);
<>	144:ef7eb2e8f9f7	1225	break;
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	default:
<>	144:ef7eb2e8f9f7	1228	break;
<>	144:ef7eb2e8f9f7	1229	}
<>	144:ef7eb2e8f9f7	1230	}
<>	144:ef7eb2e8f9f7	1231
<>	144:ef7eb2e8f9f7	1232	/**
<>	144:ef7eb2e8f9f7	1233	* @}
<>	144:ef7eb2e8f9f7	1234	*/
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	/** @defgroup HASHEx_Group4 HASH processing functions using DMA mode
<>	144:ef7eb2e8f9f7	1237	* @brief processing functions using DMA mode.
<>	144:ef7eb2e8f9f7	1238	*
<>	144:ef7eb2e8f9f7	1239	@verbatim
<>	144:ef7eb2e8f9f7	1240	===============================================================================
<>	144:ef7eb2e8f9f7	1241	##### HASH processing using DMA functions #####
<>	144:ef7eb2e8f9f7	1242	===============================================================================
<>	144:ef7eb2e8f9f7	1243	[..] This section provides functions allowing to calculate in DMA mode
<>	144:ef7eb2e8f9f7	1244	the hash value using one of the following algorithms:
<>	144:ef7eb2e8f9f7	1245	(+) SHA224
<>	144:ef7eb2e8f9f7	1246	(+) SHA256
<>	144:ef7eb2e8f9f7	1247
<>	144:ef7eb2e8f9f7	1248	@endverbatim
<>	144:ef7eb2e8f9f7	1249	* @{
<>	144:ef7eb2e8f9f7	1250	*/
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252
<>	144:ef7eb2e8f9f7	1253	/**
<>	144:ef7eb2e8f9f7	1254	* @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
<>	144:ef7eb2e8f9f7	1255	control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
<>	144:ef7eb2e8f9f7	1256	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1257	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1258	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	1259	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	1260	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	1261	* @retval HAL status
<>	144:ef7eb2e8f9f7	1262	*/
<>	144:ef7eb2e8f9f7	1263	HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	1264	{
<>	144:ef7eb2e8f9f7	1265	uint32_t inputaddr = (uint32_t)pInBuffer;
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	/* Process Locked */
<>	144:ef7eb2e8f9f7	1268	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1269
<>	144:ef7eb2e8f9f7	1270	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1271	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1272
<>	144:ef7eb2e8f9f7	1273	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	1274	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	1275	{
<>	144:ef7eb2e8f9f7	1276	/* Select the SHA224 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	1277	the message digest of a new message */
<>	144:ef7eb2e8f9f7	1278	HASH->CR \|= HASH_ALGOSELECTION_SHA224 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	1279	}
<>	144:ef7eb2e8f9f7	1280
<>	144:ef7eb2e8f9f7	1281	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1282	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/* Set the phase */
<>	144:ef7eb2e8f9f7	1285	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	/* Set the HASH DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1288	hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1289	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1290	hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* Enable the DMA In DMA Stream */
<>	144:ef7eb2e8f9f7	1293	HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	/* Enable DMA requests */
<>	144:ef7eb2e8f9f7	1296	HASH->CR \|= (HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	1297
<>	144:ef7eb2e8f9f7	1298	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1299	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301	/* Return function status */
<>	144:ef7eb2e8f9f7	1302	return HAL_OK;
<>	144:ef7eb2e8f9f7	1303	}
<>	144:ef7eb2e8f9f7	1304
<>	144:ef7eb2e8f9f7	1305	/**
<>	144:ef7eb2e8f9f7	1306	* @brief Returns the computed digest in SHA224
<>	144:ef7eb2e8f9f7	1307	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1308	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1309	* @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
<>	144:ef7eb2e8f9f7	1310	* @param Timeout: Timeout value
<>	144:ef7eb2e8f9f7	1311	* @retval HAL status
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313	HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef hhash, uint8_t pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1314	{
<>	144:ef7eb2e8f9f7	1315	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/* Process Locked */
<>	144:ef7eb2e8f9f7	1318	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	1321	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323	/* Get tick */
<>	144:ef7eb2e8f9f7	1324	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1325
<>	144:ef7eb2e8f9f7	1326	while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<>	144:ef7eb2e8f9f7	1327	{
<>	144:ef7eb2e8f9f7	1328	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1329	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1330	{
<>	144:ef7eb2e8f9f7	1331	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	1332	{
<>	144:ef7eb2e8f9f7	1333	/* Change state */
<>	144:ef7eb2e8f9f7	1334	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	1335
<>	144:ef7eb2e8f9f7	1336	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1337	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1340	}
<>	144:ef7eb2e8f9f7	1341	}
<>	144:ef7eb2e8f9f7	1342	}
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/* Read the message digest */
<>	144:ef7eb2e8f9f7	1345	HASHEx_GetDigest(pOutBuffer, 28);
<>	144:ef7eb2e8f9f7	1346
<>	144:ef7eb2e8f9f7	1347	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	1348	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1351	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/* Return function status */
<>	144:ef7eb2e8f9f7	1354	return HAL_OK;
<>	144:ef7eb2e8f9f7	1355	}
<>	144:ef7eb2e8f9f7	1356
<>	144:ef7eb2e8f9f7	1357	/**
<>	144:ef7eb2e8f9f7	1358	* @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
<>	144:ef7eb2e8f9f7	1359	control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
<>	144:ef7eb2e8f9f7	1360	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1361	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1362	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	1363	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	1364	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	1365	* @retval HAL status
<>	144:ef7eb2e8f9f7	1366	*/
<>	144:ef7eb2e8f9f7	1367	HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	1368	{
<>	144:ef7eb2e8f9f7	1369	uint32_t inputaddr = (uint32_t)pInBuffer;
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/* Process Locked */
<>	144:ef7eb2e8f9f7	1372	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1375	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1376
<>	144:ef7eb2e8f9f7	1377	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	1378	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	1379	{
<>	144:ef7eb2e8f9f7	1380	/* Select the SHA256 mode and reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	1381	the message digest of a new message */
<>	144:ef7eb2e8f9f7	1382	HASH->CR \|= HASH_ALGOSELECTION_SHA256 \| HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	1383	}
<>	144:ef7eb2e8f9f7	1384
<>	144:ef7eb2e8f9f7	1385	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1386	__HAL_HASH_SET_NBVALIDBITS(Size);
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/* Set the phase */
<>	144:ef7eb2e8f9f7	1389	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Set the HASH DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1392	hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1393	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1394	hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/* Enable the DMA In DMA Stream */
<>	144:ef7eb2e8f9f7	1397	HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4 ? (Size+3)/4:Size/4));
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/* Enable DMA requests */
<>	144:ef7eb2e8f9f7	1400	HASH->CR \|= (HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	/* Process UnLock */
<>	144:ef7eb2e8f9f7	1403	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	/* Return function status */
<>	144:ef7eb2e8f9f7	1406	return HAL_OK;
<>	144:ef7eb2e8f9f7	1407	}
<>	144:ef7eb2e8f9f7	1408
<>	144:ef7eb2e8f9f7	1409	/**
<>	144:ef7eb2e8f9f7	1410	* @brief Returns the computed digest in SHA256.
<>	144:ef7eb2e8f9f7	1411	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1412	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1413	* @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
<>	144:ef7eb2e8f9f7	1414	* @param Timeout: Timeout value
<>	144:ef7eb2e8f9f7	1415	* @retval HAL status
<>	144:ef7eb2e8f9f7	1416	*/
<>	144:ef7eb2e8f9f7	1417	HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef hhash, uint8_t pOutBuffer, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1418	{
<>	144:ef7eb2e8f9f7	1419	uint32_t tickstart = 0;
<>	144:ef7eb2e8f9f7	1420
<>	144:ef7eb2e8f9f7	1421	/* Process Locked */
<>	144:ef7eb2e8f9f7	1422	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	1425	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1426
<>	144:ef7eb2e8f9f7	1427	/* Get tick */
<>	144:ef7eb2e8f9f7	1428	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	1429
<>	144:ef7eb2e8f9f7	1430	while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<>	144:ef7eb2e8f9f7	1431	{
<>	144:ef7eb2e8f9f7	1432	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	1433	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	1434	{
<>	144:ef7eb2e8f9f7	1435	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	1436	{
<>	144:ef7eb2e8f9f7	1437	/* Change state */
<>	144:ef7eb2e8f9f7	1438	hhash->State = HAL_HASH_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	1439
<>	144:ef7eb2e8f9f7	1440	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1441	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1444	}
<>	144:ef7eb2e8f9f7	1445	}
<>	144:ef7eb2e8f9f7	1446	}
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	/* Read the message digest */
<>	144:ef7eb2e8f9f7	1449	HASHEx_GetDigest(pOutBuffer, 32);
<>	144:ef7eb2e8f9f7	1450
<>	144:ef7eb2e8f9f7	1451	/* Change HASH peripheral state */
<>	144:ef7eb2e8f9f7	1452	hhash->State = HAL_HASH_STATE_READY;
<>	144:ef7eb2e8f9f7	1453
<>	144:ef7eb2e8f9f7	1454	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1455	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1456
<>	144:ef7eb2e8f9f7	1457	/* Return function status */
<>	144:ef7eb2e8f9f7	1458	return HAL_OK;
<>	144:ef7eb2e8f9f7	1459	}
<>	144:ef7eb2e8f9f7	1460
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/**
<>	144:ef7eb2e8f9f7	1463	* @}
<>	144:ef7eb2e8f9f7	1464	*/
<>	144:ef7eb2e8f9f7	1465	/** @defgroup HASHEx_Group5 HMAC processing functions using DMA mode
<>	144:ef7eb2e8f9f7	1466	* @brief HMAC processing functions using DMA mode .
<>	144:ef7eb2e8f9f7	1467	*
<>	144:ef7eb2e8f9f7	1468	@verbatim
<>	144:ef7eb2e8f9f7	1469	===============================================================================
<>	144:ef7eb2e8f9f7	1470	##### HMAC processing using DMA functions #####
<>	144:ef7eb2e8f9f7	1471	===============================================================================
<>	144:ef7eb2e8f9f7	1472	[..] This section provides functions allowing to calculate in DMA mode
<>	144:ef7eb2e8f9f7	1473	the HMAC value using one of the following algorithms:
<>	144:ef7eb2e8f9f7	1474	(+) SHA224
<>	144:ef7eb2e8f9f7	1475	(+) SHA256
<>	144:ef7eb2e8f9f7	1476
<>	144:ef7eb2e8f9f7	1477	@endverbatim
<>	144:ef7eb2e8f9f7	1478	* @{
<>	144:ef7eb2e8f9f7	1479	*/
<>	144:ef7eb2e8f9f7	1480
<>	144:ef7eb2e8f9f7	1481	/**
<>	144:ef7eb2e8f9f7	1482	* @brief Initializes the HASH peripheral in HMAC SHA224 mode
<>	144:ef7eb2e8f9f7	1483	* then enables DMA to control data transfer.
<>	144:ef7eb2e8f9f7	1484	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1485	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1486	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	1487	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	1488	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	1489	* @retval HAL status
<>	144:ef7eb2e8f9f7	1490	*/
<>	144:ef7eb2e8f9f7	1491	HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	1492	{
<>	144:ef7eb2e8f9f7	1493	uint32_t inputaddr;
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495	/* Process Locked */
<>	144:ef7eb2e8f9f7	1496	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1499	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1500
<>	144:ef7eb2e8f9f7	1501	/* Save buffer pointer and size in handle */
<>	144:ef7eb2e8f9f7	1502	hhash->pHashInBuffPtr = pInBuffer;
<>	144:ef7eb2e8f9f7	1503	hhash->HashBuffSize = Size;
<>	144:ef7eb2e8f9f7	1504	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1505
<>	144:ef7eb2e8f9f7	1506	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	1507	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	1508	{
<>	144:ef7eb2e8f9f7	1509	/* Check if key size is greater than 64 bytes */
<>	144:ef7eb2e8f9f7	1510	if(hhash->Init.KeySize > 64)
<>	144:ef7eb2e8f9f7	1511	{
<>	144:ef7eb2e8f9f7	1512	/* Select the HMAC SHA224 mode */
<>	144:ef7eb2e8f9f7	1513	HASH->CR \|= (HASH_ALGOSELECTION_SHA224 \| HASH_ALGOMODE_HMAC \| HASH_HMAC_KEYTYPE_LONGKEY \| HASH_CR_INIT);
<>	144:ef7eb2e8f9f7	1514	}
<>	144:ef7eb2e8f9f7	1515	else
<>	144:ef7eb2e8f9f7	1516	{
<>	144:ef7eb2e8f9f7	1517	/* Select the HMAC SHA224 mode */
<>	144:ef7eb2e8f9f7	1518	HASH->CR \|= (HASH_ALGOSELECTION_SHA224 \| HASH_ALGOMODE_HMAC \| HASH_CR_INIT);
<>	144:ef7eb2e8f9f7	1519	}
<>	144:ef7eb2e8f9f7	1520	}
<>	144:ef7eb2e8f9f7	1521
<>	144:ef7eb2e8f9f7	1522	/* Set the phase */
<>	144:ef7eb2e8f9f7	1523	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1526	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	1527
<>	144:ef7eb2e8f9f7	1528	/* Get the key address */
<>	144:ef7eb2e8f9f7	1529	inputaddr = (uint32_t)(hhash->Init.pKey);
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	/* Set the HASH DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1532	hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1533	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1534	hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536	/* Enable the DMA In DMA Stream */
<>	144:ef7eb2e8f9f7	1537	HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
<>	144:ef7eb2e8f9f7	1538	/* Enable DMA requests */
<>	144:ef7eb2e8f9f7	1539	HASH->CR \|= (HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1542	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1543
<>	144:ef7eb2e8f9f7	1544	/* Return function status */
<>	144:ef7eb2e8f9f7	1545	return HAL_OK;
<>	144:ef7eb2e8f9f7	1546	}
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	/**
<>	144:ef7eb2e8f9f7	1549	* @brief Initializes the HASH peripheral in HMAC SHA256 mode
<>	144:ef7eb2e8f9f7	1550	* then enables DMA to control data transfer.
<>	144:ef7eb2e8f9f7	1551	* @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1552	* the configuration information for HASH module
<>	144:ef7eb2e8f9f7	1553	* @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<>	144:ef7eb2e8f9f7	1554	* @param Size: Length of the input buffer in bytes.
<>	144:ef7eb2e8f9f7	1555	* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<>	144:ef7eb2e8f9f7	1556	* @retval HAL status
<>	144:ef7eb2e8f9f7	1557	*/
<>	144:ef7eb2e8f9f7	1558	HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef hhash, uint8_t pInBuffer, uint32_t Size)
<>	144:ef7eb2e8f9f7	1559	{
<>	144:ef7eb2e8f9f7	1560	uint32_t inputaddr;
<>	144:ef7eb2e8f9f7	1561
<>	144:ef7eb2e8f9f7	1562	/* Process Locked */
<>	144:ef7eb2e8f9f7	1563	__HAL_LOCK(hhash);
<>	144:ef7eb2e8f9f7	1564
<>	144:ef7eb2e8f9f7	1565	/* Change the HASH state */
<>	144:ef7eb2e8f9f7	1566	hhash->State = HAL_HASH_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/* Save buffer pointer and size in handle */
<>	144:ef7eb2e8f9f7	1569	hhash->pHashInBuffPtr = pInBuffer;
<>	144:ef7eb2e8f9f7	1570	hhash->HashBuffSize = Size;
<>	144:ef7eb2e8f9f7	1571	hhash->HashInCount = 0;
<>	144:ef7eb2e8f9f7	1572
<>	144:ef7eb2e8f9f7	1573	/* Check if initialization phase has already been performed */
<>	144:ef7eb2e8f9f7	1574	if(hhash->Phase == HAL_HASH_PHASE_READY)
<>	144:ef7eb2e8f9f7	1575	{
<>	144:ef7eb2e8f9f7	1576	/* Check if key size is greater than 64 bytes */
<>	144:ef7eb2e8f9f7	1577	if(hhash->Init.KeySize > 64)
<>	144:ef7eb2e8f9f7	1578	{
<>	144:ef7eb2e8f9f7	1579	/* Select the HMAC SHA256 mode */
<>	144:ef7eb2e8f9f7	1580	HASH->CR \|= (HASH_ALGOSELECTION_SHA256 \| HASH_ALGOMODE_HMAC \| HASH_HMAC_KEYTYPE_LONGKEY);
<>	144:ef7eb2e8f9f7	1581	}
<>	144:ef7eb2e8f9f7	1582	else
<>	144:ef7eb2e8f9f7	1583	{
<>	144:ef7eb2e8f9f7	1584	/* Select the HMAC SHA256 mode */
<>	144:ef7eb2e8f9f7	1585	HASH->CR \|= (HASH_ALGOSELECTION_SHA256 \| HASH_ALGOMODE_HMAC);
<>	144:ef7eb2e8f9f7	1586	}
<>	144:ef7eb2e8f9f7	1587	/* Reset the HASH processor core, so that the HASH will be ready to compute
<>	144:ef7eb2e8f9f7	1588	the message digest of a new message */
<>	144:ef7eb2e8f9f7	1589	HASH->CR \|= HASH_CR_INIT;
<>	144:ef7eb2e8f9f7	1590	}
<>	144:ef7eb2e8f9f7	1591
<>	144:ef7eb2e8f9f7	1592	/* Set the phase */
<>	144:ef7eb2e8f9f7	1593	hhash->Phase = HAL_HASH_PHASE_PROCESS;
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	/* Configure the number of valid bits in last word of the message */
<>	144:ef7eb2e8f9f7	1596	__HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598	/* Get the key address */
<>	144:ef7eb2e8f9f7	1599	inputaddr = (uint32_t)(hhash->Init.pKey);
<>	144:ef7eb2e8f9f7	1600
<>	144:ef7eb2e8f9f7	1601	/* Set the HASH DMA transfer complete callback */
<>	144:ef7eb2e8f9f7	1602	hhash->hdmain->XferCpltCallback = HASHEx_DMAXferCplt;
<>	144:ef7eb2e8f9f7	1603	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1604	hhash->hdmain->XferErrorCallback = HASHEx_DMAError;
<>	144:ef7eb2e8f9f7	1605
<>	144:ef7eb2e8f9f7	1606	/* Enable the DMA In DMA Stream */
<>	144:ef7eb2e8f9f7	1607	HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4 ? (hhash->Init.KeySize+3)/4:hhash->Init.KeySize/4));
<>	144:ef7eb2e8f9f7	1608	/* Enable DMA requests */
<>	144:ef7eb2e8f9f7	1609	HASH->CR \|= (HASH_CR_DMAE);
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1612	__HAL_UNLOCK(hhash);
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Return function status */
<>	144:ef7eb2e8f9f7	1615	return HAL_OK;
<>	144:ef7eb2e8f9f7	1616	}
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/**
<>	144:ef7eb2e8f9f7	1619	* @}
<>	144:ef7eb2e8f9f7	1620	*/
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	/**
<>	144:ef7eb2e8f9f7	1623	* @}
<>	144:ef7eb2e8f9f7	1624	*/
<>	144:ef7eb2e8f9f7	1625	#endif /* HAL_HASH_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	/**
<>	144:ef7eb2e8f9f7	1628	* @}
<>	144:ef7eb2e8f9f7	1629	*/
<>	144:ef7eb2e8f9f7	1630	#endif /* STM32F756xx \|\| STM32F777xx \|\| STM32F779xx */
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	/**
<>	144:ef7eb2e8f9f7	1633	* @}
<>	144:ef7eb2e8f9f7	1634	*/
<>	144:ef7eb2e8f9f7	1635
<>	144:ef7eb2e8f9f7	1636	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	10 Sep 2016
Imports:	1
Forks:	0
Commits:	148
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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