Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_dma_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of DMA HAL extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F7xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F7xx_HAL_DMA_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f7xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup DMAEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup DMAEx_Exported_Types DMAEx Exported Types
<> 144:ef7eb2e8f9f7 59 * @brief DMAEx Exported types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL DMA Memory definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 MEMORY0 = 0x00U, /*!< Memory 0 */
<> 144:ef7eb2e8f9f7 69 MEMORY1 = 0x01U, /*!< Memory 1 */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 }HAL_DMA_MemoryTypeDef;
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /**
<> 144:ef7eb2e8f9f7 74 * @}
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @defgroup DMA_Exported_Constants DMA Exported Constants
<> 144:ef7eb2e8f9f7 80 * @brief DMA Exported constants
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** @defgroup DMAEx_Channel_selection DMA Channel selection
<> 144:ef7eb2e8f9f7 85 * @brief DMAEx channel selection
<> 144:ef7eb2e8f9f7 86 * @{
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 #define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
<> 144:ef7eb2e8f9f7 89 #define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
<> 144:ef7eb2e8f9f7 90 #define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
<> 144:ef7eb2e8f9f7 91 #define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
<> 144:ef7eb2e8f9f7 92 #define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
<> 144:ef7eb2e8f9f7 93 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
<> 144:ef7eb2e8f9f7 94 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
<> 144:ef7eb2e8f9f7 95 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
<> 144:ef7eb2e8f9f7 96 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 97 #define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
<> 144:ef7eb2e8f9f7 98 #define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
<> 144:ef7eb2e8f9f7 99 #define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/
<> 144:ef7eb2e8f9f7 100 #define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/
<> 144:ef7eb2e8f9f7 101 #define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/
<> 144:ef7eb2e8f9f7 102 #define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/
<> 144:ef7eb2e8f9f7 103 #define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/
<> 144:ef7eb2e8f9f7 104 #define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/
<> 144:ef7eb2e8f9f7 105 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @}
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @}
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
<> 144:ef7eb2e8f9f7 117 * @brief DMAEx Exported functions
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
<> 144:ef7eb2e8f9f7 122 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* IO operation functions *******************************************************/
<> 144:ef7eb2e8f9f7 127 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 128 HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
<> 144:ef7eb2e8f9f7 129 HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @}
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 139 /** @defgroup DMAEx_Private_Macros DMA Private Macros
<> 144:ef7eb2e8f9f7 140 * @brief DMAEx private macros
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
<> 144:ef7eb2e8f9f7 144 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 145 ((CHANNEL) == DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 146 ((CHANNEL) == DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 147 ((CHANNEL) == DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 148 ((CHANNEL) == DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 149 ((CHANNEL) == DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 150 ((CHANNEL) == DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 151 ((CHANNEL) == DMA_CHANNEL_7) || \
<> 144:ef7eb2e8f9f7 152 ((CHANNEL) == DMA_CHANNEL_8) || \
<> 144:ef7eb2e8f9f7 153 ((CHANNEL) == DMA_CHANNEL_9) || \
<> 144:ef7eb2e8f9f7 154 ((CHANNEL) == DMA_CHANNEL_10) || \
<> 144:ef7eb2e8f9f7 155 ((CHANNEL) == DMA_CHANNEL_11) || \
<> 144:ef7eb2e8f9f7 156 ((CHANNEL) == DMA_CHANNEL_12) || \
<> 144:ef7eb2e8f9f7 157 ((CHANNEL) == DMA_CHANNEL_13) || \
<> 144:ef7eb2e8f9f7 158 ((CHANNEL) == DMA_CHANNEL_14) || \
<> 144:ef7eb2e8f9f7 159 ((CHANNEL) == DMA_CHANNEL_15))
<> 144:ef7eb2e8f9f7 160 #else
<> 144:ef7eb2e8f9f7 161 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
<> 144:ef7eb2e8f9f7 162 ((CHANNEL) == DMA_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 163 ((CHANNEL) == DMA_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 164 ((CHANNEL) == DMA_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 165 ((CHANNEL) == DMA_CHANNEL_4) || \
<> 144:ef7eb2e8f9f7 166 ((CHANNEL) == DMA_CHANNEL_5) || \
<> 144:ef7eb2e8f9f7 167 ((CHANNEL) == DMA_CHANNEL_6) || \
<> 144:ef7eb2e8f9f7 168 ((CHANNEL) == DMA_CHANNEL_7))
<> 144:ef7eb2e8f9f7 169 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175 /** @defgroup DMAEx_Private_Functions DMAEx Private Functions
<> 144:ef7eb2e8f9f7 176 * @brief DMAEx Private functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @}
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /**
<> 144:ef7eb2e8f9f7 188 * @}
<> 144:ef7eb2e8f9f7 189 */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 192 }
<> 144:ef7eb2e8f9f7 193 #endif
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 #endif /* __STM32F7xx_HAL_DMA_H */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/