Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_ll_sdmmc.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_ll_sdmmc.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.2
<> 144:ef7eb2e8f9f7 6 * @date 11-December-2015
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SDMMC HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_LL_SDMMC_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_LL_SDMMC_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F2xx_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SDMMC_LL
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief SDMMC Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref SDIO_Clock_Edge */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
<> 144:ef7eb2e8f9f7 71 enabled or disabled.
<> 144:ef7eb2e8f9f7 72 This parameter can be a value of @ref SDIO_Clock_Bypass */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
<> 144:ef7eb2e8f9f7 75 disabled when the bus is idle.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref SDIO_Clock_Power_Save */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t BusWide; /*!< Specifies the SDIO bus width.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref SDIO_Bus_Wide */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
<> 144:ef7eb2e8f9f7 82 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
<> 144:ef7eb2e8f9f7 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 }SDIO_InitTypeDef;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /**
<> 144:ef7eb2e8f9f7 91 * @brief SDIO Command Control structure
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 typedef struct
<> 144:ef7eb2e8f9f7 94 {
<> 144:ef7eb2e8f9f7 95 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
<> 144:ef7eb2e8f9f7 96 to a card as part of a command message. If a command
<> 144:ef7eb2e8f9f7 97 contains an argument, it must be loaded into this register
<> 144:ef7eb2e8f9f7 98 before writing the command to the command register. */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
<> 144:ef7eb2e8f9f7 101 Max_Data = 64 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 uint32_t Response; /*!< Specifies the SDIO response type.
<> 144:ef7eb2e8f9f7 104 This parameter can be a value of @ref SDIO_Response_Type */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
<> 144:ef7eb2e8f9f7 107 enabled or disabled.
<> 144:ef7eb2e8f9f7 108 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
<> 144:ef7eb2e8f9f7 111 is enabled or disabled.
<> 144:ef7eb2e8f9f7 112 This parameter can be a value of @ref SDIO_CPSM_State */
<> 144:ef7eb2e8f9f7 113 }SDIO_CmdInitTypeDef;
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 144:ef7eb2e8f9f7 117 * @brief SDIO Data Control structure
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef struct
<> 144:ef7eb2e8f9f7 120 {
<> 144:ef7eb2e8f9f7 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
<> 144:ef7eb2e8f9f7 126 This parameter can be a value of @ref SDIO_Data_Block_Size */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
<> 144:ef7eb2e8f9f7 129 is a read or write.
<> 144:ef7eb2e8f9f7 130 This parameter can be a value of @ref SDIO_Transfer_Direction */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
<> 144:ef7eb2e8f9f7 133 This parameter can be a value of @ref SDIO_Transfer_Type */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
<> 144:ef7eb2e8f9f7 136 is enabled or disabled.
<> 144:ef7eb2e8f9f7 137 This parameter can be a value of @ref SDIO_DPSM_State */
<> 144:ef7eb2e8f9f7 138 }SDIO_DataInitTypeDef;
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /**
<> 144:ef7eb2e8f9f7 141 * @}
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 /** @defgroup SDIO_Clock_Edge Clock Edge
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 153 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
<> 144:ef7eb2e8f9f7 156 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
<> 144:ef7eb2e8f9f7 157 /**
<> 144:ef7eb2e8f9f7 158 * @}
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /** @defgroup SDIO_Clock_Bypass Clock Bypass
<> 144:ef7eb2e8f9f7 162 * @{
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 165 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
<> 144:ef7eb2e8f9f7 168 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
<> 144:ef7eb2e8f9f7 169 /**
<> 144:ef7eb2e8f9f7 170 * @}
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
<> 144:ef7eb2e8f9f7 174 * @{
<> 144:ef7eb2e8f9f7 175 */
<> 144:ef7eb2e8f9f7 176 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 177 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
<> 144:ef7eb2e8f9f7 180 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
<> 144:ef7eb2e8f9f7 181 /**
<> 144:ef7eb2e8f9f7 182 * @}
<> 144:ef7eb2e8f9f7 183 */
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /** @defgroup SDIO_Bus_Wide Bus Width
<> 144:ef7eb2e8f9f7 186 * @{
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 189 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
<> 144:ef7eb2e8f9f7 190 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
<> 144:ef7eb2e8f9f7 193 ((WIDE) == SDIO_BUS_WIDE_4B) || \
<> 144:ef7eb2e8f9f7 194 ((WIDE) == SDIO_BUS_WIDE_8B))
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 203 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
<> 144:ef7eb2e8f9f7 206 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @}
<> 144:ef7eb2e8f9f7 209 */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /** @defgroup SDIO_Clock_Division Clock Division
<> 144:ef7eb2e8f9f7 212 * @{
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
<> 144:ef7eb2e8f9f7 215 /**
<> 144:ef7eb2e8f9f7 216 * @}
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /** @defgroup SDIO_Command_Index Command Index
<> 144:ef7eb2e8f9f7 220 * @{
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup SDIO_Response_Type Response Type
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 231 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
<> 144:ef7eb2e8f9f7 232 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
<> 144:ef7eb2e8f9f7 235 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
<> 144:ef7eb2e8f9f7 236 ((RESPONSE) == SDIO_RESPONSE_LONG))
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 245 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
<> 144:ef7eb2e8f9f7 246 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
<> 144:ef7eb2e8f9f7 249 ((WAIT) == SDIO_WAIT_IT) || \
<> 144:ef7eb2e8f9f7 250 ((WAIT) == SDIO_WAIT_PEND))
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /** @defgroup SDIO_CPSM_State CPSM State
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 259 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
<> 144:ef7eb2e8f9f7 262 ((CPSM) == SDIO_CPSM_ENABLE))
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup SDIO_Response_Registers Response Register
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 #define SDIO_RESP1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 271 #define SDIO_RESP2 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 272 #define SDIO_RESP3 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 273 #define SDIO_RESP4 ((uint32_t)0x0000000C)
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
<> 144:ef7eb2e8f9f7 276 ((RESP) == SDIO_RESP2) || \
<> 144:ef7eb2e8f9f7 277 ((RESP) == SDIO_RESP3) || \
<> 144:ef7eb2e8f9f7 278 ((RESP) == SDIO_RESP4))
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /** @defgroup SDIO_Data_Length Data Lenght
<> 144:ef7eb2e8f9f7 284 * @{
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup SDIO_Data_Block_Size Data Block Size
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 295 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
<> 144:ef7eb2e8f9f7 296 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
<> 144:ef7eb2e8f9f7 297 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
<> 144:ef7eb2e8f9f7 298 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
<> 144:ef7eb2e8f9f7 299 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
<> 144:ef7eb2e8f9f7 300 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
<> 144:ef7eb2e8f9f7 301 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
<> 144:ef7eb2e8f9f7 302 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
<> 144:ef7eb2e8f9f7 303 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
<> 144:ef7eb2e8f9f7 304 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
<> 144:ef7eb2e8f9f7 305 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
<> 144:ef7eb2e8f9f7 306 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
<> 144:ef7eb2e8f9f7 307 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
<> 144:ef7eb2e8f9f7 308 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
<> 144:ef7eb2e8f9f7 311 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
<> 144:ef7eb2e8f9f7 312 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
<> 144:ef7eb2e8f9f7 313 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
<> 144:ef7eb2e8f9f7 314 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
<> 144:ef7eb2e8f9f7 315 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
<> 144:ef7eb2e8f9f7 316 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
<> 144:ef7eb2e8f9f7 317 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
<> 144:ef7eb2e8f9f7 318 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
<> 144:ef7eb2e8f9f7 319 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
<> 144:ef7eb2e8f9f7 320 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
<> 144:ef7eb2e8f9f7 321 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
<> 144:ef7eb2e8f9f7 322 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
<> 144:ef7eb2e8f9f7 323 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
<> 144:ef7eb2e8f9f7 324 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @}
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /** @defgroup SDIO_Transfer_Direction Transfer Direction
<> 144:ef7eb2e8f9f7 330 * @{
<> 144:ef7eb2e8f9f7 331 */
<> 144:ef7eb2e8f9f7 332 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 333 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
<> 144:ef7eb2e8f9f7 336 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @}
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /** @defgroup SDIO_Transfer_Type Transfer Type
<> 144:ef7eb2e8f9f7 342 * @{
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 345 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
<> 144:ef7eb2e8f9f7 348 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
<> 144:ef7eb2e8f9f7 349 /**
<> 144:ef7eb2e8f9f7 350 * @}
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /** @defgroup SDIO_DPSM_State DPSM State
<> 144:ef7eb2e8f9f7 354 * @{
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 357 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
<> 144:ef7eb2e8f9f7 360 ((DPSM) == SDIO_DPSM_ENABLE))
<> 144:ef7eb2e8f9f7 361 /**
<> 144:ef7eb2e8f9f7 362 * @}
<> 144:ef7eb2e8f9f7 363 */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
<> 144:ef7eb2e8f9f7 366 * @{
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 369 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
<> 144:ef7eb2e8f9f7 372 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
<> 144:ef7eb2e8f9f7 373 /**
<> 144:ef7eb2e8f9f7 374 * @}
<> 144:ef7eb2e8f9f7 375 */
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
<> 144:ef7eb2e8f9f7 378 * @{
<> 144:ef7eb2e8f9f7 379 */
<> 144:ef7eb2e8f9f7 380 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 381 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 382 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 383 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 384 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 385 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
<> 144:ef7eb2e8f9f7 386 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
<> 144:ef7eb2e8f9f7 387 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
<> 144:ef7eb2e8f9f7 388 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
<> 144:ef7eb2e8f9f7 389 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
<> 144:ef7eb2e8f9f7 390 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
<> 144:ef7eb2e8f9f7 391 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
<> 144:ef7eb2e8f9f7 392 #define SDIO_IT_TXACT SDIO_STA_TXACT
<> 144:ef7eb2e8f9f7 393 #define SDIO_IT_RXACT SDIO_STA_RXACT
<> 144:ef7eb2e8f9f7 394 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 395 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 396 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 397 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 398 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 399 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 400 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
<> 144:ef7eb2e8f9f7 401 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
<> 144:ef7eb2e8f9f7 402 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
<> 144:ef7eb2e8f9f7 403 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
<> 144:ef7eb2e8f9f7 404 /**
<> 144:ef7eb2e8f9f7 405 * @}
<> 144:ef7eb2e8f9f7 406 */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /** @defgroup SDIO_Flags Flags
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
<> 144:ef7eb2e8f9f7 412 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
<> 144:ef7eb2e8f9f7 413 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
<> 144:ef7eb2e8f9f7 414 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
<> 144:ef7eb2e8f9f7 415 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
<> 144:ef7eb2e8f9f7 416 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
<> 144:ef7eb2e8f9f7 417 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
<> 144:ef7eb2e8f9f7 418 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
<> 144:ef7eb2e8f9f7 419 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
<> 144:ef7eb2e8f9f7 420 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
<> 144:ef7eb2e8f9f7 421 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
<> 144:ef7eb2e8f9f7 422 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
<> 144:ef7eb2e8f9f7 423 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
<> 144:ef7eb2e8f9f7 424 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
<> 144:ef7eb2e8f9f7 425 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
<> 144:ef7eb2e8f9f7 426 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
<> 144:ef7eb2e8f9f7 427 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
<> 144:ef7eb2e8f9f7 428 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
<> 144:ef7eb2e8f9f7 429 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
<> 144:ef7eb2e8f9f7 430 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
<> 144:ef7eb2e8f9f7 431 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
<> 144:ef7eb2e8f9f7 432 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
<> 144:ef7eb2e8f9f7 433 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
<> 144:ef7eb2e8f9f7 434 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
<> 144:ef7eb2e8f9f7 435 /**
<> 144:ef7eb2e8f9f7 436 * @}
<> 144:ef7eb2e8f9f7 437 */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * @}
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 443 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
<> 144:ef7eb2e8f9f7 444 * @{
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
<> 144:ef7eb2e8f9f7 448 * @{
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 /* ------------ SDIO registers bit address in the alias region -------------- */
<> 144:ef7eb2e8f9f7 451 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /* --- CLKCR Register ---*/
<> 144:ef7eb2e8f9f7 454 /* Alias word address of CLKEN bit */
<> 144:ef7eb2e8f9f7 455 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
<> 144:ef7eb2e8f9f7 456 #define CLKEN_BITNUMBER 0x08
<> 144:ef7eb2e8f9f7 457 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* --- CMD Register ---*/
<> 144:ef7eb2e8f9f7 460 /* Alias word address of SDIOSUSPEND bit */
<> 144:ef7eb2e8f9f7 461 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
<> 144:ef7eb2e8f9f7 462 #define SDIOSUSPEND_BITNUMBER 0x0B
<> 144:ef7eb2e8f9f7 463 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Alias word address of ENCMDCOMPL bit */
<> 144:ef7eb2e8f9f7 466 #define ENCMDCOMPL_BITNUMBER 0x0C
<> 144:ef7eb2e8f9f7 467 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Alias word address of NIEN bit */
<> 144:ef7eb2e8f9f7 470 #define NIEN_BITNUMBER 0x0D
<> 144:ef7eb2e8f9f7 471 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 /* Alias word address of ATACMD bit */
<> 144:ef7eb2e8f9f7 474 #define ATACMD_BITNUMBER 0x0E
<> 144:ef7eb2e8f9f7 475 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /* --- DCTRL Register ---*/
<> 144:ef7eb2e8f9f7 478 /* Alias word address of DMAEN bit */
<> 144:ef7eb2e8f9f7 479 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
<> 144:ef7eb2e8f9f7 480 #define DMAEN_BITNUMBER 0x03
<> 144:ef7eb2e8f9f7 481 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /* Alias word address of RWSTART bit */
<> 144:ef7eb2e8f9f7 484 #define RWSTART_BITNUMBER 0x08
<> 144:ef7eb2e8f9f7 485 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Alias word address of RWSTOP bit */
<> 144:ef7eb2e8f9f7 488 #define RWSTOP_BITNUMBER 0x09
<> 144:ef7eb2e8f9f7 489 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* Alias word address of RWMOD bit */
<> 144:ef7eb2e8f9f7 492 #define RWMOD_BITNUMBER 0x0A
<> 144:ef7eb2e8f9f7 493 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Alias word address of SDIOEN bit */
<> 144:ef7eb2e8f9f7 496 #define SDIOEN_BITNUMBER 0x0B
<> 144:ef7eb2e8f9f7 497 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @}
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
<> 144:ef7eb2e8f9f7 503 * @brief SDMMC_LL registers bit address in the alias region
<> 144:ef7eb2e8f9f7 504 * @{
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 /* ---------------------- SDIO registers bit mask --------------------------- */
<> 144:ef7eb2e8f9f7 508 /* --- CLKCR Register ---*/
<> 144:ef7eb2e8f9f7 509 /* CLKCR register clear mask */
<> 144:ef7eb2e8f9f7 510 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
<> 144:ef7eb2e8f9f7 511 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
<> 144:ef7eb2e8f9f7 512 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* --- PWRCTRL Register ---*/
<> 144:ef7eb2e8f9f7 515 /* --- DCTRL Register ---*/
<> 144:ef7eb2e8f9f7 516 /* SDIO DCTRL Clear Mask */
<> 144:ef7eb2e8f9f7 517 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
<> 144:ef7eb2e8f9f7 518 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /* --- CMD Register ---*/
<> 144:ef7eb2e8f9f7 521 /* CMD Register clear mask */
<> 144:ef7eb2e8f9f7 522 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
<> 144:ef7eb2e8f9f7 523 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
<> 144:ef7eb2e8f9f7 524 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* SDIO RESP Registers Address */
<> 144:ef7eb2e8f9f7 527 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* SDIO Initialization Frequency (400KHz max) */
<> 144:ef7eb2e8f9f7 530 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* SDIO Data Transfer Frequency (25MHz max) */
<> 144:ef7eb2e8f9f7 533 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @}
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
<> 144:ef7eb2e8f9f7 539 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 540 * @{
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /**
<> 144:ef7eb2e8f9f7 544 * @brief Enable the SDIO device.
<> 144:ef7eb2e8f9f7 545 * @retval None
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /**
<> 144:ef7eb2e8f9f7 550 * @brief Disable the SDIO device.
<> 144:ef7eb2e8f9f7 551 * @retval None
<> 144:ef7eb2e8f9f7 552 */
<> 144:ef7eb2e8f9f7 553 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /**
<> 144:ef7eb2e8f9f7 556 * @brief Enable the SDIO DMA transfer.
<> 144:ef7eb2e8f9f7 557 * @retval None
<> 144:ef7eb2e8f9f7 558 */
<> 144:ef7eb2e8f9f7 559 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 560
<> 144:ef7eb2e8f9f7 561 /**
<> 144:ef7eb2e8f9f7 562 * @brief Disable the SDIO DMA transfer.
<> 144:ef7eb2e8f9f7 563 * @retval None
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /**
<> 144:ef7eb2e8f9f7 568 * @brief Enable the SDIO device interrupt.
<> 144:ef7eb2e8f9f7 569 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 570 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 571 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 572 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 573 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 574 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 575 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 576 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 577 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 578 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 579 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 580 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 581 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 582 * bus mode interrupt
<> 144:ef7eb2e8f9f7 583 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 584 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 585 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 586 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 587 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 588 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 589 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 590 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 591 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 592 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 593 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 594 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 595 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 596 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 597 * @retval None
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Disable the SDIO device interrupt.
<> 144:ef7eb2e8f9f7 603 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 604 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
<> 144:ef7eb2e8f9f7 605 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 606 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 607 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 608 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 609 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 610 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 611 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 612 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 613 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 614 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 615 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 616 * bus mode interrupt
<> 144:ef7eb2e8f9f7 617 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 618 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 619 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 620 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 621 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 622 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 623 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 624 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 625 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 626 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 627 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 628 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 629 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 630 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 631 * @retval None
<> 144:ef7eb2e8f9f7 632 */
<> 144:ef7eb2e8f9f7 633 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /**
<> 144:ef7eb2e8f9f7 636 * @brief Checks whether the specified SDIO flag is set or not.
<> 144:ef7eb2e8f9f7 637 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 638 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 639 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 640 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 641 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 642 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 643 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 644 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 645 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 646 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 647 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 648 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 649 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
<> 144:ef7eb2e8f9f7 650 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 651 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
<> 144:ef7eb2e8f9f7 652 * @arg SDIO_FLAG_TXACT: Data transmit in progress
<> 144:ef7eb2e8f9f7 653 * @arg SDIO_FLAG_RXACT: Data receive in progress
<> 144:ef7eb2e8f9f7 654 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
<> 144:ef7eb2e8f9f7 655 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
<> 144:ef7eb2e8f9f7 656 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
<> 144:ef7eb2e8f9f7 657 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
<> 144:ef7eb2e8f9f7 658 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
<> 144:ef7eb2e8f9f7 659 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
<> 144:ef7eb2e8f9f7 660 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
<> 144:ef7eb2e8f9f7 661 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
<> 144:ef7eb2e8f9f7 662 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 663 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 664 * @retval The new state of SDIO_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @brief Clears the SDIO pending flags.
<> 144:ef7eb2e8f9f7 671 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 672 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 673 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 674 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
<> 144:ef7eb2e8f9f7 675 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
<> 144:ef7eb2e8f9f7 676 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
<> 144:ef7eb2e8f9f7 677 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
<> 144:ef7eb2e8f9f7 678 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
<> 144:ef7eb2e8f9f7 679 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
<> 144:ef7eb2e8f9f7 680 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
<> 144:ef7eb2e8f9f7 681 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
<> 144:ef7eb2e8f9f7 682 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
<> 144:ef7eb2e8f9f7 683 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
<> 144:ef7eb2e8f9f7 684 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
<> 144:ef7eb2e8f9f7 685 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
<> 144:ef7eb2e8f9f7 686 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 687 * @retval None
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @brief Checks whether the specified SDIO interrupt has occurred or not.
<> 144:ef7eb2e8f9f7 693 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 694 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
<> 144:ef7eb2e8f9f7 695 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 696 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 697 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 698 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 699 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 700 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 701 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 702 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 703 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 704 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 705 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 706 * bus mode interrupt
<> 144:ef7eb2e8f9f7 707 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 708 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
<> 144:ef7eb2e8f9f7 709 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
<> 144:ef7eb2e8f9f7 710 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
<> 144:ef7eb2e8f9f7 711 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
<> 144:ef7eb2e8f9f7 712 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
<> 144:ef7eb2e8f9f7 713 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
<> 144:ef7eb2e8f9f7 714 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
<> 144:ef7eb2e8f9f7 715 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
<> 144:ef7eb2e8f9f7 716 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
<> 144:ef7eb2e8f9f7 717 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
<> 144:ef7eb2e8f9f7 718 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
<> 144:ef7eb2e8f9f7 719 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 720 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
<> 144:ef7eb2e8f9f7 721 * @retval The new state of SDIO_IT (SET or RESET).
<> 144:ef7eb2e8f9f7 722 */
<> 144:ef7eb2e8f9f7 723 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /**
<> 144:ef7eb2e8f9f7 726 * @brief Clears the SDIO's interrupt pending bits.
<> 144:ef7eb2e8f9f7 727 * @param __INSTANCE__ : Pointer to SDIO register base
<> 144:ef7eb2e8f9f7 728 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<> 144:ef7eb2e8f9f7 729 * This parameter can be one or a combination of the following values:
<> 144:ef7eb2e8f9f7 730 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 731 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
<> 144:ef7eb2e8f9f7 732 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
<> 144:ef7eb2e8f9f7 733 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
<> 144:ef7eb2e8f9f7 734 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
<> 144:ef7eb2e8f9f7 735 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
<> 144:ef7eb2e8f9f7 736 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
<> 144:ef7eb2e8f9f7 737 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
<> 144:ef7eb2e8f9f7 738 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
<> 144:ef7eb2e8f9f7 739 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
<> 144:ef7eb2e8f9f7 740 * bus mode interrupt
<> 144:ef7eb2e8f9f7 741 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
<> 144:ef7eb2e8f9f7 742 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
<> 144:ef7eb2e8f9f7 743 * @retval None
<> 144:ef7eb2e8f9f7 744 */
<> 144:ef7eb2e8f9f7 745 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 749 * @retval None
<> 144:ef7eb2e8f9f7 750 */
<> 144:ef7eb2e8f9f7 751 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /**
<> 144:ef7eb2e8f9f7 754 * @brief Disable Start the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 755 * @retval None
<> 144:ef7eb2e8f9f7 756 */
<> 144:ef7eb2e8f9f7 757 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /**
<> 144:ef7eb2e8f9f7 760 * @brief Enable Start the SD I/O Read Wait operation.
<> 144:ef7eb2e8f9f7 761 * @retval None
<> 144:ef7eb2e8f9f7 762 */
<> 144:ef7eb2e8f9f7 763 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @brief Disable Stop the SD I/O Read Wait operations.
<> 144:ef7eb2e8f9f7 767 * @retval None
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /**
<> 144:ef7eb2e8f9f7 772 * @brief Enable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 773 * @retval None
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /**
<> 144:ef7eb2e8f9f7 778 * @brief Disable the SD I/O Mode Operation.
<> 144:ef7eb2e8f9f7 779 * @retval None
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /**
<> 144:ef7eb2e8f9f7 784 * @brief Enable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 785 * @retval None
<> 144:ef7eb2e8f9f7 786 */
<> 144:ef7eb2e8f9f7 787 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /**
<> 144:ef7eb2e8f9f7 790 * @brief Disable the SD I/O Suspend command sending.
<> 144:ef7eb2e8f9f7 791 * @retval None
<> 144:ef7eb2e8f9f7 792 */
<> 144:ef7eb2e8f9f7 793 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /**
<> 144:ef7eb2e8f9f7 796 * @brief Enable the command completion signal.
<> 144:ef7eb2e8f9f7 797 * @retval None
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /**
<> 144:ef7eb2e8f9f7 802 * @brief Disable the command completion signal.
<> 144:ef7eb2e8f9f7 803 * @retval None
<> 144:ef7eb2e8f9f7 804 */
<> 144:ef7eb2e8f9f7 805 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /**
<> 144:ef7eb2e8f9f7 808 * @brief Enable the CE-ATA interrupt.
<> 144:ef7eb2e8f9f7 809 * @retval None
<> 144:ef7eb2e8f9f7 810 */
<> 144:ef7eb2e8f9f7 811 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 /**
<> 144:ef7eb2e8f9f7 814 * @brief Disable the CE-ATA interrupt.
<> 144:ef7eb2e8f9f7 815 * @retval None
<> 144:ef7eb2e8f9f7 816 */
<> 144:ef7eb2e8f9f7 817 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 /**
<> 144:ef7eb2e8f9f7 820 * @brief Enable send CE-ATA command (CMD61).
<> 144:ef7eb2e8f9f7 821 * @retval None
<> 144:ef7eb2e8f9f7 822 */
<> 144:ef7eb2e8f9f7 823 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /**
<> 144:ef7eb2e8f9f7 826 * @brief Disable send CE-ATA command (CMD61).
<> 144:ef7eb2e8f9f7 827 * @retval None
<> 144:ef7eb2e8f9f7 828 */
<> 144:ef7eb2e8f9f7 829 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @}
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 840 /** @addtogroup SDMMC_LL_Exported_Functions
<> 144:ef7eb2e8f9f7 841 * @{
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 845 /** @addtogroup HAL_SDMMC_LL_Group1
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
<> 144:ef7eb2e8f9f7 849 /**
<> 144:ef7eb2e8f9f7 850 * @}
<> 144:ef7eb2e8f9f7 851 */
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 854 /** @addtogroup HAL_SDMMC_LL_Group2
<> 144:ef7eb2e8f9f7 855 * @{
<> 144:ef7eb2e8f9f7 856 */
<> 144:ef7eb2e8f9f7 857 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 858 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 859 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @}
<> 144:ef7eb2e8f9f7 862 */
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 /* Peripheral Control functions ************************************************/
<> 144:ef7eb2e8f9f7 865 /** @addtogroup HAL_SDMMC_LL_Group3
<> 144:ef7eb2e8f9f7 866 * @{
<> 144:ef7eb2e8f9f7 867 */
<> 144:ef7eb2e8f9f7 868 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 869 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 870 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 /* Command path state machine (CPSM) management functions */
<> 144:ef7eb2e8f9f7 873 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
<> 144:ef7eb2e8f9f7 874 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 875 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /* Data path state machine (DPSM) management functions */
<> 144:ef7eb2e8f9f7 878 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
<> 144:ef7eb2e8f9f7 879 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 880 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* SDIO IO Cards mode management functions */
<> 144:ef7eb2e8f9f7 883 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /**
<> 144:ef7eb2e8f9f7 886 * @}
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /**
<> 144:ef7eb2e8f9f7 890 * @}
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /**
<> 144:ef7eb2e8f9f7 894 * @}
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903 #endif
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 #endif /* __STM32F2xx_LL_SDMMC_H */
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/