Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_ll_fsmc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_ll_fsmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.2
<> 144:ef7eb2e8f9f7 6 * @date 11-December-2015
<> 144:ef7eb2e8f9f7 7 * @brief FSMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FSMC peripheral features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
<> 144:ef7eb2e8f9f7 20 (+) The NOR/PSRAM memory controller
<> 144:ef7eb2e8f9f7 21 (+) The NAND/PC Card memory controller
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
<> 144:ef7eb2e8f9f7 24 memories and 16-bit PC memory cards. Its main purposes are:
<> 144:ef7eb2e8f9f7 25 (+) to translate AHB transactions into the appropriate external device protocol.
<> 144:ef7eb2e8f9f7 26 (+) to meet the access time requirements of the external memory devices.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 [..] All external memories share the addresses, data and control signals with the controller.
<> 144:ef7eb2e8f9f7 29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
<> 144:ef7eb2e8f9f7 30 only one access at a time to an external device.
<> 144:ef7eb2e8f9f7 31 The main features of the FSMC controller are the following:
<> 144:ef7eb2e8f9f7 32 (+) Interface with static-memory mapped devices including:
<> 144:ef7eb2e8f9f7 33 (++) Static random access memory (SRAM).
<> 144:ef7eb2e8f9f7 34 (++) Read-only memory (ROM).
<> 144:ef7eb2e8f9f7 35 (++) NOR Flash memory/OneNAND Flash memory.
<> 144:ef7eb2e8f9f7 36 (++) PSRAM (4 memory banks).
<> 144:ef7eb2e8f9f7 37 (++) 16-bit PC Card compatible devices.
<> 144:ef7eb2e8f9f7 38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
<> 144:ef7eb2e8f9f7 39 data.
<> 144:ef7eb2e8f9f7 40 (+) Independent Chip Select control for each memory bank.
<> 144:ef7eb2e8f9f7 41 (+) Independent configuration for each memory bank.
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 @endverbatim
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 * @attention
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 50 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 51 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 55 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 57 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 58 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup FSMC_LL FSMC Low Layer
<> 144:ef7eb2e8f9f7 82 * @brief FSMC driver modules
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 91 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 92 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 /** @addtogroup FSMC_LL_Private_Functions
<> 144:ef7eb2e8f9f7 95 * @{
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @addtogroup FSMC_LL_NORSRAM
<> 144:ef7eb2e8f9f7 99 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 100 *
<> 144:ef7eb2e8f9f7 101 @verbatim
<> 144:ef7eb2e8f9f7 102 ==============================================================================
<> 144:ef7eb2e8f9f7 103 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 104 ==============================================================================
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 [..]
<> 144:ef7eb2e8f9f7 107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 108 to run the NORSRAM external devices.
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 113 (+) FSMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 114 FSMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 115 (+) FSMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 @endverbatim
<> 144:ef7eb2e8f9f7 119 * @{
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 123 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 124 *
<> 144:ef7eb2e8f9f7 125 @verbatim
<> 144:ef7eb2e8f9f7 126 ==============================================================================
<> 144:ef7eb2e8f9f7 127 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 128 ==============================================================================
<> 144:ef7eb2e8f9f7 129 [..]
<> 144:ef7eb2e8f9f7 130 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 131 (+) Initialize and configure the FSMC NORSRAM interface
<> 144:ef7eb2e8f9f7 132 (+) De-initialize the FSMC NORSRAM interface
<> 144:ef7eb2e8f9f7 133 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 @endverbatim
<> 144:ef7eb2e8f9f7 136 * @{
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @brief Initialize the FSMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 141 * control parameters in the FSMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 142 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 143 * @param Init: Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 144 * @retval HAL status
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /* Check the parameters */
<> 144:ef7eb2e8f9f7 151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 152 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 153 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 159 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 160 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 161 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 163 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 166 tmpr = Device->BTCR[Init->NSBank];
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
<> 144:ef7eb2e8f9f7 169 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
<> 144:ef7eb2e8f9f7 170 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
<> 144:ef7eb2e8f9f7 171 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
<> 144:ef7eb2e8f9f7 172 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
<> 144:ef7eb2e8f9f7 173 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
<> 144:ef7eb2e8f9f7 174 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
<> 144:ef7eb2e8f9f7 175 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 176 tmpr |= (uint32_t)(Init->DataAddressMux |\
<> 144:ef7eb2e8f9f7 177 Init->MemoryType |\
<> 144:ef7eb2e8f9f7 178 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 179 Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 180 Init->WaitSignalPolarity |\
<> 144:ef7eb2e8f9f7 181 Init->WrapMode |\
<> 144:ef7eb2e8f9f7 182 Init->WaitSignalActive |\
<> 144:ef7eb2e8f9f7 183 Init->WriteOperation |\
<> 144:ef7eb2e8f9f7 184 Init->WaitSignal |\
<> 144:ef7eb2e8f9f7 185 Init->ExtendedMode |\
<> 144:ef7eb2e8f9f7 186 Init->AsynchronousWait |\
<> 144:ef7eb2e8f9f7 187 Init->WriteBurst
<> 144:ef7eb2e8f9f7 188 );
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 Device->BTCR[Init->NSBank] = tmpr;
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 return HAL_OK;
<> 144:ef7eb2e8f9f7 198 }
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /**
<> 144:ef7eb2e8f9f7 201 * @brief DeInitialize the FSMC_NORSRAM peripheral
<> 144:ef7eb2e8f9f7 202 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 203 * @param ExDevice: Pointer to NORSRAM extended mode device instance
<> 144:ef7eb2e8f9f7 204 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 205 * @retval HAL status
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 208 {
<> 144:ef7eb2e8f9f7 209 /* Check the parameters */
<> 144:ef7eb2e8f9f7 210 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 211 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Disable the FSMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 214 __FSMC_NORSRAM_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* De-initialize the FSMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 217 /* FSMC_NORSRAM_BANK1 */
<> 144:ef7eb2e8f9f7 218 if(Bank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 Device->BTCR[Bank] = 0x000030DB;
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 223 else
<> 144:ef7eb2e8f9f7 224 {
<> 144:ef7eb2e8f9f7 225 Device->BTCR[Bank] = 0x000030D2;
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 229 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return HAL_OK;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 237 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 238 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 239 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 240 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 241 * @retval HAL status
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Check the parameters */
<> 144:ef7eb2e8f9f7 248 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 249 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 250 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 251 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 252 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 253 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 254 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 257 tmpr = Device->BTCR[Bank + 1];
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
<> 144:ef7eb2e8f9f7 260 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
<> 144:ef7eb2e8f9f7 261 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
<> 144:ef7eb2e8f9f7 262 FSMC_BTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* Set FSMC_NORSRAM device timing parameters */
<> 144:ef7eb2e8f9f7 265 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 266 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 267 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 268 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 269 (((Timing->CLKDivision)-1) << 20) |\
<> 144:ef7eb2e8f9f7 270 (((Timing->DataLatency)-2) << 24) |\
<> 144:ef7eb2e8f9f7 271 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 Device->BTCR[Bank + 1] = tmpr;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 return HAL_OK;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 280 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 281 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 282 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 283 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 284 * @retval HAL status
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 144:ef7eb2e8f9f7 291 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 292 {
<> 144:ef7eb2e8f9f7 293 /* Check the parameters */
<> 144:ef7eb2e8f9f7 294 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 295 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 296 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 297 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 298 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Get the BWTR register value */
<> 144:ef7eb2e8f9f7 301 tmpr = Device->BWTR[Bank];
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
<> 144:ef7eb2e8f9f7 304 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
<> 144:ef7eb2e8f9f7 305 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 308 ((Timing->AddressHoldTime) << 4) |\
<> 144:ef7eb2e8f9f7 309 ((Timing->DataSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 310 ((Timing->BusTurnAroundDuration) << 16) |\
<> 144:ef7eb2e8f9f7 311 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 Device->BWTR[Bank] = tmpr;
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 else
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 Device->BWTR[Bank] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 318 }
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 return HAL_OK;
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
<> 144:ef7eb2e8f9f7 327 * @brief management functions
<> 144:ef7eb2e8f9f7 328 *
<> 144:ef7eb2e8f9f7 329 @verbatim
<> 144:ef7eb2e8f9f7 330 ==============================================================================
<> 144:ef7eb2e8f9f7 331 ##### FSMC_NORSRAM Control functions #####
<> 144:ef7eb2e8f9f7 332 ==============================================================================
<> 144:ef7eb2e8f9f7 333 [..]
<> 144:ef7eb2e8f9f7 334 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 335 the FSMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 @endverbatim
<> 144:ef7eb2e8f9f7 338 * @{
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief Enables dynamically FSMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 343 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 344 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 345 * @retval HAL status
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 /* Enable write operation */
<> 144:ef7eb2e8f9f7 350 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 return HAL_OK;
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @brief Disables dynamically FSMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 357 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 358 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 359 * @retval HAL status
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 /* Disable write operation */
<> 144:ef7eb2e8f9f7 364 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 return HAL_OK;
<> 144:ef7eb2e8f9f7 367 }
<> 144:ef7eb2e8f9f7 368 /**
<> 144:ef7eb2e8f9f7 369 * @}
<> 144:ef7eb2e8f9f7 370 */
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @}
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /** @addtogroup FSMC_LL_NAND
<> 144:ef7eb2e8f9f7 377 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 378 *
<> 144:ef7eb2e8f9f7 379 @verbatim
<> 144:ef7eb2e8f9f7 380 ==============================================================================
<> 144:ef7eb2e8f9f7 381 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 382 ==============================================================================
<> 144:ef7eb2e8f9f7 383 [..]
<> 144:ef7eb2e8f9f7 384 This driver contains a set of APIs to interface with the FSMC NAND banks in order
<> 144:ef7eb2e8f9f7 385 to run the NAND external devices.
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 388 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
<> 144:ef7eb2e8f9f7 389 (+) FSMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 390 FSMC_NAND_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 391 (+) FSMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 392 FSMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 393 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 394 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
<> 144:ef7eb2e8f9f7 395 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 @endverbatim
<> 144:ef7eb2e8f9f7 398 * @{
<> 144:ef7eb2e8f9f7 399 */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 402 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 403 *
<> 144:ef7eb2e8f9f7 404 @verbatim
<> 144:ef7eb2e8f9f7 405 ==============================================================================
<> 144:ef7eb2e8f9f7 406 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 407 ==============================================================================
<> 144:ef7eb2e8f9f7 408 [..]
<> 144:ef7eb2e8f9f7 409 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 410 (+) Initialize and configure the FSMC NAND interface
<> 144:ef7eb2e8f9f7 411 (+) De-initialize the FSMC NAND interface
<> 144:ef7eb2e8f9f7 412 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 @endverbatim
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @brief Initializes the FSMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 420 * control parameters in the FSMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 421 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 422 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 423 * @retval HAL status
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Check the parameters */
<> 144:ef7eb2e8f9f7 430 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 431 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 432 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 433 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 434 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 435 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 436 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 if(Init->NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 439 {
<> 144:ef7eb2e8f9f7 440 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 441 tmpr = Device->PCR2;
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443 else
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 446 tmpr = Device->PCR3;
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
<> 144:ef7eb2e8f9f7 450 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
<> 144:ef7eb2e8f9f7 451 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
<> 144:ef7eb2e8f9f7 452 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 455 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 456 FSMC_PCR_MEMORY_TYPE_NAND |\
<> 144:ef7eb2e8f9f7 457 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 458 Init->EccComputation |\
<> 144:ef7eb2e8f9f7 459 Init->ECCPageSize |\
<> 144:ef7eb2e8f9f7 460 ((Init->TCLRSetupTime) << 9) |\
<> 144:ef7eb2e8f9f7 461 ((Init->TARSetupTime) << 13));
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 if(Init->NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 464 {
<> 144:ef7eb2e8f9f7 465 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 466 Device->PCR2 = tmpr;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468 else
<> 144:ef7eb2e8f9f7 469 {
<> 144:ef7eb2e8f9f7 470 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 471 Device->PCR3 = tmpr;
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 return HAL_OK;
<> 144:ef7eb2e8f9f7 475 }
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 479 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 480 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 481 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 482 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 483 * @retval HAL status
<> 144:ef7eb2e8f9f7 484 */
<> 144:ef7eb2e8f9f7 485 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /* Check the parameters */
<> 144:ef7eb2e8f9f7 490 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 491 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 492 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 493 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 498 tmpr = Device->PMEM2;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 else
<> 144:ef7eb2e8f9f7 501 {
<> 144:ef7eb2e8f9f7 502 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 503 tmpr = Device->PMEM3;
<> 144:ef7eb2e8f9f7 504 }
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 507 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
<> 144:ef7eb2e8f9f7 508 FSMC_PMEM2_MEMHIZ2));
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /* Set FSMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 511 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 512 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 513 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 514 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 515 );
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 518 {
<> 144:ef7eb2e8f9f7 519 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 520 Device->PMEM2 = tmpr;
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 else
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 525 Device->PMEM3 = tmpr;
<> 144:ef7eb2e8f9f7 526 }
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 return HAL_OK;
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 533 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 534 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 535 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 536 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 537 * @retval HAL status
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Check the parameters */
<> 144:ef7eb2e8f9f7 544 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 545 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 546 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 547 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 552 tmpr = Device->PATT2;
<> 144:ef7eb2e8f9f7 553 }
<> 144:ef7eb2e8f9f7 554 else
<> 144:ef7eb2e8f9f7 555 {
<> 144:ef7eb2e8f9f7 556 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 557 tmpr = Device->PATT3;
<> 144:ef7eb2e8f9f7 558 }
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 561 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
<> 144:ef7eb2e8f9f7 562 FSMC_PATT2_ATTHIZ2));
<> 144:ef7eb2e8f9f7 563
<> 144:ef7eb2e8f9f7 564 /* Set FSMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 565 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 566 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 567 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 568 ((Timing->HiZSetupTime) << 24)
<> 144:ef7eb2e8f9f7 569 );
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 574 Device->PATT2 = tmpr;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 else
<> 144:ef7eb2e8f9f7 577 {
<> 144:ef7eb2e8f9f7 578 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 579 Device->PATT3 = tmpr;
<> 144:ef7eb2e8f9f7 580 }
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 return HAL_OK;
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /**
<> 144:ef7eb2e8f9f7 586 * @brief DeInitializes the FSMC_NAND device
<> 144:ef7eb2e8f9f7 587 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 588 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 589 * @retval HAL status
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 594 __FSMC_NAND_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* De-initialize the NAND Bank */
<> 144:ef7eb2e8f9f7 597 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 /* Set the FSMC_NAND_BANK2 registers to their reset values */
<> 144:ef7eb2e8f9f7 600 Device->PCR2 = 0x00000018;
<> 144:ef7eb2e8f9f7 601 Device->SR2 = 0x00000040;
<> 144:ef7eb2e8f9f7 602 Device->PMEM2 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 603 Device->PATT2 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605 /* FSMC_Bank3_NAND */
<> 144:ef7eb2e8f9f7 606 else
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 /* Set the FSMC_NAND_BANK3 registers to their reset values */
<> 144:ef7eb2e8f9f7 609 Device->PCR3 = 0x00000018;
<> 144:ef7eb2e8f9f7 610 Device->SR3 = 0x00000040;
<> 144:ef7eb2e8f9f7 611 Device->PMEM3 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 612 Device->PATT3 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 return HAL_OK;
<> 144:ef7eb2e8f9f7 616 }
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @}
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
<> 144:ef7eb2e8f9f7 622 * @brief management functions
<> 144:ef7eb2e8f9f7 623 *
<> 144:ef7eb2e8f9f7 624 @verbatim
<> 144:ef7eb2e8f9f7 625 ==============================================================================
<> 144:ef7eb2e8f9f7 626 ##### FSMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 627 ==============================================================================
<> 144:ef7eb2e8f9f7 628 [..]
<> 144:ef7eb2e8f9f7 629 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 630 the FSMC NAND interface.
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 @endverbatim
<> 144:ef7eb2e8f9f7 633 * @{
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief Enables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 638 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 639 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 640 * @retval HAL status
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 645 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 646 {
<> 144:ef7eb2e8f9f7 647 Device->PCR2 |= FSMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 648 }
<> 144:ef7eb2e8f9f7 649 else
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 Device->PCR3 |= FSMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654 return HAL_OK;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 659 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 660 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 661 * @retval HAL status
<> 144:ef7eb2e8f9f7 662 */
<> 144:ef7eb2e8f9f7 663 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 666 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 667 {
<> 144:ef7eb2e8f9f7 668 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 669 }
<> 144:ef7eb2e8f9f7 670 else
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 return HAL_OK;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /**
<> 144:ef7eb2e8f9f7 679 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 680 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 681 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 682 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 683 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 684 * @retval HAL status
<> 144:ef7eb2e8f9f7 685 */
<> 144:ef7eb2e8f9f7 686 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 uint32_t tickstart = 0;
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* Check the parameters */
<> 144:ef7eb2e8f9f7 691 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 692 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /* Get tick */
<> 144:ef7eb2e8f9f7 695 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Wait until FIFO is empty */
<> 144:ef7eb2e8f9f7 698 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 701 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 /* Get the ECCR2 register value */
<> 144:ef7eb2e8f9f7 713 *ECCval = (uint32_t)Device->ECCR2;
<> 144:ef7eb2e8f9f7 714 }
<> 144:ef7eb2e8f9f7 715 else
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Get the ECCR3 register value */
<> 144:ef7eb2e8f9f7 718 *ECCval = (uint32_t)Device->ECCR3;
<> 144:ef7eb2e8f9f7 719 }
<> 144:ef7eb2e8f9f7 720
<> 144:ef7eb2e8f9f7 721 return HAL_OK;
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /**
<> 144:ef7eb2e8f9f7 725 * @}
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /**
<> 144:ef7eb2e8f9f7 729 * @}
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 /** @addtogroup FSMC_LL_PCCARD
<> 144:ef7eb2e8f9f7 733 * @brief PCCARD Controller functions
<> 144:ef7eb2e8f9f7 734 *
<> 144:ef7eb2e8f9f7 735 @verbatim
<> 144:ef7eb2e8f9f7 736 ==============================================================================
<> 144:ef7eb2e8f9f7 737 ##### How to use PCCARD device driver #####
<> 144:ef7eb2e8f9f7 738 ==============================================================================
<> 144:ef7eb2e8f9f7 739 [..]
<> 144:ef7eb2e8f9f7 740 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
<> 144:ef7eb2e8f9f7 741 to run the PCCARD/compact flash external devices.
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
<> 144:ef7eb2e8f9f7 744 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
<> 144:ef7eb2e8f9f7 745 (+) FSMC PCCARD bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 746 FSMC_PCCARD_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 747 (+) FSMC PCCARD bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 748 FSMC_PCCARD_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 749 (+) FSMC PCCARD bank IO space timing configuration using the function
<> 144:ef7eb2e8f9f7 750 FSMC_PCCARD_IOSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 @endverbatim
<> 144:ef7eb2e8f9f7 753 * @{
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755
<> 144:ef7eb2e8f9f7 756 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 757 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 758 *
<> 144:ef7eb2e8f9f7 759 @verbatim
<> 144:ef7eb2e8f9f7 760 ==============================================================================
<> 144:ef7eb2e8f9f7 761 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 762 ==============================================================================
<> 144:ef7eb2e8f9f7 763 [..]
<> 144:ef7eb2e8f9f7 764 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 765 (+) Initialize and configure the FSMC PCCARD interface
<> 144:ef7eb2e8f9f7 766 (+) De-initialize the FSMC PCCARD interface
<> 144:ef7eb2e8f9f7 767 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 @endverbatim
<> 144:ef7eb2e8f9f7 770 * @{
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 /**
<> 144:ef7eb2e8f9f7 774 * @brief Initializes the FSMC_PCCARD device according to the specified
<> 144:ef7eb2e8f9f7 775 * control parameters in the FSMC_PCCARD_HandleTypeDef
<> 144:ef7eb2e8f9f7 776 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 777 * @param Init: Pointer to PCCARD Initialization structure
<> 144:ef7eb2e8f9f7 778 * @retval HAL status
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 781 {
<> 144:ef7eb2e8f9f7 782 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Check the parameters */
<> 144:ef7eb2e8f9f7 785 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 786 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 787 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Get PCCARD control register value */
<> 144:ef7eb2e8f9f7 790 tmpr = Device->PCR4;
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Clear TAR, TCLR, PWAITEN and PWID bits */
<> 144:ef7eb2e8f9f7 793 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
<> 144:ef7eb2e8f9f7 794 FSMC_PCR4_PWID));
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Set FSMC_PCCARD device control parameters */
<> 144:ef7eb2e8f9f7 797 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 798 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
<> 144:ef7eb2e8f9f7 799 (Init->TCLRSetupTime << 9) |\
<> 144:ef7eb2e8f9f7 800 (Init->TARSetupTime << 13));
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 Device->PCR4 = tmpr;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 return HAL_OK;
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /**
<> 144:ef7eb2e8f9f7 808 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 809 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 810 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 811 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 812 * @retval HAL status
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Check the parameters */
<> 144:ef7eb2e8f9f7 819 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 820 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 821 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 822 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Get PCCARD common space timing register value */
<> 144:ef7eb2e8f9f7 825 tmpr = Device->PMEM4;
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 828 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
<> 144:ef7eb2e8f9f7 829 FSMC_PMEM4_MEMHIZ4));
<> 144:ef7eb2e8f9f7 830 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 831 tmpr |= (uint32_t)((Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 832 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 833 (Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 834 ((Timing->HiZSetupTime) << 24));
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 Device->PMEM4 = tmpr;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 return HAL_OK;
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 843 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 844 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 845 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 846 * @retval HAL status
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 849 {
<> 144:ef7eb2e8f9f7 850 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /* Check the parameters */
<> 144:ef7eb2e8f9f7 853 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 854 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 855 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 856 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Get PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 859 tmpr = Device->PATT4;
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 862 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
<> 144:ef7eb2e8f9f7 863 FSMC_PATT4_ATTHIZ4));
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 866 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 867 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 868 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 869 ((Timing->HiZSetupTime) << 24));
<> 144:ef7eb2e8f9f7 870 Device->PATT4 = tmpr;
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 return HAL_OK;
<> 144:ef7eb2e8f9f7 873 }
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 /**
<> 144:ef7eb2e8f9f7 876 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
<> 144:ef7eb2e8f9f7 877 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 878 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 879 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 880 * @retval HAL status
<> 144:ef7eb2e8f9f7 881 */
<> 144:ef7eb2e8f9f7 882 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 883 {
<> 144:ef7eb2e8f9f7 884 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Check the parameters */
<> 144:ef7eb2e8f9f7 887 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 888 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 889 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 890 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /* Get FSMC_PCCARD device timing parameters */
<> 144:ef7eb2e8f9f7 893 tmpr = Device->PIO4;
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
<> 144:ef7eb2e8f9f7 896 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
<> 144:ef7eb2e8f9f7 897 FSMC_PIO4_IOHIZ4));
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /* Set FSMC_PCCARD device timing parameters */
<> 144:ef7eb2e8f9f7 900 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 901 ((Timing->WaitSetupTime) << 8) |\
<> 144:ef7eb2e8f9f7 902 ((Timing->HoldSetupTime) << 16) |\
<> 144:ef7eb2e8f9f7 903 ((Timing->HiZSetupTime) << 24));
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 Device->PIO4 = tmpr;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 return HAL_OK;
<> 144:ef7eb2e8f9f7 908 }
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /**
<> 144:ef7eb2e8f9f7 911 * @brief DeInitializes the FSMC_PCCARD device
<> 144:ef7eb2e8f9f7 912 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 913 * @retval HAL status
<> 144:ef7eb2e8f9f7 914 */
<> 144:ef7eb2e8f9f7 915 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
<> 144:ef7eb2e8f9f7 916 {
<> 144:ef7eb2e8f9f7 917 /* Disable the FSMC_PCCARD device */
<> 144:ef7eb2e8f9f7 918 __FSMC_PCCARD_DISABLE(Device);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* De-initialize the FSMC_PCCARD device */
<> 144:ef7eb2e8f9f7 921 Device->PCR4 = 0x00000018;
<> 144:ef7eb2e8f9f7 922 Device->SR4 = 0x00000000;
<> 144:ef7eb2e8f9f7 923 Device->PMEM4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 924 Device->PATT4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 925 Device->PIO4 = 0xFCFCFCFC;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 return HAL_OK;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @}
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * @}
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @}
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /**
<> 144:ef7eb2e8f9f7 943 * @}
<> 144:ef7eb2e8f9f7 944 */
<> 144:ef7eb2e8f9f7 945
<> 144:ef7eb2e8f9f7 946 /**
<> 144:ef7eb2e8f9f7 947 * @}
<> 144:ef7eb2e8f9f7 948 */
<> 144:ef7eb2e8f9f7 949 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/