Johannes Stratmann / mbed-dev

added prescaler for 16 bit pwm in LPC1347 target

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_nor.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_nor.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of NOR HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F2xx_HAL_NOR_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F2xx_HAL_NOR_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f2xx_ll_fsmc.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 51 * @{
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup NOR
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /* Exported typedef ----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59 /** @defgroup NOR_Exported_Types NOR Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL SRAM State structures definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 69 HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
<> 144:ef7eb2e8f9f7 70 HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
<> 144:ef7eb2e8f9f7 71 HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
<> 144:ef7eb2e8f9f7 72 HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
<> 144:ef7eb2e8f9f7 73 }HAL_NOR_StateTypeDef;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /**
<> 144:ef7eb2e8f9f7 76 * @brief FSMC NOR Status typedef
<> 144:ef7eb2e8f9f7 77 */
<> 144:ef7eb2e8f9f7 78 typedef enum
<> 144:ef7eb2e8f9f7 79 {
<> 144:ef7eb2e8f9f7 80 HAL_NOR_STATUS_SUCCESS = 0U,
<> 144:ef7eb2e8f9f7 81 HAL_NOR_STATUS_ONGOING,
<> 144:ef7eb2e8f9f7 82 HAL_NOR_STATUS_ERROR,
<> 144:ef7eb2e8f9f7 83 HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 84 }HAL_NOR_StatusTypeDef;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /**
<> 144:ef7eb2e8f9f7 87 * @brief FSMC NOR ID typedef
<> 144:ef7eb2e8f9f7 88 */
<> 144:ef7eb2e8f9f7 89 typedef struct
<> 144:ef7eb2e8f9f7 90 {
<> 144:ef7eb2e8f9f7 91 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 uint16_t Device_Code1;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint16_t Device_Code2;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
<> 144:ef7eb2e8f9f7 98 These codes can be accessed by performing read operations with specific
<> 144:ef7eb2e8f9f7 99 control signals and addresses set.They can also be accessed by issuing
<> 144:ef7eb2e8f9f7 100 an Auto Select command */
<> 144:ef7eb2e8f9f7 101 }NOR_IDTypeDef;
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @brief FSMC NOR CFI typedef
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 typedef struct
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 /*!< Defines the information stored in the memory's Common flash interface
<> 144:ef7eb2e8f9f7 109 which contains a description of various electrical and timing parameters,
<> 144:ef7eb2e8f9f7 110 density information and functions supported by the memory */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 uint16_t CFI_1;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 uint16_t CFI_2;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 uint16_t CFI_3;
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 uint16_t CFI_4;
<> 144:ef7eb2e8f9f7 119 }NOR_CFITypeDef;
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /**
<> 144:ef7eb2e8f9f7 122 * @brief NOR handle Structure definition
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 typedef struct
<> 144:ef7eb2e8f9f7 125 {
<> 144:ef7eb2e8f9f7 126 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 HAL_LockTypeDef Lock; /*!< NOR locking object */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 }NOR_HandleTypeDef;
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @}
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /** @defgroup NOR_Exported_Macros NOR Exported Macros
<> 144:ef7eb2e8f9f7 144 * @{
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146 /** @brief Reset NOR handle state
<> 144:ef7eb2e8f9f7 147 * @param __HANDLE__: specifies the NOR handle.
<> 144:ef7eb2e8f9f7 148 * @retval None
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 151 /**
<> 144:ef7eb2e8f9f7 152 * @}
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 156 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 157 * @{
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 165 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
<> 144:ef7eb2e8f9f7 166 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 167 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 168 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 169 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
<> 144:ef7eb2e8f9f7 175 * @{
<> 144:ef7eb2e8f9f7 176 */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 179 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
<> 144:ef7eb2e8f9f7 180 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 181 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
<> 144:ef7eb2e8f9f7 182 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
<> 144:ef7eb2e8f9f7 185 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
<> 144:ef7eb2e8f9f7 188 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
<> 144:ef7eb2e8f9f7 189 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* NOR Control functions *****************************************************/
<> 144:ef7eb2e8f9f7 199 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 200 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @}
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
<> 144:ef7eb2e8f9f7 206 * @{
<> 144:ef7eb2e8f9f7 207 */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /* NOR State functions ********************************************************/
<> 144:ef7eb2e8f9f7 210 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 211 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @}
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 221 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 222 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 223 /** @defgroup NOR_Private_Constants NOR Private Constants
<> 144:ef7eb2e8f9f7 224 * @{
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 /* NOR device IDs addresses */
<> 144:ef7eb2e8f9f7 227 #define MC_ADDRESS ((uint16_t)0x0000U)
<> 144:ef7eb2e8f9f7 228 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
<> 144:ef7eb2e8f9f7 229 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
<> 144:ef7eb2e8f9f7 230 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* NOR CFI IDs addresses */
<> 144:ef7eb2e8f9f7 233 #define CFI1_ADDRESS ((uint16_t)0x61U)
<> 144:ef7eb2e8f9f7 234 #define CFI2_ADDRESS ((uint16_t)0x62U)
<> 144:ef7eb2e8f9f7 235 #define CFI3_ADDRESS ((uint16_t)0x63U)
<> 144:ef7eb2e8f9f7 236 #define CFI4_ADDRESS ((uint16_t)0x64U)
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* NOR operation wait timeout */
<> 144:ef7eb2e8f9f7 239 #define NOR_TMEOUT ((uint16_t)0xFFFFU)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* NOR memory data width */
<> 144:ef7eb2e8f9f7 242 #define NOR_MEMORY_8B ((uint8_t)0x0U)
<> 144:ef7eb2e8f9f7 243 #define NOR_MEMORY_16B ((uint8_t)0x1U)
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* NOR memory device read/write start address */
<> 144:ef7eb2e8f9f7 246 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
<> 144:ef7eb2e8f9f7 247 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
<> 144:ef7eb2e8f9f7 248 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
<> 144:ef7eb2e8f9f7 249 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
<> 144:ef7eb2e8f9f7 250 /**
<> 144:ef7eb2e8f9f7 251 * @}
<> 144:ef7eb2e8f9f7 252 */
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 255 /** @defgroup NOR_Private_Macros NOR Private Macros
<> 144:ef7eb2e8f9f7 256 * @{
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258 /**
<> 144:ef7eb2e8f9f7 259 * @brief NOR memory address shifting.
<> 144:ef7eb2e8f9f7 260 * @param __NOR_ADDRESS__: NOR base address
<> 144:ef7eb2e8f9f7 261 * @param __NOR_MEMORY_WIDTH__: NOR memory width
<> 144:ef7eb2e8f9f7 262 * @param __ADDRESS__: NOR memory address
<> 144:ef7eb2e8f9f7 263 * @retval NOR shifted address value
<> 144:ef7eb2e8f9f7 264 */
<> 144:ef7eb2e8f9f7 265 #define NOR_ADDR_SHIFT(__NOR_ADDRESS__, __NOR_MEMORY_WIDTH__, __ADDRESS__) \
<> 144:ef7eb2e8f9f7 266 ((uint32_t)(((__NOR_MEMORY_WIDTH__) == NOR_MEMORY_16B)? \
<> 144:ef7eb2e8f9f7 267 ((uint32_t)((__NOR_ADDRESS__) + (2U * (__ADDRESS__)))): \
<> 144:ef7eb2e8f9f7 268 ((uint32_t)((__NOR_ADDRESS__) + (__ADDRESS__)))))
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /**
<> 144:ef7eb2e8f9f7 271 * @brief NOR memory write data to specified address.
<> 144:ef7eb2e8f9f7 272 * @param __ADDRESS__: NOR memory address
<> 144:ef7eb2e8f9f7 273 * @param __DATA__: Data to write
<> 144:ef7eb2e8f9f7 274 * @retval None
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276 #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 /**
<> 144:ef7eb2e8f9f7 279 * @}
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292 #endif
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 #endif /* __STM32F2xx_HAL_NOR_H */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/